sim/testsuite/sim/frv/nfsubs.cgs

   1 # frv testcase for nfsubs $FRi,$FRj,$FRk
   2 # mach: fr500 fr550 frv
   3
   4         .include "testutils.inc"
   5
   6         float_constants
   7         start
   8         load_float_constants
   9
  10         .global nfsubs
  11 nfsubs:
  12         nfsubs          fr0,fr16,fr1
  13         test_fr_fr      fr1,fr0
  14         test_spr_immed  0,fner1
  15         test_spr_immed  0,fner0
  16         nfsubs          fr4,fr16,fr1
  17         test_fr_fr      fr1,fr4
  18         test_spr_immed  0,fner1
  19         test_spr_immed  0,fner0
  20         nfsubs          fr8,fr16,fr1
  21         test_fr_fr      fr1,fr8
  22         test_spr_immed  0,fner1
  23         test_spr_immed  0,fner0
  24         nfsubs          fr12,fr16,fr1
  25         test_fr_fr      fr1,fr12
  26         test_spr_immed  0,fner1
  27         test_spr_immed  0,fner0
  28         nfsubs          fr16,fr16,fr1
  29         test_fr_fr      fr1,fr16
  30         test_fr_fr      fr1,fr20
  31         test_spr_immed  0,fner1
  32         test_spr_immed  0,fner0
  33         nfsubs          fr20,fr16,fr1
  34         test_fr_fr      fr1,fr16
  35         test_fr_fr      fr1,fr20
  36         test_spr_immed  0,fner1
  37         test_spr_immed  0,fner0
  38         nfsubs          fr24,fr16,fr1
  39         test_fr_fr      fr1,fr24
  40         test_spr_immed  0,fner1
  41         test_spr_immed  0,fner0
  42         nfsubs          fr28,fr16,fr1
  43         test_fr_fr      fr1,fr28
  44         test_spr_immed  0,fner1
  45         test_spr_immed  0,fner0
  46         nfsubs          fr32,fr16,fr1
  47         test_fr_fr      fr1,fr32
  48         test_spr_immed  0,fner1
  49         test_spr_immed  0,fner0
  50         nfsubs          fr36,fr16,fr1
  51         test_fr_fr      fr1,fr36
  52         test_spr_immed  0,fner1
  53         test_spr_immed  0,fner0
  54         nfsubs          fr40,fr16,fr1
  55         test_fr_fr      fr1,fr40
  56         test_spr_immed  0,fner1
  57         test_spr_immed  0,fner0
  58         nfsubs          fr44,fr16,fr1
  59         test_fr_fr      fr1,fr44
  60         test_spr_immed  0,fner1
  61         test_spr_immed  0,fner0
  62         nfsubs          fr48,fr16,fr1
  63         test_fr_fr      fr1,fr48
  64         test_spr_immed  0,fner1
  65         test_spr_immed  0,fner0
  66         nfsubs          fr52,fr16,fr1
  67         test_fr_fr      fr1,fr52
  68         test_spr_immed  0,fner1
  69         test_spr_immed  0,fner0
  70
  71         nfsubs          fr0,fr20,fr1
  72         test_fr_fr      fr1,fr0
  73         test_spr_immed  0,fner1
  74         test_spr_immed  0,fner0
  75         nfsubs          fr4,fr20,fr1
  76         test_fr_fr      fr1,fr4
  77         test_spr_immed  0,fner1
  78         test_spr_immed  0,fner0
  79         nfsubs          fr8,fr20,fr1
  80         test_fr_fr      fr1,fr8
  81         test_spr_immed  0,fner1
  82         test_spr_immed  0,fner0
  83         nfsubs          fr12,fr20,fr1
  84         test_fr_fr      fr1,fr12
  85         test_spr_immed  0,fner1
  86         test_spr_immed  0,fner0
  87         nfsubs          fr16,fr20,fr1
  88         test_fr_fr      fr1,fr16
  89         test_fr_fr      fr1,fr20
  90         test_spr_immed  0,fner1
  91         test_spr_immed  0,fner0
  92         nfsubs          fr20,fr20,fr1
  93         test_fr_fr      fr1,fr16
  94         test_fr_fr      fr1,fr20
  95         test_spr_immed  0,fner1
  96         test_spr_immed  0,fner0
  97         nfsubs          fr24,fr20,fr1
  98         test_fr_fr      fr1,fr24
  99         test_spr_immed  0,fner1
 100         test_spr_immed  0,fner0
 101         nfsubs          fr28,fr20,fr1
 102         test_fr_fr      fr1,fr28
 103         test_spr_immed  0,fner1
 104         test_spr_immed  0,fner0
 105         nfsubs          fr32,fr20,fr1
 106         test_fr_fr      fr1,fr32
 107         test_spr_immed  0,fner1
 108         test_spr_immed  0,fner0
 109         nfsubs          fr36,fr20,fr1
 110         test_fr_fr      fr1,fr36
 111         test_spr_immed  0,fner1
 112         test_spr_immed  0,fner0
 113         nfsubs          fr40,fr20,fr1
 114         test_fr_fr      fr1,fr40
 115         test_spr_immed  0,fner1
 116         test_spr_immed  0,fner0
 117         nfsubs          fr44,fr20,fr1
 118         test_fr_fr      fr1,fr44
 119         test_spr_immed  0,fner1
 120         test_spr_immed  0,fner0
 121         nfsubs          fr48,fr20,fr1
 122         test_fr_fr      fr1,fr48
 123         test_spr_immed  0,fner1
 124         test_spr_immed  0,fner0
 125         nfsubs          fr52,fr20,fr1
 126         test_fr_fr      fr1,fr52
 127         test_spr_immed  0,fner1
 128         test_spr_immed  0,fner0
 129
 130         nfsubs          fr32,fr36,fr1
 131         test_fr_fr      fr1,fr8
 132         test_spr_immed  0,fner1
 133         test_spr_immed  0,fner0
 134
 135         nfsubs          fr44,fr40,fr1
 136         test_fr_fr      fr1,fr36
 137         test_spr_immed  0,fner1
 138         test_spr_immed  0,fner0
 139
 140         ; try to cause exceptions
 141         nfsubs          fr4,fr28,fr1
 142 ;       test_fr_fr      fr1,fr44
 143         test_spr_immed  0,fner1
 144         test_spr_immed  0,fner0
 145
 146         nfsubs          fr0,fr28,fr1
 147 ;       test_fr_fr      fr1,fr44
 148         test_spr_immed  0,fner1
 149         test_spr_immed  0,fner0
 150
 151         nfsubs          fr56,fr28,fr1
 152 ;       test_fr_fr      fr1,fr44
 153         test_spr_immed  0,fner1
 154         test_spr_immed  0,fner0
 155
 156         nfsubs          fr60,fr28,fr1
 157 ;       test_fr_fr      fr1,fr44
 158         test_spr_immed  2,fner1
 159         test_spr_immed  0,fner0
 160
 161         pass
 162
 163