sim/testsuite/sim/sh/bld.s

   1 # sh testcase for bld
   2 # mach:  all
   3 # as(sh):       -defsym sim_cpu=0
   4 # as(shdsp):    -defsym sim_cpu=1 -dsp
   5
   6         .include "testutils.inc"
   7
   8         .align 2
   9 _x:     .long   0xa5a5a5a5
  10 _y:     .long   0x55555555
  11
  12         start
  13
  14 bld_b_imm_disp12_reg:
  15         set_grs_a5a5
  16         mov.l   x, r1
  17
  18         bld.b   #0, @(0, r1)
  19         bf8k    mfail
  20         bld.b   #1, @(0, r1)
  21         bt8k    mfail
  22         bld.b   #2, @(0, r1)
  23         bf8k    mfail
  24         bld.b   #3, @(0, r1)
  25         bt8k    mfail
  26
  27         bld.b   #4, @(0, r1)
  28         bt8k    mfail
  29         bld.b   #5, @(0, r1)
  30         bf8k    mfail
  31         bld.b   #6, @(0, r1)
  32         bt8k    mfail
  33         bld.b   #7, @(0, r1)
  34         bf8k    mfail
  35
  36         bld.b   #0, @(1, r1)
  37         bf8k    mfail
  38         bld.b   #1, @(1, r1)
  39         bt8k    mfail
  40         bld.b   #2, @(1, r1)
  41         bf8k    mfail
  42         bld.b   #3, @(1, r1)
  43         bt8k    mfail
  44
  45         bld.b   #4, @(1, r1)
  46         bt8k    mfail
  47         bld.b   #5, @(1, r1)
  48         bf8k    mfail
  49         bld.b   #6, @(1, r1)
  50         bt8k    mfail
  51         bld.b   #7, @(1, r1)
  52         bf8k    mfail
  53
  54         bld.b   #0, @(2, r1)
  55         bf8k    mfail
  56         bld.b   #1, @(2, r1)
  57         bt8k    mfail
  58         bld.b   #2, @(2, r1)
  59         bf8k    mfail
  60         bld.b   #3, @(2, r1)
  61         bt8k    mfail
  62
  63         bld.b   #4, @(2, r1)
  64         bt8k    mfail
  65         bld.b   #5, @(2, r1)
  66         bf8k    mfail
  67         bld.b   #6, @(2, r1)
  68         bt8k    mfail
  69         bld.b   #7, @(2, r1)
  70         bf8k    mfail
  71
  72         bld.b   #0, @(3, r1)
  73         bf8k    mfail
  74         bld.b   #1, @(3, r1)
  75         bt8k    mfail
  76         bld.b   #2, @(3, r1)
  77         bf8k    mfail
  78         bld.b   #3, @(3, r1)
  79         bt8k    mfail
  80
  81         bld.b   #4, @(3, r1)
  82         bt8k    mfail
  83         bld.b   #5, @(3, r1)
  84         bf8k    mfail
  85         bld.b   #6, @(3, r1)
  86         bt8k    mfail
  87         bld.b   #7, @(3, r1)
  88         bf8k    mfail
  89
  90         assertreg _x, r1
  91
  92 bld_imm_reg:
  93         set_greg 0xa5a5a5a5, r1
  94         bld     #0, r1
  95         bf8k    mfail
  96         bld     #1, r1
  97         bt8k    mfail
  98         bld     #2, r1
  99         bf8k    mfail
 100         bld     #3, r1
 101         bt8k    mfail
 102
 103         bld     #4, r1
 104         bt8k    mfail
 105         bld     #5, r1
 106         bf8k    mfail
 107         bld     #6, r1
 108         bt8k    mfail
 109         bld     #7, r1
 110         bf8k    mfail
 111
 112         test_grs_a5a5
 113
 114         pass
 115
 116         exit 0
 117
 118         .align 2
 119 x:      .long   _x
 120 y:      .long   _y
 121