4 #define error(x) { printf(x); exit( 999); }
6 void wrtest( unsigned *reg
, unsigned w
, unsigned e
)
14 printf( "wrtest: at 0x%08lx wrote=0x%08x read=0x%08x expected=0x%08x\n",
21 DMA tag in target format (LE).
22 BE=0x00000000_00000000_aaaaaaa0_ip00cccc
24 typedef struct { unsigned tagL
__attribute__ ((aligned (16))), tagH
, pke1
, pke0
; } quad
;
26 quad data0
= { 3, 2, 1, 0};
28 /* DMArefe 1, data0 */ quad dma_refe
= { 0x0c000001, 000, 0, 0};
29 /* DMAcnt 2 */ quad dma_cnt
= { 0x10000002, 0, 0, 0};
30 quad data1
= { 7, 6, 5, 4};
31 quad data2
= { 11, 10, 9, 8};
32 /* DMAnext 3,dma_ref */ quad dma_next
= { 0x20000003, 000, 0, 0};
33 quad data3
= { 15, 14, 13, 12};
34 quad data4
= { 19, 18, 17, 16};
35 quad data5
= { 23, 22, 21, 20};
37 quad data6
= { 27, 26, 25, 24};
38 quad data7
= { 31, 30, 29, 28};
39 quad data8
= { 35, 34, 33, 32};
40 /* DMAref 1,data6 */ quad dma_ref
= { 0x30000001, 000, 0, 0};
41 /* DMArefs 2,data7 */ quad dma_refs
= { 0x40000002, 000, 0, 0};
42 /* DMAcall 3,dma_cal2 */quad dma_call
= { 0x50000003, 000, 0, 0};
43 quad data9
= { 39, 38, 37, 36};
44 quad dataA
= { 43, 42, 41, 40};
45 quad dataB
= { 47, 46, 45, 44};
46 /* DMAend 1 */ quad dma_end
= { 0x78000001, 0, 0, 0};
47 quad dataE
= { 59, 58, 57, 56};
49 /* DMAcall 1,dma_rt2 */ quad dma_cal2
= { 0x50000001, 000, 0, 0 };
50 quad dataC
= { 51, 50, 49, 48};
51 /* DMAret 0 */ quad dma_ret
= { 0x60000000, 0, 0, 0};
53 /* DMAret 1 */ quad dma_rt2
= { 0x60000001, 0, 0, 0};
54 quad dataD
= { 55, 54, 53, 52};
59 #define DMA_D0_START 0x10008000
60 #define DMA_D0_CHCR (unsigned*) 0x10008000
61 #define DMA_Dn_CHCR__STR 0x00000100
62 #define DMA_Dn_CHCR__TIE 0x00000080
63 #define DMA_Dn_CHCR__TTE 0x00000040
64 #define DMA_Dn_CHCR__MOD 0x0000000c
65 #define DMA_Dn_CHCR__MOD_NORM 0x00000000
66 #define DMA_Dn_CHCR__MOD_CHAIN 0x00000004
67 #define DMA_Dn_CHCR__DIR 0x00000001
68 #define DMA_D0_MADR (unsigned*) 0x10008010
69 #define DMA_D0_QWC (unsigned*) 0x10008020
70 #define DMA_D0_TADR (unsigned*) 0x10008030
71 #define DMA_D0_ASR0 (unsigned*) 0x10008040
72 #define DMA_D0_ASR1 (unsigned*) 0x10008050
73 #define DMA_D0_PKTFLAG (unsigned*) 0x10008060 /* virtual reg to indicate presence of tag in data */
74 #define DMA_D0_END 0x10008070
76 #define DMA_D1_START 0x10009000
77 #define DMA_D1_CHCR (unsigned*) 0x10009000
78 #define DMA_D1_MADR (unsigned*) 0x10009010
79 #define DMA_D1_QWC (unsigned*) 0x10009020
80 #define DMA_D1_TADR (unsigned*) 0x10009030
81 #define DMA_D1_ASR0 (unsigned*) 0x10009040
82 #define DMA_D1_ASR1 (unsigned*) 0x10009050
83 #define DMA_D1_PKTFLAG (unsigned*) 0x10009060 /* virtual reg to indicate presence of tag in data */
84 #define DMA_D1_END 0x10009070
86 #define DMA_D2_START 0x1000a000
87 #define DMA_D2_CHCR (unsigned*) 0x1000a000
88 #define DMA_D2_MADR (unsigned*) 0x1000a010
89 #define DMA_D2_QWC (unsigned*) 0x1000a020
90 #define DMA_D2_TADR (unsigned*) 0x1000a030
91 #define DMA_D2_ASR0 (unsigned*) 0x1000a040
92 #define DMA_D2_ASR1 (unsigned*) 0x1000a050
93 #define DMA_D2_PKTFLAG (unsigned*) 0x1000a060 /* virtual reg to indicate presence of tag in data */
94 #define DMA_D2_END 0x1000a070
96 #define DMA_D_CTRL (unsigned*) 0x1000e000
97 #define DMA_D_CTRL__DMAE 0x00000001
98 #define DMA_D_STAT (unsigned*) 0x1000e010
99 #define DMA_D_STAT__TOGGLE 0x63ff0000
100 #define DMA_D_STAT__CLEAR 0x0000e3ff
101 #define DMA_D_PCR (unsigned*) 0x1000e020
102 #define DMA_D_PCR__PCE 0x80000000
103 #define DMA_D_PCR__CDE 0x03ff0000
104 #define DMA_D_PCR__CDE0 0x00010000
105 #define DMA_D_PCR__CDE1 0x00020000
106 #define DMA_D_PCR__CDE2 0x00040000
107 #define DMA_D_SQWC (unsigned*) 0x1000e030
108 #define DMA_D_RBSR (unsigned*) 0x1000e040
109 #define DMA_D_RBOR (unsigned*) 0x1000e050
110 #define DMA_D_STADR (unsigned*) 0x1000e060
112 #define DMA_TAG_IRQ 0x80000000;
117 printf( "Testing DMA_D_CTRL...\n");
119 if( *reg
) error( "Not initialized to zero.\n");
120 wrtest( reg
, 0x00000555, 0x00000555);
121 wrtest( reg
, 0x000002aa, 0x000002aa);
124 printf( "Testing DMA_D_STAT...\n");
126 if( *reg
) error( "Not initialized to zero.\n");
127 wrtest( reg
, 0xffffffff, 0x63ff0000);
128 wrtest( reg
, 0x63ff0000, 0x00000000);
130 printf( "Testing DMA_D_PCR...\n");
132 if( *reg
) error( "Not initialized to zero.\n");
133 wrtest( reg
, 0x80000000, 0x83ff0000);
134 wrtest( reg
, 0x8fff0000, 0x83ff0000);
135 wrtest( reg
, 0x05550000, 0x01550000);
136 wrtest( reg
, 0x0155aaaa, 0x015502aa);
137 wrtest( reg
, 0x00005555, 0x00000155);
140 printf( "Testing DMA_D_SQWC...\n");
142 if( *reg
) error( "Not initialized to zero.\n");
143 wrtest( reg
, 0x5555aaaa, 0x005500aa);
144 wrtest( reg
, 0xaaaa5555, 0x00aa0055);
147 printf( "Testing DMA_D_RBOR...\n");
149 if( *reg
) error( "Not initialized to zero.\n");
150 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
151 wrtest( reg
, 0xaaaa5555, 0x2aaa5550);
154 printf( "Testing DMA_D_RBSR...\n");
156 if( *reg
) error( "Not initialized to zero.\n");
157 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
158 wrtest( reg
, 0xaaaa5555, 0x2aaa5550);
161 printf( "Testing DMA_D_STADR...\n");
163 if( *reg
) error( "Not initialized to zero.\n");
164 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
165 wrtest( reg
, 0xaaaa5555, 0x2aaa5550);
168 printf( "Testing DMA_D0_CHCR...\n");
170 if( *reg
) error( "Not initialized to zero.\n");
171 wrtest( reg
, 0x5555aaaa, 0x000000aa);
172 wrtest( reg
, 0xaaaa5555, 0x00000155);
175 printf( "Testing DMA_D0_MADR...\n");
177 if( *reg
) error( "Not initialized to zero.\n");
178 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
179 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
182 printf( "Testing DMA_D0_TADR...\n");
184 if( *reg
) error( "Not initialized to zero.\n");
185 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
186 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
189 printf( "Testing DMA_D0_ASR0...\n");
191 if( *reg
) error( "Not initialized to zero.\n");
192 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
193 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
196 printf( "Testing DMA_D0_ASR1...\n");
198 if( *reg
) error( "Not initialized to zero.\n");
199 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
200 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
203 printf( "Testing DMA_D0_QWC...\n");
205 if( *reg
) error( "Not initialized to zero.\n");
206 wrtest( reg
, 0x5555aaaa, 0x0000aaaa);
207 wrtest( reg
, 0xaaaa5555, 0x00005555);
210 printf( "Testing DMA_D0_PKTFLAG...\n");
211 reg
= DMA_D0_PKTFLAG
;
212 if( *reg
) error( "Not initialized to zero.\n");
213 wrtest( reg
, 0x5555aaaa, 0x5555aaaa);
214 wrtest( reg
, 0xaaaa5555, 0xaaaa5555);
217 printf( "Testing DMA_D1_CHCR...\n");
219 if( *reg
) error( "Not initialized to zero.\n");
220 wrtest( reg
, 0x5555aaaa, 0x000000aa);
221 wrtest( reg
, 0xaaaa5555, 0x00000155);
224 printf( "Testing DMA_D1_MADR...\n");
226 if( *reg
) error( "Not initialized to zero.\n");
227 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
228 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
231 printf( "Testing DMA_D1_TADR...\n");
233 if( *reg
) error( "Not initialized to zero.\n");
234 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
235 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
238 printf( "Testing DMA_D1_ASR0...\n");
240 if( *reg
) error( "Not initialized to zero.\n");
241 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
242 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
245 printf( "Testing DMA_D1_ASR1...\n");
247 if( *reg
) error( "Not initialized to zero.\n");
248 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
249 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
252 printf( "Testing DMA_D1_QWC...\n");
254 if( *reg
) error( "Not initialized to zero.\n");
255 wrtest( reg
, 0x5555aaaa, 0x0000aaaa);
256 wrtest( reg
, 0xaaaa5555, 0x00005555);
259 printf( "Testing DMA_D1_PKTFLAG...\n");
260 reg
= DMA_D1_PKTFLAG
;
261 if( *reg
) error( "Not initialized to zero.\n");
262 wrtest( reg
, 0x5555aaaa, 0x5555aaaa);
263 wrtest( reg
, 0xaaaa5555, 0xaaaa5555);
266 printf( "Testing DMA_D2_CHCR...\n");
268 if( *reg
) error( "Not initialized to zero.\n");
269 wrtest( reg
, 0x5555aaaa, 0x000000aa);
270 wrtest( reg
, 0xaaaa5555, 0x00000155);
273 printf( "Testing DMA_D2_MADR...\n");
275 if( *reg
) error( "Not initialized to zero.\n");
276 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
277 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
280 printf( "Testing DMA_D2_TADR...\n");
282 if( *reg
) error( "Not initialized to zero.\n");
283 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
284 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
287 printf( "Testing DMA_D2_ASR0...\n");
289 if( *reg
) error( "Not initialized to zero.\n");
290 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
291 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
294 printf( "Testing DMA_D2_ASR1...\n");
296 if( *reg
) error( "Not initialized to zero.\n");
297 wrtest( reg
, 0x5555aaaa, 0x5555aaa0);
298 wrtest( reg
, 0x2aaa5555, 0x2aaa5550);
301 printf( "Testing DMA_D2_QWC...\n");
305 printf ("Not initialized to zero (0x%08x).\n", *reg
);
308 wrtest( reg
, 0x5555aaaa, 0x0000aaaa);
309 wrtest( reg
, 0xaaaa5555, 0x00005555);
312 printf( "Testing DMA_D2_PKTFLAG...\n");
313 reg
= DMA_D2_PKTFLAG
;
314 if( *reg
) error( "Not initialized to zero.\n");
315 wrtest( reg
, 0x5555aaaa, 0x5555aaaa);
316 wrtest( reg
, 0xaaaa5555, 0xaaaa5555);
319 /* Initiate a non-chained 0-length transfer. */
320 printf ("\nPreparing for a DMA1 NORM transfer...\n");
321 reg
= DMA_D_CTRL
; /* enable DMA */
322 *reg
= DMA_D_CTRL__DMAE
;
323 reg
= DMA_D1_QWC
; /* set # of quad words to xfr */
325 reg
= DMA_D1_MADR
; /* set data address */
328 printf ("Ready...\n");
329 *reg
= DMA_Dn_CHCR__STR
| DMA_Dn_CHCR__MOD_NORM
;
334 printf ("D1_QWC is not zero after transfer.\n");
338 if (*reg
!= 0x00012340)
340 printf ("D1_MADR value is wrong after transfer.\n");
344 if ((*reg
& DMA_Dn_CHCR__STR
) != 0)
346 printf ("D1_CHCR.STR is not reset after transfer.\n");
349 printf ("Completed OK...\n");
351 /* Initiate a chained transfer. */
353 /* Some of the "tag" fields couldn't be initialised statically. */
354 /* The first address is unaligned to force a warning. */
355 dma_refe
.tagH
= (unsigned)&data0
+ 1;
356 dma_next
.tagH
= (unsigned)&dma_ref
;
357 dma_ref
.tagH
= (unsigned)&data6
;
358 dma_refs
.tagH
= (unsigned)&data7
;
359 dma_call
.tagH
= (unsigned)&dma_cal2
;
360 dma_cal2
.tagH
= (unsigned)&dma_rt2
;
362 printf ("\nPreparing for a DMA0 TAG transfer...\n");
363 reg
= DMA_D_PCR
; /* disable DMA0 */
364 *reg
&= ~DMA_D_PCR__CDE0
;
365 *reg
|= DMA_D_PCR__PCE
;
366 reg
= DMA_D_CTRL
; /* enable DMA */
367 *reg
= DMA_D_CTRL__DMAE
;
368 reg
= DMA_D0_TADR
; /* set tag address */
369 *reg
= (unsigned) & dma_refe
;
370 reg
= DMA_D0_QWC
; /* set fictitious count */
372 printf ("Ready...\n");
374 *reg
= DMA_Dn_CHCR__STR
| DMA_Dn_CHCR__TTE
| DMA_Dn_CHCR__MOD_CHAIN
;
379 printf ("DMA0 transfer not inhibited by DMA_D_PCR__CDE0 (%d).\n", *reg
);
382 reg
= DMA_D_PCR
; /* enable DMA0 */
383 *reg
&= ~DMA_D_PCR__PCE
;
388 printf ("D0_QWC is not zero after transfer.\n");
392 if (*reg
!= (unsigned)&dma_cal2
)
394 printf ("D0_MADR value is wrong after transfer.\n");
398 if ((*reg
& DMA_Dn_CHCR__STR
) != 0)
400 printf ("D0_CHCR.STR is not reset after transfer.\n");
403 printf ("Completed OK...\n");
405 /* Initiate a chained transfer that will be suspended
408 /* Request suspension part way through. */
409 dma_ref
.tagL
|= DMA_TAG_IRQ
;
411 printf ("\nPreparing for a DMA2 TAG transfer with suspension...\n");
412 reg
= DMA_D_CTRL
; /* enable DMA */
413 *reg
= DMA_D_CTRL__DMAE
;
414 reg
= DMA_D2_TADR
; /* set tag address */
415 *reg
= (unsigned) & dma_refe
;
416 printf ("Ready...\n");
418 *reg
= DMA_Dn_CHCR__STR
| DMA_Dn_CHCR__MOD_CHAIN
;
419 printf ("returns...\n");
424 printf ("D2_QWC (0x%08x) is not zero after suspension.\n", *reg
);
428 if (*reg
!= (unsigned)&data7
)
430 printf ("D2_MADR value (0x%08x) is wrong after suspension.\n", *reg
);
434 if (*reg
!= (unsigned)&dma_refs
)
436 printf ("D2_TADR value (0x%08x) is wrong after suspension.\n", *reg
);
440 if ((*reg
& DMA_Dn_CHCR__STR
) != 0)
442 printf ("D2_CHCR.STR (0x%08x) is not reset after suspension.\n", *reg
);
446 if ((*reg
& DMA_D_PCR__PCE
) == 0)
448 printf ("DMA_D_PCR__PCE not set by transfer.\n");
451 printf ("Suspended OK...\n");
453 /* Reset the suspension request and continue. */
454 dma_ref
.tagL
&= ~DMA_TAG_IRQ
;
456 *reg
|= DMA_Dn_CHCR__STR
;
461 printf ("D2_QWC (0x%08x) is not zero after transfer.\n", *reg
);
465 if (*reg
!= (unsigned)&dma_cal2
)
467 printf ("D2_MADR value (0x%08x) is wrong after transfer.\n", *reg
);
471 if ((*reg
& DMA_Dn_CHCR__STR
) != 0)
473 printf ("D2_CHCR.STR (0x%08x) is not reset after transfer.\n", *reg
);
477 if (*reg
& DMA_D_PCR__PCE
)
479 printf ("DMA_D_PCR__PCE not reset by transfer.\n");
482 printf ("Completed OK...\n");
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