sim/testsuite/sky/t-pke3.trc

   1 # PKE tests for code coverage
   2 #
   3 #
   4 #
   5 # ---- STCYCL/CYCLE ----
   6 #
   7 # Test STCYCL instruction
   8 0 0x0100fedc_00000000_00000000_00000000 0x00000000 PPPP
   9 # Attempt erroneous write to CYCLE register
  10 ! 0x10003840 0x0000dead
  11 # Read CYCLE register; confirm proper value
  12 ? 0x10003840 0x0000fedc 0xffffffff
  13 # Read STAT register; confirm ER1 not set
  14 ? 0x10003800 0x00000000 0x00002000
  15 #
  16 #
  17 # ---- OFFSET/OFST ----
  18 #
  19 # Test OFFSET instruction on PKE1
  20 1 0x0200ffff_00000000_00000000_00000000 0x00000000 PPPP
  21 # Attempt erroneous write to OFFSET register
  22 ! 0x10003cb0 0x0000dead
  23 # Read OFST register; confirm proper 10-bit value
  24 ? 0x10003cb0 0x000003ff 0xffffffff
  25 # Read STAT register; confirm DBF=0
  26 ? 0x10003c00 0x00000000 0x00000080
  27 # Read DBF register; confirm DBF=0
  28 ? 0x10003cf0 0x00000000 0x00000001
  29 # Read STAT register; confirm ER1 not set
  30 ? 0x10003c00 0x00000000 0x00002000
  31 #
  32 #
  33 # ---- BASE/BASE ----
  34 #
  35 # Test BASE instruction on PKE1
  36 1 0x0300ffff_00000000_00000000_00000000 0x00000000 PPPP
  37 # Attempt erroneous write to BASE register
  38 ! 0x10003ca0 0x0000dead
  39 # Read BASE register; confirm proper 10-bit value
  40 ? 0x10003ca0 0x000003ff 0xffffffff
  41 # Read STAT register; confirm DBF=0
  42 ? 0x10003c00 0x00000000 0x00000080
  43 # Read DBF register; confirm DBF=0
  44 ? 0x10003cf0 0x00000000 0x00000001
  45 #
  46 #
  47 # ---- ITOP/ITOPS ----
  48 #
  49 # Test ITOP instruction
  50 0 0x0400ffff_00000000_00000000_00000000 0x00000000 PPPP
  51 # Attempt erroneous write to ITOPS register
  52 ! 0x10003890 0x0000dead
  53 # Read ITOPS register; confirm proper 10-bit value
  54 ? 0x10003890 0x000003ff 0xffffffff
  55 # Read STAT register; confirm ER1 not set
  56 ? 0x10003800 0x00000000 0x00002000
  57 #
  58 #
  59 # ---- STMOD/MODE ----
  60 #
  61 # Test STMOD instruction
  62 0 0x05000003_00000000_00000000_00000000 0x00000000 PPPP
  63 # Attempt erroneous write to MODE register
  64 ! 0x10003850 0x0000dead
  65 # Read MODE register; confirm proper value
  66 ? 0x10003850 0x00000003 0xffffffff
  67 # Test STMOD instruction with junk upper bits
  68 0 0x0500dad1_00000000_00000000_00000000 0x00000000 PPPP
  69 # Read MODE register; confirm proper value
  70 ? 0x10003850 0x00000001 0xffffffff
  71 # Read STAT register; confirm ER1 not set
  72 ? 0x10003800 0x00000000 0x00002000
  73 #
  74 #
  75 # ---- STMARK/MARK ----
  76 #
  77 # Test MARK instruction
  78 0 0x0700abcd_00000000_00000000_00000000 0x00000000 PPPP
  79 # Read STAT register; confirm MRK bit set
  80 ? 0x10003800 0x00000040 0x00000040
  81 # Read MARK register
  82 ? 0x10003830 0x0000abcd 0xffffffff
  83 # Write MARK register
  84 ! 0x10003830 0x00001234
  85 # Read STAT register; confirm MRK bit clear
  86 ? 0x10003800 0x00000000 0x00000040
  87 # Read MARK register
  88 ? 0x10003830 0x00001234 0xffffffff
  89 #
  90 #
  91 # ---- ERROR/ER1 ----
  92 #
  93 # A bad PKEcode
  94 1 0x00000000_00000000_00000000_08000000 0x00000000 PPPP
  95 # should put PKE into stalled mode, not executing following PKENOPs
  96 # Read STAT register; confirm ER1 bit set
  97 ? 0x10003c00 0x00002000 0x00002000
  98 # Read CODE register; confirm PKE is stuck at bad code
  99 ? 0x10003c80 0x08000000 0xffffffff
 100 # Reset PKE
 101 ! 0x10003c10 0x00000001
 102 # Read STAT register; confirm ER1 no longer set
 103 ? 0x10003c00 0x00000000 0x00002000
 104 #
 105 #
 106 # ---- STMASK/MASK ----
 107 #
 108 # Test STMASK instruction; leave operand out for now
 109 0 0x20000000_00000000_00000000_00000000 0x00000000 PPPP
 110 # Read STAT register; confirm PPS field set at WAIT
 111 ? 0x10003800 0x00000001 0x00000003
 112 # Add operand for STMASK instruction
 113 0 0x00000000_00000000_00000000_1234abcd 0x00000000 PPPP
 114 # Erroneous write to MASK register
 115 ! 0x10003870 0x98765432
 116 # Read MASK register
 117 ? 0x10003870 0x1234abcd 0xffffffff
 118 # Read STAT register; confirm ER1 not set
 119 ? 0x10003800 0x00000000 0x00002000
 120 #
 121 #
 122 # ---- DIRECT ----
 123 #
 124 # Test DIRECT instruction; leave operand out for now
 125 1 0x50000001_00000000_00000000_00000000 0x00000000 PPPP
 126 # Read STAT register; confirm PPS field set at WAIT
 127 ? 0x10003c00 0x00000001 0x00000003
 128 # Supply operand - it's a bad GPUIF tag
 129 1 0x00000000_00000000_00000000_00000000 0x00000000 ....
 130 # Test DIRECT instruction with bad operand alignment
 131 1 0x00000000_50000001_00000000_00000000 0x00000000 PPPP
 132 # Read STAT register; confirm ER1 bit set
 133 ? 0x10003c00 0x00002000 0x00002000
 134 # Reset PKE
 135 ! 0x10003c10 0x00000001
 136 # Read STAT register; confirm ER1 no longer set
 137 ? 0x10003c00 0x00000000 0x00002000
 138 # Test DIRECT instruction with bad operand alignment
 139 1 0x00000000_00000000_50000001_00000000 0x00000000 PPPP
 140 # Read STAT register; confirm ER1 bit set
 141 ? 0x10003c00 0x00002000 0x00002000
 142 # Reset PKE
 143 ! 0x10003c10 0x00000001
 144 # Read STAT register; confirm ER1 no longer set
 145 ? 0x10003c00 0x00000000 0x00002000
 146 # Test DIRECT instruction with bad operand alignment
 147 1 0x00000000_00000000_00000000_50000001 0x00000000 PPPP
 148 # Read STAT register; confirm ER1 bit set
 149 ? 0x10003c00 0x00002000 0x00002000
 150 # Reset PKE
 151 ! 0x10003c10 0x00000001
 152 # Read STAT register; confirm ER1 no longer set
 153 ? 0x10003c00 0x00000000 0x00002000
 154 #
 155 #
 156 # ---- MPG - PKE0 ----
 157 #
 158 # Test MPG instruction; leave operand out for now
 159 0 0x4a080000_00000000_00000000_00000000 0x00000000 PPPP
 160 # Read STAT register; confirm PPS field set at WAIT
 161 ? 0x10003800 0x00000001 0x00000003
 162 # Supply operands - eight two junk VU instruction word-pairs with real source-addr's
 163 0 0xdeadbeef_0bad0bad_beef0bad_2bad2bad 0x00000010 ....
 164 0 0xabcdbeef_44332211_12987423_95555999 0x00000100 ....
 165 0 0xdeadabcd_75577588_beef0bad_89abcdef 0x00001000 ....
 166 0 0xa5a5a5a5_5aaa5533_01234567_77889900 0x00010000 ....
 167 # Check that instructions were loaded properly
 168 ? 0x11000000 0x2bad2bad 0xffffffff
 169 ? 0x11000004 0xbeef0bad 0xffffffff
 170 ? 0x11000014 0x12987423 0xffffffff
 171 ? 0x11000028 0x75577588 0xffffffff
 172 ? 0x1100003c 0xa5a5a5a5 0xffffffff
 173 # Check that source addresses were loaded properly
 174 ? 0x21000000 0x00000010 0xffffffff
 175 ? 0x21000004 0x00000010 0xffffffff
 176 ? 0x21000008 0x00000100 0xffffffff
 177 ? 0x2100000c 0x00000100 0xffffffff
 178 ? 0x21000010 0x00001000 0xffffffff
 179 ? 0x21000014 0x00001000 0xffffffff
 180 ? 0x21000018 0x00010000 0xffffffff
 181 ? 0x2100001c 0x00010000 0xffffffff
 182 # Test MPG instruction with bad operand alignment
 183 0 0x00000000_4a020000_00000000_00000000 0x00000000 PPPP
 184 # Read STAT register; confirm ER1 bit set
 185 ? 0x10003800 0x00002000 0x00002000
 186 # Reset PKE
 187 ! 0x10003810 0x00000001
 188 # Read STAT register; confirm ER1 no longer set
 189 ? 0x10003800 0x00000000 0x00002000
 190 # Test MPG instruction with good operand alignment
 191 0 0x00000000_00000000_4a010000_00000000 0x00000000 ..PP
 192 # Read STAT register; confirm ER1 bit not set
 193 ? 0x10003800 0x00000000 0x00002000
 194 # Test MPG instruction with bad operand alignment
 195 0 0x00000000_00000000_00000000_4a010000 0x00000000 PPPP
 196 # Read STAT register; confirm ER1 bit set
 197 ? 0x10003800 0x00002000 0x00002000
 198 # Reset PKE
 199 ! 0x10003810 0x00000001
 200 # Read STAT register; confirm ER1 no longer set
 201 ? 0x10003800 0x00000000 0x00002000
 202 #
 203 #
 204 # ---- MPG - PKE1 ----
 205 #
 206 # Test MPG instruction; leave operand out for now
 207 1 0x4a080000_00000000_00000000_00000000 0x00000000 PPPP
 208 # Read STAT register; confirm PPS field set at WAIT
 209 ? 0x10003c00 0x00000001 0x00000003
 210 # Supply operands - eight two junk VU instruction word-pairs with real source-addr's
 211 1 0xdeadbeef_0bad0bad_beef0bad_2bad2bad 0x00000010 ....
 212 1 0xabcdbeef_44332211_12987423_95555999 0x00000100 ....
 213 1 0xdeadabcd_75577588_beef0bad_89abcdef 0x00001000 ....
 214 1 0xa5a5a5a5_5aaa5533_01234567_77889900 0x00010000 ....
 215 # Check that instructions were loaded properly
 216 ? 0x11008000 0x2bad2bad 0xffffffff
 217 ? 0x11008004 0xbeef0bad 0xffffffff
 218 ? 0x11008014 0x12987423 0xffffffff
 219 ? 0x11008028 0x75577588 0xffffffff
 220 ? 0x1100803c 0xa5a5a5a5 0xffffffff
 221 # Check that source addresses were loaded properly
 222 ? 0x21008000 0x00000010 0xffffffff
 223 ? 0x21008004 0x00000010 0xffffffff
 224 ? 0x21008008 0x00000100 0xffffffff
 225 ? 0x2100800c 0x00000100 0xffffffff
 226 ? 0x21008010 0x00001000 0xffffffff
 227 ? 0x21008014 0x00001000 0xffffffff
 228 ? 0x21008018 0x00010000 0xffffffff
 229 ? 0x2100801c 0x00010000 0xffffffff
 230 # Test MPG instruction with bad operand alignment
 231 1 0x00000000_4a020000_00000000_00000000 0x00000000 PPPP
 232 # Read STAT register; confirm ER1 bit set
 233 ? 0x10003c00 0x00002000 0x00002000
 234 # Reset PKE
 235 ! 0x10003c10 0x00000001
 236 # Read STAT register; confirm ER1 no longer set
 237 ? 0x10003c00 0x00000000 0x00002000
 238 # Test MPG instruction with good operand alignment
 239 1 0x00000000_00000000_4a010000_00000000 0x00000000 ..PP
 240 # Read STAT register; confirm ER1 bit not set
 241 ? 0x10003c00 0x00000000 0x00002000
 242 # Test MPG instruction with bad operand alignment
 243 1 0x00000000_00000000_00000000_4a010000 0x00000000 PPPP
 244 # Read STAT register; confirm ER1 bit set
 245 ? 0x10003c00 0x00002000 0x00002000
 246 # Reset PKE
 247 ! 0x10003c10 0x00000001
 248 # Read STAT register; confirm ER1 no longer set
 249 ? 0x10003c00 0x00000000 0x00002000
 250 #
 251 #
 252 # ---- STROW/ROW + DMA mismatch ----
 253 #
 254 # Test STROW instruction; leave operand out for now
 255 0 0x30000000_00000000_00000000_00000000 0x00000000 PPPP
 256 # Read STAT register; confirm PPS field set at WAIT
 257 ? 0x10003800 0x00000001 0x00000003
 258 # Write ERR register; mask ER0 stalling
 259 ! 0x10003820 0x00000002
 260 # Supply operand - four words
 261 0 0x1234abcd_2345bcde_ffffffff_ffffffff 0x00000000 ..DD
 262 0 0x00000000_00000000_5432dcba_76543210 0x00000000 PP..
 263 # Read STAT register; confirm ER0 (DMA mismatch)
 264 ? 0x10003800 0x00001000 0x00001000
 265 # Make erroneous write
 266 ! 0x10003900 0x11111111
 267 ! 0x10003910 0x22222222
 268 ! 0x10003920 0x33333333
 269 ! 0x10003930 0x44444444
 270 # Check row registers for value
 271 ? 0x10003900 0x2345bcde 0xffffffff
 272 ? 0x10003910 0x1234abcd 0xffffffff
 273 ? 0x10003920 0x76543210 0xffffffff
 274 ? 0x10003930 0x5432dcba 0xffffffff
 275 # Read STAT register; confirm ER1 not set
 276 ? 0x10003800 0x00000000 0x00002000
 277 # Reset PKE
 278 ! 0x10003810 0x00000001
 279 #
 280 #
 281 # ---- STCOL/COL + STOP/CONTINUE ----
 282 #
 283 # Test STCOL instruction; leave operand out for now
 284 0 0x31000000_00000000_00000000_00000000 0x00000000 PPPP
 285 # Read STAT register; confirm PPS field set at WAIT
 286 ? 0x10003800 0x00000001 0x00000003
 287 # Stop PKE with FBK bit
 288 ! 0x10003810 0x00000002
 289 # Supply operand - four words
 290 0 0x1234abcd_2345bcde_5432dcba_76543210 0x00000000 ....
 291 # Confirm that PKE is continuing to stall due to FBK
 292 ? 0x10003800 0x00000200 0x00000200
 293 ? 0x10003800 0x00000200 0x00000200
 294 ? 0x10003800 0x00000200 0x00000200
 295 # Resume PKE with STC bit
 296 ! 0x10003810 0x00000008
 297 # Read STAT register; confirm FBK no longer set
 298 ? 0x10003800 0x00000000 0x00000200
 299 # Check column registers for value
 300 ? 0x10003940 0x76543210 0xffffffff
 301 ? 0x10003950 0x5432dcba 0xffffffff
 302 ? 0x10003960 0x2345bcde 0xffffffff
 303 ? 0x10003970 0x1234abcd 0xffffffff
 304 # Read STAT register; confirm ER1 not set
 305 ? 0x10003800 0x00000000 0x00002000
 306 #
 307 #
 308 # ---- MSKPATH3 ----
 309 #
 310 # Set then clear MSKPATH3 on PKE1
 311 1 0x06008000_00000000_06000000_00000000 0x00000000 PPPP
 312 # Read STAT register; confirm ER1 not set
 313 ? 0x10003c00 0x00000000 0x00002000
 314 # Erroneously run this on PKE0
 315 0 0x06008000_00000000_06000000_00000000 0x00000000 PPPP
 316 # Read STAT register; confirm ER1 set
 317 ? 0x10003800 0x00002000 0x00002000
 318 # Reset PKE0
 319 ! 0x10003810 0x00000001
 320 #
 321 #
 322 # ---- memory-mapped port reading ----
 323 #
 324 # Erroneously read words from FIFO ports
 325 ? 0x10004000 0x00000000 0xffffffff
 326 ? 0x10004004 0x00000000 0xffffffff
 327 ? 0x10004008 0x00000000 0xffffffff
 328 ? 0x1000400c 0x00000000 0xffffffff
 329 ? 0x10005000 0x00000000 0xffffffff
 330 ? 0x10005004 0x00000000 0xffffffff
 331 ? 0x10005008 0x00000000 0xffffffff
 332 ? 0x1000500c 0x00000000 0xffffffff
 333 #