Extend xor-endian and per-cpu support in core module.
[deliverable/binutils-gdb.git] / sim / tic80 / ChangeLog
1 Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
4 (sim_write): Ditto for write.
5
6 Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
7
8 * sim-calls.c (sim_load): Set STATE_LOADED_P.
9
10 * sim-main.h: Include <unistd.h>.
11
12 * sim-calls.c (sim_set_callback): Delete.
13 (sim_open): Add/install callback argument.
14 (sim_size): Delete.
15
16 Mon May 19 18:59:33 1997 Mike Meissner <meissner@cygnus.com>
17
18 * configure.in: Check for getpid, kill functions.
19 * config{.in,ure}: Regenerate.
20
21 * insns (do_trap): Add support for kill, getpid system calls.
22
23 * sim-main.h (errno.h): Include.
24 (getpid,kill): Define as NOPs if the host doesn't have them.
25
26 Mon May 19 14:58:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
27
28 * sim-calls.c (sim_open): Set the simulator base magic number.
29 (sim_load): Delete prototype of sim_load_file.
30 (sim_open): Define sd to be &simulation.
31
32 Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
33
34 * insns (illegal, fp_unavailable): Halt instead of abort the
35 simulator.
36
37 * insns: Replace calls to engine_error with sim_engine_abort.
38 Ditto for engine_halt V sim_engine_halt.
39
40 Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
41
42 * interp.c (engine_run_until_stop): Delete. Moved to common.
43 (engine_step): Ditto.
44 (engine_step): Ditto.
45 (engine_halt): Ditto.
46 (engine_restart): Ditto.
47 (engine_halt): Ditto.
48 (engine_error): Ditto.
49
50 * sim-calls.c (sim_stop): Delete. Moved to common.
51 (sim_stop_reason): Ditto.
52 (sim_resume): Ditto.
53
54 * Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
55 sim-resume, sim-reason, sim-stop modules.
56
57 Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
58
59 * ic (compute): Drop check for REG == 0, now always forced to
60 zero.
61
62 * cpu.h (GPR_SET): New macro update the gpr.
63 * insns (do_add): Use GPR_SET to update the GPR register.
64
65 * sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
66
67 * Makefile.in (tmp-igen): Specify zero-r0 so that every
68 instruction clears r0.
69
70 * interp.c (engine_run_until_stop): Igen now generates code to
71 clear r0.
72 (engine_step): Ditto.
73
74 Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
75
76 * insns (do_shift): When rot==0 and zero/sign merge treat it as
77 32.
78 (set_fp_reg): For interger conversion, use sim-fpu fpu2i
79 functions.
80 (do_fmpy): Perform iii and uuu using integer arithmetic.
81
82 * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
83
84 * insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
85 conversion.
86 (do_fcmp): Update to use new fp compare functions. Make reg nr arg
87 instead of reg. Stops fp overflow.
88 (get_fp_reg): Assume val is valid when reg == 0.
89 (set_fp_reg): Fix double conversion.
90
91 * misc.c (tic80_trace_fpu1): New function, trace simple fp op.
92
93 * insns (do_frnd): Add tracing.
94
95 * cpu.h (TRACE_FPU1): Ditto.
96
97 * insns (do_trap): Printf formatting.
98
99 Wed May 14 18:05:50 1997 Mike Meissner <meissner@cygnus.com>
100
101 * misc.c (tic80_trace_fpu{3,2,2i}): Align columns with other
102 insns. Use %g to print floating point instead of %f in case the
103 numbers are real large.
104
105 Tue May 13 18:00:10 1997 Mike Meissner <meissner@cygnus.com>
106
107 * insns (do_trap): For system calls that are defined, but not
108 provided return EINVAL. Temporarily add traps 74-79 to just print
109 the register state.
110
111 * interp.c (engine_{run_until_stop,step}): Before executing
112 instructions, make sure r0 == 0.
113
114 Tue May 13 16:39:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
115
116 * alu.h (IMEM): Take full cia not just IP as argument.
117
118 * interp.c (engine_run_until_stop): Delete handling of annuled
119 instructions.
120 (engine_step): Ditto.
121
122 * insn (do_branch): New function.
123 (do_bbo, do_bbz, do_bcnd, do_bsr, do_jsr): Use do_branch to handle
124 annuled branches.
125
126 Mon May 12 17:15:52 1997 Mike Meissner <meissner@cygnus.com>
127
128 * insns (do_{ld,st}): Fix tracing for ld/st.
129
130 Mon May 12 11:12:24 1997 Andrew Cagney <cagney@b1.cygnus.com>
131
132 * sim-calls.c (sim_stop_reason): Restore keep_running after a
133 CNTRL-C, don't re-clear it.
134
135 * interp.c (engine_error): stop rather than signal with SIGABRT
136 when an error.
137
138 * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
139 rDest + 1. Also done by Michael Meissner <meissner@cygnus.com>
140 (do_st): Converse for store.
141
142 * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
143
144 Sun May 11 11:02:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
145
146 * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
147 was cleared.
148
149 * interp.c (engine_step): New function. Single step the simulator
150 taking care of cntrl-c during a step.
151
152 * sim-calls.c (sim_resume): Differentiate between stepping and
153 running so that a cntrl-c during a step is reported.
154
155 Sun May 11 10:54:31 1997 Mark Alexander <marka@cygnus.com>
156
157 * sim-calls.c (sim_fetch_register): Use correct reg base.
158 (sim_store_register): Ditto.
159
160 Sun May 11 10:25:14 1997 Michael Meissner <meissner@cygnus.com>
161
162 * cpu.h (tic80_trace_shift): Add declaration.
163 (TRACE_SHIFT): New macro to trace shift instructions.
164
165 * misc.c (tic80_trace_alu2): Align spacing.
166 (tic80_trace_shift): New function to trace shifts.
167
168 * insns (lmo): Add missing 0b prefix to bits.
169 (do_shift): Use ~ (unsigned32)0, instead of -1. Use TRACE_SHIFT
170 instead of TRACE_ALU2.
171 (sl r): Use EndMask as is, instead of using Source+1 register.
172 (subu): Operands are unsigned, not signed.
173 (do_{ld,st}): Fix endian problems with ld.d/st.d.
174
175 Sat May 10 12:35:47 1997 Michael Meissner <meissner@cygnus.com>
176
177 * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
178 signed.
179
180 Fri May 9 15:47:36 1997 Mike Meissner <meissner@cygnus.com>
181
182 * insns (cmp_vals,do_cmp): Produce the correct bits as specified
183 by the architecture.
184 (xor): Fix xor immediate patterns to use the correct bits.
185
186 Fri May 9 09:55:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
187
188 * alu.h (long_immediate): Adjust the CIA delay-pointer as well as
189 the NIA when a 64bit insn.
190
191 Thu May 8 11:57:47 1997 Michael Meissner <meissner@cygnus.com>
192
193 * insns (jsr,bsr): For non-allulled calls, set r31 so that the
194 return address does not reexecute the instruction in the delay
195 slot.
196 (bbo,bbz): Complement bit number to reverse the one's complement
197 that the assembler is required to do.
198
199 * misc.c (tic80_trace_*): Change format slightly to accomidate
200 real large decimal values.
201
202 Thu May 8 14:07:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
203
204 * sim-calls.c (sim_do_command): Implement.
205 (sim_store_register): Fix typo T2H v H2T.
206
207 Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
208
209 * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add.
210 * insn: Clean up fpu tracing.
211
212 * sim-calls.c (sim_create_inferior): Start out with interrupts
213 enabled.
214
215 * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument
216 sink
217
218 * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement.
219
220 * insns (do_*): Remove MY_INDEX/indx argument from support functions,
221 igen now handles this.
222
223 * cpu.h (CR): New macro - access TIc80 control registers.
224
225 * misc.c: New file.
226 (tic80_cr2index): New function, map control register opcode index
227 into the internal CR enum.
228
229 * interp.c
230 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from
231 here
232 * misc.c: to here.
233
234 * Makefile.in (SIM_OBJS): Add misc.o.
235
236 Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com>
237
238 * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on
239 big endian hosts.
240 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Declare
241 new functions.
242 (TRACE_{ALU{2,3},NOP,SINK{1,2},{,U}COND_BR,LD,ST}): New macros to
243 trace various instruction types.
244
245 * insns: Modify all instructions to support semantic tracing.
246
247 * interp.c (toplevel): Include itable.h.
248 (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): New
249 functions to provide semantic level tracing information.
250
251 Mon May 5 11:50:43 1997 Andrew Cagney <cagney@b1.cygnus.com>
252
253 * alu.h: Update usage of core object to reflect recent changes in
254 ../common/sim-*core.
255 * sim-calls.c (sim_open): Ditto.
256
257 Mon May 5 14:10:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
258
259 * insn (cmnd): No-op cache flushes.
260
261 * insns (do_trap): Allow writes to STDERR.
262
263 * Makefile.in (SIM_OBJS): Link in sim-fpu.o.
264 (SIM_EXTRA_LIBS): Link in the math library.
265
266 * alu.h: Add support for floating point unit using sim-alu.
267
268 * insns (fadd, fsub, fmpy, fdiv, fcmp, frnd*): Implement.
269
270 Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
271
272 * sim-calls.c: Include sim-utils.h and sim-options.h.
273
274 * sim-main.h (sim_state): Drop sim_events and sim_core members,
275 moved to simulator base type.
276
277 * alu.h (IMEM, MEM, STORE): Update track changes in common
278 directory.
279
280 * insns: Drop cia argument from functions, igen now handles this.
281
282 * interp.c (engine_init): Include string.h/strings.h to define
283 memset et.al.
284
285 * sim-main.h (sim_cia): Delcare, tracking common dir changes.
286
287 * cpu.h (sim_cpu): Update instruction_address with sim_cia.
288
289 Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
290
291 * sim-main.h (signal.h): Include so that SIG* available to all
292 callers of sig_halt.
293
294 * insns (do_shift): New function, implement shift operations.
295 (do_trap): Add handler for trap 73 - SIGTRAP.
296
297 Tue Apr 29 10:58:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
298
299 * alu.h (MEM, STORE): Force addresses to be correctly aligned.
300
301 * insns (do_jsr): Fix.
302 (do_st, do_ld): Handle 64bit transfers.
303 (do_trap): Match libgloss.
304 (rdcr): Implement nop - Dest == r0 - variant.
305
306 * sim-calls.c (sim_create_inferior): Initialize SP.
307
308 * Makefile.in (ENGINE_H): Everything now depends on sim-options.h.
309 (support.o): Depends on ENGINE_H.
310
311 * cpu.h: Four accumulators.
312
313 * Makefile.in (tmp-igen): Include line number information in
314 generated files.
315
316 * insns (dld, dst): Fill in.
317
318 Mon Apr 28 13:02:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
319
320 * insns (vld): Fix instruction format wrong.
321
322 Thu Apr 24 16:43:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
323
324 * dc: Add additional rules so that minor opcode files are
325 detected.
326 * insns: Enable more instructions.
327
328 * sim-calls.c (sim_fetch_register,sim_store_register, sim_write):
329 Implement.
330
331 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
332
333 * configure: Regenerated to track ../common/aclocal.m4 changes.
334 * Makefile.in (SIM_OBJS): Add sim-module.o, sim-profile.o.
335 * sim-calls.c (sim_open): Call sim_module_uninstall if argument
336 parsing fails. Call sim_post_argv_init.
337 (sim_close): Call sim_module_uninstall.
338
339 Wed Apr 23 20:05:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
340
341 * insns (and, bbo, bcnd, bsr, dcache, jsr, or, xor, nor): Enable.
342 * ic: Add fields for enabled instructions.
343
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