1 // Texas Instruments TMS320C80 (MVP) Simulator.
4 // The following is called when ever an illegal instruction is encountered.
7 sim_io_eprintf (SD, "0x%lx: illegal instruction\n", (unsigned long) cia.ip);
8 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
11 // The following is called when ever an FP op is attempted with FPU disabled.
12 :internal::::fp_unavailable:
14 sim_io_eprintf (SD, "0x%lx: floating-point unavailable\n", (unsigned long) cia.ip);
15 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGFPE);
18 // Handle a branch instruction
19 :function:::instruction_address:do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
21 instruction_address nia;
32 *rLink = cia.dp + sizeof (instruction_word);
39 // Signed Integer Add - add source1, source2, dest
40 :function:::void:do_add:unsigned32 *rDest, signed32 source1, signed32 source2
47 TRACE_ALU3 (MY_INDEX, result, source1, source2);
48 /* FIXME - a signed add may cause an exception */
50 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
51 "add <SignedImmediate>, r<Source2>, r<Dest>"
53 do_add (_SD, rDest, vSource1, vSource2);
55 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
56 "add r<Source1>, r<Source2>, r<Dest>"
58 do_add (_SD, rDest, vSource1, vSource2);
60 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./+LongSignedImmediate::::add l
61 "add 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
63 do_add (_SD, rDest, LongSignedImmediate, vSource2);
67 // Unsigned Integer Add - addu source1, source2, dest
68 :function:::void:do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
70 unsigned32 result = source1 + source2;
71 TRACE_ALU3 (MY_INDEX, result, source1, source2);
75 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
76 "addu <SignedImmediate>, r<Source2>, r<Dest>"
78 do_addu (_SD, rDest, vSource1, vSource2);
80 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
81 "addu r<Source1>, r<Source2>, r<Dest>"
83 do_addu (_SD, rDest, vSource1, vSource2);
85 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./+LongSignedImmediate::::addu l
86 "addu 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
88 do_addu (_SD, rDest, LongSignedImmediate, vSource2);
92 :function:::void:do_and:signed32 *rDest, signed32 source1, signed32 source2
94 unsigned32 result = source1 & source2;
95 TRACE_ALU3 (MY_INDEX, result, source1, source2);
101 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
102 "and.tt <UnsignedImmediate>, r<Source2>, r<Dest>"
104 do_and (_SD, rDest, vSource1, vSource2);
106 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
107 "and.tt r<Source1>, r<Source2>, r<Dest>"
109 do_and (_SD, rDest, vSource1, vSource2);
111 31.Dest,26.Source2,21.0b110010001,12.1,11./+LongSignedImmediate::::and.tt l
112 "and.tt 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
114 do_and (_SD, rDest, LongSignedImmediate, vSource2);
119 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
120 "and.ff <UnsignedImmediate>, r<Source2>, r<Dest>"
122 do_and (_SD, rDest, ~vSource1, ~vSource2);
124 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
125 "and.ff r<Source1>, r<Source2>, r<Dest>"
127 do_and (_SD, rDest, ~vSource1, ~vSource2);
129 31.Dest,26.Source2,21.0b110011000,12.1,11./+LongSignedImmediate::::and.ff l
130 "and.ff 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
132 do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
136 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
137 "and.ft <UnsignedImmediate>, r<Source2>, r<Dest>"
139 do_and (_SD, rDest, ~vSource1, vSource2);
141 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
142 "and.ft r<Source1>, r<Source2>, r<Dest>"
144 do_and (_SD, rDest, ~vSource1, vSource2);
146 31.Dest,26.Source2,21.0b110010100,12.1,11./+LongSignedImmediate::::and.ft l
147 "and.ft 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
149 do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
153 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
154 "and.tf <UnsignedImmediate>, r<Source2>, r<Dest>"
156 do_and (_SD, rDest, vSource1, ~vSource2);
158 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
159 "and.tf r<Source1>, r<Source2>, r<Dest>"
161 do_and (_SD, rDest, vSource1, ~vSource2);
163 31.Dest,26.Source2,21.0b110010010,12.1,11./+LongSignedImmediate::::and.tf l
164 "and.tf 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
166 do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
170 :function:::instruction_address:do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
173 address_word target = cia.ip + 4 * offset;
174 if (MASKED32 (source, bitnum, bitnum))
176 nia = do_branch (_SD, annul, target, 0, NULL);
181 TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target, -1, -1);
191 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
192 "bbo%s<A> <SignedOffset>, r<Source>, <bitnum>"
194 nia = do_bbo (_SD, nia, bitnum, vSource, A, vSignedOffset);
196 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
197 "bbo%s<A> r<IndOff>, r<Source>, <bitnum>"
199 nia = do_bbo (_SD, nia, bitnum, vSource, A, rIndOff);
201 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./+LongSignedImmediate::::bbo l
202 "bbo%s<A> <LongSignedImmediate>, r<Source>, <bitnum>"
204 nia = do_bbo (_SD, nia, bitnum, vSource, A, LongSignedImmediate);
208 :function:::instruction_address:do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
211 address_word target = cia.ip + 4 * offset;
212 if (!MASKED32 (source, bitnum, bitnum))
214 nia = do_branch (_SD, annul, target, 0, NULL);
219 TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target, -1, -1);
222 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
223 "bbz%s<A> <SignedOffset>, r<Source>, <bitnum>"
225 nia = do_bbz (_SD, nia, bitnum, vSource, A, vSignedOffset);
227 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
228 "bbz%s<A> r<IndOff>, r<Source>, <bitnum>"
230 nia = do_bbz (_SD, nia, bitnum, vSource, A, rIndOff);
232 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./+LongSignedImmediate::::bbz l
233 "bbz%s<A> <LongSignedImmediate>, r<Source>, <bitnum>"
235 nia = do_bbz (_SD, nia, bitnum, vSource, A, LongSignedImmediate);
239 :function:::instruction_address:do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
242 int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
243 int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
245 address_word target = cia.ip + 4 * offset;
248 case 0: val = SEXT32 (source, 7); break;
249 case 1: val = SEXT32 (source, 15); break;
250 case 2: val = source; break;
251 default: sim_engine_abort (SD, CPU, cia, "bcnd - reserved size");
255 case 0: condition = 0; break;
256 case 1: condition = val > 0; break;
257 case 2: condition = val == 0; break;
258 case 3: condition = val >= 0; break;
259 case 4: condition = val < 0; break;
260 case 5: condition = val != 0; break;
261 case 6: condition = val <= 0; break;
262 default: condition = 1; break;
266 nia = do_branch (_SD, annul, target, 0, NULL);
268 TRACE_COND_BR(MY_INDEX, condition, val, target, size, code);
271 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
272 "bcnd%s<A> <SignedOffset>, r<Source>, <Code>"
274 nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
276 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
277 "bcnd%s<A> r<IndOff>, r<Source>, <Code>"
279 nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
281 31.Code,26.Source,21.0b11100110,13.A,12.1,11./+LongSignedImmediate::::bcnd l
282 "bcnd%s<A> <LongSignedImmediate>, r<Source>, <Code>"
284 nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
287 // br[.a] - see bbz[.a]
291 :function:::sim_cia:do_brcr:instruction_address nia, int cr
293 if (cr >= 0x4000 || !(CPU)->is_user_mode)
295 unsigned32 control = CR (cr);
296 unsigned32 ie = control & 0x00000001;
297 unsigned32 pc = control & 0xfffffffc;
298 unsigned32 is_user_mode = control & 0x00000002;
299 (CPU)->is_user_mode = is_user_mode;
302 (CPU)->cr[IE_CR] |= IE_CR_IE;
304 (CPU)->cr[IE_CR] &= ~IE_CR_IE;
306 TRACE_UCOND_BR (MY_INDEX, nia.dp);
309 31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i
312 nia = do_brcr (_SD, nia, UCRN);
314 31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r
317 nia = do_brcr (_SD, nia, UCRN);
319 31.//,27.0,26.//,21.0b110000110,12.1,11./+UnsignedControlRegisterNumber::::brcr l
320 "brcr CR[<UnsignedControlRegisterNumber>]"
322 nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber);
326 :function:::instruction_address:do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
328 address_word target = cia.ip + 4 * offset;
329 nia = do_branch (_SD, annul, target, 1, rLink);
330 TRACE_UCOND_BR (MY_INDEX, target);
333 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
334 "bsr%s<A> <SignedOffset>, r<Link>"
336 nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
338 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
339 "bsr%s<A> r<IndOff>, r<Link>"
341 nia = do_bsr (_SD, nia, rLink, A, rIndOff);
343 31.Link,26./,21.0b11100000,13.A,12.1,11./+LongSignedImmediate::::bsr l
344 "bsr%s<A> <LongSignedImmediate>, r<Link>"
346 nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
350 :function:::void:do_cmnd:signed32 source
352 int Reset = EXTRACTED32 (source, 31, 31);
353 int Halt = EXTRACTED32 (source, 30, 30);
354 int Unhalt = EXTRACTED32 (source, 29, 29);
355 /* int ICR = EXTRACTED32 (source, 28, 28); */
356 /* int DCR = EXTRACTED32 (source, 27, 27); */
357 int Task = EXTRACTED32 (source, 14, 14);
358 int Msg = EXTRACTED32 (source, 13, 13);
359 int VC = EXTRACTED32 (source, 10, 10);
360 int TC = EXTRACTED32 (source, 9, 9);
361 int MP = EXTRACTED32 (source, 8, 8);
362 int PP = EXTRACTED32 (source, 3, 0);
363 /* what is implemented? */
365 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
366 (unsigned long) cia.ip);
368 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
369 (unsigned long) cia.ip);
371 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
372 (unsigned long) cia.ip);
376 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
378 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
379 (unsigned long) cia.ip);
380 /* if (ICR || DCR); */
382 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
383 (unsigned long) cia.ip);
385 sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
386 (unsigned long) cia.ip);
388 TRACE_SINK1 (MY_INDEX, source);
390 31./,21.0b0000010,14.UI::::cmnd i
395 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
398 do_cmnd (_SD, vSource);
400 31./,21.0b110000010,12.1,11./+LongUnsignedImmediate::::cmnd l
401 "cmnd <LongUnsignedImmediate>"
403 do_cmnd (_SD, LongUnsignedImmediate);
407 :function:::unsigned32:cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2
409 unsigned32 field = 0;
410 if (s1 == s2) field |= 0x001;
411 if (s1 != s2) field |= 0x002;
412 if (s1 > s2) field |= 0x004;
413 if (s1 <= s2) field |= 0x008;
414 if (s1 < s2) field |= 0x010;
415 if (s1 >= s2) field |= 0x020;
416 if (u1 > u2) field |= 0x040;
417 if (u1 <= u2) field |= 0x080;
418 if (u1 < u2) field |= 0x100;
419 if (u1 >= u2) field |= 0x200;
422 :function:::void:do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
424 unsigned32 field = 0;
425 field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
426 field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
427 (signed16)source2, (unsigned16)source2) << 10;
428 field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
429 (signed8)source2, (unsigned8)source2);
430 TRACE_CMP (MY_INDEX, field, source1, source2);
433 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
434 "cmp <SignedImmediate>, r<Source2>, r<Dest>"
436 do_cmp (_SD, rDest, vSource1, vSource2);
438 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
439 "cmp r<Source1>, r<Source2>, r<Dest>"
441 do_cmp (_SD, rDest, vSource1, vSource2);
443 31.Dest,26.Source2,21.0b111010000,12.1,11./+LongSignedImmediate::::cmp l
444 "cmp 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
446 do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
457 31./,27.F,26.Source2,21.0b0111,17.m,16.0b00,14.SignedOffset::::dcache i
458 "dcache%s<F> <SignedOffset> (r<Source2>%s<m>)"
460 TRACE_NOP (MY_INDEX);
463 31./,27.F,26.Source2,21.0b110111,15.m,14.0b00,12.0,11./,4.Source1::::dcache r
464 "dcache%s<F> r<Source1> (r<Source2>%s<m>)"
466 TRACE_NOP (MY_INDEX);
469 31./,27.F,26.Source2,21.0b110111,15.m,14.0b00,12.1,11./+LongSignedImmediate::::dcache l
470 "dcache%s<F> <LongSignedImmediate> (r<Source2>%s<m>)"
472 TRACE_NOP (MY_INDEX);
477 void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
479 do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
481 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
482 "dld%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Dest>"
484 do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
486 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dld l
487 "dld%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Dest>"
489 do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
493 void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
495 do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
497 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
498 "dld.u%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Dest>"
500 do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
502 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dld.u l
503 "dld.u%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Dest>"
505 do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
509 void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
511 do_st (_SD, Source, base, rBase, m, sz, S, offset);
513 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
514 "dst%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Source>"
516 do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
518 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./+LongSignedImmediateOffset::::dst l
519 "dst%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Source>"
521 do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
525 31./,21.0b1111111,14.1,13.0,12.0,11./::::estop
528 31./,27.1,26./,21.0b0000001,14.UTN::::etrap i
529 31./,27.1,26./,21.0b110000001,12.0,11./,4.iUTN::::etrap r
530 31./,27.1,26./,21.0b110000001,12.1,11./::::etrap l
533 // exts - see shift.ds
536 // extu - see shift.dz
539 sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
545 sim_fpu_32to (&ans, val);
549 sim_engine_abort (SD, CPU, cia, "DP immediate invalid");
551 sim_engine_abort (SD, CPU, cia, "DP FP register must be even");
553 sim_engine_abort (SD, CPU, cia, "DP FP register must be >= 2");
554 sim_fpu_232to (&ans, GPR (reg + 1), GPR (reg));
556 case 2: /* 32 bit signed integer */
557 sim_fpu_i32to (&ans, val, 0);
559 case 3: /* 32 bit unsigned integer */
560 sim_fpu_u32to (&ans, val, 0);
563 sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
567 void::function::set_fp_reg:int Dest, sim_fpu val, int PD
573 sim_fpu_to32 (&GPR (Dest), &val);
579 sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be even");
581 sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be >= 2");
582 sim_fpu_to232 (&GPR (Dest + 1), &GPR (Dest + 0), &val);
587 sim_fpu_to32i (&GPR (Dest), &val, 0);
590 case 3: /* unsigned */
592 sim_fpu_to32u (&GPR (Dest), &val, 0);
596 sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
600 // fadd.{s|d}{s|d}{s|d}
601 void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
604 sim_fpu_add (&ans, &s1, &s2);
605 TRACE_FPU3 (ans, s1, s2);
606 set_fp_reg (_SD, Dest, ans, PD);
608 const char *::function::str_PX:int PX
619 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
620 "fadd.%s<PX#P1>%s<PX#P2>%s<PX#PD> r<Source1>, r<Source2>, r<Dest>"
622 do_fadd (_SD, Dest, PD,
623 get_fp_reg (_SD, Source1, vSource1, P1),
624 get_fp_reg (_SD, Source2, vSource2, P2));
626 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fadd l
627 "fadd.%s<PX#P1>%s<PX#P2>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Source2>, r<Dest>"
629 do_fadd (_SD, Dest, PD,
630 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
631 get_fp_reg (_SD, Source2, vSource2, P2));
635 // fcmp.{s|d}{s|d}{s|d}
636 void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
638 unsigned32 result = 0;
639 if (sim_fpu_is_nan (&s1) || sim_fpu_is_nan (&s2))
640 result |= BIT32 (30);
643 result |= BIT32 (31);
644 if (sim_fpu_is_eq (&s1, &s2)) result |= BIT32(20);
645 if (sim_fpu_is_ne (&s1, &s2)) result |= BIT32(21);
646 if (sim_fpu_is_gt (&s1, &s2)) result |= BIT32(22);
647 if (sim_fpu_is_le (&s1, &s2)) result |= BIT32(23);
648 if (sim_fpu_is_lt (&s1, &s2)) result |= BIT32(24);
649 if (sim_fpu_is_ge (&s1, &s2)) result |= BIT32(25);
650 if (sim_fpu_is_lt (&s1, &sim_fpu_zero)
651 || sim_fpu_is_gt (&s1, &s2)) result |= BIT32(26);
652 if (sim_fpu_is_lt (&sim_fpu_zero, &s1)
653 && sim_fpu_is_lt (&s1, &s2)) result |= BIT32(27);
654 if (sim_fpu_is_le (&sim_fpu_zero, &s1)
655 && sim_fpu_is_le (&s1, &s2)) result |= BIT32(28);
656 if (sim_fpu_is_le (&s1, &sim_fpu_zero)
657 || sim_fpu_is_ge (&s1, &s2)) result |= BIT32(29);
660 TRACE_FPU2CMP (result, s1, s2);
662 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
663 "fcmp.%s<PX#P1>%s<PX#P2> r<Source1>, r<Source2>, r<Dest>"
666 get_fp_reg (_SD, Source1, vSource1, P1),
667 get_fp_reg (_SD, Source2, vSource2, P2));
669 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fcmp l
670 "fcmp.%s<PX#P1>%s<PX#P2> 0x%08lx<SinglePrecisionFloatingPoint>, r<Source2>, r<Dest>"
673 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
674 get_fp_reg (_SD, Source2, vSource2, P2));
678 // fdiv.{s|d}{s|d}{s|d}
679 void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
682 sim_fpu_div (&ans, &s1, &s2);
683 TRACE_FPU3 (ans, s1, s2);
684 set_fp_reg (_SD, Dest, ans, PD);
686 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
687 "fdiv.%s<PX#P1>%s<PX#P2>%s<PX#PD> r<Source1>, r<Source2>, r<Dest>"
689 do_fdiv (_SD, Dest, PD,
690 get_fp_reg (_SD, Source1, vSource1, P1),
691 get_fp_reg (_SD, Source2, vSource2, P2));
693 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fdiv l
694 "fdiv.%s<PX#P1>%s<PX#P2>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Source2>, r<Dest>"
696 do_fdiv (_SD, Dest, PD,
697 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
698 get_fp_reg (_SD, Source2, vSource2, P2));
701 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
702 void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
710 sim_fpu_to64i (&i1, &s1, 0);
711 sim_fpu_to64i (&i2, &s2, 0);
712 GPR (Dest) = i1 * i2;
713 TRACE_FPU2I (GPR (Dest), s1, s2);
716 case 3: /* unsigned */
720 sim_fpu_to64u (&u1, &s1, 0);
721 sim_fpu_to64u (&u2, &s2, 0);
722 GPR (Dest) = u1 * u2;
723 TRACE_FPU2I (GPR (Dest), s1, s2);
729 sim_fpu_mul (&ans, &s1, &s2);
730 set_fp_reg (_SD, Dest, ans, PD);
731 TRACE_FPU3 (ans, s1, s2);
735 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
736 "fmpy.%s<PX#P1>%s<PX#P2>%s<PX#PD> r<Source1>, r<Source2>, r<Dest>"
738 do_fmpy (_SD, Dest, PD,
739 get_fp_reg (_SD, Source1, vSource1, P1),
740 get_fp_reg (_SD, Source2, vSource2, P2));
742 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fmpy l
743 "fmpy.%s<PX#P1>%s<PX#P2>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Source2>, r<Dest>"
745 do_fmpy (_SD, Dest, PD,
746 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
747 get_fp_reg (_SD, Source2, vSource2, P2));
750 // frndm.{s|d|i|u}{s|d|i|u}
751 void::function::do_frnd:int Dest, int PD, sim_fpu s1
753 set_fp_reg (_SD, Dest, s1, PD);
756 31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
757 "frndm.%s<PX#P1>%s<PX#PD> r<Source>, r<Dest>"
759 do_frnd (_SD, Dest, PD,
760 get_fp_reg (_SD, Source, vSource, P1));
762 31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./+SinglePrecisionFloatingPoint::f::frndm l
763 "frndm.%s<PX#P1>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Dest>"
765 do_frnd (_SD, Dest, PD,
766 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
769 // frndn.{s|d|i|u}{s|d|i|u}
770 31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
771 "frndn.%s<PX#P1>%s<PX#PD> r<Source>, r<Dest>"
773 do_frnd (_SD, Dest, PD,
774 get_fp_reg (_SD, Source, vSource, P1));
776 31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./+SinglePrecisionFloatingPoint::f::frndn l
777 "frndn.%s<PX#P1>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Dest>"
779 do_frnd (_SD, Dest, PD,
780 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
783 // frndp.{s|d|i|u}{s|d|i|u}
784 31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
785 "frndp.%s<PX#P1>%s<PX#PD> r<Source>, r<Dest>"
787 do_frnd (_SD, Dest, PD,
788 get_fp_reg (_SD, Source, vSource, P1));
790 31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./+SinglePrecisionFloatingPoint::f::frndp l
791 "frndp.%s<PX#P1>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Dest>"
793 do_frnd (_SD, Dest, PD,
794 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
797 // frndz.{s|d|i|u}{s|d|i|u}
798 31.Dest,26./,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
799 "frndz.%s<PX#P1>%s<PX#PD> r<Source>, r<Dest>"
801 do_frnd (_SD, Dest, PD,
802 get_fp_reg (_SD, Source, vSource, P1));
804 31.Dest,26./,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./+SinglePrecisionFloatingPoint::f::frndz l
805 "frndz.%s<PX#P1>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Dest>"
807 do_frnd (_SD, Dest, PD,
808 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1));
811 // fsqrt.{s|d}{s|d}{s|d}
812 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source, unsigned32 Source2
813 # sim_io_error ("fsqrt");
814 31.Dest,26./,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source::f::fsqrt r
815 "fsqrt.%s<PX#P1>%s<PX#PD> r<Source>, r<Dest>"
816 # do_fsqrt (_SD, rDest, vSource);
817 31.Dest,26./,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./+SinglePrecisionFloatingPoint::f::fsqrt l
818 "fsqrt.%s<PX#P1>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Dest>"
819 # do_fsqrt (_SD, rDest, SinglePrecisionFloatingPoint);
822 // fsub.{s|d}{s|d}{s|d}
823 void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
826 sim_fpu_sub (&ans, &s1, &s2);
827 TRACE_FPU3 (ans, s1, s2);
828 set_fp_reg (_SD, Dest, ans, PD);
830 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
831 "fsub.%s<PX#P1>%s<PX#P2>%s<PX#PD> r<Source1>, r<Source2>, r<Dest>"
833 do_fsub (_SD, Dest, PD,
834 get_fp_reg (_SD, Source1, vSource1, P1),
835 get_fp_reg (_SD, Source2, vSource2, P2));
837 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./+SinglePrecisionFloatingPoint::f::fsub l
838 "fsub.%s<PX#P1>%s<PX#P2>%s<PX#PD> 0x%08lx<SinglePrecisionFloatingPoint>, r<Source2>, r<Dest>"
840 do_fsub (_SD, Dest, PD,
841 get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
842 get_fp_reg (_SD, Source2, vSource2, P2));
846 31./,21.0b0000000,14./::::illop
848 31./,21.0b111111111,12./::::illop l
856 instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
858 address_word target = offset + base;
859 TRACE_UCOND_BR (MY_INDEX, target);
860 nia = do_branch (_SD, annul, target, 1, rLink);
862 sim_engine_abort (SD, CPU, cia,
863 "0x%lx: destination address 0x%lx misaligned",
864 (unsigned long) cia.ip,
865 (unsigned long) nia.dp);
868 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
869 "jsr%s<A> <SignedOffset>, r<Link>"
871 nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
873 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.IndOff::::jsr r
874 "jsr%s<A> r<IndOff>, r<Link>"
876 nia = do_jsr (_SD, nia, rLink, A, rIndOff, vBase);
878 31.Link,26.Base,21.0b11100010,13.A,12.1,11./+LongSignedImmediate::::jsr l
879 "jsr%s<A> <LongSignedImmediate>, r<Link>"
881 nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
885 void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
891 addr = base + (S ? (offset << 0) : offset);
894 GPR(Dest) = MEM (signed, addr, 1);
897 addr = base + (S ? (offset << 1) : offset);
900 GPR(Dest) = MEM (signed, addr, 2);
903 addr = base + (S ? (offset << 2) : offset);
906 GPR(Dest) = MEM (signed, addr, 4);
912 sim_engine_abort (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
914 addr = base + (S ? (offset << 3) : offset);
917 val = MEM (signed, addr, 8);
918 GPR(Dest + 1) = VH4_8 (val);
919 GPR(Dest + 0) = VL4_8 (val);
924 sim_engine_abort (SD, CPU, cia, "ld - invalid sz %d", sz);
926 TRACE_LD (GPR(Dest), m, S, base, offset);
928 const char *::function::str_sz:int sz
939 const char *::function::str_m:int m
946 const char *::function::str_S:int S
953 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
954 "ld%s<sz> <SignedOffset> (r<Base>%s<m>), r<Dest>"
956 do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
958 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
959 "ld%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Dest>"
961 do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
963 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::ld l
964 "ld%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Dest>"
966 do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
970 void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
976 addr = base + (S ? (offset << 0) : offset);
977 *rDest = MEM (unsigned, addr, 1);
980 addr = base + (S ? (offset << 1) : offset);
981 *rDest = MEM (unsigned, addr, 2);
985 sim_engine_abort (SD, CPU, cia, "ld.u - invalid sz %d", sz);
989 TRACE_LD (m, S, *rDest, base, offset);
991 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
992 "ld.u%s<sz> <SignedOffset> (r<Base>%s<m>), r<Dest>"
994 do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
996 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
997 "ld.u%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Dest>"
999 do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
1001 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::ld.u l
1002 "ld.u%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Dest>"
1004 do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
1008 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
1009 "lmo r<Source>, r<Dest>"
1012 for (b = 0; b < 32; b++)
1013 if (vSource & BIT32 (31 - b))
1015 TRACE_ALU2 (MY_INDEX, b, vSource);
1020 // nop - see rdcr 0, r0
1023 void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
1025 unsigned32 result = Source1 | Source2;
1026 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1031 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
1032 "or.tt <UnsignedImmediate>, r<Source2>, r<Dest>"
1034 do_or (_SD, rDest, vSource1, vSource2);
1036 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
1037 "or.tt r<Source1>, r<Source2>, r<Dest>"
1039 do_or (_SD, rDest, vSource1, vSource2);
1041 31.Dest,26.Source2,21.0b110010111,12.1,11./+LongUnsignedImmediate::::or.tt l
1042 "or.tt 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1044 do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
1048 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
1049 "or.ff <UnsignedImmediate>, r<Source2>, r<Dest>"
1051 do_or (_SD, rDest, ~vSource1, ~vSource2);
1053 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
1054 "or.ff r<Source1>, r<Source2>, r<Dest>"
1056 do_or (_SD, rDest, ~vSource1, ~vSource2);
1058 31.Dest,26.Source2,21.0b110011110,12.1,11./+LongUnsignedImmediate::::or.ff l
1059 "or.ff 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1061 do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
1065 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
1066 "or.ft <UnsignedImmediate>, r<Source2>, r<Dest>"
1068 do_or (_SD, rDest, ~vSource1, vSource2);
1070 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
1071 "or.ft r<Source1>, r<Source2>, r<Dest>"
1073 do_or (_SD, rDest, ~vSource1, vSource2);
1075 31.Dest,26.Source2,21.0b110011101,12.1,11./+LongUnsignedImmediate::::or.ft l
1076 "or.ft 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1078 do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
1082 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
1083 "or.tf <UnsignedImmediate>, r<Source2>, r<Dest>"
1085 do_or (_SD, rDest, vSource1, ~vSource2);
1087 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
1088 "or.tf r<Source1>, r<Source2>, r<Dest>"
1090 do_or (_SD, rDest, vSource1, ~vSource2);
1092 31.Dest,26.Source2,21.0b110011011,12.1,11./+LongUnsignedImmediate::::or.tf l
1093 "or.tf 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1095 do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
1099 void::function::do_rdcr:unsigned32 Dest, int cr
1101 TRACE_SINK2 (MY_INDEX, Dest, cr);
1102 GPR (Dest) = CR (cr);
1104 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
1105 "rdcr CR[<UCRN>], r<Dest>"
1107 do_rdcr (_SD, Dest, UCRN);
1109 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
1110 "rdcr CR[r<INDCR>], r<Dest>"
1112 do_rdcr (_SD, Dest, UCRN);
1114 31.Dest,26.0,21.0b110000100,12.1,11./+UnsignedControlRegisterNumber::::rdcr l
1115 "rdcr CR[<UnsignedControlRegisterNumber>], r<Dest>"
1117 do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
1121 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
1122 "rmo r<Source>, r<Dest>"
1125 for (b = 0; b < 32; b++)
1126 if (vSource & BIT32 (b))
1130 TRACE_ALU2 (MY_INDEX, b, vSource);
1143 // sl.{d|e|i}{m|s|z}
1144 void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
1146 /* see 10-30 for a reasonable description */
1147 unsigned32 input = source;
1150 unsigned32 shiftmask;
1153 /* rotate the source */
1156 rotated = ROTR32 (source, Rotate);
1157 nRotate = (- Rotate) & 31;
1161 rotated = ROTL32 (source, Rotate);
1164 /* form the end mask */
1166 endmask = ~ (unsigned32)0;
1168 endmask = (1 << EndMask) - 1;
1171 /* form the shiftmask */
1174 case 0: case 1: case 2:
1175 shiftmask = ~ (unsigned32)0; /* disabled */
1177 case 3: case 5: /* enabled - 0 -> 32 */
1179 shiftmask = ~ (unsigned32)0;
1181 shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
1184 shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
1187 shiftmask = ~((1 << nRotate) - 1); /* inverted */
1190 sim_engine_abort (SD, CPU, cia,
1191 "0x%lx: Invalid merge (%d) for shift",
1192 (long) cia.ip, (int) source);
1195 /* and the composite mask */
1196 cm = shiftmask & endmask;
1200 case 0: case 3: case 6: /* zero */
1201 GPR (Dest) = rotated & cm;
1203 case 1: case 4: case 7: /* merge */
1204 GPR (Dest) = (rotated & cm) | (GPR (Dest) & ~cm);
1206 case 2: case 5: /* sign */
1209 GPR (Dest) = rotated & cm;
1210 for (b = 1; b <= 31; b++)
1211 if (!MASKED32 (cm, b, b))
1212 GPR (Dest) |= INSERTED32 (EXTRACTED32 (GPR (Dest), b - 1, b - 1),
1217 sim_engine_abort (SD, CPU, cia,
1218 "0x%lx: Invalid merge (%d)",
1219 (long) cia.ip, (int) source);
1221 TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
1223 const char *::function::str_Merge:int Merge
1227 case 0: return "dz";
1228 case 1: return "dm";
1229 case 2: return "ds";
1230 case 3: return "ez";
1231 case 4: return "em";
1232 case 5: return "es";
1233 case 6: return "iz";
1234 case 7: return "im";
1235 default: return "?";
1238 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
1239 "sl.%s<Merge> <Rotate>, <EndMask>, r<Source>, r<Dest>"
1241 do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
1243 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
1244 "sl.%s<Merge> r<RotReg>, <EndMask>, r<Source>, r<Dest>"
1246 do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
1249 // sli.{d|e|i}{m|s|z} - see shift
1252 // sr.{d|e|i}{m|s|z} - see shift
1255 // sra - see sr.es - see shift
1258 // sri.{d|e|i}{m|s|z} - see shift
1265 void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
1271 addr = base + (S ? (offset << 0) : offset);
1272 STORE (addr, 1, GPR(Source));
1275 addr = base + (S ? (offset << 1) : offset);
1276 STORE (addr, 2, GPR(Source));
1279 addr = base + (S ? (offset << 2) : offset);
1280 STORE (addr, 4, GPR(Source));
1286 sim_engine_abort (SD, CPU, cia,
1287 "0x%lx: st.d with odd source register %d",
1289 addr = base + (S ? (offset << 3) : offset);
1290 val = U8_4 (GPR(Source + 1), GPR(Source));
1291 STORE (addr, 8, val);
1296 sim_engine_abort (SD, CPU, cia, "st - invalid sz %d", sz);
1300 TRACE_ST (Source, m, S, base, offset);
1302 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
1303 "st%s<sz> <SignedOffset> (r<Base>%s<m>), r<Source>"
1305 do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
1307 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
1308 "st%s<sz> r<IndOff>%s<S> (r<Base>%s<m>), r<Source>"
1310 do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
1312 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./+LongSignedImmediateOffset::::st l
1313 "st%s<sz> 0x%08lx<LongSignedImmediateOffset>%s<S> (r<Base>%s<m>), r<Source>"
1315 do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
1319 void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
1321 ALU_BEGIN (Source1);
1324 TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
1326 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
1327 "sub <SignedImmediate>, r<Source2>, r<Dest>"
1329 do_sub (_SD, rDest, vSource1, vSource2);
1331 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
1332 "sub r<Source1>, r<Source2>, r<Dest>"
1334 do_sub (_SD, rDest, vSource1, vSource2);
1336 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./+LongSignedImmediate::::sub l
1337 "sub 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
1339 do_sub (_SD, rDest, LongSignedImmediate, vSource2);
1343 void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
1345 unsigned32 result = Source1 - Source2;
1346 TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
1349 // NOTE - the book has 15.1 which conflicts with subu.
1350 31.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i
1351 "subu <SignedImmediate>, r<Source2>, r<Dest>"
1353 do_subu (_SD, rDest, vSource1, vSource2);
1355 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
1356 "subu r<Source1>, r<Source2>, r<Dest>"
1358 do_subu (_SD, rDest, vSource1, vSource2);
1360 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./+LongSignedImmediate::::subu l
1361 "subu 0x%08lx<LongSignedImmediate>, r<Source2>, r<Dest>"
1363 do_subu (_SD, rDest, LongSignedImmediate, vSource2);
1367 void::function::do_swcr:int Dest, signed32 source, signed32 cr
1369 tic80_control_regs reg = tic80_index2cr (cr);
1370 /* cache the old CR value */
1371 unsigned32 old_cr = CR (cr);
1372 /* Handle the write if allowed */
1373 if (cr >= 0x4000 || !(CPU)->is_user_mode)
1383 /* Finish off the read */
1384 GPR (Dest) = old_cr;
1385 TRACE_SINK3 (MY_INDEX, source, cr, Dest);
1387 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
1388 "swcr CR[<UCRN>], r<Dest>"
1390 do_swcr (_SD, Dest, vSource, UCRN);
1392 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
1393 "swcr CR[r<INDCR>], r<Dest>"
1395 do_swcr (_SD, Dest, vSource, UCRN);
1397 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./+LongUnsignedControlRegisterNumber::::swcr l
1398 "swcr CR[<LongUnsignedControlRegisterNumber>], r<Dest>"
1400 do_swcr (_SD, Dest, vSource, LongUnsignedControlRegisterNumber);
1404 void::function::do_trap:unsigned32 trap_number
1407 TRACE_SINK1 (MY_INDEX, trap_number);
1408 switch (trap_number)
1415 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR(2));
1422 for (i = 0; i < GPR(6); i++)
1425 c = MEM (unsigned, GPR(4) + i, 1);
1426 sim_io_write_stdout (SD, &c, 1);
1428 else if (GPR(2) == 2)
1429 for (i = 0; i < GPR(6); i++)
1432 c = MEM (unsigned, GPR(4) + i, 1);
1433 sim_io_write_stderr (SD, &c, 1);
1436 sim_engine_abort (SD, CPU, cia,
1437 "0x%lx: write to invalid fid %d",
1438 (long) cia.ip, (int) GPR(2));
1442 case 20: /* GETPID */
1448 if ( GPR (2) != (unsigned) getpid ())
1450 int ret = kill (GPR(2), GPR(4));
1458 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, GPR(4));
1462 /* For system calls which are defined, just return EINVAL instead of trapping */
1465 GPR(2) = -22; /* -EINVAL */
1468 sim_engine_abort (SD, CPU, cia,
1469 "0x%lx: unknown syscall %d",
1470 (long) cia.ip, (int) GPR(15));
1474 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1476 /* Add a few traps for now to print the register state */
1483 if (!TRACE_ALU_P (CPU))
1484 trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
1485 itable[MY_INDEX].line_nr, "trap",
1486 "Trap %ld", (long) trap_number);
1488 for (i = 0; i < 32; i++)
1489 sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
1490 (((i+1) % 8) == 0) ? "\n" : "");
1491 sim_io_write_stderr (SD, "\n", 1);
1495 sim_engine_abort (SD, CPU, cia,
1496 "0x%lx: unsupported trap %d",
1497 (long) cia.ip, (int) trap_number);
1500 31./,27.0,26./,21.0b0000001,14.UTN::::trap i
1505 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
1510 31./,27.0,26./,21.0b110000001,12.1,11./+UTN::::trap l
1517 31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r
1518 31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l
1521 // vld{0|1}.{s|d} - see above - same instruction
1522 #31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld
1526 #31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra
1527 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr
1528 #31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia
1529 31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir
1533 31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r
1534 31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l
1538 #31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra
1539 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr
1540 #31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia
1541 31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir
1545 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r
1546 31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l
1550 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r
1551 31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l
1555 31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r
1556 31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l
1559 // vst.{s|d} - see above - same instruction
1560 #31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst
1564 31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r
1565 31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l
1568 // wrcr - see swcr, creg, source, r0
1572 void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
1574 unsigned32 result = ~ (source1 ^ source2);
1575 TRACE_ALU3 (MY_INDEX, result, source1, source2);
1578 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
1579 "xnor <UnsignedImmediate>, r<Source2>, r<Dest>"
1581 do_xnor (_SD, rDest, vSource1, vSource2);
1583 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
1584 "xnor r<Source1>, r<Source2>, r<Dest>"
1586 do_xnor (_SD, rDest, vSource1, vSource2);
1588 31.Dest,26.Source2,21.0b110011001,12.1,11./+LongUnsignedImmediate::::xnor l
1589 "xnor 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1591 do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
1595 void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
1597 unsigned32 result = source1 ^ source2;
1598 TRACE_ALU3 (MY_INDEX, result, source1, source2);
1601 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
1602 "xor <UnsignedImmediate>, r<Source2>, r<Dest>"
1604 do_xor (_SD, rDest, vSource1, vSource2);
1606 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
1607 "xor r<Source1>, r<Source2>, r<Dest>"
1609 do_xor (_SD, rDest, vSource1, vSource2);
1611 31.Dest,26.Source2,21.0b110010110,12.1,11./+LongUnsignedImmediate::::xor l
1612 "xor 0x%08lx<LongUnsignedImmediate>, r<Source2>, r<Dest>"
1614 do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);