sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (hash): Update to be more accurate.
   4         (lookup_hash): Call hash rather than computing the hash
   5         code here.
   6         (do_format_1_2): Handle format 1 and format 2 instructions.
   7         Get operands correctly and call the target function.
   8         (do_format_6): Get operands correctly and call the target
   9         function.
  10         (do_formats_9_10): Rough cut so shift ops will work.
  11         (sim_resume): Tweak to deal with format 1 and format 2
  12         handling in a single funtion.  Don't update the PC
  13         for format 3 insns.  Fix typos.
  14         * simops.c: Slightly reorganize.  Add condition code handling
  15         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  16         and "not" instructions.
  17         * v850_sim.h (reg_t): Registers are 32bits.
  18         (_state): The V850 has 32 general registers.  Add a 32bit
  19         psw and pc register too.  Add accessor macros
  20
  21         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  22         changes from the d10v simulator.
  23
  24         * simops.c: Add shift support.
  25
  26         * simops.c: Add multiply & divide support.  Abort for system
  27         instructions.
  28
  29         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  30         and subr.  No condition codes yet.
  31
  32 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  33
  34         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  35         gencode.c, interp.c, simops.c: Created.
  36