4 /* General config options */
7 #define WITH_MODULO_MEMORY 1
8 #define WITH_WATCHPOINTS 1
11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
13 #define WITH_TARGET_WORD_MSB 31
16 #include "sim-basics.h"
17 #include "sim-signal.h"
20 typedef address_word sim_cia
;
22 typedef struct _sim_cpu SIM_CPU
;
31 typedef unsigned8 uint8
;
32 typedef signed16 int16
;
33 typedef unsigned16 uint16
;
34 typedef signed32 int32
;
35 typedef unsigned32 uint32
;
36 typedef unsigned32 reg_t
;
37 typedef unsigned64 reg64_t
;
40 /* The current state of the processor; registers, memory, etc. */
42 typedef struct _v850_regs
{
43 reg_t regs
[32]; /* general-purpose registers */
44 reg_t sregs
[32]; /* system registers, including psw */
46 int dummy_mem
; /* where invalid accesses go */
47 reg_t mpu0_sregs
[28]; /* mpu0 system registers */
48 reg_t mpu1_sregs
[28]; /* mpu1 system registers */
49 reg_t fpu_sregs
[28]; /* fpu system registers */
50 reg_t selID_sregs
[7][32]; /* system registers, selID 1 thru selID 7 */
51 reg64_t vregs
[32]; /* vector registers. */
56 /* ... simulator specific members ... */
58 reg_t psw_mask
; /* only allow non-reserved bits to be set */
59 sim_event
*pending_nmi
;
60 /* ... base type ... */
65 sim_cpu
*cpu
[MAX_NR_PROCESSORS
];
76 /* For compatibility, until all functions converted to passing
77 SIM_DESC as an argument */
78 extern SIM_DESC simulator
;
81 #define V850_ROM_SIZE 0x8000
82 #define V850_LOW_END 0x200000
83 #define V850_HIGH_START 0xffe000
86 /* Because we are still using the old semantic table, provide compat
87 macro's that store the instruction where the old simops expects
92 OP
[0] = inst
& 0x1f; /* RRRRR -> reg1 */
93 OP
[1] = (inst
>> 11) & 0x1f; /* rrrrr -> reg2 */
94 OP
[2] = (inst
>> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
100 OP[0] = instruction_0 & 0x1f; \
101 OP[1] = (instruction_0 >> 11) & 0x1f; \
103 OP[3] = instruction_0
105 #define COMPAT_1(CALL) \
112 OP[0] = instruction_0 & 0x1f; \
113 OP[1] = (instruction_0 >> 11) & 0x1f; \
114 OP[2] = instruction_1; \
115 OP[3] = (instruction_1 << 16) | instruction_0
117 #define COMPAT_2(CALL) \
124 #define GR ((CPU)->reg.regs)
125 #define SR ((CPU)->reg.sregs)
126 #define VR ((CPU)->reg.vregs)
127 #define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
128 #define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
129 #define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
132 #define State (STATE_CPU (simulator, 0)->reg)
133 #define PC (State.pc)
135 #define SP (State.regs[SP_REGNO])
136 #define EP (State.regs[30])
138 #define EIPC (State.sregs[0])
139 #define EIPSW (State.sregs[1])
140 #define FEPC (State.sregs[2])
141 #define FEPSW (State.sregs[3])
142 #define ECR (State.sregs[4])
143 #define PSW (State.sregs[5])
145 #define EIIC (State.sregs[13])
146 #define FEIC (State.sregs[14])
147 #define DBIC (SR[15])
148 #define CTPC (SR[16])
149 #define CTPSW (SR[17])
150 #define DBPC (State.sregs[18])
151 #define DBPSW (State.sregs[19])
152 #define CTBP (State.sregs[20])
154 #define EIWR (SR[28])
155 #define FEWR (SR[29])
156 #define DBWR (SR[30])
157 #define BSEL (SR[31])
159 #define PSW_US BIT32 (8)
169 #define PSW_NPV (1<<18)
170 #define PSW_DMP (1<<17)
171 #define PSW_IMP (1<<16)
173 #define ECR_EICC 0x0000ffff
174 #define ECR_FECC 0xffff0000
178 #define FPSR (FPU_SR[6])
180 #define FPEPC (FPU_SR[7])
181 #define FPST (FPU_SR[8])
183 #define FPCC (FPU_SR[9])
184 #define FPCFG (FPU_SR[10])
185 #define FPCFG_REGNO 10
187 #define FPSR_DEM 0x00200000
188 #define FPSR_SEM 0x00100000
189 #define FPSR_RM 0x000c0000
190 #define FPSR_RN 0x00000000
191 #define FPSR_FS 0x00020000
192 #define FPSR_PR 0x00010000
194 #define FPSR_XC 0x0000fc00
195 #define FPSR_XCE 0x00008000
196 #define FPSR_XCV 0x00004000
197 #define FPSR_XCZ 0x00002000
198 #define FPSR_XCO 0x00001000
199 #define FPSR_XCU 0x00000800
200 #define FPSR_XCI 0x00000400
202 #define FPSR_XE 0x000003e0
203 #define FPSR_XEV 0x00000200
204 #define FPSR_XEZ 0x00000100
205 #define FPSR_XEO 0x00000080
206 #define FPSR_XEU 0x00000040
207 #define FPSR_XEI 0x00000020
209 #define FPSR_XP 0x0000001f
210 #define FPSR_XPV 0x00000010
211 #define FPSR_XPZ 0x00000008
212 #define FPSR_XPO 0x00000004
213 #define FPSR_XPU 0x00000002
214 #define FPSR_XPI 0x00000001
216 #define FPST_PR 0x00008000
217 #define FPST_XCE 0x00002000
218 #define FPST_XCV 0x00001000
219 #define FPST_XCZ 0x00000800
220 #define FPST_XCO 0x00000400
221 #define FPST_XCU 0x00000200
222 #define FPST_XCI 0x00000100
224 #define FPST_XPV 0x00000010
225 #define FPST_XPZ 0x00000008
226 #define FPST_XPO 0x00000004
227 #define FPST_XPU 0x00000002
228 #define FPST_XPI 0x00000001
230 #define FPCFG_RM 0x00000180
231 #define FPCFG_XEV 0x00000010
232 #define FPCFG_XEZ 0x00000008
233 #define FPCFG_XEO 0x00000004
234 #define FPCFG_XEU 0x00000002
235 #define FPCFG_XEI 0x00000001
240 #define CLEAR_FPCC(bbb)\
241 (FPSR &= ~(1 << (bbb+24)))
243 #define SET_FPCC(bbb)\
244 (FPSR |= 1 << (bbb+24))
246 #define TEST_FPCC(bbb)\
247 ((FPSR & (1 << (bbb+24))) != 0)
249 #define FPSR_GET_ROUND() \
250 (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
251 : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
252 : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
253 : sim_fpu_round_zero)
277 #define MPM (MPU1_SR[0])
278 #define MPC (MPU1_SR[1])
280 #define TID (MPU1_SR[2])
281 #define PPA (MPU1_SR[3])
282 #define PPM (MPU1_SR[4])
283 #define PPC (MPU1_SR[5])
284 #define DCC (MPU1_SR[6])
285 #define DCV0 (MPU1_SR[7])
286 #define DCV1 (MPU1_SR[8])
287 #define SPAL (MPU1_SR[10])
288 #define SPAU (MPU1_SR[11])
289 #define IPA0L (MPU1_SR[12])
290 #define IPA0U (MPU1_SR[13])
291 #define IPA1L (MPU1_SR[14])
292 #define IPA1U (MPU1_SR[15])
293 #define IPA2L (MPU1_SR[16])
294 #define IPA2U (MPU1_SR[17])
295 #define IPA3L (MPU1_SR[18])
296 #define IPA3U (MPU1_SR[19])
297 #define DPA0L (MPU1_SR[20])
298 #define DPA0U (MPU1_SR[21])
299 #define DPA1L (MPU1_SR[22])
300 #define DPA1U (MPU1_SR[23])
301 #define DPA2L (MPU1_SR[24])
302 #define DPA2U (MPU1_SR[25])
303 #define DPA3L (MPU1_SR[26])
304 #define DPA3U (MPU1_SR[27])
308 #define SPAL_SPS 0x10
310 #define VIP (MPU0_SR[0])
311 #define VMECR (MPU0_SR[4])
312 #define VMTID (MPU0_SR[5])
313 #define VMADR (MPU0_SR[6])
314 #define VPECR (MPU0_SR[8])
315 #define VPTID (MPU0_SR[9])
316 #define VPADR (MPU0_SR[10])
317 #define VDECR (MPU0_SR[12])
318 #define VDTID (MPU0_SR[13])
323 #define VMECR_VMX 0x2
324 #define VMECR_VMR 0x4
325 #define VMECR_VMW 0x8
326 #define VMECR_VMS 0x10
327 #define VMECR_VMRMW 0x20
328 #define VMECR_VMMS 0x40
330 #define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
334 #define IPE0 (IPA0L & IPA_IPE)
335 #define IPE1 (IPA1L & IPA_IPE)
336 #define IPE2 (IPA2L & IPA_IPE)
337 #define IPE3 (IPA3L & IPA_IPE)
338 #define IPX0 (IPA0L & IPA_IPX)
339 #define IPX1 (IPA1L & IPA_IPX)
340 #define IPX2 (IPA2L & IPA_IPX)
341 #define IPX3 (IPA3L & IPA_IPX)
342 #define IPR0 (IPA0L & IPA_IPR)
343 #define IPR1 (IPA1L & IPA_IPR)
344 #define IPR2 (IPA2L & IPA_IPR)
345 #define IPR3 (IPA3L & IPA_IPR)
347 #define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
351 #define DPE0 (DPA0L & DPA_DPE)
352 #define DPE1 (DPA1L & DPA_DPE)
353 #define DPE2 (DPA2L & DPA_DPE)
354 #define DPE3 (DPA3L & DPA_DPE)
355 #define DPR0 (DPA0L & DPA_DPR)
356 #define DPR1 (DPA1L & DPA_DPR)
357 #define DPR2 (DPA2L & DPA_DPR)
358 #define DPR3 (DPA3L & DPA_DPR)
359 #define DPW0 (DPA0L & DPA_DPW)
360 #define DPW1 (DPA1L & DPA_DPW)
361 #define DPW2 (DPA2L & DPA_DPW)
362 #define DPW3 (DPA3L & DPA_DPW)
365 #define DCC_DCE1 0x10000
367 #define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
368 #define PPC_PPC 0xfffffffe
370 #define PPC_PPM 0x0000fff8
373 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
375 /* sign-extend a 4-bit number */
376 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
378 /* sign-extend a 5-bit number */
379 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
381 /* sign-extend a 9-bit number */
382 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
384 /* sign-extend a 22-bit number */
385 #define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
387 /* sign extend a 40 bit number */
388 #define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
389 ^ (~UNSIGNED64 (0x7fffffffff))) \
390 + UNSIGNED64 (0x8000000000))
392 /* sign extend a 44 bit number */
393 #define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
394 ^ (~ UNSIGNED64 (0x7ffffffffff))) \
395 + UNSIGNED64 (0x80000000000))
397 /* sign extend a 60 bit number */
398 #define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
399 ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
400 + UNSIGNED64 (0x800000000000000))
402 /* No sign extension */
405 #define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
407 #define RLW(x) load_mem (x, 4)
409 /* Function declarations. */
412 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
414 #define IMEM16_IMMED(EA,N) \
415 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
416 PC, exec_map, (EA) + (N) * 2)
418 #define load_mem(ADDR,LEN) \
419 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
420 PC, read_map, (ADDR))
422 #define store_mem(ADDR,LEN,DATA) \
423 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
424 PC, write_map, (ADDR), (DATA))
427 /* compare cccc field against PSW */
428 int condition_met (unsigned code
);
431 /* Debug/tracing calls */
470 void trace_input (char *name
, enum op_types type
, int size
);
471 void trace_output (enum op_types result
);
472 void trace_result (int has_result
, unsigned32 result
);
474 extern int trace_num_values
;
475 extern unsigned32 trace_values
[];
476 extern unsigned32 trace_pc
;
477 extern const char *trace_name
;
478 extern int trace_module
;
480 #define TRACE_BRANCH0() \
482 if (TRACE_BRANCH_P (CPU)) { \
483 trace_module = TRACE_BRANCH_IDX; \
485 trace_name = itable[MY_INDEX].name; \
486 trace_num_values = 0; \
487 trace_result (1, (nia)); \
491 #define TRACE_BRANCH1(IN1) \
493 if (TRACE_BRANCH_P (CPU)) { \
494 trace_module = TRACE_BRANCH_IDX; \
496 trace_name = itable[MY_INDEX].name; \
497 trace_values[0] = (IN1); \
498 trace_num_values = 1; \
499 trace_result (1, (nia)); \
503 #define TRACE_BRANCH2(IN1, IN2) \
505 if (TRACE_BRANCH_P (CPU)) { \
506 trace_module = TRACE_BRANCH_IDX; \
508 trace_name = itable[MY_INDEX].name; \
509 trace_values[0] = (IN1); \
510 trace_values[1] = (IN2); \
511 trace_num_values = 2; \
512 trace_result (1, (nia)); \
516 #define TRACE_BRANCH3(IN1, IN2, IN3) \
518 if (TRACE_BRANCH_P (CPU)) { \
519 trace_module = TRACE_BRANCH_IDX; \
521 trace_name = itable[MY_INDEX].name; \
522 trace_values[0] = (IN1); \
523 trace_values[1] = (IN2); \
524 trace_values[2] = (IN3); \
525 trace_num_values = 3; \
526 trace_result (1, (nia)); \
530 #define TRACE_LD(ADDR,RESULT) \
532 if (TRACE_MEMORY_P (CPU)) { \
533 trace_module = TRACE_MEMORY_IDX; \
535 trace_name = itable[MY_INDEX].name; \
536 trace_values[0] = (ADDR); \
537 trace_num_values = 1; \
538 trace_result (1, (RESULT)); \
542 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
544 if (TRACE_MEMORY_P (CPU)) { \
545 trace_module = TRACE_MEMORY_IDX; \
547 trace_name = (NAME); \
548 trace_values[0] = (ADDR); \
549 trace_num_values = 1; \
550 trace_result (1, (RESULT)); \
554 #define TRACE_ST(ADDR,RESULT) \
556 if (TRACE_MEMORY_P (CPU)) { \
557 trace_module = TRACE_MEMORY_IDX; \
559 trace_name = itable[MY_INDEX].name; \
560 trace_values[0] = (ADDR); \
561 trace_num_values = 1; \
562 trace_result (1, (RESULT)); \
566 #define TRACE_FP_INPUT_FPU1(V0) \
568 if (TRACE_FPU_P (CPU)) \
571 sim_fpu_to64 (&f0, (V0)); \
572 trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
576 #define TRACE_FP_INPUT_FPU2(V0, V1) \
578 if (TRACE_FPU_P (CPU)) \
581 sim_fpu_to64 (&f0, (V0)); \
582 sim_fpu_to64 (&f1, (V1)); \
583 trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
587 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
589 if (TRACE_FPU_P (CPU)) \
591 unsigned64 f0, f1, f2; \
592 sim_fpu_to64 (&f0, (V0)); \
593 sim_fpu_to64 (&f1, (V1)); \
594 sim_fpu_to64 (&f2, (V2)); \
595 trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
599 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
601 if (TRACE_FPU_P (CPU)) \
605 TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
606 TRACE_IDX (data) = TRACE_FPU_IDX; \
607 sim_fpu_to64 (&f1, (V1)); \
608 sim_fpu_to64 (&f2, (V2)); \
609 save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
610 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
611 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
615 #define TRACE_FP_INPUT_WORD2(V0, V1) \
617 if (TRACE_FPU_P (CPU)) \
618 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
621 #define TRACE_FP_RESULT_FPU1(R0) \
623 if (TRACE_FPU_P (CPU)) \
626 sim_fpu_to64 (&f0, (R0)); \
627 trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
631 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
633 #define TRACE_FP_RESULT_WORD2(R0, R1) \
635 if (TRACE_FPU_P (CPU)) \
636 trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
640 #define trace_input(NAME, IN1, IN2)
641 #define trace_output(RESULT)
642 #define trace_result(HAS_RESULT, RESULT)
644 #define TRACE_ALU_INPUT0()
645 #define TRACE_ALU_INPUT1(IN0)
646 #define TRACE_ALU_INPUT2(IN0, IN1)
647 #define TRACE_ALU_INPUT2(IN0, IN1)
648 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
649 #define TRACE_ALU_RESULT(RESULT)
651 #define TRACE_BRANCH0()
652 #define TRACE_BRANCH1(IN1)
653 #define TRACE_BRANCH2(IN1, IN2)
654 #define TRACE_BRANCH2(IN1, IN2, IN3)
656 #define TRACE_LD(ADDR,RESULT)
657 #define TRACE_ST(ADDR,RESULT)
661 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
662 #define GPR_CLEAR(N) (State.regs[(N)] = 0)
664 extern void divun ( unsigned int N
,
665 unsigned long int als
,
666 unsigned long int sfi
,
667 unsigned32
/*unsigned long int*/ * quotient_ptr
,
668 unsigned32
/*unsigned long int*/ * remainder_ptr
,
671 extern void divn ( unsigned int N
,
672 unsigned long int als
,
673 unsigned long int sfi
,
674 signed32
/*signed long int*/ * quotient_ptr
,
675 signed32
/*signed long int*/ * remainder_ptr
,
678 extern int type1_regs
[];
679 extern int type2_regs
[];
680 extern int type3_regs
[];
682 #define SESR_OV (1 << 0)
683 #define SESR_SOV (1 << 1)
685 #define SESR (State.sregs[12])
687 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
688 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
689 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
690 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
698 SESR |= SESR_OV | SESR_SOV; \
701 else if (z < -0x8000) \
703 SESR |= SESR_OV | SESR_SOV; \
714 if (z > 0x7fffffff) \
716 SESR |= SESR_OV | SESR_SOV; \
719 else if (z < -0x80000000) \
721 SESR |= SESR_OV | SESR_SOV; \
731 signed64 z = (X) & 0xffff; \
734 SESR |= SESR_OV | SESR_SOV; \
737 else if (z & 0x8000) \
739 z = (- z) & 0xffff; \
748 signed64 z = (X) & 0xffffffff; \
749 if (z == 0x80000000) \
751 SESR |= SESR_OV | SESR_SOV; \
754 else if (z & 0x80000000) \
756 z = (- z) & 0xffffffff; \
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