sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* General config options */
   5
   6 #define WITH_CORE
   7 #define WITH_MODULO_MEMORY 1
   8 #define WITH_WATCHPOINTS 1
   9
  10
  11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
  12
  13 #define WITH_TARGET_WORD_MSB 31
  14
  15 #include "config.h"
  16 #include "sim-basics.h"
  17 #include "sim-signal.h"
  18 #include "sim-fpu.h"
  19 #include "sim-base.h"
  20
  21 #include "simops.h"
  22 #include "bfd.h"
  23
  24
  25 typedef signed8 int8;
  26 typedef unsigned8 uint8;
  27 typedef signed16 int16;
  28 typedef unsigned16 uint16;
  29 typedef signed32 int32;
  30 typedef unsigned32 uint32;
  31 typedef unsigned32 reg_t;
  32 typedef unsigned64 reg64_t;
  33
  34
  35 /* The current state of the processor; registers, memory, etc.  */
  36
  37 typedef struct _v850_regs {
  38   reg_t regs[32];               /* general-purpose registers */
  39   reg_t sregs[32];              /* system registers, including psw */
  40   reg_t pc;
  41   int dummy_mem;                /* where invalid accesses go */
  42   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  43   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  44   reg_t fpu_sregs[28];          /* fpu system registers */
  45   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  46   reg64_t vregs[32];            /* vector registers.  */
  47 } v850_regs;
  48
  49 struct _sim_cpu
  50 {
  51   /* ... simulator specific members ... */
  52   v850_regs reg;
  53   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  54   sim_event *pending_nmi;
  55   /* ... base type ... */
  56   sim_cpu_base base;
  57 };
  58
  59 struct sim_state {
  60   sim_cpu *cpu[MAX_NR_PROCESSORS];
  61 #if 0
  62   SIM_ADDR rom_size;
  63   SIM_ADDR low_end;
  64   SIM_ADDR high_start;
  65   SIM_ADDR high_base;
  66   void *mem;
  67 #endif
  68   sim_state_base base;
  69 };
  70
  71 /* For compatibility, until all functions converted to passing
  72    SIM_DESC as an argument */
  73 extern SIM_DESC simulator;
  74
  75
  76 #define V850_ROM_SIZE 0x8000
  77 #define V850_LOW_END 0x200000
  78 #define V850_HIGH_START 0xffe000
  79
  80
  81 /* Because we are still using the old semantic table, provide compat
  82    macro's that store the instruction where the old simops expects
  83    it. */
  84
  85 extern uint32 OP[4];
  86 #if 0
  87 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  88 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  89 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  90 OP[3] = inst;
  91 #endif
  92
  93 #define SAVE_1 \
  94 PC = cia; \
  95 OP[0] = instruction_0 & 0x1f; \
  96 OP[1] = (instruction_0 >> 11) & 0x1f; \
  97 OP[2] = 0; \
  98 OP[3] = instruction_0
  99
 100 #define COMPAT_1(CALL) \
 101 SAVE_1; \
 102 PC += (CALL); \
 103 nia = PC
 104
 105 #define SAVE_2 \
 106 PC = cia; \
 107 OP[0] = instruction_0 & 0x1f; \
 108 OP[1] = (instruction_0 >> 11) & 0x1f; \
 109 OP[2] = instruction_1; \
 110 OP[3] = (instruction_1 << 16) | instruction_0
 111
 112 #define COMPAT_2(CALL) \
 113 SAVE_2; \
 114 PC += (CALL); \
 115 nia = PC
 116
 117
 118 /* new */
 119 #define GR  ((CPU)->reg.regs)
 120 #define SR  ((CPU)->reg.sregs)
 121 #define VR  ((CPU)->reg.vregs)
 122 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
 123 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
 124 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
 125
 126 /* old */
 127 #define State    (STATE_CPU (simulator, 0)->reg)
 128 #define PC      (State.pc)
 129 #define SP_REGNO        3
 130 #define SP      (State.regs[SP_REGNO])
 131 #define EP      (State.regs[30])
 132
 133 #define EIPC  (State.sregs[0])
 134 #define EIPSW (State.sregs[1])
 135 #define FEPC  (State.sregs[2])
 136 #define FEPSW (State.sregs[3])
 137 #define ECR   (State.sregs[4])
 138 #define PSW   (State.sregs[5])
 139 #define PSW_REGNO   5
 140 #define EIIC  (State.sregs[13])
 141 #define FEIC  (State.sregs[14])
 142 #define DBIC  (SR[15])
 143 #define CTPC  (SR[16])
 144 #define CTPSW (SR[17])
 145 #define DBPC  (State.sregs[18])
 146 #define DBPSW (State.sregs[19])
 147 #define CTBP  (State.sregs[20])
 148 #define DIR   (SR[21])
 149 #define EIWR  (SR[28])
 150 #define FEWR  (SR[29])
 151 #define DBWR  (SR[30])
 152 #define BSEL  (SR[31])
 153
 154 #define PSW_US BIT32 (8)
 155 #define PSW_NP 0x80
 156 #define PSW_EP 0x40
 157 #define PSW_ID 0x20
 158 #define PSW_SAT 0x10
 159 #define PSW_CY 0x8
 160 #define PSW_OV 0x4
 161 #define PSW_S 0x2
 162 #define PSW_Z 0x1
 163
 164 #define PSW_NPV (1<<18)
 165 #define PSW_DMP (1<<17)
 166 #define PSW_IMP (1<<16)
 167
 168 #define ECR_EICC 0x0000ffff
 169 #define ECR_FECC 0xffff0000
 170
 171 /* FPU */
 172
 173 #define FPSR  (FPU_SR[6])
 174 #define FPSR_REGNO 6
 175 #define FPEPC (FPU_SR[7])
 176 #define FPST  (FPU_SR[8])
 177 #define FPST_REGNO 8
 178 #define FPCC  (FPU_SR[9])
 179 #define FPCFG (FPU_SR[10])
 180 #define FPCFG_REGNO 10
 181
 182 #define FPSR_DEM  0x00200000
 183 #define FPSR_SEM  0x00100000
 184 #define FPSR_RM   0x000c0000
 185 #define FPSR_RN   0x00000000
 186 #define FPSR_FS   0x00020000
 187 #define FPSR_PR   0x00010000
 188
 189 #define FPSR_XC   0x0000fc00
 190 #define FPSR_XCE  0x00008000
 191 #define FPSR_XCV  0x00004000
 192 #define FPSR_XCZ  0x00002000
 193 #define FPSR_XCO  0x00001000
 194 #define FPSR_XCU  0x00000800
 195 #define FPSR_XCI  0x00000400
 196
 197 #define FPSR_XE   0x000003e0
 198 #define FPSR_XEV  0x00000200
 199 #define FPSR_XEZ  0x00000100
 200 #define FPSR_XEO  0x00000080
 201 #define FPSR_XEU  0x00000040
 202 #define FPSR_XEI  0x00000020
 203
 204 #define FPSR_XP   0x0000001f
 205 #define FPSR_XPV  0x00000010
 206 #define FPSR_XPZ  0x00000008
 207 #define FPSR_XPO  0x00000004
 208 #define FPSR_XPU  0x00000002
 209 #define FPSR_XPI  0x00000001
 210
 211 #define FPST_PR   0x00008000
 212 #define FPST_XCE  0x00002000
 213 #define FPST_XCV  0x00001000
 214 #define FPST_XCZ  0x00000800
 215 #define FPST_XCO  0x00000400
 216 #define FPST_XCU  0x00000200
 217 #define FPST_XCI  0x00000100
 218
 219 #define FPST_XPV  0x00000010
 220 #define FPST_XPZ  0x00000008
 221 #define FPST_XPO  0x00000004
 222 #define FPST_XPU  0x00000002
 223 #define FPST_XPI  0x00000001
 224
 225 #define FPCFG_RM   0x00000180
 226 #define FPCFG_XEV  0x00000010
 227 #define FPCFG_XEZ  0x00000008
 228 #define FPCFG_XEO  0x00000004
 229 #define FPCFG_XEU  0x00000002
 230 #define FPCFG_XEI  0x00000001
 231
 232 #define GET_FPCC()\
 233  ((FPSR >> 24) &0xf)
 234
 235 #define CLEAR_FPCC(bbb)\
 236   (FPSR &= ~(1 << (bbb+24)))
 237
 238 #define SET_FPCC(bbb)\
 239  (FPSR |= 1 << (bbb+24))
 240
 241 #define TEST_FPCC(bbb)\
 242   ((FPSR & (1 << (bbb+24))) != 0)
 243
 244 #define FPSR_GET_ROUND()                                        \
 245   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 246    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 247    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 248    : sim_fpu_round_zero)
 249
 250
 251 enum FPU_COMPARE {
 252   FPU_CMP_F = 0,
 253   FPU_CMP_UN,
 254   FPU_CMP_EQ,
 255   FPU_CMP_UEQ,
 256   FPU_CMP_OLT,
 257   FPU_CMP_ULT,
 258   FPU_CMP_OLE,
 259   FPU_CMP_ULE,
 260   FPU_CMP_SF,
 261   FPU_CMP_NGLE,
 262   FPU_CMP_SEQ,
 263   FPU_CMP_NGL,
 264   FPU_CMP_LT,
 265   FPU_CMP_NGE,
 266   FPU_CMP_LE,
 267   FPU_CMP_NGT
 268 };
 269
 270
 271 /* MPU */
 272 #define MPM     (MPU1_SR[0])
 273 #define MPC     (MPU1_SR[1])
 274 #define MPC_REGNO 1
 275 #define TID     (MPU1_SR[2])
 276 #define PPA     (MPU1_SR[3])
 277 #define PPM     (MPU1_SR[4])
 278 #define PPC     (MPU1_SR[5])
 279 #define DCC     (MPU1_SR[6])
 280 #define DCV0    (MPU1_SR[7])
 281 #define DCV1    (MPU1_SR[8])
 282 #define SPAL    (MPU1_SR[10])
 283 #define SPAU    (MPU1_SR[11])
 284 #define IPA0L   (MPU1_SR[12])
 285 #define IPA0U   (MPU1_SR[13])
 286 #define IPA1L   (MPU1_SR[14])
 287 #define IPA1U   (MPU1_SR[15])
 288 #define IPA2L   (MPU1_SR[16])
 289 #define IPA2U   (MPU1_SR[17])
 290 #define IPA3L   (MPU1_SR[18])
 291 #define IPA3U   (MPU1_SR[19])
 292 #define DPA0L   (MPU1_SR[20])
 293 #define DPA0U   (MPU1_SR[21])
 294 #define DPA1L   (MPU1_SR[22])
 295 #define DPA1U   (MPU1_SR[23])
 296 #define DPA2L   (MPU1_SR[24])
 297 #define DPA2U   (MPU1_SR[25])
 298 #define DPA3L   (MPU1_SR[26])
 299 #define DPA3U   (MPU1_SR[27])
 300
 301 #define PPC_PPE 0x1
 302 #define SPAL_SPE 0x1
 303 #define SPAL_SPS 0x10
 304
 305 #define VIP     (MPU0_SR[0])
 306 #define VMECR   (MPU0_SR[4])
 307 #define VMTID   (MPU0_SR[5])
 308 #define VMADR   (MPU0_SR[6])
 309 #define VPECR   (MPU0_SR[8])
 310 #define VPTID   (MPU0_SR[9])
 311 #define VPADR   (MPU0_SR[10])
 312 #define VDECR   (MPU0_SR[12])
 313 #define VDTID   (MPU0_SR[13])
 314
 315 #define MPM_AUE 0x2
 316 #define MPM_MPE 0x1
 317
 318 #define VMECR_VMX   0x2
 319 #define VMECR_VMR   0x4
 320 #define VMECR_VMW   0x8
 321 #define VMECR_VMS   0x10
 322 #define VMECR_VMRMW 0x20
 323 #define VMECR_VMMS  0x40
 324
 325 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 326 #define IPA_IPE 0x1
 327 #define IPA_IPX 0x2
 328 #define IPA_IPR 0x4
 329 #define IPE0    (IPA0L & IPA_IPE)
 330 #define IPE1    (IPA1L & IPA_IPE)
 331 #define IPE2    (IPA2L & IPA_IPE)
 332 #define IPE3    (IPA3L & IPA_IPE)
 333 #define IPX0    (IPA0L & IPA_IPX)
 334 #define IPX1    (IPA1L & IPA_IPX)
 335 #define IPX2    (IPA2L & IPA_IPX)
 336 #define IPX3    (IPA3L & IPA_IPX)
 337 #define IPR0    (IPA0L & IPA_IPR)
 338 #define IPR1    (IPA1L & IPA_IPR)
 339 #define IPR2    (IPA2L & IPA_IPR)
 340 #define IPR3    (IPA3L & IPA_IPR)
 341
 342 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 343 #define DPA_DPE 0x1
 344 #define DPA_DPR 0x4
 345 #define DPA_DPW 0x8
 346 #define DPE0    (DPA0L & DPA_DPE)
 347 #define DPE1    (DPA1L & DPA_DPE)
 348 #define DPE2    (DPA2L & DPA_DPE)
 349 #define DPE3    (DPA3L & DPA_DPE)
 350 #define DPR0    (DPA0L & DPA_DPR)
 351 #define DPR1    (DPA1L & DPA_DPR)
 352 #define DPR2    (DPA2L & DPA_DPR)
 353 #define DPR3    (DPA3L & DPA_DPR)
 354 #define DPW0    (DPA0L & DPA_DPW)
 355 #define DPW1    (DPA1L & DPA_DPW)
 356 #define DPW2    (DPA2L & DPA_DPW)
 357 #define DPW3    (DPA3L & DPA_DPW)
 358
 359 #define DCC_DCE0 0x1
 360 #define DCC_DCE1 0x10000
 361
 362 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 363 #define PPC_PPC 0xfffffffe
 364 #define PPC_PPE 0x1
 365 #define PPC_PPM 0x0000fff8
 366
 367
 368 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 369
 370 /* sign-extend a 4-bit number */
 371 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 372
 373 /* sign-extend a 5-bit number */
 374 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 375
 376 /* sign-extend a 9-bit number */
 377 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 378
 379 /* sign-extend a 22-bit number */
 380 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 381
 382 /* sign extend a 40 bit number */
 383 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 384                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 385                          + UNSIGNED64 (0x8000000000))
 386
 387 /* sign extend a 44 bit number */
 388 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 389                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 390                          + UNSIGNED64 (0x80000000000))
 391
 392 /* sign extend a 60 bit number */
 393 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 394                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 395                          + UNSIGNED64 (0x800000000000000))
 396
 397 /* No sign extension */
 398 #define NOP(x)          (x)
 399
 400 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 401
 402 #define RLW(x) load_mem (x, 4)
 403
 404 /* Function declarations.  */
 405
 406 #define IMEM16(EA) \
 407 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 408
 409 #define IMEM16_IMMED(EA,N) \
 410 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 411                          PC, exec_map, (EA) + (N) * 2)
 412
 413 #define load_mem(ADDR,LEN) \
 414 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 415                                PC, read_map, (ADDR))
 416
 417 #define store_mem(ADDR,LEN,DATA) \
 418 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 419                                 PC, write_map, (ADDR), (DATA))
 420
 421
 422 /* compare cccc field against PSW */
 423 int condition_met (unsigned code);
 424
 425
 426 /* Debug/tracing calls */
 427
 428 enum op_types
 429 {
 430   OP_UNKNOWN,
 431   OP_NONE,
 432   OP_TRAP,
 433   OP_REG,
 434   OP_REG_REG,
 435   OP_REG_REG_CMP,
 436   OP_REG_REG_MOVE,
 437   OP_IMM_REG,
 438   OP_IMM_REG_CMP,
 439   OP_IMM_REG_MOVE,
 440   OP_COND_BR,
 441   OP_LOAD16,
 442   OP_STORE16,
 443   OP_LOAD32,
 444   OP_STORE32,
 445   OP_JUMP,
 446   OP_IMM_REG_REG,
 447   OP_UIMM_REG_REG,
 448   OP_IMM16_REG_REG,
 449   OP_UIMM16_REG_REG,
 450   OP_BIT,
 451   OP_EX1,
 452   OP_EX2,
 453   OP_LDSR,
 454   OP_STSR,
 455   OP_BIT_CHANGE,
 456   OP_REG_REG_REG,
 457   OP_REG_REG3,
 458   OP_IMM_REG_REG_REG,
 459   OP_PUSHPOP1,
 460   OP_PUSHPOP2,
 461   OP_PUSHPOP3,
 462 };
 463
 464 #ifdef DEBUG
 465 void trace_input (char *name, enum op_types type, int size);
 466 void trace_output (enum op_types result);
 467 void trace_result (int has_result, unsigned32 result);
 468
 469 extern int trace_num_values;
 470 extern unsigned32 trace_values[];
 471 extern unsigned32 trace_pc;
 472 extern const char *trace_name;
 473 extern int trace_module;
 474
 475 #define TRACE_BRANCH0() \
 476 do { \
 477   if (TRACE_BRANCH_P (CPU)) { \
 478     trace_module = TRACE_BRANCH_IDX; \
 479     trace_pc = cia; \
 480     trace_name = itable[MY_INDEX].name; \
 481     trace_num_values = 0; \
 482     trace_result (1, (nia)); \
 483   } \
 484 } while (0)
 485
 486 #define TRACE_BRANCH1(IN1) \
 487 do { \
 488   if (TRACE_BRANCH_P (CPU)) { \
 489     trace_module = TRACE_BRANCH_IDX; \
 490     trace_pc = cia; \
 491     trace_name = itable[MY_INDEX].name; \
 492     trace_values[0] = (IN1); \
 493     trace_num_values = 1; \
 494     trace_result (1, (nia)); \
 495   } \
 496 } while (0)
 497
 498 #define TRACE_BRANCH2(IN1, IN2) \
 499 do { \
 500   if (TRACE_BRANCH_P (CPU)) { \
 501     trace_module = TRACE_BRANCH_IDX; \
 502     trace_pc = cia; \
 503     trace_name = itable[MY_INDEX].name; \
 504     trace_values[0] = (IN1); \
 505     trace_values[1] = (IN2); \
 506     trace_num_values = 2; \
 507     trace_result (1, (nia)); \
 508   } \
 509 } while (0)
 510
 511 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 512 do { \
 513   if (TRACE_BRANCH_P (CPU)) { \
 514     trace_module = TRACE_BRANCH_IDX; \
 515     trace_pc = cia; \
 516     trace_name = itable[MY_INDEX].name; \
 517     trace_values[0] = (IN1); \
 518     trace_values[1] = (IN2); \
 519     trace_values[2] = (IN3); \
 520     trace_num_values = 3; \
 521     trace_result (1, (nia)); \
 522   } \
 523 } while (0)
 524
 525 #define TRACE_LD(ADDR,RESULT) \
 526 do { \
 527   if (TRACE_MEMORY_P (CPU)) { \
 528     trace_module = TRACE_MEMORY_IDX; \
 529     trace_pc = cia; \
 530     trace_name = itable[MY_INDEX].name; \
 531     trace_values[0] = (ADDR); \
 532     trace_num_values = 1; \
 533     trace_result (1, (RESULT)); \
 534   } \
 535 } while (0)
 536
 537 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 538 do { \
 539   if (TRACE_MEMORY_P (CPU)) { \
 540     trace_module = TRACE_MEMORY_IDX; \
 541     trace_pc = cia; \
 542     trace_name = (NAME); \
 543     trace_values[0] = (ADDR); \
 544     trace_num_values = 1; \
 545     trace_result (1, (RESULT)); \
 546   } \
 547 } while (0)
 548
 549 #define TRACE_ST(ADDR,RESULT) \
 550 do { \
 551   if (TRACE_MEMORY_P (CPU)) { \
 552     trace_module = TRACE_MEMORY_IDX; \
 553     trace_pc = cia; \
 554     trace_name = itable[MY_INDEX].name; \
 555     trace_values[0] = (ADDR); \
 556     trace_num_values = 1; \
 557     trace_result (1, (RESULT)); \
 558   } \
 559 } while (0)
 560
 561 #define TRACE_FP_INPUT_FPU1(V0) \
 562 do { \
 563   if (TRACE_FPU_P (CPU)) \
 564     { \
 565       unsigned64 f0; \
 566       sim_fpu_to64 (&f0, (V0)); \
 567       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 568     } \
 569 } while (0)
 570
 571 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 572 do { \
 573   if (TRACE_FPU_P (CPU)) \
 574     { \
 575       unsigned64 f0, f1; \
 576       sim_fpu_to64 (&f0, (V0)); \
 577       sim_fpu_to64 (&f1, (V1)); \
 578       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 579     } \
 580 } while (0)
 581
 582 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 583 do { \
 584   if (TRACE_FPU_P (CPU)) \
 585     { \
 586       unsigned64 f0, f1, f2; \
 587       sim_fpu_to64 (&f0, (V0)); \
 588       sim_fpu_to64 (&f1, (V1)); \
 589       sim_fpu_to64 (&f2, (V2)); \
 590       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 591     } \
 592 } while (0)
 593
 594 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 595 do { \
 596   if (TRACE_FPU_P (CPU)) \
 597     { \
 598       int d0 = (V0); \
 599       unsigned64 f1, f2; \
 600       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 601       TRACE_IDX (data) = TRACE_FPU_IDX; \
 602       sim_fpu_to64 (&f1, (V1)); \
 603       sim_fpu_to64 (&f2, (V2)); \
 604       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 605       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 606       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 607     } \
 608 } while (0)
 609
 610 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 611 do { \
 612   if (TRACE_FPU_P (CPU)) \
 613     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 614 } while (0)
 615
 616 #define TRACE_FP_RESULT_FPU1(R0) \
 617 do { \
 618   if (TRACE_FPU_P (CPU)) \
 619     { \
 620       unsigned64 f0; \
 621       sim_fpu_to64 (&f0, (R0)); \
 622       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 623     } \
 624 } while (0)
 625
 626 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 627
 628 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 629 do { \
 630   if (TRACE_FPU_P (CPU)) \
 631     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 632 } while (0)
 633
 634 #else
 635 #define trace_input(NAME, IN1, IN2)
 636 #define trace_output(RESULT)
 637 #define trace_result(HAS_RESULT, RESULT)
 638
 639 #define TRACE_ALU_INPUT0()
 640 #define TRACE_ALU_INPUT1(IN0)
 641 #define TRACE_ALU_INPUT2(IN0, IN1)
 642 #define TRACE_ALU_INPUT2(IN0, IN1)
 643 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 644 #define TRACE_ALU_RESULT(RESULT)
 645
 646 #define TRACE_BRANCH0()
 647 #define TRACE_BRANCH1(IN1)
 648 #define TRACE_BRANCH2(IN1, IN2)
 649 #define TRACE_BRANCH2(IN1, IN2, IN3)
 650
 651 #define TRACE_LD(ADDR,RESULT)
 652 #define TRACE_ST(ADDR,RESULT)
 653
 654 #endif
 655
 656 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 657 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 658
 659 extern void divun ( unsigned int       N,
 660                     unsigned long int  als,
 661                     unsigned long int  sfi,
 662                     unsigned32 /*unsigned long int*/ *  quotient_ptr,
 663                     unsigned32 /*unsigned long int*/ *  remainder_ptr,
 664                     int *overflow_ptr
 665                     );
 666 extern void divn ( unsigned int       N,
 667                    unsigned long int  als,
 668                    unsigned long int  sfi,
 669                    signed32 /*signed long int*/ *  quotient_ptr,
 670                    signed32 /*signed long int*/ *  remainder_ptr,
 671                    int *overflow_ptr
 672                    );
 673 extern int type1_regs[];
 674 extern int type2_regs[];
 675 extern int type3_regs[];
 676
 677 #define SESR_OV   (1 << 0)
 678 #define SESR_SOV  (1 << 1)
 679
 680 #define SESR      (State.sregs[12])
 681
 682 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 683 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 684 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 685 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 686
 687 #define SAT16(X)                        \
 688   do                                    \
 689     {                                   \
 690       signed64 z = (X);                 \
 691       if (z > 0x7fff)                   \
 692         {                               \
 693           SESR |= SESR_OV | SESR_SOV;   \
 694           z = 0x7fff;                   \
 695         }                               \
 696       else if (z < -0x8000)             \
 697         {                               \
 698           SESR |= SESR_OV | SESR_SOV;   \
 699           z = - 0x8000;                 \
 700         }                               \
 701       (X) = z;                          \
 702     }                                   \
 703   while (0)
 704
 705 #define SAT32(X)                        \
 706   do                                    \
 707     {                                   \
 708       signed64 z = (X);                 \
 709       if (z > 0x7fffffff)               \
 710         {                               \
 711           SESR |= SESR_OV | SESR_SOV;   \
 712           z = 0x7fffffff;               \
 713         }                               \
 714       else if (z < -0x80000000)         \
 715         {                               \
 716           SESR |= SESR_OV | SESR_SOV;   \
 717           z = - 0x80000000;             \
 718         }                               \
 719       (X) = z;                          \
 720     }                                   \
 721   while (0)
 722
 723 #define ABS16(X)                        \
 724   do                                    \
 725     {                                   \
 726       signed64 z = (X) & 0xffff;        \
 727       if (z == 0x8000)                  \
 728         {                               \
 729           SESR |= SESR_OV | SESR_SOV;   \
 730           z = 0x7fff;                   \
 731         }                               \
 732       else if (z & 0x8000)              \
 733         {                               \
 734           z = (- z) & 0xffff;           \
 735         }                               \
 736       (X) = z;                          \
 737     }                                   \
 738   while (0)
 739
 740 #define ABS32(X)                        \
 741   do                                    \
 742     {                                   \
 743       signed64 z = (X) & 0xffffffff;    \
 744       if (z == 0x80000000)              \
 745         {                               \
 746           SESR |= SESR_OV | SESR_SOV;   \
 747           z = 0x7fffffff;               \
 748         }                               \
 749       else if (z & 0x80000000)          \
 750         {                               \
 751           z = (- z) & 0xffffffff;       \
 752         }                               \
 753       (X) = z;                          \
 754     }                                   \
 755   while (0)
 756
 757 #endif