sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* General config options */
   5
   6 #define WITH_CORE
   7 #define WITH_MODULO_MEMORY 1
   8 #define WITH_WATCHPOINTS 1
   9
  10
  11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
  12
  13 #define WITH_TARGET_WORD_MSB 31
  14
  15 #include "config.h"
  16 #include "sim-basics.h"
  17 #include "sim-signal.h"
  18 #include "sim-fpu.h"
  19
  20 typedef address_word sim_cia;
  21
  22 #include "sim-base.h"
  23
  24 #include "simops.h"
  25 #include "bfd.h"
  26
  27
  28 typedef signed8 int8;
  29 typedef unsigned8 uint8;
  30 typedef signed16 int16;
  31 typedef unsigned16 uint16;
  32 typedef signed32 int32;
  33 typedef unsigned32 uint32;
  34 typedef unsigned32 reg_t;
  35 typedef unsigned64 reg64_t;
  36
  37
  38 /* The current state of the processor; registers, memory, etc.  */
  39
  40 typedef struct _v850_regs {
  41   reg_t regs[32];               /* general-purpose registers */
  42   reg_t sregs[32];              /* system registers, including psw */
  43   reg_t pc;
  44   int dummy_mem;                /* where invalid accesses go */
  45   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  46   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  47   reg_t fpu_sregs[28];          /* fpu system registers */
  48   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  49   reg64_t vregs[32];            /* vector registers.  */
  50 } v850_regs;
  51
  52 struct _sim_cpu
  53 {
  54   /* ... simulator specific members ... */
  55   v850_regs reg;
  56   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  57   sim_event *pending_nmi;
  58   /* ... base type ... */
  59   sim_cpu_base base;
  60 };
  61
  62 #define CIA_GET(CPU) ((CPU)->reg.pc + 0)
  63 #define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
  64
  65 struct sim_state {
  66   sim_cpu cpu[MAX_NR_PROCESSORS];
  67 #if (WITH_SMP)
  68 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  69 #else
  70 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  71 #endif
  72 #if 0
  73   SIM_ADDR rom_size;
  74   SIM_ADDR low_end;
  75   SIM_ADDR high_start;
  76   SIM_ADDR high_base;
  77   void *mem;
  78 #endif
  79   sim_state_base base;
  80 };
  81
  82 /* For compatibility, until all functions converted to passing
  83    SIM_DESC as an argument */
  84 extern SIM_DESC simulator;
  85
  86
  87 #define V850_ROM_SIZE 0x8000
  88 #define V850_LOW_END 0x200000
  89 #define V850_HIGH_START 0xffe000
  90
  91
  92 /* Because we are still using the old semantic table, provide compat
  93    macro's that store the instruction where the old simops expects
  94    it. */
  95
  96 extern uint32 OP[4];
  97 #if 0
  98 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  99 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
 100 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
 101 OP[3] = inst;
 102 #endif
 103
 104 #define SAVE_1 \
 105 PC = cia; \
 106 OP[0] = instruction_0 & 0x1f; \
 107 OP[1] = (instruction_0 >> 11) & 0x1f; \
 108 OP[2] = 0; \
 109 OP[3] = instruction_0
 110
 111 #define COMPAT_1(CALL) \
 112 SAVE_1; \
 113 PC += (CALL); \
 114 nia = PC
 115
 116 #define SAVE_2 \
 117 PC = cia; \
 118 OP[0] = instruction_0 & 0x1f; \
 119 OP[1] = (instruction_0 >> 11) & 0x1f; \
 120 OP[2] = instruction_1; \
 121 OP[3] = (instruction_1 << 16) | instruction_0
 122
 123 #define COMPAT_2(CALL) \
 124 SAVE_2; \
 125 PC += (CALL); \
 126 nia = PC
 127
 128
 129 /* new */
 130 #define GR  ((CPU)->reg.regs)
 131 #define SR  ((CPU)->reg.sregs)
 132 #define VR  ((CPU)->reg.vregs)
 133 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
 134 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
 135 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
 136
 137 /* old */
 138 #define State    (STATE_CPU (simulator, 0)->reg)
 139 #define PC      (State.pc)
 140 #define SP_REGNO        3
 141 #define SP      (State.regs[SP_REGNO])
 142 #define EP      (State.regs[30])
 143
 144 #define EIPC  (State.sregs[0])
 145 #define EIPSW (State.sregs[1])
 146 #define FEPC  (State.sregs[2])
 147 #define FEPSW (State.sregs[3])
 148 #define ECR   (State.sregs[4])
 149 #define PSW   (State.sregs[5])
 150 #define PSW_REGNO   5
 151 #define EIIC  (State.sregs[13])
 152 #define FEIC  (State.sregs[14])
 153 #define DBIC  (SR[15])
 154 #define CTPC  (SR[16])
 155 #define CTPSW (SR[17])
 156 #define DBPC  (State.sregs[18])
 157 #define DBPSW (State.sregs[19])
 158 #define CTBP  (State.sregs[20])
 159 #define DIR   (SR[21])
 160 #define EIWR  (SR[28])
 161 #define FEWR  (SR[29])
 162 #define DBWR  (SR[30])
 163 #define BSEL  (SR[31])
 164
 165 #define PSW_US BIT32 (8)
 166 #define PSW_NP 0x80
 167 #define PSW_EP 0x40
 168 #define PSW_ID 0x20
 169 #define PSW_SAT 0x10
 170 #define PSW_CY 0x8
 171 #define PSW_OV 0x4
 172 #define PSW_S 0x2
 173 #define PSW_Z 0x1
 174
 175 #define PSW_NPV (1<<18)
 176 #define PSW_DMP (1<<17)
 177 #define PSW_IMP (1<<16)
 178
 179 #define ECR_EICC 0x0000ffff
 180 #define ECR_FECC 0xffff0000
 181
 182 /* FPU */
 183
 184 #define FPSR  (FPU_SR[6])
 185 #define FPSR_REGNO 6
 186 #define FPEPC (FPU_SR[7])
 187 #define FPST  (FPU_SR[8])
 188 #define FPST_REGNO 8
 189 #define FPCC  (FPU_SR[9])
 190 #define FPCFG (FPU_SR[10])
 191 #define FPCFG_REGNO 10
 192
 193 #define FPSR_DEM  0x00200000
 194 #define FPSR_SEM  0x00100000
 195 #define FPSR_RM   0x000c0000
 196 #define FPSR_RN   0x00000000
 197 #define FPSR_FS   0x00020000
 198 #define FPSR_PR   0x00010000
 199
 200 #define FPSR_XC   0x0000fc00
 201 #define FPSR_XCE  0x00008000
 202 #define FPSR_XCV  0x00004000
 203 #define FPSR_XCZ  0x00002000
 204 #define FPSR_XCO  0x00001000
 205 #define FPSR_XCU  0x00000800
 206 #define FPSR_XCI  0x00000400
 207
 208 #define FPSR_XE   0x000003e0
 209 #define FPSR_XEV  0x00000200
 210 #define FPSR_XEZ  0x00000100
 211 #define FPSR_XEO  0x00000080
 212 #define FPSR_XEU  0x00000040
 213 #define FPSR_XEI  0x00000020
 214
 215 #define FPSR_XP   0x0000001f
 216 #define FPSR_XPV  0x00000010
 217 #define FPSR_XPZ  0x00000008
 218 #define FPSR_XPO  0x00000004
 219 #define FPSR_XPU  0x00000002
 220 #define FPSR_XPI  0x00000001
 221
 222 #define FPST_PR   0x00008000
 223 #define FPST_XCE  0x00002000
 224 #define FPST_XCV  0x00001000
 225 #define FPST_XCZ  0x00000800
 226 #define FPST_XCO  0x00000400
 227 #define FPST_XCU  0x00000200
 228 #define FPST_XCI  0x00000100
 229
 230 #define FPST_XPV  0x00000010
 231 #define FPST_XPZ  0x00000008
 232 #define FPST_XPO  0x00000004
 233 #define FPST_XPU  0x00000002
 234 #define FPST_XPI  0x00000001
 235
 236 #define FPCFG_RM   0x00000180
 237 #define FPCFG_XEV  0x00000010
 238 #define FPCFG_XEZ  0x00000008
 239 #define FPCFG_XEO  0x00000004
 240 #define FPCFG_XEU  0x00000002
 241 #define FPCFG_XEI  0x00000001
 242
 243 #define GET_FPCC()\
 244  ((FPSR >> 24) &0xf)
 245
 246 #define CLEAR_FPCC(bbb)\
 247   (FPSR &= ~(1 << (bbb+24)))
 248
 249 #define SET_FPCC(bbb)\
 250  (FPSR |= 1 << (bbb+24))
 251
 252 #define TEST_FPCC(bbb)\
 253   ((FPSR & (1 << (bbb+24))) != 0)
 254
 255 #define FPSR_GET_ROUND()                                        \
 256   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 257    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 258    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 259    : sim_fpu_round_zero)
 260
 261
 262 enum FPU_COMPARE {
 263   FPU_CMP_F = 0,
 264   FPU_CMP_UN,
 265   FPU_CMP_EQ,
 266   FPU_CMP_UEQ,
 267   FPU_CMP_OLT,
 268   FPU_CMP_ULT,
 269   FPU_CMP_OLE,
 270   FPU_CMP_ULE,
 271   FPU_CMP_SF,
 272   FPU_CMP_NGLE,
 273   FPU_CMP_SEQ,
 274   FPU_CMP_NGL,
 275   FPU_CMP_LT,
 276   FPU_CMP_NGE,
 277   FPU_CMP_LE,
 278   FPU_CMP_NGT
 279 };
 280
 281
 282 /* MPU */
 283 #define MPM     (MPU1_SR[0])
 284 #define MPC     (MPU1_SR[1])
 285 #define MPC_REGNO 1
 286 #define TID     (MPU1_SR[2])
 287 #define PPA     (MPU1_SR[3])
 288 #define PPM     (MPU1_SR[4])
 289 #define PPC     (MPU1_SR[5])
 290 #define DCC     (MPU1_SR[6])
 291 #define DCV0    (MPU1_SR[7])
 292 #define DCV1    (MPU1_SR[8])
 293 #define SPAL    (MPU1_SR[10])
 294 #define SPAU    (MPU1_SR[11])
 295 #define IPA0L   (MPU1_SR[12])
 296 #define IPA0U   (MPU1_SR[13])
 297 #define IPA1L   (MPU1_SR[14])
 298 #define IPA1U   (MPU1_SR[15])
 299 #define IPA2L   (MPU1_SR[16])
 300 #define IPA2U   (MPU1_SR[17])
 301 #define IPA3L   (MPU1_SR[18])
 302 #define IPA3U   (MPU1_SR[19])
 303 #define DPA0L   (MPU1_SR[20])
 304 #define DPA0U   (MPU1_SR[21])
 305 #define DPA1L   (MPU1_SR[22])
 306 #define DPA1U   (MPU1_SR[23])
 307 #define DPA2L   (MPU1_SR[24])
 308 #define DPA2U   (MPU1_SR[25])
 309 #define DPA3L   (MPU1_SR[26])
 310 #define DPA3U   (MPU1_SR[27])
 311
 312 #define PPC_PPE 0x1
 313 #define SPAL_SPE 0x1
 314 #define SPAL_SPS 0x10
 315
 316 #define VIP     (MPU0_SR[0])
 317 #define VMECR   (MPU0_SR[4])
 318 #define VMTID   (MPU0_SR[5])
 319 #define VMADR   (MPU0_SR[6])
 320 #define VPECR   (MPU0_SR[8])
 321 #define VPTID   (MPU0_SR[9])
 322 #define VPADR   (MPU0_SR[10])
 323 #define VDECR   (MPU0_SR[12])
 324 #define VDTID   (MPU0_SR[13])
 325
 326 #define MPM_AUE 0x2
 327 #define MPM_MPE 0x1
 328
 329 #define VMECR_VMX   0x2
 330 #define VMECR_VMR   0x4
 331 #define VMECR_VMW   0x8
 332 #define VMECR_VMS   0x10
 333 #define VMECR_VMRMW 0x20
 334 #define VMECR_VMMS  0x40
 335
 336 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 337 #define IPA_IPE 0x1
 338 #define IPA_IPX 0x2
 339 #define IPA_IPR 0x4
 340 #define IPE0    (IPA0L & IPA_IPE)
 341 #define IPE1    (IPA1L & IPA_IPE)
 342 #define IPE2    (IPA2L & IPA_IPE)
 343 #define IPE3    (IPA3L & IPA_IPE)
 344 #define IPX0    (IPA0L & IPA_IPX)
 345 #define IPX1    (IPA1L & IPA_IPX)
 346 #define IPX2    (IPA2L & IPA_IPX)
 347 #define IPX3    (IPA3L & IPA_IPX)
 348 #define IPR0    (IPA0L & IPA_IPR)
 349 #define IPR1    (IPA1L & IPA_IPR)
 350 #define IPR2    (IPA2L & IPA_IPR)
 351 #define IPR3    (IPA3L & IPA_IPR)
 352
 353 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 354 #define DPA_DPE 0x1
 355 #define DPA_DPR 0x4
 356 #define DPA_DPW 0x8
 357 #define DPE0    (DPA0L & DPA_DPE)
 358 #define DPE1    (DPA1L & DPA_DPE)
 359 #define DPE2    (DPA2L & DPA_DPE)
 360 #define DPE3    (DPA3L & DPA_DPE)
 361 #define DPR0    (DPA0L & DPA_DPR)
 362 #define DPR1    (DPA1L & DPA_DPR)
 363 #define DPR2    (DPA2L & DPA_DPR)
 364 #define DPR3    (DPA3L & DPA_DPR)
 365 #define DPW0    (DPA0L & DPA_DPW)
 366 #define DPW1    (DPA1L & DPA_DPW)
 367 #define DPW2    (DPA2L & DPA_DPW)
 368 #define DPW3    (DPA3L & DPA_DPW)
 369
 370 #define DCC_DCE0 0x1
 371 #define DCC_DCE1 0x10000
 372
 373 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 374 #define PPC_PPC 0xfffffffe
 375 #define PPC_PPE 0x1
 376 #define PPC_PPM 0x0000fff8
 377
 378
 379 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 380
 381 /* sign-extend a 4-bit number */
 382 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 383
 384 /* sign-extend a 5-bit number */
 385 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 386
 387 /* sign-extend a 9-bit number */
 388 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 389
 390 /* sign-extend a 22-bit number */
 391 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 392
 393 /* sign extend a 40 bit number */
 394 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 395                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 396                          + UNSIGNED64 (0x8000000000))
 397
 398 /* sign extend a 44 bit number */
 399 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 400                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 401                          + UNSIGNED64 (0x80000000000))
 402
 403 /* sign extend a 60 bit number */
 404 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 405                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 406                          + UNSIGNED64 (0x800000000000000))
 407
 408 /* No sign extension */
 409 #define NOP(x)          (x)
 410
 411 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 412
 413 #define RLW(x) load_mem (x, 4)
 414
 415 /* Function declarations.  */
 416
 417 #define IMEM16(EA) \
 418 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 419
 420 #define IMEM16_IMMED(EA,N) \
 421 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 422                          PC, exec_map, (EA) + (N) * 2)
 423
 424 #define load_mem(ADDR,LEN) \
 425 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 426                                PC, read_map, (ADDR))
 427
 428 #define store_mem(ADDR,LEN,DATA) \
 429 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 430                                 PC, write_map, (ADDR), (DATA))
 431
 432
 433 /* compare cccc field against PSW */
 434 int condition_met (unsigned code);
 435
 436
 437 /* Debug/tracing calls */
 438
 439 enum op_types
 440 {
 441   OP_UNKNOWN,
 442   OP_NONE,
 443   OP_TRAP,
 444   OP_REG,
 445   OP_REG_REG,
 446   OP_REG_REG_CMP,
 447   OP_REG_REG_MOVE,
 448   OP_IMM_REG,
 449   OP_IMM_REG_CMP,
 450   OP_IMM_REG_MOVE,
 451   OP_COND_BR,
 452   OP_LOAD16,
 453   OP_STORE16,
 454   OP_LOAD32,
 455   OP_STORE32,
 456   OP_JUMP,
 457   OP_IMM_REG_REG,
 458   OP_UIMM_REG_REG,
 459   OP_IMM16_REG_REG,
 460   OP_UIMM16_REG_REG,
 461   OP_BIT,
 462   OP_EX1,
 463   OP_EX2,
 464   OP_LDSR,
 465   OP_STSR,
 466   OP_BIT_CHANGE,
 467   OP_REG_REG_REG,
 468   OP_REG_REG3,
 469   OP_IMM_REG_REG_REG,
 470   OP_PUSHPOP1,
 471   OP_PUSHPOP2,
 472   OP_PUSHPOP3,
 473 };
 474
 475 #ifdef DEBUG
 476 void trace_input (char *name, enum op_types type, int size);
 477 void trace_output (enum op_types result);
 478 void trace_result (int has_result, unsigned32 result);
 479
 480 extern int trace_num_values;
 481 extern unsigned32 trace_values[];
 482 extern unsigned32 trace_pc;
 483 extern const char *trace_name;
 484 extern int trace_module;
 485
 486 #define TRACE_BRANCH0() \
 487 do { \
 488   if (TRACE_BRANCH_P (CPU)) { \
 489     trace_module = TRACE_BRANCH_IDX; \
 490     trace_pc = cia; \
 491     trace_name = itable[MY_INDEX].name; \
 492     trace_num_values = 0; \
 493     trace_result (1, (nia)); \
 494   } \
 495 } while (0)
 496
 497 #define TRACE_BRANCH1(IN1) \
 498 do { \
 499   if (TRACE_BRANCH_P (CPU)) { \
 500     trace_module = TRACE_BRANCH_IDX; \
 501     trace_pc = cia; \
 502     trace_name = itable[MY_INDEX].name; \
 503     trace_values[0] = (IN1); \
 504     trace_num_values = 1; \
 505     trace_result (1, (nia)); \
 506   } \
 507 } while (0)
 508
 509 #define TRACE_BRANCH2(IN1, IN2) \
 510 do { \
 511   if (TRACE_BRANCH_P (CPU)) { \
 512     trace_module = TRACE_BRANCH_IDX; \
 513     trace_pc = cia; \
 514     trace_name = itable[MY_INDEX].name; \
 515     trace_values[0] = (IN1); \
 516     trace_values[1] = (IN2); \
 517     trace_num_values = 2; \
 518     trace_result (1, (nia)); \
 519   } \
 520 } while (0)
 521
 522 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 523 do { \
 524   if (TRACE_BRANCH_P (CPU)) { \
 525     trace_module = TRACE_BRANCH_IDX; \
 526     trace_pc = cia; \
 527     trace_name = itable[MY_INDEX].name; \
 528     trace_values[0] = (IN1); \
 529     trace_values[1] = (IN2); \
 530     trace_values[2] = (IN3); \
 531     trace_num_values = 3; \
 532     trace_result (1, (nia)); \
 533   } \
 534 } while (0)
 535
 536 #define TRACE_LD(ADDR,RESULT) \
 537 do { \
 538   if (TRACE_MEMORY_P (CPU)) { \
 539     trace_module = TRACE_MEMORY_IDX; \
 540     trace_pc = cia; \
 541     trace_name = itable[MY_INDEX].name; \
 542     trace_values[0] = (ADDR); \
 543     trace_num_values = 1; \
 544     trace_result (1, (RESULT)); \
 545   } \
 546 } while (0)
 547
 548 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 549 do { \
 550   if (TRACE_MEMORY_P (CPU)) { \
 551     trace_module = TRACE_MEMORY_IDX; \
 552     trace_pc = cia; \
 553     trace_name = (NAME); \
 554     trace_values[0] = (ADDR); \
 555     trace_num_values = 1; \
 556     trace_result (1, (RESULT)); \
 557   } \
 558 } while (0)
 559
 560 #define TRACE_ST(ADDR,RESULT) \
 561 do { \
 562   if (TRACE_MEMORY_P (CPU)) { \
 563     trace_module = TRACE_MEMORY_IDX; \
 564     trace_pc = cia; \
 565     trace_name = itable[MY_INDEX].name; \
 566     trace_values[0] = (ADDR); \
 567     trace_num_values = 1; \
 568     trace_result (1, (RESULT)); \
 569   } \
 570 } while (0)
 571
 572 #define TRACE_FP_INPUT_FPU1(V0) \
 573 do { \
 574   if (TRACE_FPU_P (CPU)) \
 575     { \
 576       unsigned64 f0; \
 577       sim_fpu_to64 (&f0, (V0)); \
 578       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 579     } \
 580 } while (0)
 581
 582 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 583 do { \
 584   if (TRACE_FPU_P (CPU)) \
 585     { \
 586       unsigned64 f0, f1; \
 587       sim_fpu_to64 (&f0, (V0)); \
 588       sim_fpu_to64 (&f1, (V1)); \
 589       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 590     } \
 591 } while (0)
 592
 593 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 594 do { \
 595   if (TRACE_FPU_P (CPU)) \
 596     { \
 597       unsigned64 f0, f1, f2; \
 598       sim_fpu_to64 (&f0, (V0)); \
 599       sim_fpu_to64 (&f1, (V1)); \
 600       sim_fpu_to64 (&f2, (V2)); \
 601       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 602     } \
 603 } while (0)
 604
 605 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 606 do { \
 607   if (TRACE_FPU_P (CPU)) \
 608     { \
 609       int d0 = (V0); \
 610       unsigned64 f1, f2; \
 611       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 612       TRACE_IDX (data) = TRACE_FPU_IDX; \
 613       sim_fpu_to64 (&f1, (V1)); \
 614       sim_fpu_to64 (&f2, (V2)); \
 615       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 616       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 617       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 618     } \
 619 } while (0)
 620
 621 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 622 do { \
 623   if (TRACE_FPU_P (CPU)) \
 624     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 625 } while (0)
 626
 627 #define TRACE_FP_RESULT_FPU1(R0) \
 628 do { \
 629   if (TRACE_FPU_P (CPU)) \
 630     { \
 631       unsigned64 f0; \
 632       sim_fpu_to64 (&f0, (R0)); \
 633       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 634     } \
 635 } while (0)
 636
 637 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 638
 639 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 640 do { \
 641   if (TRACE_FPU_P (CPU)) \
 642     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 643 } while (0)
 644
 645 #else
 646 #define trace_input(NAME, IN1, IN2)
 647 #define trace_output(RESULT)
 648 #define trace_result(HAS_RESULT, RESULT)
 649
 650 #define TRACE_ALU_INPUT0()
 651 #define TRACE_ALU_INPUT1(IN0)
 652 #define TRACE_ALU_INPUT2(IN0, IN1)
 653 #define TRACE_ALU_INPUT2(IN0, IN1)
 654 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 655 #define TRACE_ALU_RESULT(RESULT)
 656
 657 #define TRACE_BRANCH0()
 658 #define TRACE_BRANCH1(IN1)
 659 #define TRACE_BRANCH2(IN1, IN2)
 660 #define TRACE_BRANCH2(IN1, IN2, IN3)
 661
 662 #define TRACE_LD(ADDR,RESULT)
 663 #define TRACE_ST(ADDR,RESULT)
 664
 665 #endif
 666
 667 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 668 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 669
 670 extern void divun ( unsigned int       N,
 671                     unsigned long int  als,
 672                     unsigned long int  sfi,
 673                     unsigned32 /*unsigned long int*/ *  quotient_ptr,
 674                     unsigned32 /*unsigned long int*/ *  remainder_ptr,
 675                     int *overflow_ptr
 676                     );
 677 extern void divn ( unsigned int       N,
 678                    unsigned long int  als,
 679                    unsigned long int  sfi,
 680                    signed32 /*signed long int*/ *  quotient_ptr,
 681                    signed32 /*signed long int*/ *  remainder_ptr,
 682                    int *overflow_ptr
 683                    );
 684 extern int type1_regs[];
 685 extern int type2_regs[];
 686 extern int type3_regs[];
 687
 688 #define SESR_OV   (1 << 0)
 689 #define SESR_SOV  (1 << 1)
 690
 691 #define SESR      (State.sregs[12])
 692
 693 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 694 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 695 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 696 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 697
 698 #define SAT16(X)                        \
 699   do                                    \
 700     {                                   \
 701       signed64 z = (X);                 \
 702       if (z > 0x7fff)                   \
 703         {                               \
 704           SESR |= SESR_OV | SESR_SOV;   \
 705           z = 0x7fff;                   \
 706         }                               \
 707       else if (z < -0x8000)             \
 708         {                               \
 709           SESR |= SESR_OV | SESR_SOV;   \
 710           z = - 0x8000;                 \
 711         }                               \
 712       (X) = z;                          \
 713     }                                   \
 714   while (0)
 715
 716 #define SAT32(X)                        \
 717   do                                    \
 718     {                                   \
 719       signed64 z = (X);                 \
 720       if (z > 0x7fffffff)               \
 721         {                               \
 722           SESR |= SESR_OV | SESR_SOV;   \
 723           z = 0x7fffffff;               \
 724         }                               \
 725       else if (z < -0x80000000)         \
 726         {                               \
 727           SESR |= SESR_OV | SESR_SOV;   \
 728           z = - 0x80000000;             \
 729         }                               \
 730       (X) = z;                          \
 731     }                                   \
 732   while (0)
 733
 734 #define ABS16(X)                        \
 735   do                                    \
 736     {                                   \
 737       signed64 z = (X) & 0xffff;        \
 738       if (z == 0x8000)                  \
 739         {                               \
 740           SESR |= SESR_OV | SESR_SOV;   \
 741           z = 0x7fff;                   \
 742         }                               \
 743       else if (z & 0x8000)              \
 744         {                               \
 745           z = (- z) & 0xffff;           \
 746         }                               \
 747       (X) = z;                          \
 748     }                                   \
 749   while (0)
 750
 751 #define ABS32(X)                        \
 752   do                                    \
 753     {                                   \
 754       signed64 z = (X) & 0xffffffff;    \
 755       if (z == 0x80000000)              \
 756         {                               \
 757           SESR |= SESR_OV | SESR_SOV;   \
 758           z = 0x7fffffff;               \
 759         }                               \
 760       else if (z & 0x80000000)          \
 761         {                               \
 762           z = (- z) & 0xffffffff;       \
 763         }                               \
 764       (X) = z;                          \
 765     }                                   \
 766   while (0)
 767
 768 #endif