77102328f1d042a8dd1bb0439eb4312282c80f42
4 #include "sys/syscall.h"
35 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
36 static void trace_output
PARAMS ((enum op_types result
));
37 static int init_text_p
= 0;
38 static asection
*text
;
39 static bfd_vma text_start
;
40 static bfd_vma text_end
;
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 6
48 #define SIZE_OPERANDS 16
52 #define SIZE_VALUES 11
56 #define SIZE_LOCATION 40
60 trace_input (name
, type
, size
)
72 const char *functionname
;
73 unsigned int linenumber
;
75 if ((v850_debug
& DEBUG_TRACE
) == 0)
82 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
83 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
86 text_start
= bfd_get_section_vma (exec_bfd
, s
);
87 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
92 if (text
&& PC
>= text_start
&& PC
< text_end
)
94 filename
= (const char *)0;
95 functionname
= (const char *)0;
97 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
98 &filename
, &functionname
, &linenumber
))
103 sprintf (p
, "Line %5d ", linenumber
);
109 sprintf (p
, "Func %s ", functionname
);
114 char *q
= (char *) strrchr (filename
, '/');
115 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
124 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
126 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
127 SIZE_INSTRUCTION
, name
);
134 strcpy (buf
, "unknown");
138 sprintf (buf
, "%d", OP
[0]);
142 sprintf (buf
, "r%d", OP
[0]);
147 case OP_REG_REG_MOVE
:
148 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
153 case OP_IMM_REG_MOVE
:
154 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
158 sprintf (buf
, "%d", SEXT9 (OP
[0]));
162 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
166 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
170 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
174 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
178 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
182 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
185 case OP_UIMM_REG_REG
:
186 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
190 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
196 default: cond
= "?"; break;
197 case 0x0: cond
= "v"; break;
198 case 0x1: cond
= "c"; break;
199 case 0x2: cond
= "z"; break;
200 case 0x3: cond
= "nh"; break;
201 case 0x4: cond
= "s"; break;
202 case 0x5: cond
= "t"; break;
203 case 0x6: cond
= "lt"; break;
204 case 0x7: cond
= "le"; break;
205 case 0x8: cond
= "nv"; break;
206 case 0x9: cond
= "nc"; break;
207 case 0xa: cond
= "nz"; break;
208 case 0xb: cond
= "h"; break;
209 case 0xc: cond
= "ns"; break;
210 case 0xd: cond
= "sa"; break;
211 case 0xe: cond
= "ge"; break;
212 case 0xf: cond
= "gt"; break;
215 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
224 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
228 if ((v850_debug
& DEBUG_VALUES
) == 0)
230 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
234 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
245 case OP_REG_REG_MOVE
:
246 values
[0] = State
.regs
[OP
[0]];
252 values
[0] = State
.regs
[OP
[1]];
253 values
[1] = State
.regs
[OP
[0]];
259 values
[0] = SEXT5 (OP
[0]);
264 case OP_IMM_REG_MOVE
:
265 values
[0] = SEXT5 (OP
[0]);
270 values
[0] = State
.pc
;
271 values
[1] = SEXT9 (OP
[0]);
272 values
[2] = State
.sregs
[5];
277 values
[0] = OP
[1] * size
;
278 values
[1] = State
.regs
[30];
283 values
[0] = State
.regs
[OP
[0]];
284 values
[1] = OP
[1] * size
;
285 values
[2] = State
.regs
[30];
290 values
[0] = SEXT16 (OP
[2]);
291 values
[1] = State
.regs
[OP
[0]];
296 values
[0] = State
.regs
[OP
[1]];
297 values
[1] = SEXT16 (OP
[2]);
298 values
[2] = State
.regs
[OP
[0]];
303 values
[0] = SEXT22 (OP
[0]);
304 values
[1] = State
.pc
;
309 values
[0] = SEXT16 (OP
[0]) << size
;
310 values
[1] = State
.regs
[OP
[1]];
314 case OP_UIMM_REG_REG
:
315 values
[0] = (OP
[0] & 0xffff) << size
;
316 values
[1] = State
.regs
[OP
[1]];
325 values
[0] = State
.sregs
[5];
334 values
[0] = State
.regs
[OP
[0]];
339 values
[0] = State
.sregs
[OP
[1]];
343 for (i
= 0; i
< num_values
; i
++)
344 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
347 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
352 trace_output (result
)
353 enum op_types result
;
355 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
375 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
376 (unsigned long)State
.regs
[OP
[0]]);
380 case OP_REG_REG_MOVE
:
382 case OP_IMM_REG_MOVE
:
385 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
386 (unsigned long)State
.regs
[OP
[1]]);
390 case OP_UIMM_REG_REG
:
391 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
392 (unsigned long)State
.regs
[OP
[2]]);
397 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
398 (unsigned long)State
.regs
[OP
[1]]);
402 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
403 (unsigned long)State
.sregs
[OP
[1]]);
407 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
412 #define trace_input(NAME, IN1, IN2)
413 #define trace_output(RESULT)
424 trace_input ("sld.b", OP_LOAD16
, 1);
428 result
= load_mem (State
.regs
[30] + op2
, 1);
429 State
.regs
[OP
[0]] = SEXT8 (result
);
430 trace_output (OP_LOAD16
);
440 trace_input ("sld.h", OP_LOAD16
, 2);
444 result
= load_mem (State
.regs
[30] + op2
, 2);
445 State
.regs
[OP
[0]] = SEXT16 (result
);
446 trace_output (OP_LOAD16
);
456 trace_input ("sld.w", OP_LOAD16
, 4);
460 result
= load_mem (State
.regs
[30] + op2
, 4);
461 State
.regs
[OP
[0]] = result
;
462 trace_output (OP_LOAD16
);
469 unsigned int op0
, op1
;
472 trace_input ("sst.b", OP_STORE16
, 1);
473 op0
= State
.regs
[OP
[0]];
477 store_mem (State
.regs
[30] + op1
, 1, op0
);
478 trace_output (OP_STORE16
);
485 unsigned int op0
, op1
;
488 trace_input ("sst.h", OP_STORE16
, 2);
489 op0
= State
.regs
[OP
[0]];
493 store_mem (State
.regs
[30] + op1
, 2, op0
);
494 trace_output (OP_STORE16
);
501 unsigned int op0
, op1
;
504 trace_input ("sst.w", OP_STORE16
, 4);
505 op0
= State
.regs
[OP
[0]];
509 store_mem (State
.regs
[30] + op1
, 4, op0
);
510 trace_output (OP_STORE16
);
517 unsigned int op0
, op2
;
520 trace_input ("ld.b", OP_LOAD32
, 1);
521 op0
= State
.regs
[OP
[0]];
522 temp
= SEXT16 (OP
[2]);
524 result
= load_mem (op0
+ op2
, 1);
525 State
.regs
[OP
[1]] = SEXT8 (result
);
526 trace_output (OP_LOAD32
);
533 unsigned int op0
, op2
;
536 trace_input ("ld.h", OP_LOAD32
, 2);
537 op0
= State
.regs
[OP
[0]];
538 temp
= SEXT16 (OP
[2]);
541 result
= load_mem (op0
+ op2
, 2);
542 State
.regs
[OP
[1]] = SEXT16 (result
);
543 trace_output (OP_LOAD32
);
550 unsigned int op0
, op2
;
553 trace_input ("ld.w", OP_LOAD32
, 4);
554 op0
= State
.regs
[OP
[0]];
555 temp
= SEXT16 (OP
[2]);
558 result
= load_mem (op0
+ op2
, 4);
559 State
.regs
[OP
[1]] = result
;
560 trace_output (OP_LOAD32
);
567 unsigned int op0
, op1
, op2
;
570 trace_input ("st.b", OP_STORE32
, 1);
571 op0
= State
.regs
[OP
[0]];
572 op1
= State
.regs
[OP
[1]];
573 temp
= SEXT16 (OP
[2]);
575 store_mem (op0
+ op2
, 1, op1
);
576 trace_output (OP_STORE32
);
583 unsigned int op0
, op1
, op2
;
586 trace_input ("st.h", OP_STORE32
, 2);
587 op0
= State
.regs
[OP
[0]];
588 op1
= State
.regs
[OP
[1]];
589 temp
= SEXT16 (OP
[2] & ~0x1);
591 store_mem (op0
+ op2
, 2, op1
);
592 trace_output (OP_STORE32
);
599 unsigned int op0
, op1
, op2
;
602 trace_input ("st.w", OP_STORE32
, 4);
603 op0
= State
.regs
[OP
[0]];
604 op1
= State
.regs
[OP
[1]];
605 temp
= SEXT16 (OP
[2] & ~0x1);
607 store_mem (op0
+ op2
, 4, op1
);
608 trace_output (OP_STORE32
);
618 trace_input ("bv", OP_COND_BR
, 0);
620 psw
= State
.sregs
[5];
622 if ((psw
& PSW_OV
) != 0)
626 trace_output (OP_COND_BR
);
636 trace_input ("bl", OP_COND_BR
, 0);
638 psw
= State
.sregs
[5];
640 if ((psw
& PSW_CY
) != 0)
644 trace_output (OP_COND_BR
);
654 trace_input ("be", OP_COND_BR
, 0);
656 psw
= State
.sregs
[5];
658 if ((psw
& PSW_Z
) != 0)
662 trace_output (OP_COND_BR
);
672 trace_input ("bnh", OP_COND_BR
, 0);
674 psw
= State
.sregs
[5];
676 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
680 trace_output (OP_COND_BR
);
690 trace_input ("bn", OP_COND_BR
, 0);
692 psw
= State
.sregs
[5];
694 if ((psw
& PSW_S
) != 0)
698 trace_output (OP_COND_BR
);
708 trace_input ("br", OP_COND_BR
, 0);
711 trace_output (OP_COND_BR
);
721 trace_input ("blt", OP_COND_BR
, 0);
723 psw
= State
.sregs
[5];
725 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
729 trace_output (OP_COND_BR
);
739 trace_input ("ble", OP_COND_BR
, 0);
741 psw
= State
.sregs
[5];
743 if ((((psw
& PSW_Z
) != 0)
744 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
748 trace_output (OP_COND_BR
);
758 trace_input ("bnv", OP_COND_BR
, 0);
760 psw
= State
.sregs
[5];
762 if ((psw
& PSW_OV
) == 0)
766 trace_output (OP_COND_BR
);
776 trace_input ("bnl", OP_COND_BR
, 0);
778 psw
= State
.sregs
[5];
780 if ((psw
& PSW_CY
) == 0)
784 trace_output (OP_COND_BR
);
794 trace_input ("bne", OP_COND_BR
, 0);
796 psw
= State
.sregs
[5];
798 if ((psw
& PSW_Z
) == 0)
802 trace_output (OP_COND_BR
);
812 trace_input ("bh", OP_COND_BR
, 0);
814 psw
= State
.sregs
[5];
816 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
820 trace_output (OP_COND_BR
);
830 trace_input ("bp", OP_COND_BR
, 0);
832 psw
= State
.sregs
[5];
834 if ((psw
& PSW_S
) == 0)
838 trace_output (OP_COND_BR
);
848 trace_input ("bsa", OP_COND_BR
, 0);
850 psw
= State
.sregs
[5];
852 if ((psw
& PSW_SAT
) != 0)
856 trace_output (OP_COND_BR
);
866 trace_input ("bge", OP_COND_BR
, 0);
868 psw
= State
.sregs
[5];
870 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
874 trace_output (OP_COND_BR
);
884 trace_input ("bgt", OP_COND_BR
, 0);
886 psw
= State
.sregs
[5];
888 if ((((psw
& PSW_Z
) != 0)
889 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
893 trace_output (OP_COND_BR
);
900 /* interp.c will bump this by +2, so correct for it here. */
901 trace_input ("jmp", OP_REG
, 0);
902 State
.pc
= State
.regs
[OP
[0]] - 2;
903 trace_output (OP_REG
);
906 /* jarl disp22, reg */
910 unsigned int op0
, opc
;
913 trace_input ("jarl", OP_JUMP
, 0);
914 temp
= SEXT22 (OP
[0]);
920 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
922 State
.regs
[OP
[1]] = opc
+ 4;
923 trace_output (OP_JUMP
);
930 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
932 trace_input ("add", OP_REG_REG
, 0);
933 /* Compute the result. */
934 op0
= State
.regs
[OP
[0]];
935 op1
= State
.regs
[OP
[1]];
938 /* Compute the condition codes. */
940 s
= (result
& 0x80000000);
941 cy
= (result
< op0
|| result
< op1
);
942 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
943 && (op0
& 0x80000000) != (result
& 0x80000000));
945 /* Store the result and condition codes. */
946 State
.regs
[OP
[1]] = result
;
947 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
948 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
949 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
950 trace_output (OP_REG_REG
);
953 /* add sign_extend(imm5), reg */
957 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
960 trace_input ("add", OP_IMM_REG
, 0);
962 /* Compute the result. */
963 temp
= SEXT5 (OP
[0]);
965 op1
= State
.regs
[OP
[1]];
968 /* Compute the condition codes. */
970 s
= (result
& 0x80000000);
971 cy
= (result
< op0
|| result
< op1
);
972 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
973 && (op0
& 0x80000000) != (result
& 0x80000000));
975 /* Store the result and condition codes. */
976 State
.regs
[OP
[1]] = result
;
977 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
978 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
979 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
980 trace_output (OP_IMM_REG
);
983 /* addi sign_extend(imm16), reg, reg */
987 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
990 trace_input ("addi", OP_IMM_REG_REG
, 0);
992 /* Compute the result. */
993 temp
= SEXT16 (OP
[0]);
995 op1
= State
.regs
[OP
[1]];
998 /* Compute the condition codes. */
1000 s
= (result
& 0x80000000);
1001 cy
= (result
< op0
|| result
< op1
);
1002 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1003 && (op0
& 0x80000000) != (result
& 0x80000000));
1005 /* Store the result and condition codes. */
1006 State
.regs
[OP
[2]] = result
;
1007 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1008 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1009 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1010 trace_output (OP_IMM_REG_REG
);
1013 /* sub reg1, reg2 */
1017 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1019 trace_input ("sub", OP_REG_REG
, 0);
1020 /* Compute the result. */
1021 op0
= State
.regs
[OP
[0]];
1022 op1
= State
.regs
[OP
[1]];
1025 /* Compute the condition codes. */
1027 s
= (result
& 0x80000000);
1029 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1030 && (op1
& 0x80000000) != (result
& 0x80000000));
1032 /* Store the result and condition codes. */
1033 State
.regs
[OP
[1]] = result
;
1034 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1035 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1036 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1037 trace_output (OP_REG_REG
);
1040 /* subr reg1, reg2 */
1044 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1046 trace_input ("subr", OP_REG_REG
, 0);
1047 /* Compute the result. */
1048 op0
= State
.regs
[OP
[0]];
1049 op1
= State
.regs
[OP
[1]];
1052 /* Compute the condition codes. */
1054 s
= (result
& 0x80000000);
1056 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1057 && (op0
& 0x80000000) != (result
& 0x80000000));
1059 /* Store the result and condition codes. */
1060 State
.regs
[OP
[1]] = result
;
1061 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1062 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1063 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1064 trace_output (OP_REG_REG
);
1067 /* mulh reg1, reg2 */
1071 trace_input ("mulh", OP_REG_REG
, 0);
1072 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
1073 * (State
.regs
[OP
[0]] & 0xffff));
1074 trace_output (OP_REG_REG
);
1077 /* mulh sign_extend(imm5), reg2
1083 int value
= SEXT5 (OP
[0]);
1085 trace_input ("mulh", OP_IMM_REG
, 0);
1086 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1087 trace_output (OP_IMM_REG
);
1090 /* mulhi imm16, reg1, reg2 */
1094 int value
= OP
[0] & 0xffff;
1096 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1097 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1098 trace_output (OP_IMM_REG_REG
);
1101 /* divh reg1, reg2 */
1105 unsigned int op0
, op1
, result
, ov
, s
, z
;
1108 trace_input ("divh", OP_REG_REG
, 0);
1110 /* Compute the result. */
1111 temp
= SEXT16 (State
.regs
[OP
[0]]);
1113 op1
= State
.regs
[OP
[1]];
1115 if (op0
== 0xffffffff && op1
== 0x80000000)
1117 result
= 0x80000000;
1131 /* Compute the condition codes. */
1133 s
= (result
& 0x80000000);
1135 /* Store the result and condition codes. */
1136 State
.regs
[OP
[1]] = result
;
1137 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1138 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1139 | (ov
? PSW_OV
: 0));
1140 trace_output (OP_REG_REG
);
1147 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1149 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1150 /* Compute the result. */
1151 op0
= State
.regs
[OP
[0]];
1152 op1
= State
.regs
[OP
[1]];
1155 /* Compute the condition codes. */
1157 s
= (result
& 0x80000000);
1159 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1160 && (op1
& 0x80000000) != (result
& 0x80000000));
1162 /* Set condition codes. */
1163 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1164 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1165 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1166 trace_output (OP_REG_REG_CMP
);
1169 /* cmp sign_extend(imm5), reg */
1173 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1176 /* Compute the result. */
1177 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1178 temp
= SEXT5 (OP
[0]);
1180 op1
= State
.regs
[OP
[1]];
1183 /* Compute the condition codes. */
1185 s
= (result
& 0x80000000);
1187 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1188 && (op1
& 0x80000000) != (result
& 0x80000000));
1190 /* Set condition codes. */
1191 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1192 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1193 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1194 trace_output (OP_IMM_REG_CMP
);
1197 /* setf cccc,reg2 */
1201 /* Hack alert. We turn off a bit in op0 since we really only
1203 unsigned int op0
, psw
, result
= 0;
1205 trace_input ("setf", OP_EX1
, 0);
1207 psw
= State
.sregs
[5];
1212 result
= ((psw
& PSW_OV
) != 0);
1215 result
= ((psw
& PSW_CY
) != 0);
1218 result
= ((psw
& PSW_Z
) != 0);
1221 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
1224 result
= ((psw
& PSW_S
) != 0);
1230 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
1233 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1234 || ((psw
& PSW_Z
) != 0)) != 0);
1237 result
= ((psw
& PSW_OV
) == 0);
1240 result
= ((psw
& PSW_CY
) == 0);
1243 result
= ((psw
& PSW_Z
) == 0);
1246 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
1249 result
= ((psw
& PSW_S
) == 0);
1252 result
= ((psw
& PSW_SAT
) != 0);
1255 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
1258 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1259 || ((psw
& PSW_Z
) != 0)) == 0);
1263 State
.regs
[OP
[1]] = result
;
1264 trace_output (OP_EX1
);
1267 /* satadd reg,reg */
1271 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1273 trace_input ("satadd", OP_REG_REG
, 0);
1274 /* Compute the result. */
1275 op0
= State
.regs
[OP
[0]];
1276 op1
= State
.regs
[OP
[1]];
1279 /* Compute the condition codes. */
1281 s
= (result
& 0x80000000);
1282 cy
= (result
< op0
|| result
< op1
);
1283 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1284 && (op0
& 0x80000000) != (result
& 0x80000000));
1287 /* Store the result and condition codes. */
1288 State
.regs
[OP
[1]] = result
;
1289 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1290 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1291 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1292 | (sat
? PSW_SAT
: 0));
1294 /* Handle saturated results. */
1296 State
.regs
[OP
[1]] = 0x80000000;
1298 State
.regs
[OP
[1]] = 0x7fffffff;
1299 trace_output (OP_REG_REG
);
1302 /* satadd sign_extend(imm5), reg */
1306 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1310 trace_input ("satadd", OP_IMM_REG
, 0);
1312 /* Compute the result. */
1313 temp
= SEXT5 (OP
[0]);
1315 op1
= State
.regs
[OP
[1]];
1318 /* Compute the condition codes. */
1320 s
= (result
& 0x80000000);
1321 cy
= (result
< op0
|| result
< op1
);
1322 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1323 && (op0
& 0x80000000) != (result
& 0x80000000));
1326 /* Store the result and condition codes. */
1327 State
.regs
[OP
[1]] = result
;
1328 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1329 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1330 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1331 | (sat
? PSW_SAT
: 0));
1333 /* Handle saturated results. */
1335 State
.regs
[OP
[1]] = 0x80000000;
1337 State
.regs
[OP
[1]] = 0x7fffffff;
1338 trace_output (OP_IMM_REG
);
1341 /* satsub reg1, reg2 */
1345 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1347 trace_input ("satsub", OP_REG_REG
, 0);
1349 /* Compute the result. */
1350 op0
= State
.regs
[OP
[0]];
1351 op1
= State
.regs
[OP
[1]];
1354 /* Compute the condition codes. */
1356 s
= (result
& 0x80000000);
1358 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1359 && (op1
& 0x80000000) != (result
& 0x80000000));
1362 /* Store the result and condition codes. */
1363 State
.regs
[OP
[1]] = result
;
1364 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1365 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1366 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1367 | (sat
? PSW_SAT
: 0));
1369 /* Handle saturated results. */
1371 State
.regs
[OP
[1]] = 0x80000000;
1373 State
.regs
[OP
[1]] = 0x7fffffff;
1374 trace_output (OP_REG_REG
);
1377 /* satsubi sign_extend(imm16), reg */
1381 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1384 trace_input ("satsubi", OP_IMM_REG
, 0);
1386 /* Compute the result. */
1387 temp
= SEXT16 (OP
[0]);
1389 op1
= State
.regs
[OP
[1]];
1392 /* Compute the condition codes. */
1394 s
= (result
& 0x80000000);
1396 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1397 && (op1
& 0x80000000) != (result
& 0x80000000));
1400 /* Store the result and condition codes. */
1401 State
.regs
[OP
[1]] = result
;
1402 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1403 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1404 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1405 | (sat
? PSW_SAT
: 0));
1407 /* Handle saturated results. */
1409 State
.regs
[OP
[1]] = 0x80000000;
1411 State
.regs
[OP
[1]] = 0x7fffffff;
1412 trace_output (OP_IMM_REG
);
1415 /* satsubr reg,reg */
1419 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1421 trace_input ("satsubr", OP_REG_REG
, 0);
1423 /* Compute the result. */
1424 op0
= State
.regs
[OP
[0]];
1425 op1
= State
.regs
[OP
[1]];
1428 /* Compute the condition codes. */
1430 s
= (result
& 0x80000000);
1431 cy
= (result
< op0
);
1432 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1433 && (op1
& 0x80000000) != (result
& 0x80000000));
1436 /* Store the result and condition codes. */
1437 State
.regs
[OP
[1]] = result
;
1438 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1439 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1440 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1441 | (sat
? PSW_SAT
: 0));
1443 /* Handle saturated results. */
1445 State
.regs
[OP
[1]] = 0x80000000;
1447 State
.regs
[OP
[1]] = 0x7fffffff;
1448 trace_output (OP_REG_REG
);
1455 unsigned int op0
, op1
, result
, z
, s
;
1457 trace_input ("tst", OP_REG_REG_CMP
, 0);
1459 /* Compute the result. */
1460 op0
= State
.regs
[OP
[0]];
1461 op1
= State
.regs
[OP
[1]];
1464 /* Compute the condition codes. */
1466 s
= (result
& 0x80000000);
1468 /* Store the condition codes. */
1469 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1470 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1471 trace_output (OP_REG_REG_CMP
);
1478 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1479 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
1480 trace_output (OP_REG_REG_MOVE
);
1483 /* mov sign_extend(imm5), reg */
1487 int value
= SEXT5 (OP
[0]);
1489 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1490 State
.regs
[OP
[1]] = value
;
1491 trace_output (OP_IMM_REG_MOVE
);
1494 /* movea sign_extend(imm16), reg, reg */
1499 int value
= SEXT16 (OP
[0]);
1501 trace_input ("movea", OP_IMM_REG_REG
, 0);
1502 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1503 trace_output (OP_IMM_REG_REG
);
1506 /* movhi imm16, reg, reg */
1510 uint32 value
= (OP
[0] & 0xffff) << 16;
1512 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1513 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1514 trace_output (OP_UIMM_REG_REG
);
1517 /* sar zero_extend(imm5),reg1 */
1521 unsigned int op0
, op1
, result
, z
, s
, cy
;
1523 trace_input ("sar", OP_IMM_REG
, 0);
1525 op1
= State
.regs
[OP
[1]];
1526 result
= (signed)op1
>> op0
;
1528 /* Compute the condition codes. */
1530 s
= (result
& 0x80000000);
1531 cy
= (op1
& (1 << (op0
- 1)));
1533 /* Store the result and condition codes. */
1534 State
.regs
[OP
[1]] = result
;
1535 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1536 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1537 | (cy
? PSW_CY
: 0));
1538 trace_output (OP_IMM_REG
);
1541 /* sar reg1, reg2 */
1545 unsigned int op0
, op1
, result
, z
, s
, cy
;
1547 trace_input ("sar", OP_REG_REG
, 0);
1548 op0
= State
.regs
[OP
[0]] & 0x1f;
1549 op1
= State
.regs
[OP
[1]];
1550 result
= (signed)op1
>> op0
;
1552 /* Compute the condition codes. */
1554 s
= (result
& 0x80000000);
1555 cy
= (op1
& (1 << (op0
- 1)));
1557 /* Store the result and condition codes. */
1558 State
.regs
[OP
[1]] = result
;
1559 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1560 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1561 | (cy
? PSW_CY
: 0));
1562 trace_output (OP_REG_REG
);
1565 /* shl zero_extend(imm5),reg1 */
1569 unsigned int op0
, op1
, result
, z
, s
, cy
;
1571 trace_input ("shl", OP_IMM_REG
, 0);
1573 op1
= State
.regs
[OP
[1]];
1574 result
= op1
<< op0
;
1576 /* Compute the condition codes. */
1578 s
= (result
& 0x80000000);
1579 cy
= (op1
& (1 << (32 - op0
)));
1581 /* Store the result and condition codes. */
1582 State
.regs
[OP
[1]] = result
;
1583 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1584 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1585 | (cy
? PSW_CY
: 0));
1586 trace_output (OP_IMM_REG
);
1589 /* shl reg1, reg2 */
1593 unsigned int op0
, op1
, result
, z
, s
, cy
;
1595 trace_input ("shl", OP_REG_REG
, 0);
1596 op0
= State
.regs
[OP
[0]] & 0x1f;
1597 op1
= State
.regs
[OP
[1]];
1598 result
= op1
<< op0
;
1600 /* Compute the condition codes. */
1602 s
= (result
& 0x80000000);
1603 cy
= (op1
& (1 << (32 - op0
)));
1605 /* Store the result and condition codes. */
1606 State
.regs
[OP
[1]] = result
;
1607 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1608 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1609 | (cy
? PSW_CY
: 0));
1610 trace_output (OP_REG_REG
);
1613 /* shr zero_extend(imm5),reg1 */
1617 unsigned int op0
, op1
, result
, z
, s
, cy
;
1619 trace_input ("shr", OP_IMM_REG
, 0);
1621 op1
= State
.regs
[OP
[1]];
1622 result
= op1
>> op0
;
1624 /* Compute the condition codes. */
1626 s
= (result
& 0x80000000);
1627 cy
= (op1
& (1 << (op0
- 1)));
1629 /* Store the result and condition codes. */
1630 State
.regs
[OP
[1]] = result
;
1631 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1632 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1633 | (cy
? PSW_CY
: 0));
1634 trace_output (OP_IMM_REG
);
1637 /* shr reg1, reg2 */
1641 unsigned int op0
, op1
, result
, z
, s
, cy
;
1643 trace_input ("shr", OP_REG_REG
, 0);
1644 op0
= State
.regs
[OP
[0]] & 0x1f;
1645 op1
= State
.regs
[OP
[1]];
1646 result
= op1
>> op0
;
1648 /* Compute the condition codes. */
1650 s
= (result
& 0x80000000);
1651 cy
= (op1
& (1 << (op0
- 1)));
1653 /* Store the result and condition codes. */
1654 State
.regs
[OP
[1]] = result
;
1655 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1656 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1657 | (cy
? PSW_CY
: 0));
1658 trace_output (OP_REG_REG
);
1665 unsigned int op0
, op1
, result
, z
, s
;
1667 trace_input ("or", OP_REG_REG
, 0);
1669 /* Compute the result. */
1670 op0
= State
.regs
[OP
[0]];
1671 op1
= State
.regs
[OP
[1]];
1674 /* Compute the condition codes. */
1676 s
= (result
& 0x80000000);
1678 /* Store the result and condition codes. */
1679 State
.regs
[OP
[1]] = result
;
1680 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1681 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1682 trace_output (OP_REG_REG
);
1685 /* ori zero_extend(imm16), reg, reg */
1689 unsigned int op0
, op1
, result
, z
, s
;
1691 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1692 op0
= OP
[0] & 0xffff;
1693 op1
= State
.regs
[OP
[1]];
1696 /* Compute the condition codes. */
1698 s
= (result
& 0x80000000);
1700 /* Store the result and condition codes. */
1701 State
.regs
[OP
[2]] = result
;
1702 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1703 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1704 trace_output (OP_UIMM_REG_REG
);
1711 unsigned int op0
, op1
, result
, z
, s
;
1713 trace_input ("and", OP_REG_REG
, 0);
1715 /* Compute the result. */
1716 op0
= State
.regs
[OP
[0]];
1717 op1
= State
.regs
[OP
[1]];
1720 /* Compute the condition codes. */
1722 s
= (result
& 0x80000000);
1724 /* Store the result and condition codes. */
1725 State
.regs
[OP
[1]] = result
;
1726 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1727 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1728 trace_output (OP_REG_REG
);
1731 /* andi zero_extend(imm16), reg, reg */
1735 unsigned int op0
, op1
, result
, z
;
1737 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1738 op0
= OP
[0] & 0xffff;
1739 op1
= State
.regs
[OP
[1]];
1742 /* Compute the condition codes. */
1745 /* Store the result and condition codes. */
1746 State
.regs
[OP
[2]] = result
;
1747 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1748 State
.sregs
[5] |= (z
? PSW_Z
: 0);
1749 trace_output (OP_UIMM_REG_REG
);
1756 unsigned int op0
, op1
, result
, z
, s
;
1758 trace_input ("xor", OP_REG_REG
, 0);
1760 /* Compute the result. */
1761 op0
= State
.regs
[OP
[0]];
1762 op1
= State
.regs
[OP
[1]];
1765 /* Compute the condition codes. */
1767 s
= (result
& 0x80000000);
1769 /* Store the result and condition codes. */
1770 State
.regs
[OP
[1]] = result
;
1771 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1772 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1773 trace_output (OP_REG_REG
);
1776 /* xori zero_extend(imm16), reg, reg */
1780 unsigned int op0
, op1
, result
, z
, s
;
1782 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1783 op0
= OP
[0] & 0xffff;
1784 op1
= State
.regs
[OP
[1]];
1787 /* Compute the condition codes. */
1789 s
= (result
& 0x80000000);
1791 /* Store the result and condition codes. */
1792 State
.regs
[OP
[2]] = result
;
1793 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1794 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1795 trace_output (OP_UIMM_REG_REG
);
1798 /* not reg1, reg2 */
1802 unsigned int op0
, result
, z
, s
;
1804 trace_input ("not", OP_REG_REG_MOVE
, 0);
1805 /* Compute the result. */
1806 op0
= State
.regs
[OP
[0]];
1809 /* Compute the condition codes. */
1811 s
= (result
& 0x80000000);
1813 /* Store the result and condition codes. */
1814 State
.regs
[OP
[1]] = result
;
1815 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1816 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1817 trace_output (OP_REG_REG_MOVE
);
1824 unsigned int op0
, op1
, op2
;
1827 trace_input ("set1", OP_BIT
, 0);
1828 op0
= State
.regs
[OP
[0]];
1830 temp
= SEXT16 (OP
[2]);
1832 temp
= load_mem (op0
+ op2
, 1);
1833 State
.sregs
[5] &= ~PSW_Z
;
1834 if ((temp
& (1 << op1
)) == 0)
1835 State
.sregs
[5] |= PSW_Z
;
1837 store_mem (op0
+ op2
, 1, temp
);
1838 trace_output (OP_BIT
);
1845 unsigned int op0
, op1
, op2
;
1848 trace_input ("not1", OP_BIT
, 0);
1849 op0
= State
.regs
[OP
[0]];
1851 temp
= SEXT16 (OP
[2]);
1853 temp
= load_mem (op0
+ op2
, 1);
1854 State
.sregs
[5] &= ~PSW_Z
;
1855 if ((temp
& (1 << op1
)) == 0)
1856 State
.sregs
[5] |= PSW_Z
;
1858 store_mem (op0
+ op2
, 1, temp
);
1859 trace_output (OP_BIT
);
1866 unsigned int op0
, op1
, op2
;
1869 trace_input ("clr1", OP_BIT
, 0);
1870 op0
= State
.regs
[OP
[0]];
1872 temp
= SEXT16 (OP
[2]);
1874 temp
= load_mem (op0
+ op2
, 1);
1875 State
.sregs
[5] &= ~PSW_Z
;
1876 if ((temp
& (1 << op1
)) == 0)
1877 State
.sregs
[5] |= PSW_Z
;
1878 temp
&= ~(1 << op1
);
1879 store_mem (op0
+ op2
, 1, temp
);
1880 trace_output (OP_BIT
);
1887 unsigned int op0
, op1
, op2
;
1890 trace_input ("tst1", OP_BIT
, 0);
1891 op0
= State
.regs
[OP
[0]];
1893 temp
= SEXT16 (OP
[2]);
1895 temp
= load_mem (op0
+ op2
, 1);
1896 State
.sregs
[5] &= ~PSW_Z
;
1897 if ((temp
& (1 << op1
)) == 0)
1898 State
.sregs
[5] |= PSW_Z
;
1899 trace_output (OP_BIT
);
1906 State
.exception
= SIGTRAP
;
1914 trace_input ("di", OP_NONE
, 0);
1915 State
.sregs
[5] |= PSW_ID
;
1916 trace_output (OP_NONE
);
1923 trace_input ("ei", OP_NONE
, 0);
1924 State
.sregs
[5] &= ~PSW_ID
;
1925 trace_output (OP_NONE
);
1928 /* halt, not supported */
1932 trace_input ("halt", OP_NONE
, 0);
1933 State
.exception
= SIGQUIT
;
1934 trace_output (OP_NONE
);
1937 /* reti, not supported */
1941 trace_input ("reti", OP_NONE
, 0);
1942 trace_output (OP_NONE
);
1944 if ((State
.sregs
[5] & (PSW_NP
| PSW_EP
)) == PSW_NP
)
1945 { /* Only NP is on */
1946 PC
= State
.sregs
[2] - 4; /* FEPC */
1947 State
.sregs
[5] = State
.sregs
[3]; /* FEPSW */
1951 PC
= State
.sregs
[0] - 4; /* EIPC */
1952 State
.sregs
[5] = State
.sregs
[1]; /* EIPSW */
1956 /* trap, not supportd */
1962 trace_input ("trap", OP_TRAP
, 0);
1963 trace_output (OP_TRAP
);
1965 /* Trap 31 is used for simulating OS I/O functions */
1969 int save_errno
= errno
;
1972 /* Registers passed to trap 0 */
1974 #define FUNC State.regs[6] /* function number, return value */
1975 #define PARM1 State.regs[7] /* optional parm 1 */
1976 #define PARM2 State.regs[8] /* optional parm 2 */
1977 #define PARM3 State.regs[9] /* optional parm 3 */
1979 /* Registers set by trap 0 */
1981 #define RETVAL State.regs[10] /* return value */
1982 #define RETERR State.regs[11] /* return error code */
1984 /* Turn a pointer in a register into a pointer into real memory. */
1986 #define MEMPTR(x) (map (x))
1990 #if !defined(__GO32__) && !defined(_WIN32)
1995 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
1996 (char **)MEMPTR (PARM3
));
1999 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2008 RETVAL
= pipe (host_fd
);
2009 SW (buf
, host_fd
[0]);
2010 buf
+= sizeof(uint16
);
2011 SW (buf
, host_fd
[1]);
2019 RETVAL
= wait (&status
);
2027 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2032 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2033 MEMPTR (PARM2
), PARM3
);
2035 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2036 MEMPTR (PARM2
), PARM3
);
2039 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2042 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2045 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2048 /* EXIT - caller can look in PARM1 to work out the
2050 if (PARM1
== 0xdead || PARM1
== 0x1)
2051 State
.exception
= SIGABRT
;
2053 State
.exception
= SIGQUIT
;
2057 case SYS_stat
: /* added at hmsi */
2058 /* stat system call */
2060 struct stat host_stat
;
2063 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2067 /* The hard-coded offsets and sizes were determined by using
2068 * the D10V compiler on a test program that used struct stat.
2070 SW (buf
, host_stat
.st_dev
);
2071 SW (buf
+2, host_stat
.st_ino
);
2072 SW (buf
+4, host_stat
.st_mode
);
2073 SW (buf
+6, host_stat
.st_nlink
);
2074 SW (buf
+8, host_stat
.st_uid
);
2075 SW (buf
+10, host_stat
.st_gid
);
2076 SW (buf
+12, host_stat
.st_rdev
);
2077 SLW (buf
+16, host_stat
.st_size
);
2078 SLW (buf
+20, host_stat
.st_atime
);
2079 SLW (buf
+28, host_stat
.st_mtime
);
2080 SLW (buf
+36, host_stat
.st_ctime
);
2085 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2089 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2092 /* Cast the second argument to void *, to avoid type mismatch
2093 if a prototype is present. */
2094 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2103 { /* Trap 0 -> 30 */
2104 State
.sregs
[0] = PC
+ 4; /* EIPC */
2105 State
.sregs
[1] = State
.sregs
[5]; /* EIPSW */
2106 State
.sregs
[4] &= 0xffff0000; /* Mask out EICC */
2107 State
.sregs
[4] |= 0x40 + OP
[0]; /* EICC */
2108 State
.sregs
[5] |= PSW_EP
| PSW_ID
; /* Now doing exception processing */
2109 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2119 trace_input ("ldsr", OP_LDSR
, 0);
2120 op0
= State
.regs
[OP
[0]];
2121 State
.sregs
[OP
[1]] = op0
;
2122 trace_output (OP_LDSR
);
2125 /* stsr, not supported */
2131 trace_input ("stsr", OP_STSR
, 0);
2132 op0
= State
.sregs
[OP
[1]];
2133 State
.regs
[OP
[0]] = op0
;
2134 trace_output (OP_STSR
);
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