25 #include "targ-vals.h"
27 #include "libiberty.h"
30 #if !defined(__GO32__) && !defined(_WIN32)
32 #include <sys/times.h>
36 /* This is an array of the bit positions of registers r20 .. r31 in
37 that order in a prepare/dispose instruction. */
38 int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
39 /* This is an array of the bit positions of registers r16 .. r31 in
40 that order in a push/pop instruction. */
41 int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
42 /* This is an array of the bit positions of registers r1 .. r15 in
43 that order in a push/pop instruction. */
44 int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
47 #ifndef SIZE_INSTRUCTION
48 #define SIZE_INSTRUCTION 18
52 #define SIZE_VALUES 11
56 unsigned32 trace_values
[3];
59 const char *trace_name
;
64 trace_input (name
, type
, size
)
70 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
75 trace_module
= TRACE_ALU_IDX
;
88 trace_values
[0] = State
.regs
[OP
[0]];
95 trace_values
[0] = State
.regs
[OP
[1]];
96 trace_values
[1] = State
.regs
[OP
[0]];
102 trace_values
[0] = SEXT5 (OP
[0]);
103 trace_values
[1] = OP
[1];
104 trace_num_values
= 2;
107 case OP_IMM_REG_MOVE
:
108 trace_values
[0] = SEXT5 (OP
[0]);
109 trace_num_values
= 1;
113 trace_values
[0] = State
.pc
;
114 trace_values
[1] = SEXT9 (OP
[0]);
115 trace_values
[2] = PSW
;
116 trace_num_values
= 3;
120 trace_values
[0] = OP
[1] * size
;
121 trace_values
[1] = State
.regs
[30];
122 trace_num_values
= 2;
126 trace_values
[0] = State
.regs
[OP
[0]];
127 trace_values
[1] = OP
[1] * size
;
128 trace_values
[2] = State
.regs
[30];
129 trace_num_values
= 3;
133 trace_values
[0] = EXTEND16 (OP
[2]);
134 trace_values
[1] = State
.regs
[OP
[0]];
135 trace_num_values
= 2;
139 trace_values
[0] = State
.regs
[OP
[1]];
140 trace_values
[1] = EXTEND16 (OP
[2]);
141 trace_values
[2] = State
.regs
[OP
[0]];
142 trace_num_values
= 3;
146 trace_values
[0] = SEXT22 (OP
[0]);
147 trace_values
[1] = State
.pc
;
148 trace_num_values
= 2;
152 trace_values
[0] = EXTEND16 (OP
[0]) << size
;
153 trace_values
[1] = State
.regs
[OP
[1]];
154 trace_num_values
= 2;
157 case OP_IMM16_REG_REG
:
158 trace_values
[0] = EXTEND16 (OP
[2]) << size
;
159 trace_values
[1] = State
.regs
[OP
[1]];
160 trace_num_values
= 2;
163 case OP_UIMM_REG_REG
:
164 trace_values
[0] = (OP
[0] & 0xffff) << size
;
165 trace_values
[1] = State
.regs
[OP
[1]];
166 trace_num_values
= 2;
169 case OP_UIMM16_REG_REG
:
170 trace_values
[0] = (OP
[2]) << size
;
171 trace_values
[1] = State
.regs
[OP
[1]];
172 trace_num_values
= 2;
176 trace_num_values
= 0;
180 trace_values
[0] = PSW
;
181 trace_num_values
= 1;
185 trace_num_values
= 0;
189 trace_values
[0] = State
.regs
[OP
[0]];
190 trace_num_values
= 1;
194 trace_values
[0] = State
.sregs
[OP
[1]];
195 trace_num_values
= 1;
201 trace_result (int has_result
, unsigned32 result
)
209 /* write out the values saved during the trace_input call */
212 for (i
= 0; i
< trace_num_values
; i
++)
214 sprintf (chp
, "%*s0x%.8lx", SIZE_VALUES
- 10, "",
215 (long) trace_values
[i
]);
216 chp
= strchr (chp
, '\0');
220 sprintf (chp
, "%*s", SIZE_VALUES
, "");
221 chp
= strchr (chp
, '\0');
225 /* append any result to the end of the buffer */
227 sprintf (chp
, " :: 0x%.8lx", (unsigned long)result
);
229 trace_generic (simulator
, STATE_CPU (simulator
, 0), trace_module
, buf
);
233 trace_output (result
)
234 enum op_types result
;
236 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
258 trace_result (1, State
.regs
[OP
[0]]);
262 case OP_REG_REG_MOVE
:
264 case OP_IMM_REG_MOVE
:
267 trace_result (1, State
.regs
[OP
[1]]);
271 case OP_UIMM_REG_REG
:
272 case OP_IMM16_REG_REG
:
273 case OP_UIMM16_REG_REG
:
274 trace_result (1, State
.regs
[OP
[1]]);
279 trace_result (1, State
.regs
[OP
[1]]);
285 trace_result (1, State
.sregs
[OP
[1]]);
292 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
294 condition_met (unsigned code
)
296 unsigned int psw
= PSW
;
300 case 0x0: return ((psw
& PSW_OV
) != 0);
301 case 0x1: return ((psw
& PSW_CY
) != 0);
302 case 0x2: return ((psw
& PSW_Z
) != 0);
303 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
304 case 0x4: return ((psw
& PSW_S
) != 0);
305 /*case 0x5: return 1;*/
306 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
307 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
308 case 0x8: return ((psw
& PSW_OV
) == 0);
309 case 0x9: return ((psw
& PSW_CY
) == 0);
310 case 0xa: return ((psw
& PSW_Z
) == 0);
311 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
312 case 0xc: return ((psw
& PSW_S
) == 0);
313 case 0xd: return ((psw
& PSW_SAT
) != 0);
314 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
315 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
322 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
324 unsigned long result
= (a1
+ a2
);
326 * carry
= (result
< a1
);
332 Multiply64 (boolean sign
, unsigned long op0
)
343 op1
= State
.regs
[ OP
[1] ];
347 /* Compute sign of result and adjust operands if necessary. */
349 sign
= (op0
^ op1
) & 0x80000000;
351 if (((signed long) op0
) < 0)
354 if (((signed long) op1
) < 0)
358 /* We can split the 32x32 into four 16x16 operations. This ensures
359 that we do not lose precision on 32bit only hosts: */
360 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
361 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
362 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
363 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
365 /* We now need to add all of these results together, taking care
366 to propogate the carries from the additions: */
367 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
369 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
370 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
374 /* Negate result if necessary. */
378 if (RdLo
== 0xFFFFFFFF)
387 /* Don't store into register 0. */
389 State
.regs
[ OP
[1] ] = RdLo
;
391 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
397 /* Read a null terminated string from memory, return in a buffer */
405 while (sim_core_read_1 (STATE_CPU (sd
, 0),
406 PC
, read_map
, addr
+ nr
) != 0)
408 buf
= NZALLOC (char, nr
+ 1);
409 sim_read (simulator
, addr
, buf
, nr
);
413 /* Read a null terminated argument vector from memory, return in a
416 fetch_argv (sd
, addr
)
422 char **buf
= xmalloc (max_nr
* sizeof (char*));
425 unsigned32 a
= sim_core_read_4 (STATE_CPU (sd
, 0),
426 PC
, read_map
, addr
+ nr
* 4);
428 buf
[nr
] = fetch_str (sd
, a
);
430 if (nr
== max_nr
- 1)
433 buf
= xrealloc (buf
, max_nr
* sizeof (char*));
445 trace_input ("sst.b", OP_STORE16
, 1);
447 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
449 trace_output (OP_STORE16
);
458 trace_input ("sst.h", OP_STORE16
, 2);
460 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
462 trace_output (OP_STORE16
);
471 trace_input ("sst.w", OP_STORE16
, 4);
473 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
475 trace_output (OP_STORE16
);
486 trace_input ("ld.b", OP_LOAD32
, 1);
488 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
490 State
.regs
[ OP
[1] ] = EXTEND8 (load_mem (adr
, 1));
492 trace_output (OP_LOAD32
);
503 trace_input ("ld.h", OP_LOAD32
, 2);
505 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
508 State
.regs
[ OP
[1] ] = EXTEND16 (load_mem (adr
, 2));
510 trace_output (OP_LOAD32
);
521 trace_input ("ld.w", OP_LOAD32
, 4);
523 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
526 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
528 trace_output (OP_LOAD32
);
537 trace_input ("st.b", OP_STORE32
, 1);
539 store_mem (State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
541 trace_output (OP_STORE32
);
552 trace_input ("st.h", OP_STORE32
, 2);
554 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
557 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
559 trace_output (OP_STORE32
);
570 trace_input ("st.w", OP_STORE32
, 4);
572 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
575 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
577 trace_output (OP_STORE32
);
586 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
588 trace_input ("add", OP_REG_REG
, 0);
590 /* Compute the result. */
592 op0
= State
.regs
[ OP
[0] ];
593 op1
= State
.regs
[ OP
[1] ];
597 /* Compute the condition codes. */
599 s
= (result
& 0x80000000);
600 cy
= (result
< op0
|| result
< op1
);
601 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
602 && (op0
& 0x80000000) != (result
& 0x80000000));
604 /* Store the result and condition codes. */
605 State
.regs
[OP
[1]] = result
;
606 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
607 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
608 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
609 trace_output (OP_REG_REG
);
614 /* add sign_extend(imm5), reg */
618 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
621 trace_input ("add", OP_IMM_REG
, 0);
623 /* Compute the result. */
624 temp
= SEXT5 (OP
[0]);
626 op1
= State
.regs
[OP
[1]];
629 /* Compute the condition codes. */
631 s
= (result
& 0x80000000);
632 cy
= (result
< op0
|| result
< op1
);
633 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
634 && (op0
& 0x80000000) != (result
& 0x80000000));
636 /* Store the result and condition codes. */
637 State
.regs
[OP
[1]] = result
;
638 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
639 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
640 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
641 trace_output (OP_IMM_REG
);
646 /* addi sign_extend(imm16), reg, reg */
650 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
652 trace_input ("addi", OP_IMM16_REG_REG
, 0);
654 /* Compute the result. */
656 op0
= EXTEND16 (OP
[2]);
657 op1
= State
.regs
[ OP
[0] ];
660 /* Compute the condition codes. */
662 s
= (result
& 0x80000000);
663 cy
= (result
< op0
|| result
< op1
);
664 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
665 && (op0
& 0x80000000) != (result
& 0x80000000));
667 /* Store the result and condition codes. */
668 State
.regs
[OP
[1]] = result
;
669 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
670 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
671 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
672 trace_output (OP_IMM16_REG_REG
);
681 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
683 trace_input ("sub", OP_REG_REG
, 0);
684 /* Compute the result. */
685 op0
= State
.regs
[ OP
[0] ];
686 op1
= State
.regs
[ OP
[1] ];
689 /* Compute the condition codes. */
691 s
= (result
& 0x80000000);
693 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
694 && (op1
& 0x80000000) != (result
& 0x80000000));
696 /* Store the result and condition codes. */
697 State
.regs
[OP
[1]] = result
;
698 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
699 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
700 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
701 trace_output (OP_REG_REG
);
706 /* subr reg1, reg2 */
710 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
712 trace_input ("subr", OP_REG_REG
, 0);
713 /* Compute the result. */
714 op0
= State
.regs
[ OP
[0] ];
715 op1
= State
.regs
[ OP
[1] ];
718 /* Compute the condition codes. */
720 s
= (result
& 0x80000000);
722 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
723 && (op0
& 0x80000000) != (result
& 0x80000000));
725 /* Store the result and condition codes. */
726 State
.regs
[OP
[1]] = result
;
727 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
728 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
729 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
730 trace_output (OP_REG_REG
);
739 trace_input ("mulh", OP_REG_REG
, 0);
741 State
.regs
[ OP
[1] ] = (EXTEND16 (State
.regs
[ OP
[1] ]) * EXTEND16 (State
.regs
[ OP
[0] ]));
743 trace_output (OP_REG_REG
);
748 /* mulh sign_extend(imm5), reg2 */
752 trace_input ("mulh", OP_IMM_REG
, 0);
754 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
756 trace_output (OP_IMM_REG
);
761 /* mulhi imm16, reg1, reg2 */
765 trace_input ("mulhi", OP_IMM16_REG_REG
, 0);
767 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[0] ]) * EXTEND16 (OP
[2]);
769 trace_output (OP_IMM16_REG_REG
);
774 /* divh reg1, reg2 */
778 unsigned int op0
, op1
, result
, ov
, s
, z
;
781 trace_input ("divh", OP_REG_REG
, 0);
783 /* Compute the result. */
784 temp
= EXTEND16 (State
.regs
[ OP
[0] ]);
786 op1
= State
.regs
[OP
[1]];
788 if (op0
== 0xffffffff && op1
== 0x80000000)
804 /* Compute the condition codes. */
806 s
= (result
& 0x80000000);
808 /* Store the result and condition codes. */
809 State
.regs
[OP
[1]] = result
;
810 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
811 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
812 | (ov
? PSW_OV
: 0));
813 trace_output (OP_REG_REG
);
822 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
824 trace_input ("cmp", OP_REG_REG_CMP
, 0);
825 /* Compute the result. */
826 op0
= State
.regs
[ OP
[0] ];
827 op1
= State
.regs
[ OP
[1] ];
830 /* Compute the condition codes. */
832 s
= (result
& 0x80000000);
834 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
835 && (op1
& 0x80000000) != (result
& 0x80000000));
837 /* Set condition codes. */
838 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
839 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
840 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
841 trace_output (OP_REG_REG_CMP
);
846 /* cmp sign_extend(imm5), reg */
850 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
853 /* Compute the result. */
854 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
855 temp
= SEXT5 (OP
[0]);
857 op1
= State
.regs
[OP
[1]];
860 /* Compute the condition codes. */
862 s
= (result
& 0x80000000);
864 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
865 && (op1
& 0x80000000) != (result
& 0x80000000));
867 /* Set condition codes. */
868 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
869 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
870 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
871 trace_output (OP_IMM_REG_CMP
);
880 trace_input ("setf", OP_EX1
, 0);
882 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
884 trace_output (OP_EX1
);
893 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
895 trace_input ("satadd", OP_REG_REG
, 0);
896 /* Compute the result. */
897 op0
= State
.regs
[ OP
[0] ];
898 op1
= State
.regs
[ OP
[1] ];
901 /* Compute the condition codes. */
903 s
= (result
& 0x80000000);
904 cy
= (result
< op0
|| result
< op1
);
905 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
906 && (op0
& 0x80000000) != (result
& 0x80000000));
909 /* Store the result and condition codes. */
910 State
.regs
[OP
[1]] = result
;
911 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
912 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
913 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
914 | (sat
? PSW_SAT
: 0));
916 /* Handle saturated results. */
918 State
.regs
[OP
[1]] = 0x80000000;
920 State
.regs
[OP
[1]] = 0x7fffffff;
921 trace_output (OP_REG_REG
);
926 /* satadd sign_extend(imm5), reg */
930 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
934 trace_input ("satadd", OP_IMM_REG
, 0);
936 /* Compute the result. */
937 temp
= SEXT5 (OP
[0]);
939 op1
= State
.regs
[OP
[1]];
942 /* Compute the condition codes. */
944 s
= (result
& 0x80000000);
945 cy
= (result
< op0
|| result
< op1
);
946 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
947 && (op0
& 0x80000000) != (result
& 0x80000000));
950 /* Store the result and condition codes. */
951 State
.regs
[OP
[1]] = result
;
952 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
953 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
954 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
955 | (sat
? PSW_SAT
: 0));
957 /* Handle saturated results. */
959 State
.regs
[OP
[1]] = 0x80000000;
961 State
.regs
[OP
[1]] = 0x7fffffff;
962 trace_output (OP_IMM_REG
);
967 /* satsub reg1, reg2 */
971 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
973 trace_input ("satsub", OP_REG_REG
, 0);
975 /* Compute the result. */
976 op0
= State
.regs
[ OP
[0] ];
977 op1
= State
.regs
[ OP
[1] ];
980 /* Compute the condition codes. */
982 s
= (result
& 0x80000000);
984 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
985 && (op1
& 0x80000000) != (result
& 0x80000000));
988 /* Store the result and condition codes. */
989 State
.regs
[OP
[1]] = result
;
990 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
991 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
992 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
993 | (sat
? PSW_SAT
: 0));
995 /* Handle saturated results. */
997 State
.regs
[OP
[1]] = 0x80000000;
999 State
.regs
[OP
[1]] = 0x7fffffff;
1000 trace_output (OP_REG_REG
);
1004 /* satsubi sign_extend(imm16), reg */
1008 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1011 trace_input ("satsubi", OP_IMM_REG
, 0);
1013 /* Compute the result. */
1014 temp
= EXTEND16 (OP
[2]);
1016 op1
= State
.regs
[ OP
[0] ];
1019 /* Compute the condition codes. */
1021 s
= (result
& 0x80000000);
1023 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1024 && (op1
& 0x80000000) != (result
& 0x80000000));
1027 /* Store the result and condition codes. */
1028 State
.regs
[OP
[1]] = result
;
1029 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1030 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1031 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1032 | (sat
? PSW_SAT
: 0));
1034 /* Handle saturated results. */
1036 State
.regs
[OP
[1]] = 0x80000000;
1038 State
.regs
[OP
[1]] = 0x7fffffff;
1039 trace_output (OP_IMM_REG
);
1044 /* satsubr reg,reg */
1048 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1050 trace_input ("satsubr", OP_REG_REG
, 0);
1052 /* Compute the result. */
1053 op0
= State
.regs
[ OP
[0] ];
1054 op1
= State
.regs
[ OP
[1] ];
1057 /* Compute the condition codes. */
1059 s
= (result
& 0x80000000);
1060 cy
= (result
< op0
);
1061 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1062 && (op1
& 0x80000000) != (result
& 0x80000000));
1065 /* Store the result and condition codes. */
1066 State
.regs
[OP
[1]] = result
;
1067 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1068 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1069 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1070 | (sat
? PSW_SAT
: 0));
1072 /* Handle saturated results. */
1074 State
.regs
[OP
[1]] = 0x80000000;
1076 State
.regs
[OP
[1]] = 0x7fffffff;
1077 trace_output (OP_REG_REG
);
1086 unsigned int op0
, op1
, result
, z
, s
;
1088 trace_input ("tst", OP_REG_REG_CMP
, 0);
1090 /* Compute the result. */
1091 op0
= State
.regs
[ OP
[0] ];
1092 op1
= State
.regs
[ OP
[1] ];
1095 /* Compute the condition codes. */
1097 s
= (result
& 0x80000000);
1099 /* Store the condition codes. */
1100 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1101 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1102 trace_output (OP_REG_REG_CMP
);
1107 /* mov sign_extend(imm5), reg */
1111 int value
= SEXT5 (OP
[0]);
1113 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1115 State
.regs
[ OP
[1] ] = value
;
1117 trace_output (OP_IMM_REG_MOVE
);
1122 /* movhi imm16, reg, reg */
1126 trace_input ("movhi", OP_UIMM16_REG_REG
, 16);
1128 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + (OP
[2] << 16);
1130 trace_output (OP_UIMM16_REG_REG
);
1135 /* sar zero_extend(imm5),reg1 */
1139 unsigned int op0
, op1
, result
, z
, s
, cy
;
1141 trace_input ("sar", OP_IMM_REG
, 0);
1143 op1
= State
.regs
[ OP
[1] ];
1144 result
= (signed)op1
>> op0
;
1146 /* Compute the condition codes. */
1148 s
= (result
& 0x80000000);
1149 cy
= (op1
& (1 << (op0
- 1)));
1151 /* Store the result and condition codes. */
1152 State
.regs
[ OP
[1] ] = result
;
1153 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1154 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1155 | (cy
? PSW_CY
: 0));
1156 trace_output (OP_IMM_REG
);
1161 /* sar reg1, reg2 */
1165 unsigned int op0
, op1
, result
, z
, s
, cy
;
1167 trace_input ("sar", OP_REG_REG
, 0);
1169 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1170 op1
= State
.regs
[ OP
[1] ];
1171 result
= (signed)op1
>> op0
;
1173 /* Compute the condition codes. */
1175 s
= (result
& 0x80000000);
1176 cy
= (op1
& (1 << (op0
- 1)));
1178 /* Store the result and condition codes. */
1179 State
.regs
[OP
[1]] = result
;
1180 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1181 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1182 | (cy
? PSW_CY
: 0));
1183 trace_output (OP_REG_REG
);
1188 /* shl zero_extend(imm5),reg1 */
1192 unsigned int op0
, op1
, result
, z
, s
, cy
;
1194 trace_input ("shl", OP_IMM_REG
, 0);
1196 op1
= State
.regs
[ OP
[1] ];
1197 result
= op1
<< op0
;
1199 /* Compute the condition codes. */
1201 s
= (result
& 0x80000000);
1202 cy
= (op1
& (1 << (32 - op0
)));
1204 /* Store the result and condition codes. */
1205 State
.regs
[OP
[1]] = result
;
1206 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1207 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1208 | (cy
? PSW_CY
: 0));
1209 trace_output (OP_IMM_REG
);
1214 /* shl reg1, reg2 */
1218 unsigned int op0
, op1
, result
, z
, s
, cy
;
1220 trace_input ("shl", OP_REG_REG
, 0);
1221 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1222 op1
= State
.regs
[ OP
[1] ];
1223 result
= op1
<< op0
;
1225 /* Compute the condition codes. */
1227 s
= (result
& 0x80000000);
1228 cy
= (op1
& (1 << (32 - op0
)));
1230 /* Store the result and condition codes. */
1231 State
.regs
[OP
[1]] = result
;
1232 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1233 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1234 | (cy
? PSW_CY
: 0));
1235 trace_output (OP_REG_REG
);
1240 /* shr zero_extend(imm5),reg1 */
1244 unsigned int op0
, op1
, result
, z
, s
, cy
;
1246 trace_input ("shr", OP_IMM_REG
, 0);
1248 op1
= State
.regs
[ OP
[1] ];
1249 result
= op1
>> op0
;
1251 /* Compute the condition codes. */
1253 s
= (result
& 0x80000000);
1254 cy
= (op1
& (1 << (op0
- 1)));
1256 /* Store the result and condition codes. */
1257 State
.regs
[OP
[1]] = result
;
1258 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1259 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1260 | (cy
? PSW_CY
: 0));
1261 trace_output (OP_IMM_REG
);
1266 /* shr reg1, reg2 */
1270 unsigned int op0
, op1
, result
, z
, s
, cy
;
1272 trace_input ("shr", OP_REG_REG
, 0);
1273 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1274 op1
= State
.regs
[ OP
[1] ];
1275 result
= op1
>> op0
;
1277 /* Compute the condition codes. */
1279 s
= (result
& 0x80000000);
1280 cy
= (op1
& (1 << (op0
- 1)));
1282 /* Store the result and condition codes. */
1283 State
.regs
[OP
[1]] = result
;
1284 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1285 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1286 | (cy
? PSW_CY
: 0));
1287 trace_output (OP_REG_REG
);
1296 unsigned int op0
, op1
, result
, z
, s
;
1298 trace_input ("or", OP_REG_REG
, 0);
1300 /* Compute the result. */
1301 op0
= State
.regs
[ OP
[0] ];
1302 op1
= State
.regs
[ OP
[1] ];
1305 /* Compute the condition codes. */
1307 s
= (result
& 0x80000000);
1309 /* Store the result and condition codes. */
1310 State
.regs
[OP
[1]] = result
;
1311 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1312 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1313 trace_output (OP_REG_REG
);
1318 /* ori zero_extend(imm16), reg, reg */
1322 unsigned int op0
, op1
, result
, z
, s
;
1324 trace_input ("ori", OP_UIMM16_REG_REG
, 0);
1326 op1
= State
.regs
[ OP
[0] ];
1329 /* Compute the condition codes. */
1331 s
= (result
& 0x80000000);
1333 /* Store the result and condition codes. */
1334 State
.regs
[OP
[1]] = result
;
1335 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1336 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1337 trace_output (OP_UIMM16_REG_REG
);
1346 unsigned int op0
, op1
, result
, z
, s
;
1348 trace_input ("and", OP_REG_REG
, 0);
1350 /* Compute the result. */
1351 op0
= State
.regs
[ OP
[0] ];
1352 op1
= State
.regs
[ OP
[1] ];
1355 /* Compute the condition codes. */
1357 s
= (result
& 0x80000000);
1359 /* Store the result and condition codes. */
1360 State
.regs
[OP
[1]] = result
;
1361 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1362 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1363 trace_output (OP_REG_REG
);
1368 /* andi zero_extend(imm16), reg, reg */
1372 unsigned int result
, z
;
1374 trace_input ("andi", OP_UIMM16_REG_REG
, 0);
1376 result
= OP
[2] & State
.regs
[ OP
[0] ];
1378 /* Compute the condition codes. */
1381 /* Store the result and condition codes. */
1382 State
.regs
[ OP
[1] ] = result
;
1384 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1385 PSW
|= (z
? PSW_Z
: 0);
1387 trace_output (OP_UIMM16_REG_REG
);
1396 unsigned int op0
, op1
, result
, z
, s
;
1398 trace_input ("xor", OP_REG_REG
, 0);
1400 /* Compute the result. */
1401 op0
= State
.regs
[ OP
[0] ];
1402 op1
= State
.regs
[ OP
[1] ];
1405 /* Compute the condition codes. */
1407 s
= (result
& 0x80000000);
1409 /* Store the result and condition codes. */
1410 State
.regs
[OP
[1]] = result
;
1411 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1412 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1413 trace_output (OP_REG_REG
);
1418 /* xori zero_extend(imm16), reg, reg */
1422 unsigned int op0
, op1
, result
, z
, s
;
1424 trace_input ("xori", OP_UIMM16_REG_REG
, 0);
1426 op1
= State
.regs
[ OP
[0] ];
1429 /* Compute the condition codes. */
1431 s
= (result
& 0x80000000);
1433 /* Store the result and condition codes. */
1434 State
.regs
[OP
[1]] = result
;
1435 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1436 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1437 trace_output (OP_UIMM16_REG_REG
);
1442 /* not reg1, reg2 */
1446 unsigned int op0
, result
, z
, s
;
1448 trace_input ("not", OP_REG_REG_MOVE
, 0);
1449 /* Compute the result. */
1450 op0
= State
.regs
[ OP
[0] ];
1453 /* Compute the condition codes. */
1455 s
= (result
& 0x80000000);
1457 /* Store the result and condition codes. */
1458 State
.regs
[OP
[1]] = result
;
1459 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1460 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1461 trace_output (OP_REG_REG_MOVE
);
1470 unsigned int op0
, op1
, op2
;
1473 trace_input ("set1", OP_BIT
, 0);
1474 op0
= State
.regs
[ OP
[0] ];
1476 temp
= EXTEND16 (OP
[2]);
1478 temp
= load_mem (op0
+ op2
, 1);
1480 if ((temp
& (1 << op1
)) == 0)
1483 store_mem (op0
+ op2
, 1, temp
);
1484 trace_output (OP_BIT
);
1493 unsigned int op0
, op1
, op2
;
1496 trace_input ("not1", OP_BIT
, 0);
1497 op0
= State
.regs
[ OP
[0] ];
1499 temp
= EXTEND16 (OP
[2]);
1501 temp
= load_mem (op0
+ op2
, 1);
1503 if ((temp
& (1 << op1
)) == 0)
1506 store_mem (op0
+ op2
, 1, temp
);
1507 trace_output (OP_BIT
);
1516 unsigned int op0
, op1
, op2
;
1519 trace_input ("clr1", OP_BIT
, 0);
1520 op0
= State
.regs
[ OP
[0] ];
1522 temp
= EXTEND16 (OP
[2]);
1524 temp
= load_mem (op0
+ op2
, 1);
1526 if ((temp
& (1 << op1
)) == 0)
1528 temp
&= ~(1 << op1
);
1529 store_mem (op0
+ op2
, 1, temp
);
1530 trace_output (OP_BIT
);
1539 unsigned int op0
, op1
, op2
;
1542 trace_input ("tst1", OP_BIT
, 0);
1543 op0
= State
.regs
[ OP
[0] ];
1545 temp
= EXTEND16 (OP
[2]);
1547 temp
= load_mem (op0
+ op2
, 1);
1549 if ((temp
& (1 << op1
)) == 0)
1551 trace_output (OP_BIT
);
1560 trace_input ("di", OP_NONE
, 0);
1562 trace_output (OP_NONE
);
1571 trace_input ("ei", OP_NONE
, 0);
1573 trace_output (OP_NONE
);
1582 trace_input ("halt", OP_NONE
, 0);
1583 /* FIXME this should put processor into a mode where NMI still handled */
1584 trace_output (OP_NONE
);
1585 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1586 sim_stopped
, SIM_SIGTRAP
);
1594 trace_input ("trap", OP_TRAP
, 0);
1595 trace_output (OP_TRAP
);
1597 /* Trap 31 is used for simulating OS I/O functions */
1601 int save_errno
= errno
;
1604 /* Registers passed to trap 0 */
1606 #define FUNC State.regs[6] /* function number, return value */
1607 #define PARM1 State.regs[7] /* optional parm 1 */
1608 #define PARM2 State.regs[8] /* optional parm 2 */
1609 #define PARM3 State.regs[9] /* optional parm 3 */
1611 /* Registers set by trap 0 */
1613 #define RETVAL State.regs[10] /* return value */
1614 #define RETERR State.regs[11] /* return error code */
1616 /* Turn a pointer in a register into a pointer into real memory. */
1618 #define MEMPTR(x) (map (x))
1624 #ifdef TARGET_SYS_fork
1625 case TARGET_SYS_fork
:
1632 #ifdef TARGET_SYS_execv
1633 case TARGET_SYS_execve
:
1635 char *path
= fetch_str (simulator
, PARM1
);
1636 char **argv
= fetch_argv (simulator
, PARM2
);
1637 char **envp
= fetch_argv (simulator
, PARM3
);
1638 RETVAL
= execve (path
, argv
, envp
);
1648 #ifdef TARGET_SYS_execv
1649 case TARGET_SYS_execv
:
1651 char *path
= fetch_str (simulator
, PARM1
);
1652 char **argv
= fetch_argv (simulator
, PARM2
);
1653 RETVAL
= execv (path
, argv
);
1662 #ifdef TARGET_SYS_pipe
1663 case TARGET_SYS_pipe
:
1669 RETVAL
= pipe (host_fd
);
1670 SW (buf
, host_fd
[0]);
1671 buf
+= sizeof(uint16
);
1672 SW (buf
, host_fd
[1]);
1679 #ifdef TARGET_SYS_wait
1680 case TARGET_SYS_wait
:
1684 RETVAL
= wait (&status
);
1691 #ifdef TARGET_SYS_read
1692 case TARGET_SYS_read
:
1694 char *buf
= zalloc (PARM3
);
1695 RETVAL
= sim_io_read (simulator
, PARM1
, buf
, PARM3
);
1696 sim_write (simulator
, PARM2
, buf
, PARM3
);
1702 #ifdef TARGET_SYS_write
1703 case TARGET_SYS_write
:
1705 char *buf
= zalloc (PARM3
);
1706 sim_read (simulator
, PARM2
, buf
, PARM3
);
1708 RETVAL
= sim_io_write_stdout (simulator
, buf
, PARM3
);
1710 RETVAL
= sim_io_write (simulator
, PARM1
, buf
, PARM3
);
1716 #ifdef TARGET_SYS_lseek
1717 case TARGET_SYS_lseek
:
1718 RETVAL
= sim_io_lseek (simulator
, PARM1
, PARM2
, PARM3
);
1722 #ifdef TARGET_SYS_close
1723 case TARGET_SYS_close
:
1724 RETVAL
= sim_io_close (simulator
, PARM1
);
1728 #ifdef TARGET_SYS_open
1729 case TARGET_SYS_open
:
1731 char *buf
= fetch_str (simulator
, PARM1
);
1732 RETVAL
= sim_io_open (simulator
, buf
, PARM2
);
1738 #ifdef TARGET_SYS_exit
1739 case TARGET_SYS_exit
:
1740 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
1741 /* get signal encoded by kill */
1742 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1743 sim_signalled
, PARM1
& 0xffff);
1744 else if (PARM1
== 0xdead)
1746 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1747 sim_stopped
, SIM_SIGABRT
);
1749 /* PARM1 has exit status */
1750 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1755 #if !defined(__GO32__) && !defined(_WIN32)
1756 #ifdef TARGET_SYS_stat
1757 case TARGET_SYS_stat
: /* added at hmsi */
1758 /* stat system call */
1760 struct stat host_stat
;
1762 char *path
= fetch_str (simulator
, PARM1
);
1764 RETVAL
= stat (path
, &host_stat
);
1769 /* Just wild-assed guesses. */
1770 store_mem (buf
, 2, host_stat
.st_dev
);
1771 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1772 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1773 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1774 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1775 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1776 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1777 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1778 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1779 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1780 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1787 #ifdef TARGET_SYS_chown
1788 case TARGET_SYS_chown
:
1790 char *path
= fetch_str (simulator
, PARM1
);
1791 RETVAL
= chown (path
, PARM2
, PARM3
);
1799 #ifdef TARGET_SYS_chmod
1800 case TARGET_SYS_chmod
:
1802 char *path
= fetch_str (simulator
, PARM1
);
1803 RETVAL
= chmod (path
, PARM2
);
1810 #ifdef TARGET_SYS_time
1812 case TARGET_SYS_time
:
1815 RETVAL
= time (&now
);
1816 store_mem (PARM1
, 4, now
);
1822 #if !defined(__GO32__) && !defined(_WIN32)
1823 #ifdef TARGET_SYS_times
1824 case TARGET_SYS_times
:
1827 RETVAL
= times (&tms
);
1828 store_mem (PARM1
, 4, tms
.tms_utime
);
1829 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
1830 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
1831 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
1837 #ifdef TARGET_SYS_gettimeofday
1838 #if !defined(__GO32__) && !defined(_WIN32)
1839 case TARGET_SYS_gettimeofday
:
1843 RETVAL
= gettimeofday (&t
, &tz
);
1844 store_mem (PARM1
, 4, t
.tv_sec
);
1845 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
1846 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
1847 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
1853 #ifdef TARGET_SYS_utime
1855 case TARGET_SYS_utime
:
1857 /* Cast the second argument to void *, to avoid type mismatch
1858 if a prototype is present. */
1859 sim_io_error (simulator
, "Utime not supported");
1860 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1875 { /* Trap 0 -> 30 */
1880 ECR
|= 0x40 + OP
[0];
1881 /* Flag that we are now doing exception processing. */
1882 PSW
|= PSW_EP
| PSW_ID
;
1883 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
1889 /* tst1 reg2, [reg1] */
1895 trace_input ("tst1", OP_BIT
, 1);
1897 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
1900 if ((temp
& (1 << State
.regs
[ OP
[1] & 0x7 ])) == 0)
1903 trace_output (OP_BIT
);
1908 /* mulu reg1, reg2, reg3 */
1912 trace_input ("mulu", OP_REG_REG_REG
, 0);
1914 Multiply64 (false, State
.regs
[ OP
[0] ]);
1916 trace_output (OP_REG_REG_REG
);
1921 #define BIT_CHANGE_OP( name, binop ) \
1923 unsigned int temp; \
1925 trace_input (name, OP_BIT_CHANGE, 0); \
1927 bit = 1 << State.regs[ OP[1] & 0x7 ]; \
1928 temp = load_mem (State.regs[ OP[0] ], 1); \
1931 if ((temp & bit) == 0) \
1935 store_mem (State.regs[ OP[0] ], 1, temp); \
1937 trace_output (OP_BIT_CHANGE); \
1941 /* clr1 reg2, [reg1] */
1945 BIT_CHANGE_OP ("clr1", &= ~ );
1948 /* not1 reg2, [reg1] */
1952 BIT_CHANGE_OP ("not1", ^= );
1959 BIT_CHANGE_OP ("set1", |= );
1966 trace_input ("sasf", OP_EX1
, 0);
1968 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
1970 trace_output (OP_EX1
);
1975 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
1976 (Soew_Tan@el.nec.com) */
1981 unsigned long int als
,
1982 unsigned long int sfi
,
1983 unsigned32
/*unsigned long int*/ * quotient_ptr
,
1984 unsigned32
/*unsigned long int*/ * remainder_ptr
,
1985 boolean
* overflow_ptr
1988 unsigned long ald
= sfi
>> (N
- 1);
1989 unsigned long alo
= als
;
1994 unsigned int R1
= 1;
1995 unsigned int DBZ
= (als
== 0) ? 1 : 0;
1996 unsigned long alt
= Q
? ~als
: als
;
1999 alo
= ald
+ alt
+ Q
;
2000 C
= (((alt
>> 31) & (ald
>> 31))
2001 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2004 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2005 if ((S
^ (alo
>>31)) && !C
)
2010 sfi
= (sfi
<< (32-N
+1)) | Q
;
2011 ald
= (alo
<< 1) | (sfi
>> 31);
2013 /* 2nd - N-1th Loop */
2014 for (i
= 2; i
< N
; i
++)
2016 alt
= Q
? ~als
: als
;
2017 alo
= ald
+ alt
+ Q
;
2018 C
= (((alt
>> 31) & (ald
>> 31))
2019 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2022 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2023 if ((S
^ (alo
>>31)) && !C
&& !DBZ
)
2028 sfi
= (sfi
<< 1) | Q
;
2029 ald
= (alo
<< 1) | (sfi
>> 31);
2033 alt
= Q
? ~als
: als
;
2034 alo
= ald
+ alt
+ Q
;
2035 C
= (((alt
>> 31) & (ald
>> 31))
2036 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2039 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2040 if ((S
^ (alo
>>31)) && !C
)
2045 * quotient_ptr
= (sfi
<< 1) | Q
;
2046 * remainder_ptr
= Q
? alo
: (alo
+ als
);
2047 * overflow_ptr
= DBZ
| R1
;
2050 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2055 unsigned long int als
,
2056 unsigned long int sfi
,
2057 signed32
/*signed long int*/ * quotient_ptr
,
2058 signed32
/*signed long int*/ * remainder_ptr
,
2059 boolean
* overflow_ptr
2062 unsigned long ald
= (signed long) sfi
>> (N
- 1);
2063 unsigned long alo
= als
;
2064 unsigned int SS
= als
>> 31;
2065 unsigned int SD
= sfi
>> 31;
2066 unsigned int R1
= 1;
2068 unsigned int DBZ
= als
== 0 ? 1 : 0;
2069 unsigned int Q
= ~(SS
^ SD
) & 1;
2073 unsigned long alt
= Q
? ~als
: als
;
2078 alo
= ald
+ alt
+ Q
;
2079 C
= (((alt
>> 31) & (ald
>> 31))
2080 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2082 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2084 sfi
= (sfi
<< (32-N
+1)) | Q
;
2085 ald
= (alo
<< 1) | (sfi
>> 31);
2086 if ((alo
>> 31) ^ (ald
>> 31))
2091 /* 2nd - N-1th Loop */
2093 for (i
= 2; i
< N
; i
++)
2095 alt
= Q
? ~als
: als
;
2096 alo
= ald
+ alt
+ Q
;
2097 C
= (((alt
>> 31) & (ald
>> 31))
2098 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2100 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2102 sfi
= (sfi
<< 1) | Q
;
2103 ald
= (alo
<< 1) | (sfi
>> 31);
2104 if ((alo
>> 31) ^ (ald
>> 31))
2111 alt
= Q
? ~als
: als
;
2112 alo
= ald
+ alt
+ Q
;
2113 C
= (((alt
>> 31) & (ald
>> 31))
2114 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2116 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2117 sfi
= (sfi
<< (32-N
+1));
2123 alt
= Q
? ~als
: als
;
2124 alo
= ald
+ alt
+ Q
;
2126 R1
= R1
& ((~alo
>> 31) ^ SD
);
2127 if ((alo
!= 0) && ((Q
^ (SS
^ SD
)) ^ R1
)) alo
= ald
;
2129 ald
= sfi
= (long) ((sfi
>> 1) | (SS
^ SD
) << 31) >> (32-N
-1) | Q
;
2131 ald
= sfi
= sfi
| Q
;
2133 OV
= DBZ
| ((alo
== 0) ? 0 : R1
);
2135 * remainder_ptr
= alo
;
2138 if (((alo
!= 0) && ((SS
^ SD
) ^ R1
))
2139 || ((alo
== 0) && (SS
^ R1
)))
2144 OV
= (DBZ
| R1
) ? OV
: ((alo
>> 31) & (~ald
>> 31));
2146 * quotient_ptr
= alo
;
2147 * overflow_ptr
= OV
;
2150 /* sdivun imm5, reg1, reg2, reg3 */
2154 unsigned32
/*unsigned long int*/ quotient
;
2155 unsigned32
/*unsigned long int*/ remainder
;
2156 unsigned long int divide_by
;
2157 unsigned long int divide_this
;
2158 boolean overflow
= false;
2161 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2163 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2165 divide_by
= State
.regs
[ OP
[0] ];
2166 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2168 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2170 State
.regs
[ OP
[1] ] = quotient
;
2171 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2173 /* Set condition codes. */
2174 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2176 if (overflow
) PSW
|= PSW_OV
;
2177 if (quotient
== 0) PSW
|= PSW_Z
;
2178 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2180 trace_output (OP_IMM_REG_REG_REG
);
2185 /* sdivn imm5, reg1, reg2, reg3 */
2189 signed32
/*signed long int*/ quotient
;
2190 signed32
/*signed long int*/ remainder
;
2191 signed long int divide_by
;
2192 signed long int divide_this
;
2193 boolean overflow
= false;
2196 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2198 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2200 divide_by
= State
.regs
[ OP
[0] ];
2201 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2203 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2205 State
.regs
[ OP
[1] ] = quotient
;
2206 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2208 /* Set condition codes. */
2209 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2211 if (overflow
) PSW
|= PSW_OV
;
2212 if (quotient
== 0) PSW
|= PSW_Z
;
2213 if (quotient
< 0) PSW
|= PSW_S
;
2215 trace_output (OP_IMM_REG_REG_REG
);
2220 /* sdivhun imm5, reg1, reg2, reg3 */
2224 unsigned32
/*unsigned long int*/ quotient
;
2225 unsigned32
/*unsigned long int*/ remainder
;
2226 unsigned long int divide_by
;
2227 unsigned long int divide_this
;
2228 boolean overflow
= false;
2231 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2233 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2235 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2236 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2238 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2240 State
.regs
[ OP
[1] ] = quotient
;
2241 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2243 /* Set condition codes. */
2244 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2246 if (overflow
) PSW
|= PSW_OV
;
2247 if (quotient
== 0) PSW
|= PSW_Z
;
2248 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2250 trace_output (OP_IMM_REG_REG_REG
);
2255 /* sdivhn imm5, reg1, reg2, reg3 */
2259 signed32
/*signed long int*/ quotient
;
2260 signed32
/*signed long int*/ remainder
;
2261 signed long int divide_by
;
2262 signed long int divide_this
;
2263 boolean overflow
= false;
2266 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2268 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2270 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2271 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2273 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2275 State
.regs
[ OP
[1] ] = quotient
;
2276 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2278 /* Set condition codes. */
2279 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2281 if (overflow
) PSW
|= PSW_OV
;
2282 if (quotient
== 0) PSW
|= PSW_Z
;
2283 if (quotient
< 0) PSW
|= PSW_S
;
2285 trace_output (OP_IMM_REG_REG_REG
);
2290 /* divu reg1, reg2, reg3 */
2294 unsigned long int quotient
;
2295 unsigned long int remainder
;
2296 unsigned long int divide_by
;
2297 unsigned long int divide_this
;
2298 boolean overflow
= false;
2300 trace_input ("divu", OP_REG_REG_REG
, 0);
2302 /* Compute the result. */
2304 divide_by
= State
.regs
[ OP
[0] ];
2305 divide_this
= State
.regs
[ OP
[1] ];
2313 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2314 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2316 /* Set condition codes. */
2317 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2319 if (overflow
) PSW
|= PSW_OV
;
2320 if (quotient
== 0) PSW
|= PSW_Z
;
2321 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2323 trace_output (OP_REG_REG_REG
);
2328 /* div reg1, reg2, reg3 */
2332 signed long int quotient
;
2333 signed long int remainder
;
2334 signed long int divide_by
;
2335 signed long int divide_this
;
2336 boolean overflow
= false;
2338 trace_input ("div", OP_REG_REG_REG
, 0);
2340 /* Compute the result. */
2342 divide_by
= State
.regs
[ OP
[0] ];
2343 divide_this
= State
.regs
[ OP
[1] ];
2345 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
2351 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2352 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2354 /* Set condition codes. */
2355 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2357 if (overflow
) PSW
|= PSW_OV
;
2358 if (quotient
== 0) PSW
|= PSW_Z
;
2359 if (quotient
< 0) PSW
|= PSW_S
;
2361 trace_output (OP_REG_REG_REG
);
2366 /* divhu reg1, reg2, reg3 */
2370 unsigned long int quotient
;
2371 unsigned long int remainder
;
2372 unsigned long int divide_by
;
2373 unsigned long int divide_this
;
2374 boolean overflow
= false;
2376 trace_input ("divhu", OP_REG_REG_REG
, 0);
2378 /* Compute the result. */
2380 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2381 divide_this
= State
.regs
[ OP
[1] ];
2389 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2390 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2392 /* Set condition codes. */
2393 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2395 if (overflow
) PSW
|= PSW_OV
;
2396 if (quotient
== 0) PSW
|= PSW_Z
;
2397 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2399 trace_output (OP_REG_REG_REG
);
2404 /* divh reg1, reg2, reg3 */
2408 signed long int quotient
;
2409 signed long int remainder
;
2410 signed long int divide_by
;
2411 signed long int divide_this
;
2412 boolean overflow
= false;
2414 trace_input ("divh", OP_REG_REG_REG
, 0);
2416 /* Compute the result. */
2418 divide_by
= State
.regs
[ OP
[0] ];
2419 divide_this
= EXTEND16 (State
.regs
[ OP
[1] ]);
2421 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
2427 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2428 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2430 /* Set condition codes. */
2431 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2433 if (overflow
) PSW
|= PSW_OV
;
2434 if (quotient
== 0) PSW
|= PSW_Z
;
2435 if (quotient
< 0) PSW
|= PSW_S
;
2437 trace_output (OP_REG_REG_REG
);
2442 /* mulu imm9, reg2, reg3 */
2446 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2448 Multiply64 (false, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2450 trace_output (OP_IMM_REG_REG
);
2455 /* mul imm9, reg2, reg3 */
2459 trace_input ("mul", OP_IMM_REG_REG
, 0);
2461 Multiply64 (true, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2463 trace_output (OP_IMM_REG_REG
);
2474 trace_input ("ld.hu", OP_LOAD32
, 2);
2476 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
2479 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
2481 trace_output (OP_LOAD32
);
2493 trace_input ("ld.bu", OP_LOAD32
, 1);
2495 adr
= (State
.regs
[ OP
[0] ]
2496 + (EXTEND16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1)));
2498 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
2500 trace_output (OP_LOAD32
);
2505 /* prepare list12, imm5, imm32 */
2511 trace_input ("prepare", OP_PUSHPOP1
, 0);
2513 /* Store the registers with lower number registers being placed at higher addresses. */
2514 for (i
= 0; i
< 12; i
++)
2515 if ((OP
[3] & (1 << type1_regs
[ i
])))
2518 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2521 SP
-= (OP
[3] & 0x3e) << 1;
2523 EP
= load_mem (PC
+ 4, 4);
2525 trace_output (OP_PUSHPOP1
);
2530 /* prepare list12, imm5, imm16-32 */
2536 trace_input ("prepare", OP_PUSHPOP1
, 0);
2538 /* Store the registers with lower number registers being placed at higher addresses. */
2539 for (i
= 0; i
< 12; i
++)
2540 if ((OP
[3] & (1 << type1_regs
[ i
])))
2543 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2546 SP
-= (OP
[3] & 0x3e) << 1;
2548 EP
= load_mem (PC
+ 4, 2) << 16;
2550 trace_output (OP_PUSHPOP1
);
2555 /* prepare list12, imm5, imm16 */
2561 trace_input ("prepare", OP_PUSHPOP1
, 0);
2563 /* Store the registers with lower number registers being placed at higher addresses. */
2564 for (i
= 0; i
< 12; i
++)
2565 if ((OP
[3] & (1 << type1_regs
[ i
])))
2568 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2571 SP
-= (OP
[3] & 0x3e) << 1;
2573 EP
= EXTEND16 (load_mem (PC
+ 4, 2));
2575 trace_output (OP_PUSHPOP1
);
2580 /* prepare list12, imm5, sp */
2586 trace_input ("prepare", OP_PUSHPOP1
, 0);
2588 /* Store the registers with lower number registers being placed at higher addresses. */
2589 for (i
= 0; i
< 12; i
++)
2590 if ((OP
[3] & (1 << type1_regs
[ i
])))
2593 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2596 SP
-= (OP
[3] & 0x3e) << 1;
2600 trace_output (OP_PUSHPOP1
);
2605 /* mul reg1, reg2, reg3 */
2609 trace_input ("mul", OP_REG_REG_REG
, 0);
2611 Multiply64 (true, State
.regs
[ OP
[0] ]);
2613 trace_output (OP_REG_REG_REG
);
2624 trace_input ("popmh", OP_PUSHPOP2
, 0);
2626 if (OP
[3] & (1 << 19))
2628 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2630 FEPSW
= load_mem ( SP
& ~ 3, 4);
2631 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2635 EIPSW
= load_mem ( SP
& ~ 3, 4);
2636 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2642 /* Load the registers with lower number registers being retrieved from higher addresses. */
2644 if ((OP
[3] & (1 << type2_regs
[ i
])))
2646 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
2650 trace_output (OP_PUSHPOP2
);
2661 trace_input ("popml", OP_PUSHPOP3
, 0);
2663 if (OP
[3] & (1 << 19))
2665 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2667 FEPSW
= load_mem ( SP
& ~ 3, 4);
2668 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2672 EIPSW
= load_mem ( SP
& ~ 3, 4);
2673 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2679 if (OP
[3] & (1 << 3))
2681 PSW
= load_mem (SP
& ~ 3, 4);
2685 /* Load the registers with lower number registers being retrieved from higher addresses. */
2687 if ((OP
[3] & (1 << type3_regs
[ i
])))
2689 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
2693 trace_output (OP_PUSHPOP2
);
2704 trace_input ("pushmh", OP_PUSHPOP2
, 0);
2706 /* Store the registers with lower number registers being placed at higher addresses. */
2707 for (i
= 0; i
< 16; i
++)
2708 if ((OP
[3] & (1 << type2_regs
[ i
])))
2711 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
2714 if (OP
[3] & (1 << 19))
2718 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2720 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
2721 store_mem ( SP
& ~ 3, 4, FEPSW
);
2725 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
2726 store_mem ( SP
& ~ 3, 4, EIPSW
);
2730 trace_output (OP_PUSHPOP2
);
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