c932849fa0e5892e9da4a99f8b9239e96720f88a
4 #include "sys/syscall.h"
37 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
38 static void trace_output
PARAMS ((enum op_types result
));
39 static int init_text_p
= 0;
40 static asection
*text
;
41 static bfd_vma text_start
;
42 static bfd_vma text_end
;
45 #ifndef SIZE_INSTRUCTION
46 #define SIZE_INSTRUCTION 6
50 #define SIZE_OPERANDS 16
54 #define SIZE_VALUES 11
58 #define SIZE_LOCATION 40
62 trace_input (name
, type
, size
)
74 const char *functionname
;
75 unsigned int linenumber
;
77 if ((v850_debug
& DEBUG_TRACE
) == 0)
84 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
85 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
88 text_start
= bfd_get_section_vma (exec_bfd
, s
);
89 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
94 if (text
&& PC
>= text_start
&& PC
< text_end
)
96 filename
= (const char *)0;
97 functionname
= (const char *)0;
99 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, PC
- text_start
,
100 &filename
, &functionname
, &linenumber
))
105 sprintf (p
, "Line %5d ", linenumber
);
111 sprintf (p
, "Func %s ", functionname
);
116 char *q
= (char *) strrchr (filename
, '/');
117 sprintf (p
, "File %s ", (q
) ? q
+1 : filename
);
126 (*v850_callback
->printf_filtered
) (v850_callback
, "0x%.8x: %-*.*s %-*s",
128 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
129 SIZE_INSTRUCTION
, name
);
136 strcpy (buf
, "unknown");
140 sprintf (buf
, "%d", OP
[0]);
144 sprintf (buf
, "r%d", OP
[0]);
149 case OP_REG_REG_MOVE
:
150 sprintf (buf
, "r%d,r%d", OP
[0], OP
[1]);
155 case OP_IMM_REG_MOVE
:
156 sprintf (buf
, "%d,r%d", OP
[0], OP
[1]);
160 sprintf (buf
, "%d", SEXT9 (OP
[0]));
164 sprintf (buf
, "%d[r30],r%d", OP
[1] * size
, OP
[0]);
168 sprintf (buf
, "r%d,%d[r30]", OP
[0], OP
[1] * size
);
172 sprintf (buf
, "%d[r%d],r%d", SEXT16 (OP
[2]) & ~0x1, OP
[0], OP
[1]);
176 sprintf (buf
, "r%d,%d[r%d]", OP
[1], SEXT16 (OP
[2] & ~0x1), OP
[0]);
180 sprintf (buf
, "%d,r%d", SEXT22 (OP
[0]), OP
[1]);
184 sprintf (buf
, "%d,r%d,r%d", SEXT16 (OP
[0]), OP
[1], OP
[2]);
187 case OP_UIMM_REG_REG
:
188 sprintf (buf
, "%d,r%d,r%d", OP
[0] & 0xffff, OP
[1], OP
[2]);
192 sprintf (buf
, "%d,%d[r%d]", OP
[1] & 0x7, SEXT16 (OP
[2]), OP
[0]);
198 default: cond
= "?"; break;
199 case 0x0: cond
= "v"; break;
200 case 0x1: cond
= "c"; break;
201 case 0x2: cond
= "z"; break;
202 case 0x3: cond
= "nh"; break;
203 case 0x4: cond
= "s"; break;
204 case 0x5: cond
= "t"; break;
205 case 0x6: cond
= "lt"; break;
206 case 0x7: cond
= "le"; break;
207 case 0x8: cond
= "nv"; break;
208 case 0x9: cond
= "nc"; break;
209 case 0xa: cond
= "nz"; break;
210 case 0xb: cond
= "h"; break;
211 case 0xc: cond
= "ns"; break;
212 case 0xd: cond
= "sa"; break;
213 case 0xe: cond
= "ge"; break;
214 case 0xf: cond
= "gt"; break;
217 sprintf (buf
, "%s,r%d", cond
, OP
[1]);
226 sprintf (buf
, "r%d,s%d", OP
[0], OP
[1]);
230 if ((v850_debug
& DEBUG_VALUES
) == 0)
232 (*v850_callback
->printf_filtered
) (v850_callback
, "%s\n", buf
);
236 (*v850_callback
->printf_filtered
) (v850_callback
, "%-*s", SIZE_OPERANDS
, buf
);
247 case OP_REG_REG_MOVE
:
248 values
[0] = State
.regs
[OP
[0]];
254 values
[0] = State
.regs
[OP
[1]];
255 values
[1] = State
.regs
[OP
[0]];
261 values
[0] = SEXT5 (OP
[0]);
266 case OP_IMM_REG_MOVE
:
267 values
[0] = SEXT5 (OP
[0]);
272 values
[0] = State
.pc
;
273 values
[1] = SEXT9 (OP
[0]);
274 values
[2] = State
.sregs
[5];
279 values
[0] = OP
[1] * size
;
280 values
[1] = State
.regs
[30];
285 values
[0] = State
.regs
[OP
[0]];
286 values
[1] = OP
[1] * size
;
287 values
[2] = State
.regs
[30];
292 values
[0] = SEXT16 (OP
[2]);
293 values
[1] = State
.regs
[OP
[0]];
298 values
[0] = State
.regs
[OP
[1]];
299 values
[1] = SEXT16 (OP
[2]);
300 values
[2] = State
.regs
[OP
[0]];
305 values
[0] = SEXT22 (OP
[0]);
306 values
[1] = State
.pc
;
311 values
[0] = SEXT16 (OP
[0]) << size
;
312 values
[1] = State
.regs
[OP
[1]];
316 case OP_UIMM_REG_REG
:
317 values
[0] = (OP
[0] & 0xffff) << size
;
318 values
[1] = State
.regs
[OP
[1]];
327 values
[0] = State
.sregs
[5];
336 values
[0] = State
.regs
[OP
[0]];
341 values
[0] = State
.sregs
[OP
[1]];
345 for (i
= 0; i
< num_values
; i
++)
346 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s0x%.8lx", SIZE_VALUES
- 10, "", values
[i
]);
349 (*v850_callback
->printf_filtered
) (v850_callback
, "%*s", SIZE_VALUES
, "");
354 trace_output (result
)
355 enum op_types result
;
357 if ((v850_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
377 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
378 (unsigned long)State
.regs
[OP
[0]]);
382 case OP_REG_REG_MOVE
:
384 case OP_IMM_REG_MOVE
:
387 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
388 (unsigned long)State
.regs
[OP
[1]]);
392 case OP_UIMM_REG_REG
:
393 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
394 (unsigned long)State
.regs
[OP
[2]]);
399 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
400 (unsigned long)State
.regs
[OP
[1]]);
404 (*v850_callback
->printf_filtered
) (v850_callback
, " :: 0x%.8lx",
405 (unsigned long)State
.sregs
[OP
[1]]);
409 (*v850_callback
->printf_filtered
) (v850_callback
, "\n");
414 #define trace_input(NAME, IN1, IN2)
415 #define trace_output(RESULT)
426 trace_input ("sld.b", OP_LOAD16
, 1);
430 result
= load_mem (State
.regs
[30] + op2
, 1);
431 State
.regs
[OP
[0]] = SEXT8 (result
);
432 trace_output (OP_LOAD16
);
442 trace_input ("sld.h", OP_LOAD16
, 2);
446 result
= load_mem (State
.regs
[30] + op2
, 2);
447 State
.regs
[OP
[0]] = SEXT16 (result
);
448 trace_output (OP_LOAD16
);
458 trace_input ("sld.w", OP_LOAD16
, 4);
462 result
= load_mem (State
.regs
[30] + op2
, 4);
463 State
.regs
[OP
[0]] = result
;
464 trace_output (OP_LOAD16
);
471 unsigned int op0
, op1
;
474 trace_input ("sst.b", OP_STORE16
, 1);
475 op0
= State
.regs
[OP
[0]];
479 store_mem (State
.regs
[30] + op1
, 1, op0
);
480 trace_output (OP_STORE16
);
487 unsigned int op0
, op1
;
490 trace_input ("sst.h", OP_STORE16
, 2);
491 op0
= State
.regs
[OP
[0]];
495 store_mem (State
.regs
[30] + op1
, 2, op0
);
496 trace_output (OP_STORE16
);
503 unsigned int op0
, op1
;
506 trace_input ("sst.w", OP_STORE16
, 4);
507 op0
= State
.regs
[OP
[0]];
511 store_mem (State
.regs
[30] + op1
, 4, op0
);
512 trace_output (OP_STORE16
);
519 unsigned int op0
, op2
;
522 trace_input ("ld.b", OP_LOAD32
, 1);
523 op0
= State
.regs
[OP
[0]];
524 temp
= SEXT16 (OP
[2]);
526 result
= load_mem (op0
+ op2
, 1);
527 State
.regs
[OP
[1]] = SEXT8 (result
);
528 trace_output (OP_LOAD32
);
535 unsigned int op0
, op2
;
538 trace_input ("ld.h", OP_LOAD32
, 2);
539 op0
= State
.regs
[OP
[0]];
540 temp
= SEXT16 (OP
[2]);
543 result
= load_mem (op0
+ op2
, 2);
544 State
.regs
[OP
[1]] = SEXT16 (result
);
545 trace_output (OP_LOAD32
);
552 unsigned int op0
, op2
;
555 trace_input ("ld.w", OP_LOAD32
, 4);
556 op0
= State
.regs
[OP
[0]];
557 temp
= SEXT16 (OP
[2]);
560 result
= load_mem (op0
+ op2
, 4);
561 State
.regs
[OP
[1]] = result
;
562 trace_output (OP_LOAD32
);
569 unsigned int op0
, op1
, op2
;
572 trace_input ("st.b", OP_STORE32
, 1);
573 op0
= State
.regs
[OP
[0]];
574 op1
= State
.regs
[OP
[1]];
575 temp
= SEXT16 (OP
[2]);
577 store_mem (op0
+ op2
, 1, op1
);
578 trace_output (OP_STORE32
);
585 unsigned int op0
, op1
, op2
;
588 trace_input ("st.h", OP_STORE32
, 2);
589 op0
= State
.regs
[OP
[0]];
590 op1
= State
.regs
[OP
[1]];
591 temp
= SEXT16 (OP
[2] & ~0x1);
593 store_mem (op0
+ op2
, 2, op1
);
594 trace_output (OP_STORE32
);
601 unsigned int op0
, op1
, op2
;
604 trace_input ("st.w", OP_STORE32
, 4);
605 op0
= State
.regs
[OP
[0]];
606 op1
= State
.regs
[OP
[1]];
607 temp
= SEXT16 (OP
[2] & ~0x1);
609 store_mem (op0
+ op2
, 4, op1
);
610 trace_output (OP_STORE32
);
620 trace_input ("bv", OP_COND_BR
, 0);
622 psw
= State
.sregs
[5];
624 if ((psw
& PSW_OV
) != 0)
628 trace_output (OP_COND_BR
);
638 trace_input ("bl", OP_COND_BR
, 0);
640 psw
= State
.sregs
[5];
642 if ((psw
& PSW_CY
) != 0)
646 trace_output (OP_COND_BR
);
656 trace_input ("be", OP_COND_BR
, 0);
658 psw
= State
.sregs
[5];
660 if ((psw
& PSW_Z
) != 0)
664 trace_output (OP_COND_BR
);
674 trace_input ("bnh", OP_COND_BR
, 0);
676 psw
= State
.sregs
[5];
678 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
682 trace_output (OP_COND_BR
);
692 trace_input ("bn", OP_COND_BR
, 0);
694 psw
= State
.sregs
[5];
696 if ((psw
& PSW_S
) != 0)
700 trace_output (OP_COND_BR
);
710 trace_input ("br", OP_COND_BR
, 0);
713 trace_output (OP_COND_BR
);
723 trace_input ("blt", OP_COND_BR
, 0);
725 psw
= State
.sregs
[5];
727 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
731 trace_output (OP_COND_BR
);
741 trace_input ("ble", OP_COND_BR
, 0);
743 psw
= State
.sregs
[5];
745 if ((((psw
& PSW_Z
) != 0)
746 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
750 trace_output (OP_COND_BR
);
760 trace_input ("bnv", OP_COND_BR
, 0);
762 psw
= State
.sregs
[5];
764 if ((psw
& PSW_OV
) == 0)
768 trace_output (OP_COND_BR
);
778 trace_input ("bnl", OP_COND_BR
, 0);
780 psw
= State
.sregs
[5];
782 if ((psw
& PSW_CY
) == 0)
786 trace_output (OP_COND_BR
);
796 trace_input ("bne", OP_COND_BR
, 0);
798 psw
= State
.sregs
[5];
800 if ((psw
& PSW_Z
) == 0)
804 trace_output (OP_COND_BR
);
814 trace_input ("bh", OP_COND_BR
, 0);
816 psw
= State
.sregs
[5];
818 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
822 trace_output (OP_COND_BR
);
832 trace_input ("bp", OP_COND_BR
, 0);
834 psw
= State
.sregs
[5];
836 if ((psw
& PSW_S
) == 0)
840 trace_output (OP_COND_BR
);
850 trace_input ("bsa", OP_COND_BR
, 0);
852 psw
= State
.sregs
[5];
854 if ((psw
& PSW_SAT
) != 0)
858 trace_output (OP_COND_BR
);
868 trace_input ("bge", OP_COND_BR
, 0);
870 psw
= State
.sregs
[5];
872 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
876 trace_output (OP_COND_BR
);
886 trace_input ("bgt", OP_COND_BR
, 0);
888 psw
= State
.sregs
[5];
890 if ((((psw
& PSW_Z
) != 0)
891 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
895 trace_output (OP_COND_BR
);
902 /* interp.c will bump this by +2, so correct for it here. */
903 trace_input ("jmp", OP_REG
, 0);
904 State
.pc
= State
.regs
[OP
[0]] - 2;
905 trace_output (OP_REG
);
908 /* jarl disp22, reg */
912 unsigned int op0
, opc
;
915 trace_input ("jarl", OP_JUMP
, 0);
916 temp
= SEXT22 (OP
[0]);
922 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
924 State
.regs
[OP
[1]] = opc
+ 4;
925 trace_output (OP_JUMP
);
932 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
934 trace_input ("add", OP_REG_REG
, 0);
935 /* Compute the result. */
936 op0
= State
.regs
[OP
[0]];
937 op1
= State
.regs
[OP
[1]];
940 /* Compute the condition codes. */
942 s
= (result
& 0x80000000);
943 cy
= (result
< op0
|| result
< op1
);
944 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
945 && (op0
& 0x80000000) != (result
& 0x80000000));
947 /* Store the result and condition codes. */
948 State
.regs
[OP
[1]] = result
;
949 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
950 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
951 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
952 trace_output (OP_REG_REG
);
955 /* add sign_extend(imm5), reg */
959 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
962 trace_input ("add", OP_IMM_REG
, 0);
964 /* Compute the result. */
965 temp
= SEXT5 (OP
[0]);
967 op1
= State
.regs
[OP
[1]];
970 /* Compute the condition codes. */
972 s
= (result
& 0x80000000);
973 cy
= (result
< op0
|| result
< op1
);
974 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
975 && (op0
& 0x80000000) != (result
& 0x80000000));
977 /* Store the result and condition codes. */
978 State
.regs
[OP
[1]] = result
;
979 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
980 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
981 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
982 trace_output (OP_IMM_REG
);
985 /* addi sign_extend(imm16), reg, reg */
989 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
992 trace_input ("addi", OP_IMM_REG_REG
, 0);
994 /* Compute the result. */
995 temp
= SEXT16 (OP
[0]);
997 op1
= State
.regs
[OP
[1]];
1000 /* Compute the condition codes. */
1002 s
= (result
& 0x80000000);
1003 cy
= (result
< op0
|| result
< op1
);
1004 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1005 && (op0
& 0x80000000) != (result
& 0x80000000));
1007 /* Store the result and condition codes. */
1008 State
.regs
[OP
[2]] = result
;
1009 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1010 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1011 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1012 trace_output (OP_IMM_REG_REG
);
1015 /* sub reg1, reg2 */
1019 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1021 trace_input ("sub", OP_REG_REG
, 0);
1022 /* Compute the result. */
1023 op0
= State
.regs
[OP
[0]];
1024 op1
= State
.regs
[OP
[1]];
1027 /* Compute the condition codes. */
1029 s
= (result
& 0x80000000);
1031 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1032 && (op1
& 0x80000000) != (result
& 0x80000000));
1034 /* Store the result and condition codes. */
1035 State
.regs
[OP
[1]] = result
;
1036 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1037 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1038 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1039 trace_output (OP_REG_REG
);
1042 /* subr reg1, reg2 */
1046 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1048 trace_input ("subr", OP_REG_REG
, 0);
1049 /* Compute the result. */
1050 op0
= State
.regs
[OP
[0]];
1051 op1
= State
.regs
[OP
[1]];
1054 /* Compute the condition codes. */
1056 s
= (result
& 0x80000000);
1058 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1059 && (op0
& 0x80000000) != (result
& 0x80000000));
1061 /* Store the result and condition codes. */
1062 State
.regs
[OP
[1]] = result
;
1063 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1064 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1065 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1066 trace_output (OP_REG_REG
);
1069 /* mulh reg1, reg2 */
1073 trace_input ("mulh", OP_REG_REG
, 0);
1074 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
1075 * (State
.regs
[OP
[0]] & 0xffff));
1076 trace_output (OP_REG_REG
);
1079 /* mulh sign_extend(imm5), reg2
1085 int value
= SEXT5 (OP
[0]);
1087 trace_input ("mulh", OP_IMM_REG
, 0);
1088 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1089 trace_output (OP_IMM_REG
);
1092 /* mulhi imm16, reg1, reg2 */
1096 int value
= OP
[0] & 0xffff;
1098 trace_input ("mulhi", OP_IMM_REG_REG
, 0);
1099 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
1100 trace_output (OP_IMM_REG_REG
);
1103 /* divh reg1, reg2 */
1107 unsigned int op0
, op1
, result
, ov
, s
, z
;
1110 trace_input ("divh", OP_REG_REG
, 0);
1112 /* Compute the result. */
1113 temp
= SEXT16 (State
.regs
[OP
[0]]);
1115 op1
= State
.regs
[OP
[1]];
1117 if (op0
== 0xffffffff && op1
== 0x80000000)
1119 result
= 0x80000000;
1133 /* Compute the condition codes. */
1135 s
= (result
& 0x80000000);
1137 /* Store the result and condition codes. */
1138 State
.regs
[OP
[1]] = result
;
1139 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1140 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1141 | (ov
? PSW_OV
: 0));
1142 trace_output (OP_REG_REG
);
1149 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1151 trace_input ("cmp", OP_REG_REG_CMP
, 0);
1152 /* Compute the result. */
1153 op0
= State
.regs
[OP
[0]];
1154 op1
= State
.regs
[OP
[1]];
1157 /* Compute the condition codes. */
1159 s
= (result
& 0x80000000);
1161 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1162 && (op1
& 0x80000000) != (result
& 0x80000000));
1164 /* Set condition codes. */
1165 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1166 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1167 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1168 trace_output (OP_REG_REG_CMP
);
1171 /* cmp sign_extend(imm5), reg */
1175 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1178 /* Compute the result. */
1179 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
1180 temp
= SEXT5 (OP
[0]);
1182 op1
= State
.regs
[OP
[1]];
1185 /* Compute the condition codes. */
1187 s
= (result
& 0x80000000);
1189 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1190 && (op1
& 0x80000000) != (result
& 0x80000000));
1192 /* Set condition codes. */
1193 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1194 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1195 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1196 trace_output (OP_IMM_REG_CMP
);
1199 /* setf cccc,reg2 */
1203 /* Hack alert. We turn off a bit in op0 since we really only
1205 unsigned int op0
, psw
, result
= 0;
1207 trace_input ("setf", OP_EX1
, 0);
1209 psw
= State
.sregs
[5];
1214 result
= ((psw
& PSW_OV
) != 0);
1217 result
= ((psw
& PSW_CY
) != 0);
1220 result
= ((psw
& PSW_Z
) != 0);
1223 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
1226 result
= ((psw
& PSW_S
) != 0);
1232 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
1235 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1236 || ((psw
& PSW_Z
) != 0)) != 0);
1239 result
= ((psw
& PSW_OV
) == 0);
1242 result
= ((psw
& PSW_CY
) == 0);
1245 result
= ((psw
& PSW_Z
) == 0);
1248 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
1251 result
= ((psw
& PSW_S
) == 0);
1254 result
= ((psw
& PSW_SAT
) != 0);
1257 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
1260 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
1261 || ((psw
& PSW_Z
) != 0)) == 0);
1265 State
.regs
[OP
[1]] = result
;
1266 trace_output (OP_EX1
);
1269 /* satadd reg,reg */
1273 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1275 trace_input ("satadd", OP_REG_REG
, 0);
1276 /* Compute the result. */
1277 op0
= State
.regs
[OP
[0]];
1278 op1
= State
.regs
[OP
[1]];
1281 /* Compute the condition codes. */
1283 s
= (result
& 0x80000000);
1284 cy
= (result
< op0
|| result
< op1
);
1285 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1286 && (op0
& 0x80000000) != (result
& 0x80000000));
1289 /* Store the result and condition codes. */
1290 State
.regs
[OP
[1]] = result
;
1291 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1292 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1293 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1294 | (sat
? PSW_SAT
: 0));
1296 /* Handle saturated results. */
1298 State
.regs
[OP
[1]] = 0x80000000;
1300 State
.regs
[OP
[1]] = 0x7fffffff;
1301 trace_output (OP_REG_REG
);
1304 /* satadd sign_extend(imm5), reg */
1308 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1312 trace_input ("satadd", OP_IMM_REG
, 0);
1314 /* Compute the result. */
1315 temp
= SEXT5 (OP
[0]);
1317 op1
= State
.regs
[OP
[1]];
1320 /* Compute the condition codes. */
1322 s
= (result
& 0x80000000);
1323 cy
= (result
< op0
|| result
< op1
);
1324 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
1325 && (op0
& 0x80000000) != (result
& 0x80000000));
1328 /* Store the result and condition codes. */
1329 State
.regs
[OP
[1]] = result
;
1330 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1331 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1332 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1333 | (sat
? PSW_SAT
: 0));
1335 /* Handle saturated results. */
1337 State
.regs
[OP
[1]] = 0x80000000;
1339 State
.regs
[OP
[1]] = 0x7fffffff;
1340 trace_output (OP_IMM_REG
);
1343 /* satsub reg1, reg2 */
1347 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1349 trace_input ("satsub", OP_REG_REG
, 0);
1351 /* Compute the result. */
1352 op0
= State
.regs
[OP
[0]];
1353 op1
= State
.regs
[OP
[1]];
1356 /* Compute the condition codes. */
1358 s
= (result
& 0x80000000);
1360 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1361 && (op1
& 0x80000000) != (result
& 0x80000000));
1364 /* Store the result and condition codes. */
1365 State
.regs
[OP
[1]] = result
;
1366 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1367 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1368 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1369 | (sat
? PSW_SAT
: 0));
1371 /* Handle saturated results. */
1373 State
.regs
[OP
[1]] = 0x80000000;
1375 State
.regs
[OP
[1]] = 0x7fffffff;
1376 trace_output (OP_REG_REG
);
1379 /* satsubi sign_extend(imm16), reg */
1383 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1386 trace_input ("satsubi", OP_IMM_REG
, 0);
1388 /* Compute the result. */
1389 temp
= SEXT16 (OP
[0]);
1391 op1
= State
.regs
[OP
[1]];
1394 /* Compute the condition codes. */
1396 s
= (result
& 0x80000000);
1398 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1399 && (op1
& 0x80000000) != (result
& 0x80000000));
1402 /* Store the result and condition codes. */
1403 State
.regs
[OP
[1]] = result
;
1404 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1405 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1406 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1407 | (sat
? PSW_SAT
: 0));
1409 /* Handle saturated results. */
1411 State
.regs
[OP
[1]] = 0x80000000;
1413 State
.regs
[OP
[1]] = 0x7fffffff;
1414 trace_output (OP_IMM_REG
);
1417 /* satsubr reg,reg */
1421 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1423 trace_input ("satsubr", OP_REG_REG
, 0);
1425 /* Compute the result. */
1426 op0
= State
.regs
[OP
[0]];
1427 op1
= State
.regs
[OP
[1]];
1430 /* Compute the condition codes. */
1432 s
= (result
& 0x80000000);
1433 cy
= (result
< op0
);
1434 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1435 && (op1
& 0x80000000) != (result
& 0x80000000));
1438 /* Store the result and condition codes. */
1439 State
.regs
[OP
[1]] = result
;
1440 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1441 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1442 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1443 | (sat
? PSW_SAT
: 0));
1445 /* Handle saturated results. */
1447 State
.regs
[OP
[1]] = 0x80000000;
1449 State
.regs
[OP
[1]] = 0x7fffffff;
1450 trace_output (OP_REG_REG
);
1457 unsigned int op0
, op1
, result
, z
, s
;
1459 trace_input ("tst", OP_REG_REG_CMP
, 0);
1461 /* Compute the result. */
1462 op0
= State
.regs
[OP
[0]];
1463 op1
= State
.regs
[OP
[1]];
1466 /* Compute the condition codes. */
1468 s
= (result
& 0x80000000);
1470 /* Store the condition codes. */
1471 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1472 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1473 trace_output (OP_REG_REG_CMP
);
1480 trace_input ("mov", OP_REG_REG_MOVE
, 0);
1481 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
1482 trace_output (OP_REG_REG_MOVE
);
1485 /* mov sign_extend(imm5), reg */
1489 int value
= SEXT5 (OP
[0]);
1491 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1492 State
.regs
[OP
[1]] = value
;
1493 trace_output (OP_IMM_REG_MOVE
);
1496 /* movea sign_extend(imm16), reg, reg */
1501 int value
= SEXT16 (OP
[0]);
1503 trace_input ("movea", OP_IMM_REG_REG
, 0);
1504 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1505 trace_output (OP_IMM_REG_REG
);
1508 /* movhi imm16, reg, reg */
1512 uint32 value
= (OP
[0] & 0xffff) << 16;
1514 trace_input ("movhi", OP_UIMM_REG_REG
, 16);
1515 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1516 trace_output (OP_UIMM_REG_REG
);
1519 /* sar zero_extend(imm5),reg1 */
1523 unsigned int op0
, op1
, result
, z
, s
, cy
;
1525 trace_input ("sar", OP_IMM_REG
, 0);
1527 op1
= State
.regs
[OP
[1]];
1528 result
= (signed)op1
>> op0
;
1530 /* Compute the condition codes. */
1532 s
= (result
& 0x80000000);
1533 cy
= (op1
& (1 << (op0
- 1)));
1535 /* Store the result and condition codes. */
1536 State
.regs
[OP
[1]] = result
;
1537 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1538 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1539 | (cy
? PSW_CY
: 0));
1540 trace_output (OP_IMM_REG
);
1543 /* sar reg1, reg2 */
1547 unsigned int op0
, op1
, result
, z
, s
, cy
;
1549 trace_input ("sar", OP_REG_REG
, 0);
1550 op0
= State
.regs
[OP
[0]] & 0x1f;
1551 op1
= State
.regs
[OP
[1]];
1552 result
= (signed)op1
>> op0
;
1554 /* Compute the condition codes. */
1556 s
= (result
& 0x80000000);
1557 cy
= (op1
& (1 << (op0
- 1)));
1559 /* Store the result and condition codes. */
1560 State
.regs
[OP
[1]] = result
;
1561 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1562 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1563 | (cy
? PSW_CY
: 0));
1564 trace_output (OP_REG_REG
);
1567 /* shl zero_extend(imm5),reg1 */
1571 unsigned int op0
, op1
, result
, z
, s
, cy
;
1573 trace_input ("shl", OP_IMM_REG
, 0);
1575 op1
= State
.regs
[OP
[1]];
1576 result
= op1
<< op0
;
1578 /* Compute the condition codes. */
1580 s
= (result
& 0x80000000);
1581 cy
= (op1
& (1 << (32 - op0
)));
1583 /* Store the result and condition codes. */
1584 State
.regs
[OP
[1]] = result
;
1585 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1586 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1587 | (cy
? PSW_CY
: 0));
1588 trace_output (OP_IMM_REG
);
1591 /* shl reg1, reg2 */
1595 unsigned int op0
, op1
, result
, z
, s
, cy
;
1597 trace_input ("shl", OP_REG_REG
, 0);
1598 op0
= State
.regs
[OP
[0]] & 0x1f;
1599 op1
= State
.regs
[OP
[1]];
1600 result
= op1
<< op0
;
1602 /* Compute the condition codes. */
1604 s
= (result
& 0x80000000);
1605 cy
= (op1
& (1 << (32 - op0
)));
1607 /* Store the result and condition codes. */
1608 State
.regs
[OP
[1]] = result
;
1609 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1610 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1611 | (cy
? PSW_CY
: 0));
1612 trace_output (OP_REG_REG
);
1615 /* shr zero_extend(imm5),reg1 */
1619 unsigned int op0
, op1
, result
, z
, s
, cy
;
1621 trace_input ("shr", OP_IMM_REG
, 0);
1623 op1
= State
.regs
[OP
[1]];
1624 result
= op1
>> op0
;
1626 /* Compute the condition codes. */
1628 s
= (result
& 0x80000000);
1629 cy
= (op1
& (1 << (op0
- 1)));
1631 /* Store the result and condition codes. */
1632 State
.regs
[OP
[1]] = result
;
1633 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1634 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1635 | (cy
? PSW_CY
: 0));
1636 trace_output (OP_IMM_REG
);
1639 /* shr reg1, reg2 */
1643 unsigned int op0
, op1
, result
, z
, s
, cy
;
1645 trace_input ("shr", OP_REG_REG
, 0);
1646 op0
= State
.regs
[OP
[0]] & 0x1f;
1647 op1
= State
.regs
[OP
[1]];
1648 result
= op1
>> op0
;
1650 /* Compute the condition codes. */
1652 s
= (result
& 0x80000000);
1653 cy
= (op1
& (1 << (op0
- 1)));
1655 /* Store the result and condition codes. */
1656 State
.regs
[OP
[1]] = result
;
1657 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1658 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1659 | (cy
? PSW_CY
: 0));
1660 trace_output (OP_REG_REG
);
1667 unsigned int op0
, op1
, result
, z
, s
;
1669 trace_input ("or", OP_REG_REG
, 0);
1671 /* Compute the result. */
1672 op0
= State
.regs
[OP
[0]];
1673 op1
= State
.regs
[OP
[1]];
1676 /* Compute the condition codes. */
1678 s
= (result
& 0x80000000);
1680 /* Store the result and condition codes. */
1681 State
.regs
[OP
[1]] = result
;
1682 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1683 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1684 trace_output (OP_REG_REG
);
1687 /* ori zero_extend(imm16), reg, reg */
1691 unsigned int op0
, op1
, result
, z
, s
;
1693 trace_input ("ori", OP_UIMM_REG_REG
, 0);
1694 op0
= OP
[0] & 0xffff;
1695 op1
= State
.regs
[OP
[1]];
1698 /* Compute the condition codes. */
1700 s
= (result
& 0x80000000);
1702 /* Store the result and condition codes. */
1703 State
.regs
[OP
[2]] = result
;
1704 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1705 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1706 trace_output (OP_UIMM_REG_REG
);
1713 unsigned int op0
, op1
, result
, z
, s
;
1715 trace_input ("and", OP_REG_REG
, 0);
1717 /* Compute the result. */
1718 op0
= State
.regs
[OP
[0]];
1719 op1
= State
.regs
[OP
[1]];
1722 /* Compute the condition codes. */
1724 s
= (result
& 0x80000000);
1726 /* Store the result and condition codes. */
1727 State
.regs
[OP
[1]] = result
;
1728 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1729 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1730 trace_output (OP_REG_REG
);
1733 /* andi zero_extend(imm16), reg, reg */
1737 unsigned int op0
, op1
, result
, z
;
1739 trace_input ("andi", OP_UIMM_REG_REG
, 0);
1740 op0
= OP
[0] & 0xffff;
1741 op1
= State
.regs
[OP
[1]];
1744 /* Compute the condition codes. */
1747 /* Store the result and condition codes. */
1748 State
.regs
[OP
[2]] = result
;
1749 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1750 State
.sregs
[5] |= (z
? PSW_Z
: 0);
1751 trace_output (OP_UIMM_REG_REG
);
1758 unsigned int op0
, op1
, result
, z
, s
;
1760 trace_input ("xor", OP_REG_REG
, 0);
1762 /* Compute the result. */
1763 op0
= State
.regs
[OP
[0]];
1764 op1
= State
.regs
[OP
[1]];
1767 /* Compute the condition codes. */
1769 s
= (result
& 0x80000000);
1771 /* Store the result and condition codes. */
1772 State
.regs
[OP
[1]] = result
;
1773 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1774 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1775 trace_output (OP_REG_REG
);
1778 /* xori zero_extend(imm16), reg, reg */
1782 unsigned int op0
, op1
, result
, z
, s
;
1784 trace_input ("xori", OP_UIMM_REG_REG
, 0);
1785 op0
= OP
[0] & 0xffff;
1786 op1
= State
.regs
[OP
[1]];
1789 /* Compute the condition codes. */
1791 s
= (result
& 0x80000000);
1793 /* Store the result and condition codes. */
1794 State
.regs
[OP
[2]] = result
;
1795 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1796 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1797 trace_output (OP_UIMM_REG_REG
);
1800 /* not reg1, reg2 */
1804 unsigned int op0
, result
, z
, s
;
1806 trace_input ("not", OP_REG_REG_MOVE
, 0);
1807 /* Compute the result. */
1808 op0
= State
.regs
[OP
[0]];
1811 /* Compute the condition codes. */
1813 s
= (result
& 0x80000000);
1815 /* Store the result and condition codes. */
1816 State
.regs
[OP
[1]] = result
;
1817 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1818 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1819 trace_output (OP_REG_REG_MOVE
);
1826 unsigned int op0
, op1
, op2
;
1829 trace_input ("set1", OP_BIT
, 0);
1830 op0
= State
.regs
[OP
[0]];
1832 temp
= SEXT16 (OP
[2]);
1834 temp
= load_mem (op0
+ op2
, 1);
1835 State
.sregs
[5] &= ~PSW_Z
;
1836 if ((temp
& (1 << op1
)) == 0)
1837 State
.sregs
[5] |= PSW_Z
;
1839 store_mem (op0
+ op2
, 1, temp
);
1840 trace_output (OP_BIT
);
1847 unsigned int op0
, op1
, op2
;
1850 trace_input ("not1", OP_BIT
, 0);
1851 op0
= State
.regs
[OP
[0]];
1853 temp
= SEXT16 (OP
[2]);
1855 temp
= load_mem (op0
+ op2
, 1);
1856 State
.sregs
[5] &= ~PSW_Z
;
1857 if ((temp
& (1 << op1
)) == 0)
1858 State
.sregs
[5] |= PSW_Z
;
1860 store_mem (op0
+ op2
, 1, temp
);
1861 trace_output (OP_BIT
);
1868 unsigned int op0
, op1
, op2
;
1871 trace_input ("clr1", OP_BIT
, 0);
1872 op0
= State
.regs
[OP
[0]];
1874 temp
= SEXT16 (OP
[2]);
1876 temp
= load_mem (op0
+ op2
, 1);
1877 State
.sregs
[5] &= ~PSW_Z
;
1878 if ((temp
& (1 << op1
)) == 0)
1879 State
.sregs
[5] |= PSW_Z
;
1880 temp
&= ~(1 << op1
);
1881 store_mem (op0
+ op2
, 1, temp
);
1882 trace_output (OP_BIT
);
1889 unsigned int op0
, op1
, op2
;
1892 trace_input ("tst1", OP_BIT
, 0);
1893 op0
= State
.regs
[OP
[0]];
1895 temp
= SEXT16 (OP
[2]);
1897 temp
= load_mem (op0
+ op2
, 1);
1898 State
.sregs
[5] &= ~PSW_Z
;
1899 if ((temp
& (1 << op1
)) == 0)
1900 State
.sregs
[5] |= PSW_Z
;
1901 trace_output (OP_BIT
);
1908 State
.exception
= SIGTRAP
;
1916 trace_input ("di", OP_NONE
, 0);
1917 State
.sregs
[5] |= PSW_ID
;
1918 trace_output (OP_NONE
);
1925 trace_input ("ei", OP_NONE
, 0);
1926 State
.sregs
[5] &= ~PSW_ID
;
1927 trace_output (OP_NONE
);
1930 /* halt, not supported */
1934 trace_input ("halt", OP_NONE
, 0);
1935 State
.exception
= SIGQUIT
;
1936 trace_output (OP_NONE
);
1939 /* reti, not supported */
1943 trace_input ("reti", OP_NONE
, 0);
1944 trace_output (OP_NONE
);
1946 if ((State
.sregs
[5] & (PSW_NP
| PSW_EP
)) == PSW_NP
)
1947 { /* Only NP is on */
1948 PC
= State
.sregs
[2] - 4; /* FEPC */
1949 State
.sregs
[5] = State
.sregs
[3]; /* FEPSW */
1953 PC
= State
.sregs
[0] - 4; /* EIPC */
1954 State
.sregs
[5] = State
.sregs
[1]; /* EIPSW */
1958 /* trap, not supportd */
1962 trace_input ("trap", OP_TRAP
, 0);
1963 trace_output (OP_TRAP
);
1965 /* Trap 31 is used for simulating OS I/O functions */
1969 int save_errno
= errno
;
1972 /* Registers passed to trap 0 */
1974 #define FUNC State.regs[6] /* function number, return value */
1975 #define PARM1 State.regs[7] /* optional parm 1 */
1976 #define PARM2 State.regs[8] /* optional parm 2 */
1977 #define PARM3 State.regs[9] /* optional parm 3 */
1979 /* Registers set by trap 0 */
1981 #define RETVAL State.regs[10] /* return value */
1982 #define RETERR State.regs[11] /* return error code */
1984 /* Turn a pointer in a register into a pointer into real memory. */
1986 #define MEMPTR(x) (map (x))
1990 #if !defined(__GO32__) && !defined(_WIN32)
1995 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
1996 (char **)MEMPTR (PARM3
));
1999 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2008 RETVAL
= pipe (host_fd
);
2009 SW (buf
, host_fd
[0]);
2010 buf
+= sizeof(uint16
);
2011 SW (buf
, host_fd
[1]);
2019 RETVAL
= wait (&status
);
2027 RETVAL
= v850_callback
->read (v850_callback
, PARM1
, MEMPTR (PARM2
),
2032 RETVAL
= (int)v850_callback
->write_stdout (v850_callback
,
2033 MEMPTR (PARM2
), PARM3
);
2035 RETVAL
= (int)v850_callback
->write (v850_callback
, PARM1
,
2036 MEMPTR (PARM2
), PARM3
);
2039 RETVAL
= v850_callback
->lseek (v850_callback
, PARM1
, PARM2
, PARM3
);
2042 RETVAL
= v850_callback
->close (v850_callback
, PARM1
);
2045 RETVAL
= v850_callback
->open (v850_callback
, MEMPTR (PARM1
), PARM2
);
2048 /* EXIT - caller can look in PARM1 to work out the
2050 if (PARM1
== 0xdead || PARM1
== 0x1)
2051 State
.exception
= SIGABRT
;
2053 State
.exception
= SIGQUIT
;
2056 case SYS_stat
: /* added at hmsi */
2057 /* stat system call */
2059 struct stat host_stat
;
2062 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2066 /* Just wild-assed guesses. */
2067 store_mem (buf
, 2, host_stat
.st_dev
);
2068 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2069 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2070 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2071 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2072 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2073 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2074 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2075 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2076 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2077 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2082 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2085 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2088 RETVAL
= time (MEMPTR (PARM1
));
2093 RETVAL
= times (&tms
);
2094 store_mem (PARM1
, 4, tms
.tms_utime
);
2095 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2096 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2097 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2100 case SYS_gettimeofday
:
2104 RETVAL
= gettimeofday (&t
, &tz
);
2105 store_mem (PARM1
, 4, t
.tv_sec
);
2106 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2107 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2108 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2112 /* Cast the second argument to void *, to avoid type mismatch
2113 if a prototype is present. */
2114 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2123 { /* Trap 0 -> 30 */
2124 State
.sregs
[0] = PC
+ 4; /* EIPC */
2125 State
.sregs
[1] = State
.sregs
[5]; /* EIPSW */
2126 State
.sregs
[4] &= 0xffff0000; /* Mask out EICC */
2127 State
.sregs
[4] |= 0x40 + OP
[0]; /* EICC */
2128 State
.sregs
[5] |= PSW_EP
| PSW_ID
; /* Now doing exception processing */
2129 PC
= ((OP
[0] < 0x10) ? 0x40 : 0x50) - 4;
2139 trace_input ("ldsr", OP_LDSR
, 0);
2140 op0
= State
.regs
[OP
[0]];
2141 State
.sregs
[OP
[1]] = op0
;
2142 trace_output (OP_LDSR
);
2145 /* stsr, not supported */
2151 trace_input ("stsr", OP_STSR
, 0);
2152 op0
= State
.sregs
[OP
[1]];
2153 State
.regs
[OP
[0]] = op0
;
2154 trace_output (OP_STSR
);
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