9 unsigned int op0
, op1
, op2
;
13 temp
= (temp
<< 25) >> 25;
15 result
= get_byte (State
.mem
+ State
.regs
[30] + op2
);
16 result
= (result
<< 24) >> 24;
17 State
.regs
[OP
[0]] = result
;
24 unsigned int op0
, op1
, op2
;
28 temp
= (temp
<< 25) >> 25;
30 result
= get_half (State
.mem
+ State
.regs
[30] + op2
);
31 result
= (result
<< 16) >> 16;
32 State
.regs
[OP
[0]] = result
;
39 unsigned int op0
, op1
, op2
;
43 temp
= (temp
<< 25) >> 25;
45 result
= get_word (State
.mem
+ State
.regs
[30] + op2
);
46 State
.regs
[OP
[0]] = result
;
53 unsigned int op0
, op1
, op2
;
56 op0
= State
.regs
[OP
[0]];
58 temp
= (temp
<< 25) >> 25;
60 put_byte (State
.mem
+ State
.regs
[30] + op1
, op0
);
67 unsigned int op0
, op1
, op2
;
70 op0
= State
.regs
[OP
[0]];
72 temp
= (temp
<< 25) >> 25;
74 put_half (State
.mem
+ State
.regs
[30] + op1
, op0
);
81 unsigned int op0
, op1
, op2
;
84 op0
= State
.regs
[OP
[0]];
86 temp
= (temp
<< 25) >> 25;
88 put_word (State
.mem
+ State
.regs
[30] + op1
, op0
);
95 unsigned int op0
, op1
, op2
;
98 op0
= State
.regs
[OP
[0]];
100 temp
= (temp
<< 16) >> 16;
102 result
= get_byte (State
.mem
+ op0
+ op2
);
103 result
= (result
<< 24) >> 24;
104 State
.regs
[OP
[1]] = result
;
111 unsigned int op0
, op1
, op2
;
114 op0
= State
.regs
[OP
[0]];
115 temp
= (temp
<< 16) >> 16;
118 result
= get_half (State
.mem
+ op0
+ op2
);
119 result
= (result
<< 16) >> 16;
120 State
.regs
[OP
[1]] = result
;
127 unsigned int op0
, op1
, op2
;
130 op0
= State
.regs
[OP
[0]];
131 temp
= (temp
<< 16) >> 16;
134 result
= get_word (State
.mem
+ op0
+ op2
);
135 State
.regs
[OP
[1]] = result
;
142 unsigned int op0
, op1
, op2
;
145 op0
= State
.regs
[OP
[0]];
146 op1
= State
.regs
[OP
[1]];
148 temp
= (temp
<< 16) >> 16;
150 put_byte (State
.mem
+ op0
+ op2
, op1
);
157 unsigned int op0
, op1
, op2
;
160 op0
= State
.regs
[OP
[0]];
161 op1
= State
.regs
[OP
[1]];
164 temp
= (temp
<< 16) >> 16;
166 put_half (State
.mem
+ op0
+ op2
, op1
);
173 unsigned int op0
, op1
, op2
;
176 op0
= State
.regs
[OP
[0]];
177 op1
= State
.regs
[OP
[1]];
180 temp
= (temp
<< 16) >> 16;
182 put_word (State
.mem
+ op0
+ op2
, op1
);
189 unsigned int op0
, psw
;
192 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
194 psw
= State
.sregs
[5];
196 if ((psw
& PSW_OV
) != 0)
206 unsigned int op0
, psw
;
209 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
211 psw
= State
.sregs
[5];
213 if ((psw
& PSW_CY
) != 0)
223 unsigned int op0
, psw
;
226 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
228 psw
= State
.sregs
[5];
230 if ((psw
& PSW_Z
) != 0)
240 unsigned int op0
, psw
;
243 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
245 psw
= State
.sregs
[5];
247 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0)
257 unsigned int op0
, psw
;
260 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
262 psw
= State
.sregs
[5];
264 if ((psw
& PSW_S
) != 0)
277 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
286 unsigned int op0
, psw
;
289 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
291 psw
= State
.sregs
[5];
293 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0)
303 unsigned int op0
, psw
;
306 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
308 psw
= State
.sregs
[5];
310 if ((((psw
& PSW_Z
) != 0)
311 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) != 0)
321 unsigned int op0
, psw
;
324 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
326 psw
= State
.sregs
[5];
328 if ((psw
& PSW_OV
) == 0)
338 unsigned int op0
, psw
;
341 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
343 psw
= State
.sregs
[5];
345 if ((psw
& PSW_CY
) == 0)
355 unsigned int op0
, psw
;
358 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
360 psw
= State
.sregs
[5];
362 if ((psw
& PSW_Z
) == 0)
372 unsigned int op0
, psw
;
375 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
377 psw
= State
.sregs
[5];
379 if ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0)
389 unsigned int op0
, psw
;
392 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
394 psw
= State
.sregs
[5];
396 if ((psw
& PSW_S
) == 0)
406 unsigned int op0
, psw
;
409 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
411 psw
= State
.sregs
[5];
413 if ((psw
& PSW_SAT
) != 0)
423 unsigned int op0
, psw
;
426 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
428 psw
= State
.sregs
[5];
430 if ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0)
440 unsigned int op0
, psw
;
443 temp
= (State
.regs
[OP
[0]] << 23) >> 23;
445 psw
= State
.sregs
[5];
447 if ((((psw
& PSW_Z
) != 0)
448 || (((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))) == 0)
458 /* interp.c will bump this by +2, so correct for it here. */
459 State
.pc
= State
.regs
[OP
[0]] - 2;
462 /* jarl disp22, reg */
466 unsigned int op0
, opc
;
470 temp
= (temp
<< 10) >> 10;
476 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
478 State
.regs
[OP
[1]] = opc
+ 4;
485 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
487 /* Compute the result. */
488 op0
= State
.regs
[OP
[0]];
489 op1
= State
.regs
[OP
[1]];
492 /* Compute the condition codes. */
494 s
= (result
& 0x80000000);
495 cy
= (result
< op0
|| result
< op1
);
496 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
497 && (op0
& 0x80000000) != (result
& 0x80000000));
499 /* Store the result and condition codes. */
500 State
.regs
[OP
[1]] = result
;
501 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
502 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
503 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
506 /* add sign_extend(imm5), reg */
510 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
513 /* Compute the result. */
514 temp
= (OP
[0] & 0x1f);
515 temp
= (temp
<< 27) >> 27;
517 op1
= State
.regs
[OP
[1]];
520 /* Compute the condition codes. */
522 s
= (result
& 0x80000000);
523 cy
= (result
< op0
|| result
< op1
);
524 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
525 && (op0
& 0x80000000) != (result
& 0x80000000));
527 /* Store the result and condition codes. */
528 State
.regs
[OP
[1]] = result
;
529 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
530 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
531 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
534 /* addi sign_extend(imm16), reg, reg */
538 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
541 /* Compute the result. */
542 temp
= (OP
[0] & 0xffff);
543 temp
= (temp
<< 16) >> 16;
545 op1
= State
.regs
[OP
[1]];
548 /* Compute the condition codes. */
550 s
= (result
& 0x80000000);
551 cy
= (result
< op0
|| result
< op1
);
552 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
553 && (op0
& 0x80000000) != (result
& 0x80000000));
555 /* Store the result and condition codes. */
556 State
.regs
[OP
[2]] = result
;
557 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
558 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
559 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
566 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
568 /* Compute the result. */
569 op0
= State
.regs
[OP
[0]];
570 op1
= State
.regs
[OP
[1]];
573 /* Compute the condition codes. */
575 s
= (result
& 0x80000000);
576 cy
= (result
< -op0
);
577 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
578 && (op1
& 0x80000000) != (result
& 0x80000000));
580 /* Store the result and condition codes. */
581 State
.regs
[OP
[1]] = result
;
582 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
583 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
584 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
587 /* subr reg1, reg2 */
591 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
593 /* Compute the result. */
594 op0
= State
.regs
[OP
[0]];
595 op1
= State
.regs
[OP
[1]];
598 /* Compute the condition codes. */
600 s
= (result
& 0x80000000);
601 cy
= (result
< -op1
);
602 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
603 && (op0
& 0x80000000) != (result
& 0x80000000));
605 /* Store the result and condition codes. */
606 State
.regs
[OP
[1]] = result
;
607 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
608 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
609 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
612 /* mulh reg1, reg2 */
616 State
.regs
[OP
[1]] = ((State
.regs
[OP
[1]] & 0xffff)
617 * (State
.regs
[OP
[0]] & 0xffff));
620 /* mulh sign_extend(imm5), reg2
628 value
= (value
<< 27) >> 27;
630 State
.regs
[OP
[1]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
633 /* mulhi imm16, reg1, reg2 */
639 value
= value
& 0xffff;
641 State
.regs
[OP
[2]] = (State
.regs
[OP
[1]] & 0xffff) * value
;
644 /* divh reg1, reg2 */
648 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
651 /* Compute the result. */
652 temp
= State
.regs
[OP
[0]] & 0xffff;
653 temp
= (temp
<< 16) >> 16;
655 op1
= State
.regs
[OP
[1]];
657 if (op0
== 0xffffffff && op1
== 0x80000000)
670 /* Compute the condition codes. */
672 s
= (result
& 0x80000000);
674 /* Store the result and condition codes. */
675 State
.regs
[OP
[1]] = result
;
676 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
677 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
678 | (ov
? PSW_OV
: 0));
685 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
687 /* Compute the result. */
688 op0
= State
.regs
[OP
[0]];
689 op1
= State
.regs
[OP
[1]];
692 /* Compute the condition codes. */
694 s
= (result
& 0x80000000);
695 cy
= (result
< -op0
);
696 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
697 && (op1
& 0x80000000) != (result
& 0x80000000));
699 /* Set condition codes. */
700 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
701 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
702 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
705 /* cmp sign_extend(imm5), reg */
709 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
712 /* Compute the result. */
714 temp
= (temp
<< 27) >> 27;
716 op1
= State
.regs
[OP
[1]];
719 /* Compute the condition codes. */
721 s
= (result
& 0x80000000);
722 cy
= (result
< -op0
);
723 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
724 && (op1
& 0x80000000) != (result
& 0x80000000));
726 /* Set condition codes. */
727 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
728 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
729 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
736 /* Hack alert. We turn off a bit in op0 since we really only
738 unsigned int op0
, psw
, result
;
741 psw
= State
.sregs
[5];
746 result
= ((psw
& PSW_OV
) != 0);
749 result
= ((psw
& PSW_CY
) != 0);
752 result
= ((psw
& PSW_Z
) != 0);
755 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
758 result
= ((psw
& PSW_S
) != 0);
764 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
767 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
768 || ((psw
& PSW_Z
) != 0)) != 0);
771 result
= ((psw
& PSW_OV
) == 0);
774 result
= ((psw
& PSW_CY
) == 0);
777 result
= ((psw
& PSW_Z
) == 0);
780 result
= ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
783 result
= ((psw
& PSW_S
) == 0);
786 result
= ((psw
& PSW_SAT
) != 0);
789 result
= ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
792 result
= (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0))
793 || ((psw
& PSW_Z
) != 0)) == 0);
797 State
.regs
[OP
[1]] = result
;
804 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
806 /* Compute the result. */
807 op0
= State
.regs
[OP
[0]];
808 op1
= State
.regs
[OP
[1]];
811 /* Compute the condition codes. */
813 s
= (result
& 0x80000000);
814 cy
= (result
< op0
|| result
< op1
);
815 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
816 && (op0
& 0x80000000) != (result
& 0x80000000));
819 /* Store the result and condition codes. */
820 State
.regs
[OP
[1]] = result
;
821 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
822 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
823 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
824 | (sat
? PSW_SAT
: 0));
826 /* Handle saturated results. */
827 if (sat
&& (op0
& 0x80000000))
828 State
.regs
[OP
[1]] = 0x80000000;
830 State
.regs
[OP
[1]] = 0x7fffffff;
833 /* satadd sign_extend(imm5), reg */
837 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
841 /* Compute the result. */
842 temp
= (OP
[0] & 0x1f);
843 temp
= (temp
<< 27) >> 27;
845 op1
= State
.regs
[OP
[1]];
848 /* Compute the condition codes. */
850 s
= (result
& 0x80000000);
851 cy
= (result
< op0
|| result
< op1
);
852 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
853 && (op0
& 0x80000000) != (result
& 0x80000000));
856 /* Store the result and condition codes. */
857 State
.regs
[OP
[1]] = result
;
858 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
859 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
860 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
861 | (sat
? PSW_SAT
: 0));
863 /* Handle saturated results. */
864 if (sat
&& (op0
& 0x80000000))
865 State
.regs
[OP
[1]] = 0x80000000;
867 State
.regs
[OP
[1]] = 0x7fffffff;
870 /* satsub reg1, reg2 */
874 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
876 /* Compute the result. */
877 op0
= State
.regs
[OP
[0]];
878 op1
= State
.regs
[OP
[1]];
881 /* Compute the condition codes. */
883 s
= (result
& 0x80000000);
884 cy
= (result
< -op0
);
885 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
886 && (op1
& 0x80000000) != (result
& 0x80000000));
889 /* Store the result and condition codes. */
890 State
.regs
[OP
[1]] = result
;
891 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
892 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
893 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
894 | (sat
? PSW_SAT
: 0));
896 /* Handle saturated results. */
897 if (sat
&& (op1
& 0x80000000))
898 State
.regs
[OP
[1]] = 0x80000000;
900 State
.regs
[OP
[1]] = 0x7fffffff;
903 /* satsubi sign_extend(imm16), reg */
907 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
910 /* Compute the result. */
911 temp
= (OP
[0] & 0xffff);
912 temp
= (temp
<< 16) >> 16;
914 op1
= State
.regs
[OP
[1]];
917 /* Compute the condition codes. */
919 s
= (result
& 0x80000000);
920 cy
= (result
< -op0
);
921 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
922 && (op1
& 0x80000000) != (result
& 0x80000000));
925 /* Store the result and condition codes. */
926 State
.regs
[OP
[1]] = result
;
927 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
928 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
929 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
930 | (sat
? PSW_SAT
: 0));
932 /* Handle saturated results. */
933 if (sat
&& (op1
& 0x80000000))
934 State
.regs
[OP
[1]] = 0x80000000;
936 State
.regs
[OP
[1]] = 0x7fffffff;
942 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
944 /* Compute the result. */
945 op0
= State
.regs
[OP
[0]];
946 op1
= State
.regs
[OP
[1]];
949 /* Compute the condition codes. */
951 s
= (result
& 0x80000000);
952 cy
= (result
< -op0
);
953 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
954 && (op1
& 0x80000000) != (result
& 0x80000000));
957 /* Store the result and condition codes. */
958 State
.regs
[OP
[1]] = result
;
959 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
960 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
961 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
962 | (sat
? PSW_SAT
: 0));
964 /* Handle saturated results. */
965 if (sat
&& (op0
& 0x80000000))
966 State
.regs
[OP
[1]] = 0x80000000;
968 State
.regs
[OP
[1]] = 0x7fffffff;
975 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
977 /* Compute the result. */
978 op0
= State
.regs
[OP
[0]];
979 op1
= State
.regs
[OP
[1]];
982 /* Compute the condition codes. */
984 s
= (result
& 0x80000000);
986 /* Store the condition codes. */
987 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
988 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
995 State
.regs
[OP
[1]] = State
.regs
[OP
[0]];
998 /* mov sign_extend(imm5), reg */
1004 value
= (value
<< 27) >> 27;
1005 State
.regs
[OP
[1]] = value
;
1008 /* movea sign_extend(imm16), reg, reg */
1015 value
= (value
<< 16) >> 16;
1017 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1020 /* movhi imm16, reg, reg */
1026 value
= (value
& 0xffff) << 16;
1028 State
.regs
[OP
[2]] = State
.regs
[OP
[1]] + value
;
1031 /* sar zero_extend(imm5),reg1 */
1035 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1038 op1
= State
.regs
[OP
[1]];
1039 result
= (signed)op1
>> op0
;
1041 /* Compute the condition codes. */
1043 s
= (result
& 0x80000000);
1044 cy
= (op1
& (1 << (op0
- 1)));
1046 /* Store the result and condition codes. */
1047 State
.regs
[OP
[1]] = result
;
1048 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1049 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1050 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
1053 /* sar reg1, reg2 */
1057 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1059 op0
= State
.regs
[OP
[0]] & 0x1f;
1060 op1
= State
.regs
[OP
[1]];
1061 result
= (signed)op1
>> op0
;
1063 /* Compute the condition codes. */
1065 s
= (result
& 0x80000000);
1066 cy
= (op1
& (1 << (op0
- 1)));
1068 /* Store the result and condition codes. */
1069 State
.regs
[OP
[1]] = result
;
1070 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1071 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1072 | (cy
? PSW_CY
: 0));
1075 /* shl zero_extend(imm5),reg1 */
1079 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1082 op1
= State
.regs
[OP
[1]];
1083 result
= op1
<< op0
;
1085 /* Compute the condition codes. */
1087 s
= (result
& 0x80000000);
1088 cy
= (op1
& (1 << (32 - op0
)));
1090 /* Store the result and condition codes. */
1091 State
.regs
[OP
[1]] = result
;
1092 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1093 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1094 | (cy
? PSW_CY
: 0));
1097 /* shl reg1, reg2 */
1101 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1103 op0
= State
.regs
[OP
[0]] & 0x1f;
1104 op1
= State
.regs
[OP
[1]];
1105 result
= op1
<< op0
;
1107 /* Compute the condition codes. */
1109 s
= (result
& 0x80000000);
1110 cy
= (op1
& (1 << (32 - op0
)));
1112 /* Store the result and condition codes. */
1113 State
.regs
[OP
[1]] = result
;
1114 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1115 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1116 | (cy
? PSW_CY
: 0));
1119 /* shr zero_extend(imm5),reg1 */
1123 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1126 op1
= State
.regs
[OP
[1]];
1127 result
= op1
>> op0
;
1129 /* Compute the condition codes. */
1131 s
= (result
& 0x80000000);
1132 cy
= (op1
& (1 << (op0
- 1)));
1134 /* Store the result and condition codes. */
1135 State
.regs
[OP
[1]] = result
;
1136 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1137 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1138 | (cy
? PSW_CY
: 0));
1141 /* shr reg1, reg2 */
1145 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1147 op0
= State
.regs
[OP
[0]] & 0x1f;
1148 op1
= State
.regs
[OP
[1]];
1149 result
= op1
>> op0
;
1151 /* Compute the condition codes. */
1153 s
= (result
& 0x80000000);
1154 cy
= (op1
& (1 << (op0
- 1)));
1156 /* Store the result and condition codes. */
1157 State
.regs
[OP
[1]] = result
;
1158 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1159 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1160 | (cy
? PSW_CY
: 0));
1167 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1169 /* Compute the result. */
1170 op0
= State
.regs
[OP
[0]];
1171 op1
= State
.regs
[OP
[1]];
1174 /* Compute the condition codes. */
1176 s
= (result
& 0x80000000);
1178 /* Store the result and condition codes. */
1179 State
.regs
[OP
[1]] = result
;
1180 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1181 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1184 /* ori zero_extend(imm16), reg, reg */
1188 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1190 op0
= OP
[0] & 0xffff;
1191 op1
= State
.regs
[OP
[1]];
1194 /* Compute the condition codes. */
1196 s
= (result
& 0x80000000);
1198 /* Store the result and condition codes. */
1199 State
.regs
[OP
[2]] = result
;
1200 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1201 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1208 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1210 /* Compute the result. */
1211 op0
= State
.regs
[OP
[0]];
1212 op1
= State
.regs
[OP
[1]];
1215 /* Compute the condition codes. */
1217 s
= (result
& 0x80000000);
1219 /* Store the result and condition codes. */
1220 State
.regs
[OP
[1]] = result
;
1221 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1222 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1225 /* andi zero_extend(imm16), reg, reg */
1229 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1231 op0
= OP
[0] & 0xffff;
1232 op1
= State
.regs
[OP
[1]];
1235 /* Compute the condition codes. */
1238 /* Store the result and condition codes. */
1239 State
.regs
[OP
[2]] = result
;
1240 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1241 State
.sregs
[5] |= (z
? PSW_Z
: 0);
1248 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1250 /* Compute the result. */
1251 op0
= State
.regs
[OP
[0]];
1252 op1
= State
.regs
[OP
[1]];
1255 /* Compute the condition codes. */
1257 s
= (result
& 0x80000000);
1259 /* Store the result and condition codes. */
1260 State
.regs
[OP
[1]] = result
;
1261 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1262 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1265 /* xori zero_extend(imm16), reg, reg */
1269 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
1271 op0
= OP
[0] & 0xffff;
1272 op1
= State
.regs
[OP
[1]];
1275 /* Compute the condition codes. */
1277 s
= (result
& 0x80000000);
1279 /* Store the result and condition codes. */
1280 State
.regs
[OP
[2]] = result
;
1281 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1282 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1285 /* not reg1, reg2 */
1289 unsigned int op0
, result
, z
, s
, cy
, ov
;
1291 /* Compute the result. */
1292 op0
= State
.regs
[OP
[0]];
1295 /* Compute the condition codes. */
1297 s
= (result
& 0x80000000);
1299 /* Store the result and condition codes. */
1300 State
.regs
[OP
[1]] = result
;
1301 State
.sregs
[5] &= ~(PSW_Z
| PSW_S
| PSW_OV
);
1302 State
.sregs
[5] |= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1309 unsigned int op0
, op1
, op2
;
1312 op0
= State
.regs
[OP
[0]];
1315 temp
= (temp
<< 16) >> 16;
1317 temp
= get_byte (State
.mem
+ op0
+ op2
);
1318 State
.sregs
[5] &= ~PSW_Z
;
1319 if ((temp
& (1 << op1
)) == 0)
1320 State
.sregs
[5] |= PSW_Z
;
1321 temp
|= ~(1 << op1
);
1322 put_byte (State
.mem
+ op0
+ op2
, temp
);
1329 unsigned int op0
, op1
, op2
;
1332 op0
= State
.regs
[OP
[0]];
1335 temp
= (temp
<< 16) >> 16;
1337 temp
= get_byte (State
.mem
+ op0
+ op2
);
1338 State
.sregs
[5] &= ~PSW_Z
;
1339 if ((temp
& (1 << op1
)) == 0)
1340 State
.sregs
[5] |= PSW_Z
;
1341 temp
^= ~(1 << op1
);
1342 put_byte (State
.mem
+ op0
+ op2
, temp
);
1349 unsigned int op0
, op1
, op2
;
1352 op0
= State
.regs
[OP
[0]];
1355 temp
= (temp
<< 16) >> 16;
1357 temp
= get_byte (State
.mem
+ op0
+ op2
);
1358 State
.sregs
[5] &= ~PSW_Z
;
1359 if ((temp
& (1 << op1
)) == 0)
1360 State
.sregs
[5] |= PSW_Z
;
1361 temp
&= ~(1 << op1
);
1362 put_byte (State
.mem
+ op0
+ op2
, temp
);
1369 unsigned int op0
, op1
, op2
;
1372 op0
= State
.regs
[OP
[0]];
1375 temp
= (temp
<< 16) >> 16;
1377 temp
= get_byte (State
.mem
+ op0
+ op2
);
1378 State
.sregs
[5] &= ~PSW_Z
;
1379 if ((temp
& (1 << op1
)) == 0)
1380 State
.sregs
[5] |= PSW_Z
;
1387 State
.sregs
[5] |= PSW_ID
;
1394 State
.sregs
[5] &= ~PSW_ID
;
1397 /* halt, not supported */
1404 /* reti, not supported */
1411 /* trap, not supportd */
1424 op0
= State
.regs
[OP
[0]];
1425 State
.sregs
[OP
[1]] = op0
;
1428 /* stsr, not supported */
1434 op0
= State
.sregs
[OP
[1]];
1435 State
.regs
[OP
[0]] = op0
;
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