1 :option:::insn-bit-size:16
5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6 :option:::format-names:XI,XII,XIII
7 :option:::format-names:XIV,XV
8 :option:::format-names:Z
13 :option:::multi-sim:true
16 :option:::multi-sim:true
17 :model:::v850ea:v850ea:
23 :cache:::unsigned:reg1:RRRRR:(RRRRR)
24 :cache:::unsigned:reg2:rrrrr:(rrrrr)
25 :cache:::unsigned:reg3:wwwww:(wwwww)
27 :cache:::unsigned:disp4:dddd:(dddd)
28 :cache:::unsigned:disp5:dddd:(dddd << 1)
29 :cache:::unsigned:disp7:ddddddd:ddddddd
30 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
31 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
32 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
33 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
34 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
35 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
37 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
38 :cache:::unsigned:imm6:iiiiii:iiiiii
39 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
40 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
41 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
42 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
43 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
44 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
46 :cache:::unsigned:vector:iiiii:iiiii
48 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
49 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
51 :cache:::unsigned:bit3:bbb:bbb
54 // What do we do with an illegal instruction?
57 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
59 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
66 rrrrr,001110,RRRRR:I:::add
67 "add r<reg1>, r<reg2>"
72 rrrrr,010010,iiiii:II:::add
81 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
82 "addi <simm16>, r<reg1>, r<reg2>"
90 rrrrr,001010,RRRRR:I:::and
91 "and r<reg1>, r<reg2>"
99 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
100 "andi <uimm16>, r<reg1>, r<reg2>"
102 COMPAT_2 (OP_6C0 ());
107 // Map condition code to a string
112 case 0xf: return "gt";
113 case 0xe: return "ge";
114 case 0x6: return "lt";
116 case 0x7: return "le";
118 case 0xb: return "h";
119 case 0x9: return "nl";
120 case 0x1: return "l";
122 case 0x3: return "nh";
124 case 0x2: return "e";
126 case 0xa: return "ne";
128 case 0x0: return "v";
129 case 0x8: return "nv";
130 case 0x4: return "n";
131 case 0xc: return "p";
132 /* case 0x1: return "c"; */
133 /* case 0x9: return "nc"; */
134 /* case 0x2: return "z"; */
135 /* case 0xa: return "nz"; */
136 case 0x5: return "r"; /* always */
137 case 0xd: return "sa";
144 ddddd,1011,ddd,cccc:III:::Bcond
147 int cond = condition_met (cccc);
150 TRACE_BRANCH1 (cond);
156 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
159 "bsh r<reg2>, r<reg3>"
162 TRACE_ALU_INPUT1 (GR[reg2]);
164 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
165 | MOVED32 (GR[reg2], 31, 24, 23, 16)
166 | MOVED32 (GR[reg2], 7, 0, 15, 8)
167 | MOVED32 (GR[reg2], 15, 8, 7, 0));
170 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
171 if (value == 0) PSW |= PSW_Z;
172 if (value & 0x80000000) PSW |= PSW_S;
173 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
175 TRACE_ALU_RESULT (GR[reg3]);
179 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
182 "bsw r<reg2>, r<reg3>"
184 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
186 TRACE_ALU_INPUT1 (GR[reg2]);
190 value |= (GR[reg2] << 24);
191 value |= ((GR[reg2] << 8) & 0x00ff0000);
192 value |= ((GR[reg2] >> 8) & 0x0000ff00);
195 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
197 if (value == 0) PSW |= PSW_Z;
198 if (value & 0x80000000) PSW |= PSW_S;
199 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
201 TRACE_ALU_RESULT (GR[reg3]);
205 0000001000,iiiiii:II:::callt
214 adr = (CTBP & ~1) + (imm6 << 1);
215 off = load_mem (adr, 2) & ~1; /* Force alignment */
216 nia = (CTBP & ~1) + off;
217 TRACE_BRANCH3 (adr, CTBP, off);
222 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
223 "clr1 <bit3>, <disp16>[r<reg1>]"
225 COMPAT_2 (OP_87C0 ());
228 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
231 "clr1 r<reg2>, [r<reg1>]"
233 COMPAT_2 (OP_E407E0 ());
238 0000011111100000 + 0000000101000100:X:::ctret
244 PSW = (CTPSW & (CPU)->psw_mask);
249 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
252 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
254 int cond = condition_met (cccc);
255 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
256 GR[reg3] = cond ? GR[reg1] : GR[reg2];
257 TRACE_ALU_RESULT (GR[reg3]);
260 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
263 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
265 int cond = condition_met (cccc);
266 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
267 GR[reg3] = cond ? imm5 : GR[reg2];
268 TRACE_ALU_RESULT (GR[reg3]);
272 rrrrr,001111,RRRRR:I:::cmp
273 "cmp r<reg1>, r<reg2>"
275 COMPAT_1 (OP_1E0 ());
278 rrrrr,010011,iiiii:II:::cmp
279 "cmp <imm5>, r<reg2>"
281 COMPAT_1 (OP_260 ());
287 0000011111100000 + 0000000101100000:X:::di
290 COMPAT_2 (OP_16007E0 ());
296 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
297 // "dispose <imm5>, <list12>"
298 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
301 "dispose <imm5>, <list12>":RRRRR == 0
302 "dispose <imm5>, <list12>, [reg1]"
307 trace_input ("dispose", OP_PUSHPOP1, 0);
309 SP += (OP[3] & 0x3e) << 1;
311 /* Load the registers with lower number registers being retrieved
312 from higher addresses. */
314 if ((OP[3] & (1 << type1_regs[ i ])))
316 State.regs[ 20 + i ] = load_mem (SP, 4);
320 if ((OP[3] & 0x1f0000) != 0)
322 nia = State.regs[ (OP[3] >> 16) & 0x1f];
325 trace_output (OP_PUSHPOP1);
330 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
332 "div r<reg1>, r<reg2>, r<reg3>"
334 COMPAT_2 (OP_2C007E0 ());
339 rrrrr!0,000010,RRRRR!0:I:::divh
340 "divh r<reg1>, r<reg2>"
345 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
347 "divh r<reg1>, r<reg2>, r<reg3>"
349 COMPAT_2 (OP_28007E0 ());
354 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
356 "divhu r<reg1>, r<reg2>, r<reg3>"
358 COMPAT_2 (OP_28207E0 ());
363 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
365 "divu r<reg1>, r<reg2>, r<reg3>"
367 COMPAT_2 (OP_2C207E0 ());
372 1000011111100000 + 0000000101100000:X:::ei
375 COMPAT_2 (OP_16087E0 ());
381 0000011111100000 + 0000000100100000:X:::halt
384 COMPAT_2 (OP_12007E0 ());
390 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
393 "hsw r<reg2>, r<reg3>"
396 TRACE_ALU_INPUT1 (GR[reg2]);
400 value |= (GR[reg2] << 16);
404 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
406 if (value == 0) PSW |= PSW_Z;
407 if (value & 0x80000000) PSW |= PSW_S;
408 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
410 TRACE_ALU_RESULT (GR[reg3]);
416 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
417 "jarl <disp22>, r<reg2>"
421 TRACE_BRANCH1 (GR[reg2]);
427 00000000011,RRRRR:I:::jmp
437 0000011110,dddddd + ddddddddddddddd,0:V:::jr
447 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
448 "ld.b <disp16>[r<reg1>], r<reg2>"
450 COMPAT_2 (OP_700 ());
453 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
454 "ld.h <disp16>[r<reg1>], r<reg2>"
456 COMPAT_2 (OP_720 ());
459 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
460 "ld.w <disp16>[r<reg1>], r<reg2>"
462 COMPAT_2 (OP_10720 ());
465 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
468 "ld.bu <disp16>[r<reg1>], r<reg2>"
470 COMPAT_2 (OP_10780 ());
473 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
476 "ld.hu <disp16>[r<reg1>], r<reg2>"
478 COMPAT_2 (OP_107E0 ());
483 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
484 "ldsr r<reg1>, s<regID>"
486 TRACE_ALU_INPUT1 (GR[reg1]);
488 if (&PSW == &SR[regID])
489 PSW = (GR[reg1] & (CPU)->psw_mask);
491 SR[regID] = GR[reg1];
493 TRACE_ALU_RESULT (SR[regID]);
499 rrrrr!0,000000,RRRRR:I:::mov
500 "mov r<reg1>, r<reg2>"
504 TRACE_ALU_RESULT (GR[reg2]);
508 rrrrr!0,010000,iiiii:II:::mov
509 "mov <imm5>, r<reg2>"
511 COMPAT_1 (OP_200 ());
514 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
517 "mov <imm32>, r<reg1>"
520 trace_input ("mov", OP_IMM_REG, 4);
521 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
522 trace_output (OP_IMM_REG);
528 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
529 "movea <simm16>, r<reg1>, r<reg2>"
531 TRACE_ALU_INPUT2 (GR[reg1], simm16);
532 GR[reg2] = GR[reg1] + simm16;
533 TRACE_ALU_RESULT (GR[reg2]);
539 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
540 "movhi <uimm16>, r<reg1>, r<reg2>"
542 COMPAT_2 (OP_640 ());
548 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
551 "mul r<reg1>, r<reg2>, r<reg3>"
553 COMPAT_2 (OP_22007E0 ());
556 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
559 "mul <imm9>, r<reg2>, r<reg3>"
561 COMPAT_2 (OP_24007E0 ());
566 rrrrr!0,000111,RRRRR:I:::mulh
567 "mulh r<reg1>, r<reg2>"
572 rrrrr!0,010111,iiiii:II:::mulh
573 "mulh <imm5>, r<reg2>"
575 COMPAT_1 (OP_2E0 ());
581 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
582 "mulhi <uimm16>, r<reg1>, r<reg2>"
584 COMPAT_2 (OP_6E0 ());
590 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
593 "mulu r<reg1>, r<reg2>, r<reg3>"
595 COMPAT_2 (OP_22207E0 ());
598 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
601 "mulu <imm9>, r<reg2>, r<reg3>"
603 COMPAT_2 (OP_24207E0 ());
609 0000000000000000:I:::nop
612 /* do nothing, trace nothing */
618 rrrrr,000001,RRRRR:I:::not
619 "not r<reg1>, r<reg2>"
627 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
628 "not1 <bit3>, <disp16>[r<reg1>]"
630 COMPAT_2 (OP_47C0 ());
633 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
636 "not1 r<reg2>, r<reg1>"
638 COMPAT_2 (OP_E207E0 ());
644 rrrrr,001000,RRRRR:I:::or
645 "or r<reg1>, r<reg2>"
647 COMPAT_1 (OP_100 ());
653 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
654 "ori <uimm16>, r<reg1>, r<reg2>"
656 COMPAT_2 (OP_680 ());
662 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
665 "prepare <list12>, <imm5>"
670 trace_input ("prepare", OP_PUSHPOP1, 0);
672 /* Store the registers with lower number registers being placed at
674 for (i = 0; i < 12; i++)
675 if ((OP[3] & (1 << type1_regs[ i ])))
678 store_mem (SP, 4, State.regs[ 20 + i ]);
681 SP -= (OP[3] & 0x3e) << 1;
683 trace_output (OP_PUSHPOP1);
687 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
690 "prepare <list12>, <imm5>, sp"
692 COMPAT_2 (OP_30780 ());
695 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
698 "prepare <list12>, <imm5>, <uimm16>"
700 COMPAT_2 (OP_B0780 ());
703 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
706 "prepare <list12>, <imm5>, <uimm16>"
708 COMPAT_2 (OP_130780 ());
711 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
714 "prepare <list12>, <imm5>, <uimm32>"
716 COMPAT_2 (OP_1B0780 ());
722 0000011111100000 + 0000000101000000:X:::reti
730 else if ((PSW & PSW_NP))
746 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
747 "sar r<reg1>, r<reg2>"
749 COMPAT_2 (OP_A007E0 ());
752 rrrrr,010101,iiiii:II:::sar
753 "sar <imm5>, r<reg2>"
755 COMPAT_1 (OP_2A0 ());
761 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
764 "sasf %s<cccc>, r<reg2>"
766 COMPAT_2 (OP_20007E0 ());
773 rrrrr!0,000110,RRRRR:I:::satadd
774 "satadd r<reg1>, r<reg2>"
779 rrrrr!0,010001,iiiii:II:::satadd
780 "satadd <imm5>, r<reg2>"
782 COMPAT_1 (OP_220 ());
788 rrrrr!0,000101,RRRRR:I:::satsub
789 "satsub r<reg1>, r<reg2>"
797 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
798 "satsubi <simm16>, r<reg1>, r<reg2>"
800 COMPAT_2 (OP_660 ());
806 rrrrr!0,000100,RRRRR:I:::satsubr
807 "satsubr r<reg1>, r<reg2>"
815 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
816 "setf %s<cccc>, r<reg2>"
818 COMPAT_2 (OP_7E0 ());
824 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
825 "set1 <bit3>, <disp16>[r<reg1>]"
827 COMPAT_2 (OP_7C0 ());
830 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
833 "set1 r<reg2>, [r<reg1>]"
835 COMPAT_2 (OP_E007E0 ());
841 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
842 "shl r<reg1>, r<reg2>"
844 COMPAT_2 (OP_C007E0 ());
847 rrrrr,010110,iiiii:II:::shl
848 "shl <imm5>, r<reg2>"
850 COMPAT_1 (OP_2C0 ());
856 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
857 "shr r<reg1>, r<reg2>"
859 COMPAT_2 (OP_8007E0 ());
862 rrrrr,010100,iiiii:II:::shr
863 "shr <imm5>, r<reg2>"
865 COMPAT_1 (OP_280 ());
871 rrrrr,0110,ddddddd:IV:::sld.b
872 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
873 "sld.b <disp7>[ep], r<reg2>"
875 unsigned32 addr = EP + disp7;
876 unsigned32 result = load_mem (addr, 1);
880 TRACE_LD_NAME ("sld.bu", addr, result);
884 result = EXTEND8 (result);
886 TRACE_LD (addr, result);
890 rrrrr,1000,ddddddd:IV:::sld.h
891 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
892 "sld.h <disp8>[ep], r<reg2>"
894 unsigned32 addr = EP + disp8;
895 unsigned32 result = load_mem (addr, 2);
899 TRACE_LD_NAME ("sld.hu", addr, result);
903 result = EXTEND16 (result);
905 TRACE_LD (addr, result);
909 rrrrr,1010,dddddd,0:IV:::sld.w
910 "sld.w <disp8>[ep], r<reg2>"
912 unsigned32 addr = EP + disp8;
913 unsigned32 result = load_mem (addr, 4);
915 TRACE_LD (addr, result);
918 rrrrr!0,0000110,dddd:IV:::sld.bu
921 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
922 "sld.bu <disp4>[ep], r<reg2>"
924 unsigned32 addr = EP + disp4;
925 unsigned32 result = load_mem (addr, 1);
928 result = EXTEND8 (result);
930 TRACE_LD_NAME ("sld.b", addr, result);
935 TRACE_LD (addr, result);
939 rrrrr!0,0000111,dddd:IV:::sld.hu
942 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
943 "sld.hu <disp5>[ep], r<reg2>"
945 unsigned32 addr = EP + disp5;
946 unsigned32 result = load_mem (addr, 2);
949 result = EXTEND16 (result);
951 TRACE_LD_NAME ("sld.h", addr, result);
956 TRACE_LD (addr, result);
962 rrrrr,0111,ddddddd:IV:::sst.b
963 "sst.b r<reg2>, <disp7>[ep]"
965 COMPAT_1 (OP_380 ());
968 rrrrr,1001,ddddddd:IV:::sst.h
969 "sst.h r<reg2>, <disp8>[ep]"
971 COMPAT_1 (OP_480 ());
974 rrrrr,1010,dddddd,1:IV:::sst.w
975 "sst.w r<reg2>, <disp8>[ep]"
977 COMPAT_1 (OP_501 ());
983 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
984 "st.b r<reg2>, <disp16>[r<reg1>]"
986 COMPAT_2 (OP_740 ());
989 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
990 "st.h r<reg2>, <disp16>[r<reg1>]"
992 COMPAT_2 (OP_760 ());
995 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
996 "st.w r<reg2>, <disp16>[r<reg1>]"
998 COMPAT_2 (OP_10760 ());
1004 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1005 "stsr s<regID>, r<reg2>"
1007 TRACE_ALU_INPUT1 (SR[regID]);
1008 GR[reg2] = SR[regID];
1009 TRACE_ALU_RESULT (GR[reg2]);
1015 rrrrr,001101,RRRRR:I:::sub
1016 "sub r<reg1>, r<reg2>"
1018 COMPAT_1 (OP_1A0 ());
1024 rrrrr,001100,RRRRR:I:::subr
1025 "subr r<reg1>, r<reg2>"
1027 COMPAT_1 (OP_180 ());
1033 00000000010,RRRRR:I:::switch
1040 trace_input ("switch", OP_REG, 0);
1041 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1042 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1043 trace_output (OP_REG);
1048 00000000101,RRRRR:I:::sxb
1053 TRACE_ALU_INPUT1 (GR[reg1]);
1054 GR[reg1] = EXTEND8 (GR[reg1]);
1055 TRACE_ALU_RESULT (GR[reg1]);
1059 00000000111,RRRRR:I:::sxh
1064 TRACE_ALU_INPUT1 (GR[reg1]);
1065 GR[reg1] = EXTEND16 (GR[reg1]);
1066 TRACE_ALU_RESULT (GR[reg1]);
1072 00000111111,iiiii + 0000000100000000:X:::trap
1075 COMPAT_2 (OP_10007E0 ());
1081 rrrrr,001011,RRRRR:I:::tst
1082 "tst r<reg1>, r<reg2>"
1084 COMPAT_1 (OP_160 ());
1090 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1091 "tst1 <bit3>, <disp16>[r<reg1>]"
1093 COMPAT_2 (OP_C7C0 ());
1096 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1099 "tst1 r<reg2>, [r<reg1>]"
1101 COMPAT_2 (OP_E607E0 ());
1107 rrrrr,001001,RRRRR:I:::xor
1108 "xor r<reg1>, r<reg2>"
1110 COMPAT_1 (OP_120 ());
1116 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1117 "xori <uimm16>, r<reg1>, r<reg2>"
1119 COMPAT_2 (OP_6A0 ());
1125 00000000100,RRRRR:I:::zxb
1130 TRACE_ALU_INPUT1 (GR[reg1]);
1131 GR[reg1] = GR[reg1] & 0xff;
1132 TRACE_ALU_RESULT (GR[reg1]);
1136 00000000110,RRRRR:I:::zxh
1141 TRACE_ALU_INPUT1 (GR[reg1]);
1142 GR[reg1] = GR[reg1] & 0xffff;
1143 TRACE_ALU_RESULT (GR[reg1]);
1147 // Right field must be zero so that it doesn't clash with DIVH
1148 // Left field must be non-zero so that it doesn't clash with SWITCH
1149 11111,000010,00000:I:::break
1151 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1157 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1159 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1164 signed32 divide_this;
1165 boolean overflow = false;
1168 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1170 divide_by = EXTEND16 (State.regs[ reg1 ]);
1171 divide_this = State.regs[ reg2 ];
1173 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1175 State.regs[ reg2 ] = quotient;
1176 State.regs[ reg3 ] = remainder;
1178 /* Set condition codes. */
1179 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1181 if (overflow) PSW |= PSW_OV;
1182 if (quotient == 0) PSW |= PSW_Z;
1183 if (quotient < 0) PSW |= PSW_S;
1185 trace_output (OP_IMM_REG_REG_REG);
1191 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1193 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1198 signed32 divide_this;
1199 boolean overflow = false;
1202 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1204 divide_by = State.regs[ reg1 ] & 0xffff;
1205 divide_this = State.regs[ reg2 ];
1207 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1209 State.regs[ reg2 ] = quotient;
1210 State.regs[ reg3 ] = remainder;
1212 /* Set condition codes. */
1213 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1215 if (overflow) PSW |= PSW_OV;
1216 if (quotient == 0) PSW |= PSW_Z;
1217 if (quotient & 0x80000000) PSW |= PSW_S;
1219 trace_output (OP_IMM_REG_REG_REG);
1225 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1227 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1232 signed32 divide_this;
1233 boolean overflow = false;
1236 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1238 divide_by = State.regs[ reg1 ];
1239 divide_this = State.regs[ reg2 ];
1241 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1243 State.regs[ reg2 ] = quotient;
1244 State.regs[ reg3 ] = remainder;
1246 /* Set condition codes. */
1247 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1249 if (overflow) PSW |= PSW_OV;
1250 if (quotient == 0) PSW |= PSW_Z;
1251 if (quotient < 0) PSW |= PSW_S;
1253 trace_output (OP_IMM_REG_REG_REG);
1259 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1261 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1266 signed32 divide_this;
1267 boolean overflow = false;
1270 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1272 divide_by = State.regs[ reg1 ];
1273 divide_this = State.regs[ reg2 ];
1275 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1277 State.regs[ reg2 ] = quotient;
1278 State.regs[ reg3 ] = remainder;
1280 /* Set condition codes. */
1281 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1283 if (overflow) PSW |= PSW_OV;
1284 if (quotient == 0) PSW |= PSW_Z;
1285 if (quotient & 0x80000000) PSW |= PSW_S;
1287 trace_output (OP_IMM_REG_REG_REG);
1293 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1295 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1297 COMPAT_2 (OP_18007E0 ());
1303 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1305 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1307 COMPAT_2 (OP_18207E0 ());
1313 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1315 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1317 COMPAT_2 (OP_1C007E0 ());
1323 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1325 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1327 COMPAT_2 (OP_1C207E0 ());
1333 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1340 trace_input ("pushml", OP_PUSHPOP3, 0);
1342 /* Store the registers with lower number registers being placed at
1343 higher addresses. */
1345 for (i = 0; i < 15; i++)
1346 if ((OP[3] & (1 << type3_regs[ i ])))
1349 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1352 if (OP[3] & (1 << 3))
1356 store_mem (SP & ~ 3, 4, PSW);
1359 if (OP[3] & (1 << 19))
1363 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1365 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1366 store_mem ( SP & ~ 3, 4, FEPSW);
1370 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1371 store_mem ( SP & ~ 3, 4, EIPSW);
1375 trace_output (OP_PUSHPOP2);
1381 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1385 COMPAT_2 (OP_307E0 ());
1391 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1395 COMPAT_2 (OP_107F0 ());
1401 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1405 COMPAT_2 (OP_307F0 ());