1 :option::insn-bit-size:16
5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
7 :option::format-names:XI,XII,XIII
9 # start-sanitize-v850eq
10 :option::format-names:XIV,XV
12 :option::format-names:Z
17 # start-sanitize-v850e
18 :option::multi-sim:true
22 # start-sanitize-v850eq
23 :option::multi-sim:true
24 :model::v850eq:v850eq:
31 :cache::unsigned:reg1:RRRRR:(RRRRR)
32 :cache::unsigned:reg2:rrrrr:(rrrrr)
33 :cache::unsigned:reg3:wwwww:(wwwww)
34 :cache::unsigned:regID:rrrrr:(rrrrr)
36 :cache::unsigned:disp4:dddd:(dddd)
37 # start-sanitize-v850e
38 :cache::unsigned:disp5:dddd:(dddd << 1)
40 :cache::unsigned:disp7:ddddddd:ddddddd
41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
50 :cache::unsigned:imm6:iiiiii:iiiiii
51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
52 # start-sanitize-v850eq
53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
57 # start-sanitize-v850e
58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
62 :cache::unsigned:vector:iiiii:iiiii
64 # start-sanitize-v850e
65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
69 :cache::unsigned:bit3:bbb:bbb
72 // What do we do with an illegal instruction?
75 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
77 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
84 rrrrr,001110,RRRRR:I:::add
85 "add r<reg1>, r<reg2>"
90 rrrrr,010010,iiiii:II:::add
99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
100 "addi <imm16>, r<reg1>, r<reg2>"
102 COMPAT_2 (OP_600 ());
108 rrrrr,001010,RRRRR:I:::and
109 "and r<reg1>, r<reg2>"
111 COMPAT_1 (OP_140 ());
117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
118 "andi <imm16>, r<reg1>, r<reg2>"
120 COMPAT_2 (OP_6C0 ());
126 // ddddd,1011,ddd,cccc:III:::Bcond
129 ddddd,1011,ddd,0000:III:::bv
132 COMPAT_1 (OP_580 ());
135 ddddd,1011,ddd,0001:III:::bl
138 COMPAT_1 (OP_581 ());
141 ddddd,1011,ddd,0010:III:::be
144 COMPAT_1 (OP_582 ());
147 ddddd,1011,ddd,0011:III:::bnh
150 COMPAT_1 (OP_583 ());
153 ddddd,1011,ddd,0100:III:::bn
156 COMPAT_1 (OP_584 ());
159 ddddd,1011,ddd,0101:III:::br
162 COMPAT_1 (OP_585 ());
165 ddddd,1011,ddd,0110:III:::blt
168 COMPAT_1 (OP_586 ());
171 ddddd,1011,ddd,0111:III:::ble
174 COMPAT_1 (OP_587 ());
177 ddddd,1011,ddd,1000:III:::bnv
180 COMPAT_1 (OP_588 ());
183 ddddd,1011,ddd,1001:III:::bnl
186 COMPAT_1 (OP_589 ());
189 ddddd,1011,ddd,1010:III:::bne
192 COMPAT_1 (OP_58A ());
195 ddddd,1011,ddd,1011:III:::bh
198 COMPAT_1 (OP_58B ());
201 ddddd,1011,ddd,1100:III:::bp
204 COMPAT_1 (OP_58C ());
207 ddddd,1011,ddd,1101:III:::bsa
210 COMPAT_1 (OP_58D ());
213 ddddd,1011,ddd,1110:III:::bge
216 COMPAT_1 (OP_58E ());
219 ddddd,1011,ddd,1111:III:::bgt
222 COMPAT_1 (OP_58F ());
227 // start-sanitize-v850e
229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
231 // start-sanitize-v850eq
233 // end-sanitize-v850eq
234 "bsh r<reg2>, r<reg3>"
236 COMPAT_2 (OP_34207E0 ());
241 // end-sanitize-v850e
242 // start-sanitize-v850e
244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
246 // start-sanitize-v850eq
248 // end-sanitize-v850eq
251 COMPAT_2 (OP_34007E0 ());
256 // end-sanitize-v850e
257 // start-sanitize-v850e
259 0000001000,iiiiii:II:::callt
261 // start-sanitize-v850eq
263 // end-sanitize-v850eq
266 COMPAT_1 (OP_200 ());
271 // end-sanitize-v850e
273 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
274 "clr1 <bit3>, <disp16>[r<reg1>]"
276 COMPAT_2 (OP_87C0 ());
279 // start-sanitize-v850e
280 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
282 // start-sanitize-v850eq
284 // end-sanitize-v850eq
285 "clr1 r<reg2>, [r<reg1>]"
287 COMPAT_2 (OP_E407E0 ());
292 // end-sanitize-v850e
293 // start-sanitize-v850e
295 0000011111100000 + 0000000101000100:X:::ctret
297 // start-sanitize-v850eq
299 // end-sanitize-v850eq
302 COMPAT_2 (OP_14407E0 ());
307 // end-sanitize-v850e
308 // start-sanitize-v850e
310 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
312 // start-sanitize-v850eq
314 // end-sanitize-v850eq
315 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
317 COMPAT_2 (OP_32007E0 ());
320 // end-sanitize-v850e
321 // start-sanitize-v850e
322 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
324 // start-sanitize-v850eq
326 // end-sanitize-v850eq
327 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
329 COMPAT_2 (OP_30007E0 ());
334 // end-sanitize-v850e
336 rrrrr,001111,RRRRR:I:::cmp
337 "cmp r<reg1>, r<reg2>"
339 COMPAT_1 (OP_1E0 ());
342 rrrrr,010011,iiiii:II:::cmp
343 "cmp <imm5>, r<reg2>"
345 COMPAT_1 (OP_260 ());
351 0000011111100000 + 0000000101100000:X:::di
354 COMPAT_2 (OP_16007E0 ());
359 // start-sanitize-v850e
361 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
362 // "dispose <imm5>, <list12>"
363 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
365 // start-sanitize-v850eq
367 // end-sanitize-v850eq
368 "dispose <imm5>, <list12>":RRRRR == 0
369 "dispose <imm5>, <list12>, [reg1]"
371 COMPAT_2 (OP_640 ());
376 // end-sanitize-v850e
377 // start-sanitize-v850e
379 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
381 "div r<reg1>, r<reg2>, r<reg3>"
383 COMPAT_2 (OP_2C007E0 ());
389 // end-sanitize-v850e
391 rrrrr!0,000010,RRRRR!0:I:::divh
392 "divh r<reg1>, r<reg2>"
397 // start-sanitize-v850e
398 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
400 "divh r<reg1>, r<reg2>, r<reg3>"
402 COMPAT_2 (OP_28007E0 ());
407 // end-sanitize-v850e
408 // start-sanitize-v850e
410 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
412 "divhu r<reg1>, r<reg2>, r<reg3>"
414 COMPAT_2 (OP_28207E0 ());
419 // end-sanitize-v850e
420 // start-sanitize-v850e
422 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
424 "divu r<reg1>, r<reg2>, r<reg3>"
426 COMPAT_2 (OP_2C207E0 ());
431 // end-sanitize-v850e
433 1000011111100000 + 0000000101100000:X:::ei
436 COMPAT_2 (OP_16087E0 ());
442 0000011111100000 + 0000000100100000:X:::halt
445 COMPAT_2 (OP_12007E0 ());
450 // start-sanitize-v850e
452 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
454 // start-sanitize-v850eq
456 // end-sanitize-v850eq
457 "hsw r<reg2>, r<reg3>"
459 COMPAT_2 (OP_34407E0 ());
464 // end-sanitize-v850e
466 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
467 "jarl <disp22>, r<reg2>"
469 COMPAT_2 (OP_780 ());
475 00000000011,RRRRR:I:::jmp
479 trace_input ("jmp", OP_REG, 0);
480 nia = State.regs[ reg1 ];
481 trace_output (OP_REG);
487 0000011110,dddddd + ddddddddddddddd,0:V:::jr
490 COMPAT_2 (OP_780 ());
496 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
497 "ld.b <disp16>[r<reg1>, r<reg2>"
499 COMPAT_2 (OP_700 ());
502 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
503 "ld.h <disp16>[r<reg1>], r<reg2>"
505 COMPAT_2 (OP_720 ());
508 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
509 "ld.w <disp16>[r<reg1>], r<reg2>"
511 COMPAT_2 (OP_10720 ());
514 // start-sanitize-v850e
515 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
517 // start-sanitize-v850eq
519 // end-sanitize-v850eq
520 "ld.bu <disp16>[r<reg1>], r<reg2>"
522 COMPAT_2 (OP_10780 ());
525 // end-sanitize-v850e
526 // start-sanitize-v850e
527 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
529 // start-sanitize-v850eq
531 // end-sanitize-v850eq
532 "ld.hu <disp16>[r<reg1>], r<reg2>"
534 COMPAT_2 (OP_107E0 ());
538 // end-sanitize-v850e
540 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
541 //"ldsr r<reg2>, r<regID>"
543 // COMPAT_2 (OP_2007E0 ());
545 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
546 "ldsr r<reg1>, r<regID>"
548 COMPAT_2 (OP_2007E0 ());
554 rrrrr!0,000000,RRRRR:I:::mov
555 "mov r<reg1>, r<reg2>"
560 rrrrr!0,010000,iiiii:II:::mov
561 "mov <imm5>, r<reg2>"
563 COMPAT_1 (OP_200 ());
566 // start-sanitize-v850e
567 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
569 // start-sanitize-v850eq
571 // end-sanitize-v850eq
572 "mov <imm32>, r<reg1>"
574 COMPAT_2 (OP_620 ());
579 // end-sanitize-v850e
581 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
582 "movea <imm16>, r<reg1>, r<reg2>"
584 COMPAT_2 (OP_620 ());
590 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
591 "movhi <imm16>, r<reg1>, r<reg2>"
593 COMPAT_2 (OP_640 ());
598 // start-sanitize-v850e
600 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
602 // start-sanitize-v850eq
604 // end-sanitize-v850eq
605 "mul r<reg1>, r<reg2>, r<reg3>"
607 COMPAT_2 (OP_22007E0 ());
610 // end-sanitize-v850e
611 // start-sanitize-v850e
612 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
614 // start-sanitize-v850eq
616 // end-sanitize-v850eq
617 "mul <imm9>, r<reg2>, r<reg3>"
619 COMPAT_2 (OP_24007E0 ());
624 // end-sanitize-v850e
626 rrrrr!0,000111,RRRRR:I:::mulh
627 "mulh r<reg1>, r<reg2>"
632 rrrrr!0,010111,iiiii:II:::mulh
633 "mulh <imm5>, r<reg2>"
635 COMPAT_1 (OP_2E0 ());
641 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
642 "mulhi <imm16>, r<reg1>, r<reg2>"
644 COMPAT_2 (OP_6E0 ());
649 // start-sanitize-v850e
651 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
653 // start-sanitize-v850eq
655 // end-sanitize-v850eq
656 "mulu r<reg1>, r<reg2>, r<reg3>"
658 COMPAT_2 (OP_22207E0 ());
661 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
663 // start-sanitize-v850eq
665 // end-sanitize-v850eq
666 "mulu <imm9>, r<reg2>, r<reg3>"
668 COMPAT_2 (OP_24207E0 ());
673 // end-sanitize-v850e
675 0000000000000000:I:::nop
684 rrrrr,000001,RRRRR:I:::not
685 "not r<reg1>, r<reg2>"
693 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
694 "not1 <bit3>, <disp16>[r<reg1>]"
696 COMPAT_2 (OP_47C0 ());
699 // start-sanitize-v850e
700 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
702 // start-sanitize-v850eq
704 // end-sanitize-v850eq
705 "not1 r<reg2>, r<reg1>"
707 COMPAT_2 (OP_E207E0 ());
712 // end-sanitize-v850e
714 rrrrr,001000,RRRRR:I:::or
715 "or r<reg1>, r<reg2>"
717 COMPAT_1 (OP_100 ());
723 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
724 "ori <imm16>, r<reg1>, r<reg2>"
726 COMPAT_2 (OP_680 ());
731 // start-sanitize-v850e
733 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
735 // start-sanitize-v850eq
737 // end-sanitize-v850eq
738 "prepare <list12>, <imm5>"
743 trace_input ("prepare", OP_PUSHPOP1, 0);
745 /* Store the registers with lower number registers being placed at
747 for (i = 0; i < 12; i++)
748 if ((OP[3] & (1 << type1_regs[ i ])))
751 store_mem (SP, 4, State.regs[ 20 + i ]);
754 SP -= (OP[3] & 0x3e) << 1;
756 trace_output (OP_PUSHPOP1);
760 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
762 // start-sanitize-v850eq
764 // end-sanitize-v850eq
765 "prepare <list12>, <imm5>, sp"
767 COMPAT_2 (OP_30780 ());
770 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
772 // start-sanitize-v850eq
774 // end-sanitize-v850eq
775 "prepare <list12>, <imm5>, <uimm16>"
777 COMPAT_2 (OP_B0780 ());
780 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
782 // start-sanitize-v850eq
784 // end-sanitize-v850eq
785 "prepare <list12>, <imm5>, <uimm16>"
787 COMPAT_2 (OP_130780 ());
790 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
792 // start-sanitize-v850eq
794 // end-sanitize-v850eq
795 "prepare <list12>, <imm5>, <uimm32>"
797 COMPAT_2 (OP_1B0780 ());
802 // end-sanitize-v850e
804 0000011111100000 + 0000000101000000:X:::reti
807 COMPAT_2 (OP_14007E0 ());
813 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
814 "sar r<reg1>, r<reg2>"
816 COMPAT_2 (OP_A007E0 ());
819 rrrrr,010101,iiiii:II:::sar
820 "sar <imm5>, r<reg2>"
822 COMPAT_1 (OP_2A0 ());
827 // start-sanitize-v850e
829 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
831 // start-sanitize-v850eq
833 // end-sanitize-v850eq
834 "sasf <cccc>, r<reg2>"
836 COMPAT_2 (OP_20007E0 ());
842 // end-sanitize-v850e
844 rrrrr!0,000110,RRRRR:I:::satadd
845 "satadd r<reg1>, r<reg2>"
850 rrrrr!0,010001,iiiii:II:::satadd
851 "satadd <imm5>, r<reg2>"
853 COMPAT_1 (OP_220 ());
859 rrrrr!0,000101,RRRRR:I:::satsub
860 "satsub r<reg1>, r<reg2>"
868 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
869 "satsubi <imm16>, r<reg1>, r<reg2>"
871 COMPAT_2 (OP_660 ());
877 rrrrr!0,000100,RRRRR:I:::satsubr
878 "satsubr r<reg1>, r<reg2>"
886 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
887 "setf <cccc>, r<reg2>"
889 COMPAT_2 (OP_7E0 ());
895 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
896 "set1 <bit3>, <disp16>[r<reg1>]"
898 COMPAT_2 (OP_7C0 ());
901 // start-sanitize-v850e
902 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
904 // start-sanitize-v850eq
906 // end-sanitize-v850eq
907 "set1 r<reg2>, [r<reg1>]"
909 COMPAT_2 (OP_E007E0 ());
914 // end-sanitize-v850e
916 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
917 "shl r<reg1>, r<reg2>"
919 COMPAT_2 (OP_C007E0 ());
922 rrrrr,010110,iiiii:II:::shl
923 "shl <imm5>, r<reg2>"
925 COMPAT_1 (OP_2C0 ());
931 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
932 "shr r<reg1>, r<reg2>"
934 COMPAT_2 (OP_8007E0 ());
937 rrrrr,010100,iiiii:II:::shr
938 "shr <imm5>, r<reg2>"
940 COMPAT_1 (OP_280 ());
946 rrrrr,0110,ddddddd:IV:::sld.b
947 "sld.b <disp7>[ep], r<reg2>"
949 COMPAT_1 (OP_300 ());
952 rrrrr,1000,ddddddd:IV:::sld.h
953 "sld.h <disp8>[ep], r<reg2>"
955 COMPAT_1 (OP_400 ());
958 rrrrr,1010,dddddd,0:IV:::sld.w
959 "sld.w <disp8>[ep], r<reg2>"
961 COMPAT_1 (OP_500 ());
964 // start-sanitize-v850e
965 rrrrr!0,0000110,dddd:IV:::sld.bu
966 "sld.bu <disp4>[ep], r<reg2>"
968 unsigned long result;
971 result = load_mem (State.regs[30] + disp4, 1);
973 /* start-sanitize-v850eq */
975 trace_input ("sld.b", OP_LOAD16, 1);
977 State.regs[ reg2 ] = EXTEND8 (result);
979 /* end-sanitize-v850eq */
980 trace_input ("sld.bu", OP_LOAD16, 1);
981 State.regs[ reg2 ] = result;
982 /* start-sanitize-v850eq */
984 /* end-sanitize-v850eq */
985 trace_output (OP_LOAD16);
988 // end-sanitize-v850e
989 // start-sanitize-v850e
990 rrrrr!0,0000111,dddd:IV:::sld.hu
991 "sld.hu <disp5>[ep], r<reg2>"
996 // end-sanitize-v850e
1000 rrrrr,0111,ddddddd:IV:::sst.b
1001 "sst.b r<reg2>, <disp7>[ep]"
1003 COMPAT_1 (OP_380 ());
1006 rrrrr,1001,ddddddd:IV:::sst.h
1007 "sst.h r<reg2>, <disp8>[ep]"
1009 COMPAT_1 (OP_480 ());
1012 rrrrr,1010,dddddd,1:IV:::sst.w
1013 "sst.w r<reg2>, <disp8>[ep]"
1015 COMPAT_1 (OP_501 ());
1021 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1022 "st.b r<reg2>, <disp16>[r<reg1>]"
1024 COMPAT_2 (OP_740 ());
1027 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1028 "st.h r<reg2>, <disp16>[r<reg1>]"
1030 COMPAT_2 (OP_760 ());
1033 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1034 "st.w r<reg2>, <disp16>[r<reg1>]"
1036 COMPAT_2 (OP_10760 ());
1042 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1043 //"stsr r<regID>, r<reg2>"
1045 // COMPAT_2 (OP_4007E0 ());
1047 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1048 "stsr r<regID>, r<reg1>"
1050 COMPAT_2 (OP_4007E0 ());
1056 rrrrr,001101,RRRRR:I:::sub
1057 "sub r<reg1>, r<reg2>"
1059 COMPAT_1 (OP_1A0 ());
1065 rrrrr,001100,RRRRR:I:::subr
1066 "subr r<reg1>, r<reg2>"
1068 COMPAT_1 (OP_180 ());
1073 // start-sanitize-v850e
1075 00000000010,RRRRR:I:::switch
1077 // start-sanitize-v850eq
1079 // end-sanitize-v850eq
1082 COMPAT_1 (OP_40 ());
1084 // end-sanitize-v850e
1088 // start-sanitize-v850e
1090 00000000101,RRRRR:I:::sxb
1092 // start-sanitize-v850eq
1094 // end-sanitize-v850eq
1097 COMPAT_1 (OP_A0 ());
1102 // end-sanitize-v850e
1103 // start-sanitize-v850e
1105 00000000111,RRRRR:I:::sxh
1107 // start-sanitize-v850eq
1109 // end-sanitize-v850eq
1112 COMPAT_1 (OP_E0 ());
1117 // end-sanitize-v850e
1119 00000111111,iiiii + 0000000100000000:X:::trap
1122 COMPAT_2 (OP_10007E0 ());
1128 rrrrr,001011,RRRRR:I:::tst
1129 "tst r<reg1>, r<reg2>"
1131 COMPAT_1 (OP_160 ());
1137 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1138 "tst1 <bit3>, <disp16>[r<reg1>]"
1140 COMPAT_2 (OP_C7C0 ());
1143 // start-sanitize-v850e
1144 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1146 // start-sanitize-v850eq
1148 // end-sanitize-v850eq
1149 "tst1 r<reg2>, [r<reg1>]"
1151 COMPAT_2 (OP_E607E0 ());
1156 // end-sanitize-v850e
1158 rrrrr,001001,RRRRR:I:::xor
1159 "xor r<reg1>, r<reg2>"
1161 COMPAT_1 (OP_120 ());
1167 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1168 "xori <imm16>, r<reg1>, r<reg2>"
1170 COMPAT_2 (OP_6A0 ());
1175 // start-sanitize-v850e
1177 00000000100,RRRRR:I:::zxb
1179 // start-sanitize-v850eq
1181 // end-sanitize-v850eq
1186 trace_input ("zxb", OP_REG, 0);
1188 State.regs[ OP[0] ] &= 0xff;
1190 trace_output (OP_REG);
1195 // end-sanitize-v850e
1196 // start-sanitize-v850e
1198 00000000110,RRRRR:I:::zxh
1200 // start-sanitize-v850eq
1202 // end-sanitize-v850eq
1207 trace_input ("zxh", OP_REG, 0);
1209 State.regs[ OP[0] ] &= 0xffff;
1211 trace_output (OP_REG);
1216 // end-sanitize-v850e
1217 // Special - breakpoint
1218 // 1111111111111111:Z:::breakpoint
1220 // COMPAT_2 (OP_FFFF ());
1224 // start-sanitize-v850eq
1226 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1228 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1233 signed32 divide_this;
1234 boolean overflow = false;
1237 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1239 divide_by = EXTEND16 (State.regs[ reg1 ]);
1240 divide_this = State.regs[ reg2 ];
1242 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1244 State.regs[ reg2 ] = quotient;
1245 State.regs[ reg3 ] = remainder;
1247 /* Set condition codes. */
1248 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1250 if (overflow) PSW |= PSW_OV;
1251 if (quotient == 0) PSW |= PSW_Z;
1252 if (quotient < 0) PSW |= PSW_S;
1254 trace_output (OP_IMM_REG_REG_REG);
1260 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1262 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1267 signed32 divide_this;
1268 boolean overflow = false;
1271 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1273 divide_by = State.regs[ reg1 ] & 0xffff;
1274 divide_this = State.regs[ reg2 ];
1276 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1278 State.regs[ reg2 ] = quotient;
1279 State.regs[ reg3 ] = remainder;
1281 /* Set condition codes. */
1282 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1284 if (overflow) PSW |= PSW_OV;
1285 if (quotient == 0) PSW |= PSW_Z;
1286 if (quotient & 0x80000000) PSW |= PSW_S;
1288 trace_output (OP_IMM_REG_REG_REG);
1294 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1296 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1301 signed32 divide_this;
1302 boolean overflow = false;
1305 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1307 divide_by = State.regs[ reg1 ];
1308 divide_this = State.regs[ reg2 ];
1310 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1312 State.regs[ reg2 ] = quotient;
1313 State.regs[ reg3 ] = remainder;
1315 /* Set condition codes. */
1316 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1318 if (overflow) PSW |= PSW_OV;
1319 if (quotient == 0) PSW |= PSW_Z;
1320 if (quotient < 0) PSW |= PSW_S;
1322 trace_output (OP_IMM_REG_REG_REG);
1328 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1330 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1335 signed32 divide_this;
1336 boolean overflow = false;
1339 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1341 divide_by = State.regs[ reg1 ];
1342 divide_this = State.regs[ reg2 ];
1344 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1346 State.regs[ reg2 ] = quotient;
1347 State.regs[ reg3 ] = remainder;
1349 /* Set condition codes. */
1350 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1352 if (overflow) PSW |= PSW_OV;
1353 if (quotient == 0) PSW |= PSW_Z;
1354 if (quotient & 0x80000000) PSW |= PSW_S;
1356 trace_output (OP_IMM_REG_REG_REG);
1362 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1364 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1366 COMPAT_2 (OP_18007E0 ());
1372 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1374 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1376 COMPAT_2 (OP_18207E0 ());
1382 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1384 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1386 COMPAT_2 (OP_1C007E0 ());
1392 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1394 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1396 COMPAT_2 (OP_1C207E0 ());
1402 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1409 trace_input ("pushml", OP_PUSHPOP3, 0);
1411 /* Store the registers with lower number registers being placed at
1412 higher addresses. */
1414 for (i = 0; i < 15; i++)
1415 if ((OP[3] & (1 << type3_regs[ i ])))
1418 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1421 if (OP[3] & (1 << 3))
1425 store_mem (SP & ~ 3, 4, PSW);
1428 if (OP[3] & (1 << 19))
1432 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1434 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1435 store_mem ( SP & ~ 3, 4, FEPSW);
1439 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1440 store_mem ( SP & ~ 3, 4, EIPSW);
1444 trace_output (OP_PUSHPOP2);
1450 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1454 COMPAT_2 (OP_307E0 ());
1460 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1464 COMPAT_2 (OP_107F0 ());
1470 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1474 COMPAT_2 (OP_307F0 ());
1478 // end-sanitize-v850eq