sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   abort ();
  76 }
  77
  78
  79
  80 // Add
  81
  82 rrrrr,001110,RRRRR:I:::add
  83 "add r<reg1>, r<reg2>"
  84 {
  85   COMPAT_1 (OP_1C0 ());
  86 }
  87
  88 rrrrr,010010,iiiii:II:::add
  89 "add <imm5>,r<reg2>"
  90 {
  91   COMPAT_1 (OP_240 ());
  92 }
  93
  94
  95
  96 // ADDI
  97 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
  98 "addi <imm16>, r<reg1>, r<reg2>"
  99 {
 100   COMPAT_2 (OP_600 ());
 101 }
 102
 103
 104
 105 // AND
 106 rrrrr,001010,RRRRR:I:::and
 107 "and r<reg1>, r<reg2>"
 108 {
 109   COMPAT_1 (OP_140 ());
 110 }
 111
 112
 113
 114 // ANDI
 115 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 116 "andi <imm16>, r<reg1>, r<reg2>"
 117 {
 118   COMPAT_2 (OP_6C0 ());
 119 }
 120
 121
 122
 123 // Bcond
 124 // ddddd,1011,ddd,cccc:III:::Bcond
 125 // "b<cond> disp9"
 126
 127 ddddd,1011,ddd,0000:III:::bv
 128 "bv <disp9>"
 129 {
 130   COMPAT_1 (OP_580 ());
 131 }
 132
 133 ddddd,1011,ddd,0001:III:::bl
 134 "bl <disp9>"
 135 {
 136   COMPAT_1 (OP_581 ());
 137 }
 138
 139 ddddd,1011,ddd,0010:III:::be
 140 "be <disp9>"
 141 {
 142   COMPAT_1 (OP_582 ());
 143 }
 144
 145 ddddd,1011,ddd,0011:III:::bnh
 146 "bnh <disp9>"
 147 {
 148   COMPAT_1 (OP_583 ());
 149 }
 150
 151 ddddd,1011,ddd,0100:III:::bn
 152 "bn <disp9>"
 153 {
 154   COMPAT_1 (OP_584 ());
 155 }
 156
 157 ddddd,1011,ddd,0101:III:::br
 158 "br <disp9>"
 159 {
 160   COMPAT_1 (OP_585 ());
 161 }
 162
 163 ddddd,1011,ddd,0110:III:::blt
 164 "blt <disp9>"
 165 {
 166   COMPAT_1 (OP_586 ());
 167 }
 168
 169 ddddd,1011,ddd,0111:III:::ble
 170 "ble <disp9>"
 171 {
 172   COMPAT_1 (OP_587 ());
 173 }
 174
 175 ddddd,1011,ddd,1000:III:::bnv
 176 "bnv <disp9>"
 177 {
 178   COMPAT_1 (OP_588 ());
 179 }
 180
 181 ddddd,1011,ddd,1001:III:::bnl
 182 "bnl <disp9>"
 183 {
 184   COMPAT_1 (OP_589 ());
 185 }
 186
 187 ddddd,1011,ddd,1010:III:::bne
 188 "bne <disp9>"
 189 {
 190   COMPAT_1 (OP_58A ());
 191 }
 192
 193 ddddd,1011,ddd,1011:III:::bh
 194 "bh <disp9>"
 195 {
 196   COMPAT_1 (OP_58B ());
 197 }
 198
 199 ddddd,1011,ddd,1100:III:::bp
 200 "bp <disp9>"
 201 {
 202   COMPAT_1 (OP_58C ());
 203 }
 204
 205 ddddd,1011,ddd,1101:III:::bsa
 206 "bsa <disp9>"
 207 {
 208   COMPAT_1 (OP_58D ());
 209 }
 210
 211 ddddd,1011,ddd,1110:III:::bge
 212 "bge <disp9>"
 213 {
 214   COMPAT_1 (OP_58E ());
 215 }
 216
 217 ddddd,1011,ddd,1111:III:::bgt
 218 "bgt <disp9>"
 219 {
 220   COMPAT_1 (OP_58F ());
 221 }
 222
 223
 224
 225 // start-sanitize-v850e
 226 // BSH
 227 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 228 *v850e
 229 "bsh r<reg2>, r<reg3>"
 230 {
 231   COMPAT_2 (OP_34207E0 ());
 232 }
 233
 234
 235
 236 // end-sanitize-v850e
 237 // start-sanitize-v850e
 238 // BSW
 239 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 240 *v850e
 241 "bsw r<reg2>, reg3>"
 242 {
 243   COMPAT_2 (OP_34007E0 ());
 244 }
 245
 246
 247
 248 // end-sanitize-v850e
 249 // CALLT
 250 0000001000,iiiiii:II:::callt
 251 "callt <imm6>"
 252 {
 253   COMPAT_1 (OP_200 ());
 254 }
 255
 256
 257
 258 // CLR1
 259 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 260 "clr1 <bit3>, <disp16>[r<reg1>]"
 261 {
 262   COMPAT_2 (OP_87C0 ());
 263 }
 264
 265 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 266 "clr1 r<reg2>, [r<reg1>]"
 267 {
 268   COMPAT_2 (OP_E407E0 ());
 269 }
 270
 271
 272
 273 // CTRET
 274 0000011111100000 + 0000000101000100:X:::ctret
 275 "ctret"
 276 {
 277   COMPAT_2 (OP_14407E0 ());
 278 }
 279
 280
 281
 282 // start-sanitize-v850e
 283 // CMOV
 284 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 285 *v850e
 286 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 287 {
 288   COMPAT_2 (OP_32007E0 ());
 289 }
 290
 291 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 292 *v850e
 293 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 294 {
 295   COMPAT_2 (OP_30007E0 ());
 296 }
 297
 298
 299
 300 // end-sanitize-v850e
 301 // CMP
 302 rrrrr,001111,RRRRR:I:::cmp
 303 "cmp r<reg1>, r<reg2>"
 304 {
 305   COMPAT_1 (OP_1E0 ());
 306 }
 307
 308 rrrrr,010011,iiiii:II:::cmp
 309 "cmp <imm5>, r<reg2>"
 310 {
 311   COMPAT_1 (OP_260 ());
 312 }
 313
 314
 315
 316 // DI
 317 0000011111100000 + 0000000101100000:X:::di
 318 "di"
 319 {
 320   COMPAT_2 (OP_16007E0 ());
 321 }
 322
 323
 324
 325 // start-sanitize-v850e
 326 // DISPOSE
 327 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 328 // "dispose <imm5>, <list12>"
 329 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 330 *v850e
 331 "dispose <imm5>, <list12>":RRRRR == 0
 332 "dispose <imm5>, <list12>, [reg1]"
 333 {
 334   COMPAT_2 (OP_640 ());
 335 }
 336
 337
 338
 339 // end-sanitize-v850e
 340 // start-sanitize-v850e
 341 // DIV
 342 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 343 *v850e
 344 "div r<reg1>, r<reg2>, r<reg3>"
 345 {
 346   COMPAT_2 (OP_2C007E0 ());
 347 }
 348
 349
 350
 351
 352 // end-sanitize-v850e
 353 // DIVH
 354 rrrrr!0,000010,RRRRR!0:I:::divh
 355 "divh r<reg1>, r<reg2>"
 356 {
 357   COMPAT_1 (OP_40 ());
 358 }
 359
 360 // start-sanitize-v850e
 361 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 362 *v850e
 363 "divh r<reg1>, r<reg2>, r<reg3>"
 364 {
 365   COMPAT_2 (OP_28007E0 ());
 366 }
 367
 368 // end-sanitize-v850e
 369
 370
 371 // start-sanitize-v850e
 372 // DIVHU
 373 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 374 *v850e
 375 "divhu r<reg1>, r<reg2>, r<reg3>"
 376 {
 377   COMPAT_2 (OP_28207E0 ());
 378 }
 379
 380
 381
 382 // end-sanitize-v850e
 383 // start-sanitize-v850e
 384 // DIVU
 385 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 386 *v850e
 387 "divu r<reg1>, r<reg2>, r<reg3>"
 388 {
 389   COMPAT_2 (OP_2C207E0 ());
 390 }
 391
 392
 393
 394 // end-sanitize-v850e
 395 // EI
 396 1000011111100000 + 0000000101100000:X:::ei
 397 "ei"
 398 {
 399   COMPAT_2 (OP_16087E0 ());
 400 }
 401
 402
 403
 404 // HALT
 405 0000011111100000 + 0000000100100000:X:::halt
 406 "halt"
 407 {
 408   COMPAT_2 (OP_12007E0 ());
 409 }
 410
 411
 412
 413 // HSW
 414 // start-sanitize-v850e
 415 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 416 *v850e
 417 "hsw r<reg2>, r<reg3>"
 418 {
 419   COMPAT_2 (OP_34407E0 ());
 420 }
 421
 422
 423
 424 // end-sanitize-v850e
 425 // JARL
 426 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 427 "jarl <disp22>, r<reg2>"
 428 {
 429   COMPAT_2 (OP_780 ());
 430 }
 431
 432
 433
 434 // JMP
 435 00000000011,RRRRR:I:::jmp
 436 "jmp [r<reg1>]"
 437 {
 438   COMPAT_1 (OP_60 ());
 439 }
 440
 441
 442
 443 // JR
 444 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 445 "jr <disp22>"
 446 {
 447   COMPAT_2 (OP_780 ());
 448 }
 449
 450
 451
 452 // LD
 453 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 454 "ld.b <disp16>[r<reg1>, r<reg2>"
 455 {
 456   COMPAT_2 (OP_700 ());
 457 }
 458
 459 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 460 "ld.h <disp16>[r<reg1>], r<reg2>"
 461 {
 462   COMPAT_2 (OP_720 ());
 463 }
 464
 465 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 466 "ld.w <disp16>[r<reg1>], r<reg2>"
 467 {
 468   COMPAT_2 (OP_10720 ());
 469 }
 470
 471 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 472 "ld.bu <disp16>[r<reg1>], r<reg2>"
 473 {
 474   COMPAT_2 (OP_10780 ());
 475 }
 476
 477 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 478 "ld.hu <disp16>[r<reg1>], r<reg2>"
 479 {
 480   COMPAT_2 (OP_107E0 ());
 481 }
 482
 483
 484
 485 // LDSR
 486 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 487 //"ldsr r<reg2>, r<regID>"
 488 //{
 489 //  COMPAT_2 (OP_2007E0 ());
 490 //}
 491 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 492 "ldsr r<reg1>, r<regID>"
 493 {
 494   COMPAT_2 (OP_2007E0 ());
 495 }
 496
 497
 498
 499 // MOV
 500 rrrrr!0,000000,RRRRR:I:::mov
 501 "mov r<reg1>, r<reg2>"
 502 {
 503   COMPAT_1 (OP_0 ());
 504 }
 505
 506 rrrrr!0,010000,iiiii:II:::mov
 507 "mov <imm5>, r<reg2>"
 508 {
 509   COMPAT_1 (OP_200 ());
 510 }
 511
 512 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 513 "mov <imm32>, r<reg1>"
 514 {
 515   COMPAT_2 (OP_620 ());
 516 }
 517
 518
 519
 520 // MOVEA
 521 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 522 "movea <imm16>, r<reg1>, r<reg2>"
 523 {
 524   COMPAT_2 (OP_620 ());
 525 }
 526
 527
 528
 529 // MOVHI
 530 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 531 "movhi <imm16>, r<reg1>, r<reg2>"
 532 {
 533   COMPAT_2 (OP_640 ());
 534 }
 535
 536
 537
 538 // start-sanitize-v850e
 539 // MUL
 540 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 541 *v850e
 542 "mul r<reg1>, r<reg2>, r<reg3>"
 543 {
 544   COMPAT_2 (OP_22007E0 ());
 545 }
 546
 547 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 548 *v850e
 549 "mul <imm9>, r<reg2>, r<reg3>"
 550 {
 551   COMPAT_2 (OP_24007E0 ());
 552 }
 553
 554
 555
 556 // end-sanitize-v850e
 557 // MULH
 558 rrrrr!0,000111,RRRRR:I:::mulh
 559 "mulh r<reg1>, r<reg2>"
 560 {
 561   COMPAT_1 (OP_E0 ());
 562 }
 563
 564 rrrrr!0,010111,iiiii:II:::mulh
 565 "mulh <imm5>, r<reg2>"
 566 {
 567   COMPAT_1 (OP_2E0 ());
 568 }
 569
 570
 571
 572 // MULHI
 573 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 574 "mulhi <imm16>, r<reg1>, r<reg2>"
 575 {
 576   COMPAT_2 (OP_6E0 ());
 577 }
 578
 579
 580
 581 // start-sanitize-v850e
 582 // MULU
 583 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 584 *v850e
 585 "mulu r<reg1>, r<reg2>, r<reg3>"
 586 {
 587   COMPAT_2 (OP_22207E0 ());
 588 }
 589
 590 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 591 *v850e
 592 "mulu <imm9>, r<reg2>, r<reg3>"
 593 {
 594   COMPAT_2 (OP_24207E0 ());
 595 }
 596
 597
 598
 599 // end-sanitize-v850e
 600 // NOP
 601 0000000000000000:I:::nop
 602 "nop"
 603 {
 604   COMPAT_1 (OP_0 ());
 605 }
 606
 607
 608
 609 // NOT
 610 rrrrr,000001,RRRRR:I:::not
 611 "not r<reg1>, r<reg2>"
 612 {
 613   COMPAT_1 (OP_20 ());
 614 }
 615
 616
 617
 618 // NOT1
 619 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 620 "not1 <bit3>, <disp16>[r<reg1>]"
 621 {
 622   COMPAT_2 (OP_47C0 ());
 623 }
 624
 625 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 626 "not1 r<reg2>, r<reg1>"
 627 {
 628   COMPAT_2 (OP_E207E0 ());
 629 }
 630
 631
 632
 633 // OR
 634 rrrrr,001000,RRRRR:I:::or
 635 "or r<reg1>, r<reg2>"
 636 {
 637   COMPAT_1 (OP_100 ());
 638 }
 639
 640
 641
 642 // ORI
 643 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 644 "ori <imm16>, r<reg1>, r<reg2>"
 645 {
 646   COMPAT_2 (OP_680 ());
 647 }
 648
 649
 650
 651 // start-sanitize-v850e
 652 // PREPARE
 653 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 654 *v850e
 655 "prepare <list12>, <imm5>"
 656 {
 657   COMPAT_2 (OP_10780 ());
 658 }
 659
 660 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 661 *v850e
 662 "prepare <list12>, <imm5>, sp"
 663 {
 664   COMPAT_2 (OP_30780 ());
 665 }
 666
 667 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 668 *v850e
 669 "prepare <list12>, <imm5>, <uimm16>"
 670 {
 671   COMPAT_2 (OP_B0780 ());
 672 }
 673
 674 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 675 *v850e
 676 "prepare <list12>, <imm5>, <uimm16>"
 677 {
 678   COMPAT_2 (OP_130780 ());
 679 }
 680
 681 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 682 *v850e
 683 "prepare <list12>, <imm5>, <uimm32>"
 684 {
 685   COMPAT_2 (OP_1B0780 ());
 686 }
 687
 688
 689
 690 // end-sanitize-v850e
 691 // RETI
 692 0000011111100000 + 0000000101000000:X:::reti
 693 "reti"
 694 {
 695   COMPAT_2 (OP_14007E0 ());
 696 }
 697
 698
 699
 700 // SAR
 701 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 702 "sar r<reg1>, r<reg2>"
 703 {
 704   COMPAT_2 (OP_A007E0 ());
 705 }
 706
 707 rrrrr,010101,iiiii:II:::sar
 708 "sar <imm5>, r<reg2>"
 709 {
 710   COMPAT_1 (OP_2A0 ());
 711 }
 712
 713
 714
 715 // SASF
 716 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 717 "sasf <cccc>, r<reg2>"
 718 {
 719   COMPAT_2 (OP_20007E0 ());
 720 }
 721
 722
 723
 724
 725 // SATADD
 726 rrrrr!0,000110,RRRRR:I:::satadd
 727 "satadd r<reg1>, r<reg2>"
 728 {
 729   COMPAT_1 (OP_C0 ());
 730 }
 731
 732 rrrrr!0,010001,iiiii:II:::satadd
 733 "satadd <imm5>, r<reg2>"
 734 {
 735   COMPAT_1 (OP_220 ());
 736 }
 737
 738
 739
 740 // SATSUB
 741 rrrrr!0,000101,RRRRR:I:::satsub
 742 "satsub r<reg1>, r<reg2>"
 743 {
 744   COMPAT_1 (OP_A0 ());
 745 }
 746
 747
 748
 749 // SATSUBI
 750 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 751 "satsubi <imm16>, r<reg1>, r<reg2>"
 752 {
 753   COMPAT_2 (OP_660 ());
 754 }
 755
 756
 757
 758 // SATSUBR
 759 rrrrr!0,000100,RRRRR:I:::satsubr
 760 "satsubr r<reg1>, r<reg2>"
 761 {
 762   COMPAT_1 (OP_80 ());
 763 }
 764
 765
 766
 767 // SETF
 768 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 769 "setf <cccc>, r<reg2>"
 770 {
 771   COMPAT_2 (OP_7E0 ());
 772 }
 773
 774
 775
 776 // SET1
 777 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 778 "set1 <bit3>, <disp16>[r<reg1>]"
 779 {
 780   COMPAT_2 (OP_7C0 ());
 781 }
 782
 783 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 784 "set1 r<reg2>, [r<reg1>]"
 785 {
 786   COMPAT_2 (OP_E007E0 ());
 787 }
 788
 789
 790
 791 // SHL
 792 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 793 "shl r<reg1>, r<reg2>"
 794 {
 795   COMPAT_2 (OP_C007E0 ());
 796 }
 797
 798 rrrrr,010110,iiiii:II:::shl
 799 "shl <imm5>, r<reg2>"
 800 {
 801   COMPAT_1 (OP_2C0 ());
 802 }
 803
 804
 805
 806 // SHR
 807 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 808 "shr r<reg1>, r<reg2>"
 809 {
 810   COMPAT_2 (OP_8007E0 ());
 811 }
 812
 813 rrrrr,010100,iiiii:II:::shr
 814 "shr <imm5>, r<reg2>"
 815 {
 816   COMPAT_1 (OP_280 ());
 817 }
 818
 819
 820
 821 // SLD
 822 rrrrr,0110,ddddddd:IV:::sld.b
 823 "sld.b <disp7>[ep], r<reg2>"
 824 {
 825   COMPAT_1 (OP_300 ());
 826 }
 827
 828 rrrrr,1000,ddddddd:IV:::sld.h
 829 "sld.h <disp8>[ep], r<reg2>"
 830 {
 831   COMPAT_1 (OP_400 ());
 832 }
 833
 834 rrrrr,1010,dddddd,0:IV:::sld.w
 835 "sld.w <disp8>[ep], r<reg2>"
 836 {
 837   COMPAT_1 (OP_500 ());
 838 }
 839
 840 rrrrr!0,0000110,dddd:IV:::sld.bu
 841 "sld.bu <disp4>[ep], r<reg2>"
 842 {
 843   COMPAT_1 (OP_60 ());
 844 }
 845
 846 rrrrr!0,0000111,dddd:IV:::sld.hu
 847 "sld.hu <disp5>[ep], r<reg2>"
 848 {
 849   COMPAT_1 (OP_70 ());
 850 }
 851
 852
 853
 854 // SST
 855 rrrrr,0111,ddddddd:IV:::sst.b
 856 "sst.b r<reg2>, <disp7>[ep]"
 857 {
 858   COMPAT_1 (OP_380 ());
 859 }
 860
 861 rrrrr,1001,ddddddd:IV:::sst.h
 862 "sst.h r<reg2>, <disp8>[ep]"
 863 {
 864   COMPAT_1 (OP_480 ());
 865 }
 866
 867 rrrrr,1010,dddddd,1:IV:::sst.w
 868 "sst.w r<reg2>, <disp8>[ep]"
 869 {
 870   COMPAT_1 (OP_501 ());
 871 }
 872
 873
 874
 875 // ST
 876 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 877 "st.b r<reg2>, <disp16>[r<reg1>]"
 878 {
 879   COMPAT_2 (OP_740 ());
 880 }
 881
 882 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 883 "st.h r<reg2>, <disp16>[r<reg1>]"
 884 {
 885   COMPAT_2 (OP_760 ());
 886 }
 887
 888 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 889 "st.w r<reg2>, <disp16>[r<reg1>]"
 890 {
 891   COMPAT_2 (OP_10760 ());
 892 }
 893
 894
 895
 896 // STSR
 897 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 898 //"stsr r<regID>, r<reg2>"
 899 //{
 900 //  COMPAT_2 (OP_4007E0 ());
 901 //}
 902 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 903 "stsr r<regID>, r<reg1>"
 904 {
 905   COMPAT_2 (OP_4007E0 ());
 906 }
 907
 908
 909
 910 // SUB
 911 rrrrr,001101,RRRRR:I:::sub
 912 "sub r<reg1>, r<reg2>"
 913 {
 914   COMPAT_1 (OP_1A0 ());
 915 }
 916
 917
 918
 919 // SUBR
 920 rrrrr,001100,RRRRR:I:::subr
 921 "subr r<reg1>, r<reg2>"
 922 {
 923   COMPAT_1 (OP_180 ());
 924 }
 925
 926
 927
 928 // SWITCH
 929 00000000010,RRRRR:I:::switch
 930 "switch r<reg1>"
 931 {
 932   COMPAT_1 (OP_40 ());
 933 }
 934
 935
 936
 937 // SXB
 938 00000000101,RRRRR:I:::sxb
 939 "sxb r<reg1>"
 940 {
 941   COMPAT_1 (OP_A0 ());
 942 }
 943
 944
 945
 946 // SXH
 947 00000000111,RRRRR:I:::sxh
 948 "sxh r<reg1>"
 949 {
 950   COMPAT_1 (OP_E0 ());
 951 }
 952
 953
 954
 955 // TRAP
 956 00000111111,iiiii + 0000000100000000:X:::trap
 957 "trap <vector>"
 958 {
 959   COMPAT_2 (OP_10007E0 ());
 960 }
 961
 962
 963
 964 // TST
 965 rrrrr,001011,RRRRR:I:::tst
 966 "tst r<reg1>, r<reg2>"
 967 {
 968   COMPAT_1 (OP_160 ());
 969 }
 970
 971
 972
 973 // TST1
 974 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
 975 "tst1 <bit3>, <disp16>[r<reg1>]"
 976 {
 977   COMPAT_2 (OP_C7C0 ());
 978 }
 979
 980 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
 981 "tst1 r<reg2>, [r<reg1>]"
 982 {
 983   COMPAT_2 (OP_E607E0 ());
 984 }
 985
 986
 987
 988 // XOR
 989 rrrrr,001001,RRRRR:I:::xor
 990 "xor r<reg1>, r<reg2>"
 991 {
 992   COMPAT_1 (OP_120 ());
 993 }
 994
 995
 996
 997 // XORI
 998 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 999 "xori <imm16>, r<reg1>, r<reg2>"
1000 {
1001   COMPAT_2 (OP_6A0 ());
1002 }
1003
1004
1005
1006 // ZXB
1007 00000000100,RRRRR:I:::zxb
1008 "zxb r<reg1>"
1009 {
1010   COMPAT_1 (OP_80 ());
1011 }
1012
1013
1014
1015 // ZXH
1016 00000000110,RRRRR:I:::zxh
1017 "zxh r<reg1>"
1018 {
1019   COMPAT_1 (OP_C0 ());
1020 }
1021
1022
1023
1024 // Special - breakpoint
1025 // 1111111111111111:Z:::breakpoint
1026 // {
1027 //   COMPAT_2 (OP_FFFF ());
1028 // }
1029
1030
1031 // start-sanitize-v850eq
1032 // DIVHN
1033 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1034 *v850eq
1035 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1036 {
1037   COMPAT_2 (OP_28007E0 ());
1038 }
1039
1040
1041
1042 // DIVHUN
1043 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1044 *v850eq
1045 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1046 {
1047   COMPAT_2 (OP_28207E0 ());
1048 }
1049
1050
1051
1052 // DIVN
1053 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1054 *v850eq
1055 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1056 {
1057   COMPAT_2 (OP_2C007E0 ());
1058 }
1059
1060
1061
1062 // DIVUN
1063 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1064 *v850eq
1065 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1066 {
1067   COMPAT_2 (OP_2C207E0 ());
1068 }
1069
1070
1071
1072 // SDIVHN
1073 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1074 *v850eq
1075 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1076 {
1077   COMPAT_2 (OP_18007E0 ());
1078 }
1079
1080
1081
1082 // SDIVHUN
1083 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1084 *v850eq
1085 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1086 {
1087   COMPAT_2 (OP_18207E0 ());
1088 }
1089
1090
1091
1092 // SDIVN
1093 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1094 *v850eq
1095 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1096 {
1097   COMPAT_2 (OP_1C007E0 ());
1098 }
1099
1100
1101
1102 // SDIVUN
1103 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1104 *v850eq
1105 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1106 {
1107   COMPAT_2 (OP_1C207E0 ());
1108 }
1109
1110
1111
1112 // PUSHML
1113 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1114 *v850eq
1115 "pushml <list18>"
1116 {
1117   COMPAT_2 (OP_107E0 ());
1118 }
1119
1120
1121
1122 // PUSHHML
1123 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1124 *v850eq
1125 "pushhml <list18>"
1126 {
1127   COMPAT_2 (OP_307E0 ());
1128 }
1129
1130
1131
1132 // POPML
1133 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1134 *v850eq
1135 "popml <list18>"
1136 {
1137   COMPAT_2 (OP_107F0 ());
1138 }
1139
1140
1141
1142 // POPMH
1143 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1144 *v850eq
1145 "popmh <list18>"
1146 {
1147   COMPAT_2 (OP_307F0 ());
1148 }
1149
1150
1151 // end-sanitize-v850eq