sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
  56 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  57 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  58 # start-sanitize-v850e
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  76                   (unsigned long) cia);
  77   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  78 }
  79
  80
  81
  82 // Add
  83
  84 rrrrr,001110,RRRRR:I:::add
  85 "add r<reg1>, r<reg2>"
  86 {
  87   COMPAT_1 (OP_1C0 ());
  88 }
  89
  90 rrrrr,010010,iiiii:II:::add
  91 "add <imm5>,r<reg2>"
  92 {
  93   COMPAT_1 (OP_240 ());
  94 }
  95
  96
  97
  98 // ADDI
  99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 100 "addi <simm16>, r<reg1>, r<reg2>"
 101 {
 102   COMPAT_2 (OP_600 ());
 103 }
 104
 105
 106
 107 // AND
 108 rrrrr,001010,RRRRR:I:::and
 109 "and r<reg1>, r<reg2>"
 110 {
 111   COMPAT_1 (OP_140 ());
 112 }
 113
 114
 115
 116 // ANDI
 117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 118 "andi <uimm16>, r<reg1>, r<reg2>"
 119 {
 120   COMPAT_2 (OP_6C0 ());
 121 }
 122
 123
 124
 125 // Bcond
 126 // ddddd,1011,ddd,cccc:III:::Bcond
 127 // "b<cond> disp9"
 128
 129 ddddd,1011,ddd,0000:III:::bv
 130 "bv <disp9>"
 131 {
 132   COMPAT_1 (OP_580 ());
 133 }
 134
 135 ddddd,1011,ddd,0001:III:::bl
 136 "bl <disp9>"
 137 {
 138   COMPAT_1 (OP_581 ());
 139 }
 140
 141 ddddd,1011,ddd,0010:III:::be
 142 "be <disp9>"
 143 {
 144   COMPAT_1 (OP_582 ());
 145 }
 146
 147 ddddd,1011,ddd,0011:III:::bnh
 148 "bnh <disp9>"
 149 {
 150   COMPAT_1 (OP_583 ());
 151 }
 152
 153 ddddd,1011,ddd,0100:III:::bn
 154 "bn <disp9>"
 155 {
 156   COMPAT_1 (OP_584 ());
 157 }
 158
 159 ddddd,1011,ddd,0101:III:::br
 160 "br <disp9>"
 161 {
 162   COMPAT_1 (OP_585 ());
 163 }
 164
 165 ddddd,1011,ddd,0110:III:::blt
 166 "blt <disp9>"
 167 {
 168   COMPAT_1 (OP_586 ());
 169 }
 170
 171 ddddd,1011,ddd,0111:III:::ble
 172 "ble <disp9>"
 173 {
 174   COMPAT_1 (OP_587 ());
 175 }
 176
 177 ddddd,1011,ddd,1000:III:::bnv
 178 "bnv <disp9>"
 179 {
 180   COMPAT_1 (OP_588 ());
 181 }
 182
 183 ddddd,1011,ddd,1001:III:::bnl
 184 "bnl <disp9>"
 185 {
 186   COMPAT_1 (OP_589 ());
 187 }
 188
 189 ddddd,1011,ddd,1010:III:::bne
 190 "bne <disp9>"
 191 {
 192   COMPAT_1 (OP_58A ());
 193 }
 194
 195 ddddd,1011,ddd,1011:III:::bh
 196 "bh <disp9>"
 197 {
 198   COMPAT_1 (OP_58B ());
 199 }
 200
 201 ddddd,1011,ddd,1100:III:::bp
 202 "bp <disp9>"
 203 {
 204   COMPAT_1 (OP_58C ());
 205 }
 206
 207 ddddd,1011,ddd,1101:III:::bsa
 208 "bsa <disp9>"
 209 {
 210   COMPAT_1 (OP_58D ());
 211 }
 212
 213 ddddd,1011,ddd,1110:III:::bge
 214 "bge <disp9>"
 215 {
 216   COMPAT_1 (OP_58E ());
 217 }
 218
 219 ddddd,1011,ddd,1111:III:::bgt
 220 "bgt <disp9>"
 221 {
 222   COMPAT_1 (OP_58F ());
 223 }
 224
 225
 226
 227 // start-sanitize-v850e
 228 // BSH
 229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 230 *v850e
 231 // start-sanitize-v850eq
 232 *v850eq
 233 // end-sanitize-v850eq
 234 "bsh r<reg2>, r<reg3>"
 235 {
 236   COMPAT_2 (OP_34207E0 ());
 237 }
 238
 239
 240
 241 // end-sanitize-v850e
 242 // start-sanitize-v850e
 243 // BSW
 244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 245 *v850e
 246 // start-sanitize-v850eq
 247 *v850eq
 248 // end-sanitize-v850eq
 249 "bsw r<reg2>, reg3>"
 250 {
 251   COMPAT_2 (OP_34007E0 ());
 252 }
 253
 254
 255
 256 // end-sanitize-v850e
 257 // start-sanitize-v850e
 258 // CALLT
 259 0000001000,iiiiii:II:::callt
 260 *v850e
 261 // start-sanitize-v850eq
 262 *v850eq
 263 // end-sanitize-v850eq
 264 "callt <imm6>"
 265 {
 266   unsigned long adr;
 267   SAVE_1;
 268   trace_input ("callt", OP_LOAD16, 1);
 269   CTPC  = cia + 2;
 270   CTPSW = PSW;
 271   adr = CTBP + ((OP[3] & 0x3f) << 1);
 272   nia = CTBP + load_mem (adr, 1);
 273   trace_output (OP_LOAD16);
 274 }
 275
 276
 277
 278 // end-sanitize-v850e
 279 // CLR1
 280 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 281 "clr1 <bit3>, <disp16>[r<reg1>]"
 282 {
 283   COMPAT_2 (OP_87C0 ());
 284 }
 285
 286 // start-sanitize-v850e
 287 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 288 *v850e
 289 // start-sanitize-v850eq
 290 *v850eq
 291 // end-sanitize-v850eq
 292 "clr1 r<reg2>, [r<reg1>]"
 293 {
 294   COMPAT_2 (OP_E407E0 ());
 295 }
 296
 297
 298
 299 // end-sanitize-v850e
 300 // start-sanitize-v850e
 301 // CTRET
 302 0000011111100000 + 0000000101000100:X:::ctret
 303 *v850e
 304 // start-sanitize-v850eq
 305 *v850eq
 306 // end-sanitize-v850eq
 307 "ctret"
 308 {
 309   COMPAT_2 (OP_14407E0 ());
 310 }
 311
 312
 313
 314 // end-sanitize-v850e
 315 // start-sanitize-v850e
 316 // CMOV
 317 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 318 *v850e
 319 // start-sanitize-v850eq
 320 *v850eq
 321 // end-sanitize-v850eq
 322 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 323 {
 324   COMPAT_2 (OP_32007E0 ());
 325 }
 326
 327 // end-sanitize-v850e
 328 // start-sanitize-v850e
 329 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 330 *v850e
 331 // start-sanitize-v850eq
 332 *v850eq
 333 // end-sanitize-v850eq
 334 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 335 {
 336   COMPAT_2 (OP_30007E0 ());
 337 }
 338
 339
 340
 341 // end-sanitize-v850e
 342 // CMP
 343 rrrrr,001111,RRRRR:I:::cmp
 344 "cmp r<reg1>, r<reg2>"
 345 {
 346   COMPAT_1 (OP_1E0 ());
 347 }
 348
 349 rrrrr,010011,iiiii:II:::cmp
 350 "cmp <imm5>, r<reg2>"
 351 {
 352   COMPAT_1 (OP_260 ());
 353 }
 354
 355
 356
 357 // DI
 358 0000011111100000 + 0000000101100000:X:::di
 359 "di"
 360 {
 361   COMPAT_2 (OP_16007E0 ());
 362 }
 363
 364
 365
 366 // start-sanitize-v850e
 367 // DISPOSE
 368 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 369 // "dispose <imm5>, <list12>"
 370 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 371 *v850e
 372 // start-sanitize-v850eq
 373 *v850eq
 374 // end-sanitize-v850eq
 375 "dispose <imm5>, <list12>":RRRRR == 0
 376 "dispose <imm5>, <list12>, [reg1]"
 377 {
 378   int i;
 379   SAVE_2;
 380
 381   trace_input ("dispose", OP_PUSHPOP1, 0);
 382
 383   SP += (OP[3] & 0x3e) << 1;
 384
 385   /* Load the registers with lower number registers being retrieved
 386      from higher addresses.  */
 387   for (i = 12; i--;)
 388     if ((OP[3] & (1 << type1_regs[ i ])))
 389       {
 390         State.regs[ 20 + i ] = load_mem (SP, 4);
 391         SP += 4;
 392       }
 393
 394   if ((OP[3] & 0x1f0000) != 0)
 395     {
 396       nia = State.regs[ (OP[3] >> 16) & 0x1f];
 397     }
 398
 399   trace_output (OP_PUSHPOP1);
 400 }
 401
 402
 403
 404 // end-sanitize-v850e
 405 // start-sanitize-v850e
 406 // DIV
 407 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 408 *v850e
 409 "div r<reg1>, r<reg2>, r<reg3>"
 410 {
 411   COMPAT_2 (OP_2C007E0 ());
 412 }
 413
 414
 415
 416
 417 // end-sanitize-v850e
 418 // DIVH
 419 rrrrr!0,000010,RRRRR!0:I:::divh
 420 "divh r<reg1>, r<reg2>"
 421 {
 422   COMPAT_1 (OP_40 ());
 423 }
 424
 425 // start-sanitize-v850e
 426 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 427 *v850e
 428 "divh r<reg1>, r<reg2>, r<reg3>"
 429 {
 430   COMPAT_2 (OP_28007E0 ());
 431 }
 432
 433
 434
 435 // end-sanitize-v850e
 436 // start-sanitize-v850e
 437 // DIVHU
 438 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 439 *v850e
 440 "divhu r<reg1>, r<reg2>, r<reg3>"
 441 {
 442   COMPAT_2 (OP_28207E0 ());
 443 }
 444
 445
 446
 447 // end-sanitize-v850e
 448 // start-sanitize-v850e
 449 // DIVU
 450 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 451 *v850e
 452 "divu r<reg1>, r<reg2>, r<reg3>"
 453 {
 454   COMPAT_2 (OP_2C207E0 ());
 455 }
 456
 457
 458
 459 // end-sanitize-v850e
 460 // EI
 461 1000011111100000 + 0000000101100000:X:::ei
 462 "ei"
 463 {
 464   COMPAT_2 (OP_16087E0 ());
 465 }
 466
 467
 468
 469 // HALT
 470 0000011111100000 + 0000000100100000:X:::halt
 471 "halt"
 472 {
 473   COMPAT_2 (OP_12007E0 ());
 474 }
 475
 476
 477
 478 // start-sanitize-v850e
 479 // HSW
 480 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 481 *v850e
 482 // start-sanitize-v850eq
 483 *v850eq
 484 // end-sanitize-v850eq
 485 "hsw r<reg2>, r<reg3>"
 486 {
 487   COMPAT_2 (OP_34407E0 ());
 488 }
 489
 490
 491
 492 // end-sanitize-v850e
 493 // JARL
 494 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 495 "jarl <disp22>, r<reg2>"
 496 {
 497   COMPAT_2 (OP_780 ());
 498 }
 499
 500
 501
 502 // JMP
 503 00000000011,RRRRR:I:::jmp
 504 "jmp [r<reg1>]"
 505 {
 506   SAVE_1;
 507   trace_input ("jmp", OP_REG, 0);
 508   nia = State.regs[ reg1 ];
 509   trace_output (OP_REG);
 510 }
 511
 512
 513
 514 // JR
 515 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 516 "jr <disp22>"
 517 {
 518   COMPAT_2 (OP_780 ());
 519 }
 520
 521
 522
 523 // LD
 524 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 525 "ld.b <disp16>[r<reg1>, r<reg2>"
 526 {
 527   COMPAT_2 (OP_700 ());
 528 }
 529
 530 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 531 "ld.h <disp16>[r<reg1>], r<reg2>"
 532 {
 533   COMPAT_2 (OP_720 ());
 534 }
 535
 536 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 537 "ld.w <disp16>[r<reg1>], r<reg2>"
 538 {
 539   COMPAT_2 (OP_10720 ());
 540 }
 541
 542 // start-sanitize-v850e
 543 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 544 *v850e
 545 // start-sanitize-v850eq
 546 *v850eq
 547 // end-sanitize-v850eq
 548 "ld.bu <disp16>[r<reg1>], r<reg2>"
 549 {
 550   COMPAT_2 (OP_10780 ());
 551 }
 552
 553 // end-sanitize-v850e
 554 // start-sanitize-v850e
 555 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 556 *v850e
 557 // start-sanitize-v850eq
 558 *v850eq
 559 // end-sanitize-v850eq
 560 "ld.hu <disp16>[r<reg1>], r<reg2>"
 561 {
 562   COMPAT_2 (OP_107E0 ());
 563 }
 564
 565
 566 // end-sanitize-v850e
 567 // LDSR
 568 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 569 //"ldsr r<reg2>, r<regID>"
 570 //{
 571 //  COMPAT_2 (OP_2007E0 ());
 572 //}
 573 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 574 "ldsr r<reg1>, r<regID>"
 575 {
 576   SAVE_2;
 577   trace_input ("ldsr", OP_LDSR, 0);
 578
 579   if (&PSW == &State.sregs[ regID ])
 580     PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
 581   else
 582     State.sregs[ regID ] = State.regs[ reg1 ];
 583
 584   trace_output (OP_LDSR);
 585 }
 586
 587
 588
 589 // MOV
 590 rrrrr!0,000000,RRRRR:I:::mov
 591 "mov r<reg1>, r<reg2>"
 592 {
 593   COMPAT_1 (OP_0 ());
 594 }
 595
 596 rrrrr!0,010000,iiiii:II:::mov
 597 "mov <imm5>, r<reg2>"
 598 {
 599   COMPAT_1 (OP_200 ());
 600 }
 601
 602 // start-sanitize-v850e
 603 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 604 *v850e
 605 // start-sanitize-v850eq
 606 *v850eq
 607 // end-sanitize-v850eq
 608 "mov <imm32>, r<reg1>"
 609 {
 610   SAVE_2;
 611   trace_input ("mov", OP_IMM_REG, 4);
 612   State.regs[ OP[0] ] = load_mem (PC + 2, 4);
 613   trace_output (OP_IMM_REG);
 614 }
 615
 616
 617
 618 // end-sanitize-v850e
 619 // MOVEA
 620 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 621 "movea <simm16>, r<reg1>, r<reg2>"
 622 {
 623   TRACE_ALU_INPUT2 (GR[reg1], simm16);
 624   GR[reg2] = GR[reg1] + simm16;
 625   TRACE_ALU_RESULT (GR[reg2]);
 626 }
 627
 628
 629
 630 // MOVHI
 631 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 632 "movhi <uimm16>, r<reg1>, r<reg2>"
 633 {
 634   COMPAT_2 (OP_640 ());
 635 }
 636
 637
 638
 639 // start-sanitize-v850e
 640 // MUL
 641 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 642 *v850e
 643 // start-sanitize-v850eq
 644 *v850eq
 645 // end-sanitize-v850eq
 646 "mul r<reg1>, r<reg2>, r<reg3>"
 647 {
 648   COMPAT_2 (OP_22007E0 ());
 649 }
 650
 651 // end-sanitize-v850e
 652 // start-sanitize-v850e
 653 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 654 *v850e
 655 // start-sanitize-v850eq
 656 *v850eq
 657 // end-sanitize-v850eq
 658 "mul <imm9>, r<reg2>, r<reg3>"
 659 {
 660   COMPAT_2 (OP_24007E0 ());
 661 }
 662
 663
 664
 665 // end-sanitize-v850e
 666 // MULH
 667 rrrrr!0,000111,RRRRR:I:::mulh
 668 "mulh r<reg1>, r<reg2>"
 669 {
 670   COMPAT_1 (OP_E0 ());
 671 }
 672
 673 rrrrr!0,010111,iiiii:II:::mulh
 674 "mulh <imm5>, r<reg2>"
 675 {
 676   COMPAT_1 (OP_2E0 ());
 677 }
 678
 679
 680
 681 // MULHI
 682 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 683 "mulhi <uimm16>, r<reg1>, r<reg2>"
 684 {
 685   COMPAT_2 (OP_6E0 ());
 686 }
 687
 688
 689
 690 // start-sanitize-v850e
 691 // MULU
 692 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 693 *v850e
 694 // start-sanitize-v850eq
 695 *v850eq
 696 // end-sanitize-v850eq
 697 "mulu r<reg1>, r<reg2>, r<reg3>"
 698 {
 699   COMPAT_2 (OP_22207E0 ());
 700 }
 701
 702 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 703 *v850e
 704 // start-sanitize-v850eq
 705 *v850eq
 706 // end-sanitize-v850eq
 707 "mulu <imm9>, r<reg2>, r<reg3>"
 708 {
 709   COMPAT_2 (OP_24207E0 ());
 710 }
 711
 712
 713
 714 // end-sanitize-v850e
 715 // NOP
 716 0000000000000000:I:::nop
 717 "nop"
 718 {
 719   COMPAT_1 (OP_0 ());
 720 }
 721
 722
 723
 724 // NOT
 725 rrrrr,000001,RRRRR:I:::not
 726 "not r<reg1>, r<reg2>"
 727 {
 728   COMPAT_1 (OP_20 ());
 729 }
 730
 731
 732
 733 // NOT1
 734 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 735 "not1 <bit3>, <disp16>[r<reg1>]"
 736 {
 737   COMPAT_2 (OP_47C0 ());
 738 }
 739
 740 // start-sanitize-v850e
 741 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 742 *v850e
 743 // start-sanitize-v850eq
 744 *v850eq
 745 // end-sanitize-v850eq
 746 "not1 r<reg2>, r<reg1>"
 747 {
 748   COMPAT_2 (OP_E207E0 ());
 749 }
 750
 751
 752
 753 // end-sanitize-v850e
 754 // OR
 755 rrrrr,001000,RRRRR:I:::or
 756 "or r<reg1>, r<reg2>"
 757 {
 758   COMPAT_1 (OP_100 ());
 759 }
 760
 761
 762
 763 // ORI
 764 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 765 "ori <uimm16>, r<reg1>, r<reg2>"
 766 {
 767   COMPAT_2 (OP_680 ());
 768 }
 769
 770
 771
 772 // start-sanitize-v850e
 773 // PREPARE
 774 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 775 *v850e
 776 // start-sanitize-v850eq
 777 *v850eq
 778 // end-sanitize-v850eq
 779 "prepare <list12>, <imm5>"
 780 {
 781   int  i;
 782   SAVE_2;
 783
 784   trace_input ("prepare", OP_PUSHPOP1, 0);
 785
 786   /* Store the registers with lower number registers being placed at
 787      higher addresses.  */
 788   for (i = 0; i < 12; i++)
 789     if ((OP[3] & (1 << type1_regs[ i ])))
 790       {
 791         SP -= 4;
 792         store_mem (SP, 4, State.regs[ 20 + i ]);
 793       }
 794
 795   SP -= (OP[3] & 0x3e) << 1;
 796
 797   trace_output (OP_PUSHPOP1);
 798 }
 799
 800
 801 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 802 *v850e
 803 // start-sanitize-v850eq
 804 *v850eq
 805 // end-sanitize-v850eq
 806 "prepare <list12>, <imm5>, sp"
 807 {
 808   COMPAT_2 (OP_30780 ());
 809 }
 810
 811 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 812 *v850e
 813 // start-sanitize-v850eq
 814 *v850eq
 815 // end-sanitize-v850eq
 816 "prepare <list12>, <imm5>, <uimm16>"
 817 {
 818   COMPAT_2 (OP_B0780 ());
 819 }
 820
 821 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 822 *v850e
 823 // start-sanitize-v850eq
 824 *v850eq
 825 // end-sanitize-v850eq
 826 "prepare <list12>, <imm5>, <uimm16>"
 827 {
 828   COMPAT_2 (OP_130780 ());
 829 }
 830
 831 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 832 *v850e
 833 // start-sanitize-v850eq
 834 *v850eq
 835 // end-sanitize-v850eq
 836 "prepare <list12>, <imm5>, <uimm32>"
 837 {
 838   COMPAT_2 (OP_1B0780 ());
 839 }
 840
 841
 842
 843 // end-sanitize-v850e
 844 // RETI
 845 0000011111100000 + 0000000101000000:X:::reti
 846 "reti"
 847 {
 848   COMPAT_2 (OP_14007E0 ());
 849 }
 850
 851
 852
 853 // SAR
 854 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 855 "sar r<reg1>, r<reg2>"
 856 {
 857   COMPAT_2 (OP_A007E0 ());
 858 }
 859
 860 rrrrr,010101,iiiii:II:::sar
 861 "sar <imm5>, r<reg2>"
 862 {
 863   COMPAT_1 (OP_2A0 ());
 864 }
 865
 866
 867
 868 // start-sanitize-v850e
 869 // SASF
 870 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 871 *v850e
 872 // start-sanitize-v850eq
 873 *v850eq
 874 // end-sanitize-v850eq
 875 "sasf <cccc>, r<reg2>"
 876 {
 877   COMPAT_2 (OP_20007E0 ());
 878 }
 879
 880
 881
 882
 883 // end-sanitize-v850e
 884 // SATADD
 885 rrrrr!0,000110,RRRRR:I:::satadd
 886 "satadd r<reg1>, r<reg2>"
 887 {
 888   COMPAT_1 (OP_C0 ());
 889 }
 890
 891 rrrrr!0,010001,iiiii:II:::satadd
 892 "satadd <imm5>, r<reg2>"
 893 {
 894   COMPAT_1 (OP_220 ());
 895 }
 896
 897
 898
 899 // SATSUB
 900 rrrrr!0,000101,RRRRR:I:::satsub
 901 "satsub r<reg1>, r<reg2>"
 902 {
 903   COMPAT_1 (OP_A0 ());
 904 }
 905
 906
 907
 908 // SATSUBI
 909 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 910 "satsubi <simm16>, r<reg1>, r<reg2>"
 911 {
 912   COMPAT_2 (OP_660 ());
 913 }
 914
 915
 916
 917 // SATSUBR
 918 rrrrr!0,000100,RRRRR:I:::satsubr
 919 "satsubr r<reg1>, r<reg2>"
 920 {
 921   COMPAT_1 (OP_80 ());
 922 }
 923
 924
 925
 926 // SETF
 927 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 928 "setf <cccc>, r<reg2>"
 929 {
 930   COMPAT_2 (OP_7E0 ());
 931 }
 932
 933
 934
 935 // SET1
 936 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 937 "set1 <bit3>, <disp16>[r<reg1>]"
 938 {
 939   COMPAT_2 (OP_7C0 ());
 940 }
 941
 942 // start-sanitize-v850e
 943 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 944 *v850e
 945 // start-sanitize-v850eq
 946 *v850eq
 947 // end-sanitize-v850eq
 948 "set1 r<reg2>, [r<reg1>]"
 949 {
 950   COMPAT_2 (OP_E007E0 ());
 951 }
 952
 953
 954
 955 // end-sanitize-v850e
 956 // SHL
 957 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 958 "shl r<reg1>, r<reg2>"
 959 {
 960   COMPAT_2 (OP_C007E0 ());
 961 }
 962
 963 rrrrr,010110,iiiii:II:::shl
 964 "shl <imm5>, r<reg2>"
 965 {
 966   COMPAT_1 (OP_2C0 ());
 967 }
 968
 969
 970
 971 // SHR
 972 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 973 "shr r<reg1>, r<reg2>"
 974 {
 975   COMPAT_2 (OP_8007E0 ());
 976 }
 977
 978 rrrrr,010100,iiiii:II:::shr
 979 "shr <imm5>, r<reg2>"
 980 {
 981   COMPAT_1 (OP_280 ());
 982 }
 983
 984
 985
 986 // SLD
 987 rrrrr,0110,ddddddd:IV:::sld.b
 988 "sld.b <disp7>[ep], r<reg2>"
 989 {
 990   COMPAT_1 (OP_300 ());
 991 }
 992
 993 rrrrr,1000,ddddddd:IV:::sld.h
 994 "sld.h <disp8>[ep], r<reg2>"
 995 {
 996   COMPAT_1 (OP_400 ());
 997 }
 998
 999 rrrrr,1010,dddddd,0:IV:::sld.w
1000 "sld.w <disp8>[ep], r<reg2>"
1001 {
1002   COMPAT_1 (OP_500 ());
1003 }
1004
1005 // start-sanitize-v850e
1006 rrrrr!0,0000110,dddd:IV:::sld.bu
1007 "sld.bu <disp4>[ep], r<reg2>"
1008 {
1009   unsigned long result;
1010
1011   SAVE_1;
1012   result = load_mem (State.regs[30] + disp4, 1);
1013
1014   /* start-sanitize-v850eq */
1015   if (PSW & PSW_US) {
1016     trace_input ("sld.b", OP_LOAD16, 1);
1017
1018     State.regs[ reg2 ] = EXTEND8 (result);
1019   } else {
1020   /* end-sanitize-v850eq */
1021   trace_input ("sld.bu", OP_LOAD16, 1);
1022   State.regs[ reg2 ] = result;
1023   /* start-sanitize-v850eq */
1024   }
1025   /* end-sanitize-v850eq */
1026   trace_output (OP_LOAD16);
1027 }
1028
1029 // end-sanitize-v850e
1030 // start-sanitize-v850e
1031 rrrrr!0,0000111,dddd:IV:::sld.hu
1032 "sld.hu <disp5>[ep], r<reg2>"
1033 {
1034   COMPAT_1 (OP_70 ());
1035 }
1036
1037 // end-sanitize-v850e
1038
1039
1040 // SST
1041 rrrrr,0111,ddddddd:IV:::sst.b
1042 "sst.b r<reg2>, <disp7>[ep]"
1043 {
1044   COMPAT_1 (OP_380 ());
1045 }
1046
1047 rrrrr,1001,ddddddd:IV:::sst.h
1048 "sst.h r<reg2>, <disp8>[ep]"
1049 {
1050   COMPAT_1 (OP_480 ());
1051 }
1052
1053 rrrrr,1010,dddddd,1:IV:::sst.w
1054 "sst.w r<reg2>, <disp8>[ep]"
1055 {
1056   COMPAT_1 (OP_501 ());
1057 }
1058
1059
1060
1061 // ST
1062 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1063 "st.b r<reg2>, <disp16>[r<reg1>]"
1064 {
1065   COMPAT_2 (OP_740 ());
1066 }
1067
1068 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1069 "st.h r<reg2>, <disp16>[r<reg1>]"
1070 {
1071   COMPAT_2 (OP_760 ());
1072 }
1073
1074 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1075 "st.w r<reg2>, <disp16>[r<reg1>]"
1076 {
1077   COMPAT_2 (OP_10760 ());
1078 }
1079
1080
1081
1082 // STSR
1083 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1084 //"stsr r<regID>, r<reg2>"
1085 //{
1086 //  COMPAT_2 (OP_4007E0 ());
1087 //}
1088 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1089 "stsr r<regID>, r<reg1>"
1090 {
1091   TRACE_ALU_INPUT0();
1092   GR[reg1] = SR[regID];
1093   TRACE_ALU_RESULT (GR[reg1]);
1094 }
1095
1096
1097
1098 // SUB
1099 rrrrr,001101,RRRRR:I:::sub
1100 "sub r<reg1>, r<reg2>"
1101 {
1102   COMPAT_1 (OP_1A0 ());
1103 }
1104
1105
1106
1107 // SUBR
1108 rrrrr,001100,RRRRR:I:::subr
1109 "subr r<reg1>, r<reg2>"
1110 {
1111   COMPAT_1 (OP_180 ());
1112 }
1113
1114
1115
1116 // start-sanitize-v850e
1117 // SWITCH
1118 00000000010,RRRRR:I:::switch
1119 *v850e
1120 // start-sanitize-v850eq
1121 *v850eq
1122 // end-sanitize-v850eq
1123 "switch r<reg1>"
1124 {
1125   unsigned long adr;
1126   SAVE_1;
1127   trace_input ("switch", OP_REG, 0);
1128   adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1129   nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1130   trace_output (OP_REG);
1131 }
1132
1133
1134
1135 // end-sanitize-v850e
1136 // start-sanitize-v850e
1137 // SXB
1138 00000000101,RRRRR:I:::sxb
1139 *v850e
1140 // start-sanitize-v850eq
1141 *v850eq
1142 // end-sanitize-v850eq
1143 "sxb r<reg1>"
1144 {
1145   TRACE_ALU_INPUT1 (GR[reg1]);
1146   GR[reg1] = EXTEND8 (GR[reg1]);
1147   TRACE_ALU_RESULT (GR[reg1]);
1148 }
1149
1150
1151
1152 // end-sanitize-v850e
1153 // start-sanitize-v850e
1154 // SXH
1155 00000000111,RRRRR:I:::sxh
1156 *v850e
1157 // start-sanitize-v850eq
1158 *v850eq
1159 // end-sanitize-v850eq
1160 "sxh r<reg1>"
1161 {
1162   TRACE_ALU_INPUT1 (GR[reg1]);
1163   GR[reg1] = EXTEND16 (GR[reg1]);
1164   TRACE_ALU_RESULT (GR[reg1]);
1165 }
1166
1167
1168
1169 // end-sanitize-v850e
1170 // TRAP
1171 00000111111,iiiii + 0000000100000000:X:::trap
1172 "trap <vector>"
1173 {
1174   COMPAT_2 (OP_10007E0 ());
1175 }
1176
1177
1178
1179 // TST
1180 rrrrr,001011,RRRRR:I:::tst
1181 "tst r<reg1>, r<reg2>"
1182 {
1183   COMPAT_1 (OP_160 ());
1184 }
1185
1186
1187
1188 // TST1
1189 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1190 "tst1 <bit3>, <disp16>[r<reg1>]"
1191 {
1192   COMPAT_2 (OP_C7C0 ());
1193 }
1194
1195 // start-sanitize-v850e
1196 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1197 *v850e
1198 // start-sanitize-v850eq
1199 *v850eq
1200 // end-sanitize-v850eq
1201 "tst1 r<reg2>, [r<reg1>]"
1202 {
1203   COMPAT_2 (OP_E607E0 ());
1204 }
1205
1206
1207
1208 // end-sanitize-v850e
1209 // XOR
1210 rrrrr,001001,RRRRR:I:::xor
1211 "xor r<reg1>, r<reg2>"
1212 {
1213   COMPAT_1 (OP_120 ());
1214 }
1215
1216
1217
1218 // XORI
1219 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1220 "xori <uimm16>, r<reg1>, r<reg2>"
1221 {
1222   COMPAT_2 (OP_6A0 ());
1223 }
1224
1225
1226
1227 // start-sanitize-v850e
1228 // ZXB
1229 00000000100,RRRRR:I:::zxb
1230 *v850e
1231 // start-sanitize-v850eq
1232 *v850eq
1233 // end-sanitize-v850eq
1234 "zxb r<reg1>"
1235 {
1236   TRACE_ALU_INPUT1 (GR[reg1]);
1237   GR[reg1] = GR[reg1] & 0xff;
1238   TRACE_ALU_RESULT (GR[reg1]);
1239 }
1240
1241
1242
1243 // end-sanitize-v850e
1244 // start-sanitize-v850e
1245 // ZXH
1246 00000000110,RRRRR:I:::zxh
1247 *v850e
1248 // start-sanitize-v850eq
1249 *v850eq
1250 // end-sanitize-v850eq
1251 "zxh r<reg1>"
1252 {
1253   TRACE_ALU_INPUT1 (GR[reg1]);
1254   GR[reg1] = GR[reg1] & 0xffff;
1255   TRACE_ALU_RESULT (GR[reg1]);
1256 }
1257
1258
1259
1260 // end-sanitize-v850e
1261 // Special - breakpoint - illegal
1262 // Hopefully, in the future, this instruction will go away
1263 1111111111111111 + 1111111111111111:Z:::breakpoint
1264 *v850
1265 {
1266   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1267 }
1268
1269 // start-sanitize-v850e
1270 // First field could be any nonzero value.
1271 11111,000010,00000:I:::break
1272 {
1273   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1274 }
1275
1276 // end-sanitize-v850e
1277
1278
1279 // start-sanitize-v850eq
1280 // DIVHN
1281 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1282 *v850eq
1283 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1284 {
1285   signed32 quotient;
1286   signed32 remainder;
1287   signed32 divide_by;
1288   signed32 divide_this;
1289   boolean overflow = false;
1290   SAVE_2;
1291
1292   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1293
1294   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1295   divide_this = State.regs[ reg2 ];
1296
1297   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1298
1299   State.regs[ reg2 ] = quotient;
1300   State.regs[ reg3 ] = remainder;
1301
1302   /* Set condition codes.  */
1303   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1304
1305   if (overflow)      PSW |= PSW_OV;
1306   if (quotient == 0) PSW |= PSW_Z;
1307   if (quotient <  0) PSW |= PSW_S;
1308
1309   trace_output (OP_IMM_REG_REG_REG);
1310 }
1311
1312
1313
1314 // DIVHUN
1315 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1316 *v850eq
1317 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1318 {
1319   signed32 quotient;
1320   signed32 remainder;
1321   signed32 divide_by;
1322   signed32 divide_this;
1323   boolean overflow = false;
1324   SAVE_2;
1325
1326   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1327
1328   divide_by   = State.regs[ reg1 ] & 0xffff;
1329   divide_this = State.regs[ reg2 ];
1330
1331   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1332
1333   State.regs[ reg2 ] = quotient;
1334   State.regs[ reg3 ] = remainder;
1335
1336   /* Set condition codes.  */
1337   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1338
1339   if (overflow)      PSW |= PSW_OV;
1340   if (quotient == 0) PSW |= PSW_Z;
1341   if (quotient & 0x80000000) PSW |= PSW_S;
1342
1343   trace_output (OP_IMM_REG_REG_REG);
1344 }
1345
1346
1347
1348 // DIVN
1349 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1350 *v850eq
1351 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1352 {
1353   signed32 quotient;
1354   signed32 remainder;
1355   signed32 divide_by;
1356   signed32 divide_this;
1357   boolean overflow = false;
1358   SAVE_2;
1359
1360   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1361
1362   divide_by   = State.regs[ reg1 ];
1363   divide_this = State.regs[ reg2 ];
1364
1365   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1366
1367   State.regs[ reg2 ] = quotient;
1368   State.regs[ reg3 ] = remainder;
1369
1370   /* Set condition codes.  */
1371   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1372
1373   if (overflow)      PSW |= PSW_OV;
1374   if (quotient == 0) PSW |= PSW_Z;
1375   if (quotient <  0) PSW |= PSW_S;
1376
1377   trace_output (OP_IMM_REG_REG_REG);
1378 }
1379
1380
1381
1382 // DIVUN
1383 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1384 *v850eq
1385 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1386 {
1387   signed32 quotient;
1388   signed32 remainder;
1389   signed32 divide_by;
1390   signed32 divide_this;
1391   boolean overflow = false;
1392   SAVE_2;
1393
1394   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1395
1396   divide_by   = State.regs[ reg1 ];
1397   divide_this = State.regs[ reg2 ];
1398
1399   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1400
1401   State.regs[ reg2 ] = quotient;
1402   State.regs[ reg3 ] = remainder;
1403
1404   /* Set condition codes.  */
1405   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1406
1407   if (overflow)      PSW |= PSW_OV;
1408   if (quotient == 0) PSW |= PSW_Z;
1409   if (quotient & 0x80000000) PSW |= PSW_S;
1410
1411   trace_output (OP_IMM_REG_REG_REG);
1412 }
1413
1414
1415
1416 // SDIVHN
1417 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1418 *v850eq
1419 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1420 {
1421   COMPAT_2 (OP_18007E0 ());
1422 }
1423
1424
1425
1426 // SDIVHUN
1427 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1428 *v850eq
1429 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1430 {
1431   COMPAT_2 (OP_18207E0 ());
1432 }
1433
1434
1435
1436 // SDIVN
1437 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1438 *v850eq
1439 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1440 {
1441   COMPAT_2 (OP_1C007E0 ());
1442 }
1443
1444
1445
1446 // SDIVUN
1447 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1448 *v850eq
1449 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1450 {
1451   COMPAT_2 (OP_1C207E0 ());
1452 }
1453
1454
1455
1456 // PUSHML
1457 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1458 *v850eq
1459 "pushml <list18>"
1460 {
1461   int i;
1462   SAVE_2;
1463
1464   trace_input ("pushml", OP_PUSHPOP3, 0);
1465
1466   /* Store the registers with lower number registers being placed at
1467      higher addresses.  */
1468
1469   for (i = 0; i < 15; i++)
1470     if ((OP[3] & (1 << type3_regs[ i ])))
1471       {
1472         SP -= 4;
1473         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1474       }
1475
1476   if (OP[3] & (1 << 3))
1477     {
1478       SP -= 4;
1479
1480       store_mem (SP & ~ 3, 4, PSW);
1481     }
1482
1483   if (OP[3] & (1 << 19))
1484     {
1485       SP -= 8;
1486
1487       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1488         {
1489           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1490           store_mem ( SP      & ~ 3, 4, FEPSW);
1491         }
1492       else
1493         {
1494           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1495           store_mem ( SP      & ~ 3, 4, EIPSW);
1496         }
1497     }
1498
1499   trace_output (OP_PUSHPOP2);
1500 }
1501
1502
1503
1504 // PUSHHML
1505 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1506 *v850eq
1507 "pushhml <list18>"
1508 {
1509   COMPAT_2 (OP_307E0 ());
1510 }
1511
1512
1513
1514 // POPML
1515 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1516 *v850eq
1517 "popml <list18>"
1518 {
1519   COMPAT_2 (OP_107F0 ());
1520 }
1521
1522
1523
1524 // POPMH
1525 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1526 *v850eq
1527 "popmh <list18>"
1528 {
1529   COMPAT_2 (OP_307F0 ());
1530 }
1531
1532
1533 // end-sanitize-v850eq