sound/firewire/digi00x/digi00x.h

   1 /*
   2  * digi00x.h - a part of driver for Digidesign Digi 002/003 family
   3  *
   4  * Copyright (c) 2014-2015 Takashi Sakamoto
   5  *
   6  * Licensed under the terms of the GNU General Public License, version 2.
   7  */
   8
   9 #ifndef SOUND_DIGI00X_H_INCLUDED
  10 #define SOUND_DIGI00X_H_INCLUDED
  11
  12 #include <linux/compat.h>
  13 #include <linux/device.h>
  14 #include <linux/firewire.h>
  15 #include <linux/module.h>
  16 #include <linux/mod_devicetable.h>
  17 #include <linux/delay.h>
  18 #include <linux/slab.h>
  19
  20 #include <sound/core.h>
  21 #include <sound/initval.h>
  22 #include <sound/info.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/firewire.h>
  26 #include <sound/hwdep.h>
  27
  28 #include "../lib.h"
  29 #include "../iso-resources.h"
  30 #include "../amdtp-stream.h"
  31
  32 struct snd_dg00x {
  33         struct snd_card *card;
  34         struct fw_unit *unit;
  35
  36         struct mutex mutex;
  37         spinlock_t lock;
  38
  39         struct amdtp_stream tx_stream;
  40         struct fw_iso_resources tx_resources;
  41
  42         struct amdtp_stream rx_stream;
  43         struct fw_iso_resources rx_resources;
  44
  45         unsigned int substreams_counter;
  46
  47         /* for uapi */
  48         int dev_lock_count;
  49         bool dev_lock_changed;
  50         wait_queue_head_t hwdep_wait;
  51
  52         /* For asynchronous messages. */
  53         struct fw_address_handler async_handler;
  54         u32 msg;
  55 };
  56
  57 #define DG00X_ADDR_BASE         0xffffe0000000ull
  58
  59 #define DG00X_OFFSET_STREAMING_STATE    0x0000
  60 #define DG00X_OFFSET_STREAMING_SET      0x0004
  61 #define DG00X_OFFSET_MIDI_CTL_ADDR      0x0008
  62 /* For LSB of the address               0x000c */
  63 /* unknown                              0x0010 */
  64 #define DG00X_OFFSET_MESSAGE_ADDR       0x0014
  65 /* For LSB of the address               0x0018 */
  66 /* unknown                              0x001c */
  67 /* unknown                              0x0020 */
  68 /* not used                     0x0024--0x00ff */
  69 #define DG00X_OFFSET_ISOC_CHANNELS      0x0100
  70 /* unknown                              0x0104 */
  71 /* unknown                              0x0108 */
  72 /* unknown                              0x010c */
  73 #define DG00X_OFFSET_LOCAL_RATE         0x0110
  74 #define DG00X_OFFSET_EXTERNAL_RATE      0x0114
  75 #define DG00X_OFFSET_CLOCK_SOURCE       0x0118
  76 #define DG00X_OFFSET_OPT_IFACE_MODE     0x011c
  77 /* unknown                              0x0120 */
  78 /* Mixer control on/off                 0x0124 */
  79 /* unknown                              0x0128 */
  80 #define DG00X_OFFSET_DETECT_EXTERNAL    0x012c
  81 /* unknown                              0x0138 */
  82 #define DG00X_OFFSET_MMC                0x0400
  83
  84 enum snd_dg00x_rate {
  85         SND_DG00X_RATE_44100 = 0,
  86         SND_DG00X_RATE_48000,
  87         SND_DG00X_RATE_88200,
  88         SND_DG00X_RATE_96000,
  89         SND_DG00X_RATE_COUNT,
  90 };
  91
  92 enum snd_dg00x_clock {
  93         SND_DG00X_CLOCK_INTERNAL = 0,
  94         SND_DG00X_CLOCK_SPDIF,
  95         SND_DG00X_CLOCK_ADAT,
  96         SND_DG00X_CLOCK_WORD,
  97         SND_DG00X_CLOCK_COUNT,
  98 };
  99
 100 enum snd_dg00x_optical_mode {
 101         SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
 102         SND_DG00X_OPT_IFACE_MODE_SPDIF,
 103         SND_DG00X_OPT_IFACE_MODE_COUNT,
 104 };
 105
 106 int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,
 107                    enum amdtp_stream_direction dir);
 108 int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
 109                              unsigned int pcm_channels,
 110                              unsigned int midi_ports);
 111 void amdtp_dot_reset(struct amdtp_stream *s);
 112 int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
 113                                      struct snd_pcm_runtime *runtime);
 114 void amdtp_dot_set_pcm_format(struct amdtp_stream *s, snd_pcm_format_t format);
 115
 116 int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
 117 int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
 118 void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);
 119
 120 extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
 121 extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
 122 int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
 123                                        unsigned int *rate);
 124 int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
 125                                     unsigned int *rate);
 126 int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
 127 int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
 128                                enum snd_dg00x_clock *clock);
 129 int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
 130                                           bool *detect);
 131 int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
 132 int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x, unsigned int rate);
 133 void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
 134 void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
 135 void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);
 136
 137 void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
 138 int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
 139 void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);
 140
 141 void snd_dg00x_proc_init(struct snd_dg00x *dg00x);
 142
 143 int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);
 144
 145 int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
 146 #endif