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[ALSA] cmipci: clean up struct cmipci_pcm
[deliverable/linux.git] / sound / pci / cmipci.c
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
40 #include <sound/sb.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
43
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
48 "{C-Media,CMI8738B},"
49 "{C-Media,CMI8338A},"
50 "{C-Media,CMI8338B}}");
51
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
54 #endif
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
64 #endif
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
81 #endif
82
83 /*
84 * CM8x38 registers definition
85 */
86
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
112
113 #define CM_REG_CHFORMAT 0x08
114
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
118
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
128
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
134
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
140
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
146
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
153
154 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
155 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
156 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
157 #define CM_SPDLOCKED 0x00000010
158
159 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
160 #define CM_CH1FMT_SHIFT 2
161 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
162 #define CM_CH0FMT_SHIFT 0
163
164 #define CM_REG_INT_HLDCLR 0x0C
165 #define CM_CHIP_MASK2 0xff000000
166 #define CM_CHIP_8768 0x20000000
167 #define CM_CHIP_055 0x08000000
168 #define CM_CHIP_039 0x04000000
169 #define CM_CHIP_039_6CH 0x01000000
170 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
171 #define CM_TDMA_INT_EN 0x00040000
172 #define CM_CH1_INT_EN 0x00020000
173 #define CM_CH0_INT_EN 0x00010000
174
175 #define CM_REG_INT_STATUS 0x10
176 #define CM_INTR 0x80000000
177 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
178 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
179 #define CM_UARTINT 0x00010000
180 #define CM_LTDMAINT 0x00008000
181 #define CM_HTDMAINT 0x00004000
182 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
183 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
184 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
185 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
186 #define CM_CH1BUSY 0x00000008
187 #define CM_CH0BUSY 0x00000004
188 #define CM_CHINT1 0x00000002
189 #define CM_CHINT0 0x00000001
190
191 #define CM_REG_LEGACY_CTRL 0x14
192 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
193 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
194 #define CM_VMPU_330 0x00000000
195 #define CM_VMPU_320 0x20000000
196 #define CM_VMPU_310 0x40000000
197 #define CM_VMPU_300 0x60000000
198 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
199 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
200 #define CM_VSBSEL_220 0x00000000
201 #define CM_VSBSEL_240 0x04000000
202 #define CM_VSBSEL_260 0x08000000
203 #define CM_VSBSEL_280 0x0C000000
204 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
205 #define CM_FMSEL_388 0x00000000
206 #define CM_FMSEL_3C8 0x01000000
207 #define CM_FMSEL_3E0 0x02000000
208 #define CM_FMSEL_3E8 0x03000000
209 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
210 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
211 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
212 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
213 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
214 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
215 #define CM_C_EECS 0x00040000
216 #define CM_C_EEDI46 0x00020000
217 #define CM_C_EECK46 0x00010000
218 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
219 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
220 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
221 #define CM_EXBASEN 0x00001000 /* external bass input enable */
222
223 #define CM_REG_MISC_CTRL 0x18
224 #define CM_PWD 0x80000000 /* power down */
225 #define CM_RESET 0x40000000
226 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
227 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
228 #define CM_TXVX 0x08000000 /* model 037? */
229 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
230 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
231 #define CM_SPDIF48K 0x01000000 /* write */
232 #define CM_SPATUS48K 0x01000000 /* read */
233 #define CM_ENDBDAC 0x00800000 /* enable double dac */
234 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
235 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
236 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
237 #define CM_FM_EN 0x00080000 /* enable legacy FM */
238 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
239 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
240 #define CM_VIDWPDSB 0x00010000 /* model 037? */
241 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
242 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
243 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
244 #define CM_VIDWPPRT 0x00002000 /* model 037? */
245 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
246 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
247 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
248 #define CM_ENCENTER 0x00000080
249 #define CM_FLINKON 0x00000080 /* force modem link detection on, model 037 */
250 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
251 #define CM_FLINKOFF 0x00000040 /* force modem link detection off, model 037 */
252 #define CM_UNKNOWN_18_5 0x00000020 /* ? */
253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255 #define CM_UPDDMA_2048 0x00000000
256 #define CM_UPDDMA_1024 0x00000004
257 #define CM_UPDDMA_512 0x00000008
258 #define CM_UPDDMA_256 0x0000000C
259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
262
263 #define CM_REG_TDMA_POSITION 0x1C
264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
266
267 /* byte */
268 #define CM_REG_MIXER0 0x20
269 #define CM_REG_SBVR 0x20 /* write: sb16 version */
270 #define CM_REG_DEV 0x20 /* read: hardware device version */
271
272 #define CM_REG_MIXER21 0x21
273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
276 #define CM_X_SB16 0x01 /* SB16 compatible */
277
278 #define CM_REG_SB16_DATA 0x22
279 #define CM_REG_SB16_ADDR 0x23
280
281 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
285
286 #define CM_REG_MIXER1 0x24
287 #define CM_FMMUTE 0x80 /* mute FM */
288 #define CM_FMMUTE_SHIFT 7
289 #define CM_WSMUTE 0x40 /* mute PCM */
290 #define CM_WSMUTE_SHIFT 6
291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292 #define CM_REAR2LIN_SHIFT 5
293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
294 #define CM_REAR2FRONT_SHIFT 4
295 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296 #define CM_WAVEINL_SHIFT 3
297 #define CM_WAVEINR 0x04 /* digical wave rec. right */
298 #define CM_WAVEINR_SHIFT 2
299 #define CM_X3DEN 0x02 /* 3D surround enable */
300 #define CM_X3DEN_SHIFT 1
301 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302 #define CM_CDPLAY_SHIFT 0
303
304 #define CM_REG_MIXER2 0x25
305 #define CM_RAUXREN 0x80 /* AUX right capture */
306 #define CM_RAUXREN_SHIFT 7
307 #define CM_RAUXLEN 0x40 /* AUX left capture */
308 #define CM_RAUXLEN_SHIFT 6
309 #define CM_VAUXRM 0x20 /* AUX right mute */
310 #define CM_VAUXRM_SHIFT 5
311 #define CM_VAUXLM 0x10 /* AUX left mute */
312 #define CM_VAUXLM_SHIFT 4
313 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314 #define CM_VADMIC_SHIFT 1
315 #define CM_MICGAINZ 0x01 /* mic boost */
316 #define CM_MICGAINZ_SHIFT 0
317
318 #define CM_REG_MIXER3 0x24
319 #define CM_REG_AUX_VOL 0x26
320 #define CM_VAUXL_MASK 0xf0
321 #define CM_VAUXR_MASK 0x0f
322
323 #define CM_REG_MISC 0x27
324 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
325 #define CM_XGPO1 0x20
326 // #define CM_XGPBIO 0x04
327 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
328 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
329 #define CM_SPDVALID 0x02 /* spdif input valid check */
330 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
331
332 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
333 /*
334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
335 * or identical with AC97 codec?
336 */
337 #define CM_REG_EXTERN_CODEC CM_REG_AC97
338
339 /*
340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
341 */
342 #define CM_REG_MPU_PCI 0x40
343
344 /*
345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
346 */
347 #define CM_REG_FM_PCI 0x50
348
349 /*
350 * access from SB-mixer port
351 */
352 #define CM_REG_EXTENT_IND 0xf0
353 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
354 #define CM_VPHONE_SHIFT 5
355 #define CM_VPHOM 0x10 /* Phone mute control */
356 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
357 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
358 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
359 #define CM_VADMIC3 0x01 /* Mic record boost */
360
361 /*
362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
364 * unit (readonly?).
365 */
366 #define CM_REG_PLL 0xf8
367
368 /*
369 * extended registers
370 */
371 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
372 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
373 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
374 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375
376 #define CM_REG_EXT_MISC 0x90
377 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
378 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
379 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
380 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
381 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
382 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
383 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
385
386 /*
387 * size of i/o region
388 */
389 #define CM_EXTENT_CODEC 0x100
390 #define CM_EXTENT_MIDI 0x2
391 #define CM_EXTENT_SYNTH 0x4
392
393
394 /*
395 * channels for playback / capture
396 */
397 #define CM_CH_PLAY 0
398 #define CM_CH_CAPT 1
399
400 /*
401 * flags to check device open/close
402 */
403 #define CM_OPEN_NONE 0
404 #define CM_OPEN_CH_MASK 0x01
405 #define CM_OPEN_DAC 0x10
406 #define CM_OPEN_ADC 0x20
407 #define CM_OPEN_SPDIF 0x40
408 #define CM_OPEN_MCHAN 0x80
409 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
412 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
413 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
414 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
415
416
417 #if CM_CH_PLAY == 1
418 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
419 #define CM_PLAYBACK_SPDF CM_SPDF_1
420 #define CM_CAPTURE_SPDF CM_SPDF_0
421 #else
422 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
423 #define CM_PLAYBACK_SPDF CM_SPDF_0
424 #define CM_CAPTURE_SPDF CM_SPDF_1
425 #endif
426
427
428 /*
429 * driver data
430 */
431
432 struct cmipci_pcm {
433 struct snd_pcm_substream *substream;
434 u8 running; /* dac/adc running? */
435 u8 fmt; /* format bits */
436 u8 is_dac;
437 unsigned int dma_size; /* in frames */
438 unsigned int shift;
439 unsigned int ch; /* channel (0/1) */
440 unsigned int offset; /* physical address of the buffer */
441 };
442
443 /* mixer elements toggled/resumed during ac3 playback */
444 struct cmipci_mixer_auto_switches {
445 const char *name; /* switch to toggle */
446 int toggle_on; /* value to change when ac3 mode */
447 };
448 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
449 {"PCM Playback Switch", 0},
450 {"IEC958 Output Switch", 1},
451 {"IEC958 Mix Analog", 0},
452 // {"IEC958 Out To DAC", 1}, // no longer used
453 {"IEC958 Loop", 0},
454 };
455 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
456
457 struct cmipci {
458 struct snd_card *card;
459
460 struct pci_dev *pci;
461 unsigned int device; /* device ID */
462 int irq;
463
464 unsigned long iobase;
465 unsigned int ctrl; /* FUNCTRL0 current value */
466
467 struct snd_pcm *pcm; /* DAC/ADC PCM */
468 struct snd_pcm *pcm2; /* 2nd DAC */
469 struct snd_pcm *pcm_spdif; /* SPDIF */
470
471 int chip_version;
472 int max_channels;
473 unsigned int can_ac3_sw: 1;
474 unsigned int can_ac3_hw: 1;
475 unsigned int can_multi_ch: 1;
476 unsigned int do_soft_ac3: 1;
477
478 unsigned int spdif_playback_avail: 1; /* spdif ready? */
479 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
480 int spdif_counter; /* for software AC3 */
481
482 unsigned int dig_status;
483 unsigned int dig_pcm_status;
484
485 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
486
487 int opened[2]; /* open mode */
488 struct mutex open_mutex;
489
490 unsigned int mixer_insensitive: 1;
491 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
492 int mixer_res_status[CM_SAVED_MIXERS];
493
494 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
495
496 /* external MIDI */
497 struct snd_rawmidi *rmidi;
498
499 #ifdef SUPPORT_JOYSTICK
500 struct gameport *gameport;
501 #endif
502
503 spinlock_t reg_lock;
504
505 #ifdef CONFIG_PM
506 unsigned int saved_regs[0x20];
507 unsigned char saved_mixers[0x20];
508 #endif
509 };
510
511
512 /* read/write operations for dword register */
513 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
514 {
515 outl(data, cm->iobase + cmd);
516 }
517
518 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
519 {
520 return inl(cm->iobase + cmd);
521 }
522
523 /* read/write operations for word register */
524 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
525 {
526 outw(data, cm->iobase + cmd);
527 }
528
529 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
530 {
531 return inw(cm->iobase + cmd);
532 }
533
534 /* read/write operations for byte register */
535 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
536 {
537 outb(data, cm->iobase + cmd);
538 }
539
540 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
541 {
542 return inb(cm->iobase + cmd);
543 }
544
545 /* bit operations for dword register */
546 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
547 {
548 unsigned int val, oval;
549 val = oval = inl(cm->iobase + cmd);
550 val |= flag;
551 if (val == oval)
552 return 0;
553 outl(val, cm->iobase + cmd);
554 return 1;
555 }
556
557 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
558 {
559 unsigned int val, oval;
560 val = oval = inl(cm->iobase + cmd);
561 val &= ~flag;
562 if (val == oval)
563 return 0;
564 outl(val, cm->iobase + cmd);
565 return 1;
566 }
567
568 /* bit operations for byte register */
569 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
570 {
571 unsigned char val, oval;
572 val = oval = inb(cm->iobase + cmd);
573 val |= flag;
574 if (val == oval)
575 return 0;
576 outb(val, cm->iobase + cmd);
577 return 1;
578 }
579
580 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
581 {
582 unsigned char val, oval;
583 val = oval = inb(cm->iobase + cmd);
584 val &= ~flag;
585 if (val == oval)
586 return 0;
587 outb(val, cm->iobase + cmd);
588 return 1;
589 }
590
591
592 /*
593 * PCM interface
594 */
595
596 /*
597 * calculate frequency
598 */
599
600 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
601
602 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
603 {
604 unsigned int i;
605
606 if (rate > 48000)
607 rate /= 2;
608 for (i = 0; i < ARRAY_SIZE(rates); i++) {
609 if (rates[i] == rate)
610 return i;
611 }
612 snd_BUG();
613 return 0;
614 }
615
616 #ifdef USE_VAR48KRATE
617 /*
618 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
619 * does it this way .. maybe not. Never get any information from C-Media about
620 * that <werner@suse.de>.
621 */
622 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
623 {
624 unsigned int delta, tolerance;
625 int xm, xn, xr;
626
627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
628 rate <<= 1;
629 *n = -1;
630 if (*r > 0xff)
631 goto out;
632 tolerance = rate*CM_TOLERANCE_RATE;
633
634 for (xn = (1+2); xn < (0x1f+2); xn++) {
635 for (xm = (1+2); xm < (0xff+2); xm++) {
636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
637
638 if (xr < rate)
639 delta = rate - xr;
640 else
641 delta = xr - rate;
642
643 /*
644 * If we found one, remember this,
645 * and try to find a closer one
646 */
647 if (delta < tolerance) {
648 tolerance = delta;
649 *m = xm - 2;
650 *n = xn - 2;
651 }
652 }
653 }
654 out:
655 return (*n > -1);
656 }
657
658 /*
659 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
660 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
661 * at the register CM_REG_FUNCTRL1 (0x04).
662 * Problem: other ways are also possible (any information about that?)
663 */
664 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
665 {
666 unsigned int reg = CM_REG_PLL + slot;
667 /*
668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
669 * for DSFC/ASFC (000 upto 111).
670 */
671
672 /* FIXME: Init (Do we've to set an other register first before programming?) */
673
674 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
675 snd_cmipci_write_b(cm, reg, rate>>8);
676 snd_cmipci_write_b(cm, reg, rate&0xff);
677
678 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
679 }
680 #endif /* USE_VAR48KRATE */
681
682 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
683 struct snd_pcm_hw_params *hw_params)
684 {
685 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
686 }
687
688 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *hw_params)
690 {
691 struct cmipci *cm = snd_pcm_substream_chip(substream);
692 if (params_channels(hw_params) > 2) {
693 mutex_lock(&cm->open_mutex);
694 if (cm->opened[CM_CH_PLAY]) {
695 mutex_unlock(&cm->open_mutex);
696 return -EBUSY;
697 }
698 /* reserve the channel A */
699 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
700 mutex_unlock(&cm->open_mutex);
701 }
702 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
703 }
704
705 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
706 {
707 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
710 udelay(10);
711 }
712
713 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
714 {
715 return snd_pcm_lib_free_pages(substream);
716 }
717
718
719 /*
720 */
721
722 static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
723 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
724 .count = 3,
725 .list = hw_channels,
726 .mask = 0,
727 };
728 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
729 .count = 4,
730 .list = hw_channels,
731 .mask = 0,
732 };
733 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
734 .count = 5,
735 .list = hw_channels,
736 .mask = 0,
737 };
738
739 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
740 {
741 if (channels > 2) {
742 if (!cm->can_multi_ch || !rec->ch)
743 return -EINVAL;
744 if (rec->fmt != 0x03) /* stereo 16bit only */
745 return -EINVAL;
746 }
747
748 if (cm->can_multi_ch) {
749 spin_lock_irq(&cm->reg_lock);
750 if (channels > 2) {
751 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
753 } else {
754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
756 }
757 if (channels == 8)
758 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
759 else
760 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 if (channels == 6) {
762 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
763 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
764 } else {
765 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
766 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
767 }
768 if (channels == 4)
769 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
770 else
771 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772 spin_unlock_irq(&cm->reg_lock);
773 }
774 return 0;
775 }
776
777
778 /*
779 * prepare playback/capture channel
780 * channel to be used must have been set in rec->ch.
781 */
782 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
783 struct snd_pcm_substream *substream)
784 {
785 unsigned int reg, freq, val;
786 unsigned int period_size;
787 struct snd_pcm_runtime *runtime = substream->runtime;
788
789 rec->fmt = 0;
790 rec->shift = 0;
791 if (snd_pcm_format_width(runtime->format) >= 16) {
792 rec->fmt |= 0x02;
793 if (snd_pcm_format_width(runtime->format) > 16)
794 rec->shift++; /* 24/32bit */
795 }
796 if (runtime->channels > 1)
797 rec->fmt |= 0x01;
798 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
799 snd_printd("cannot set dac channels\n");
800 return -EINVAL;
801 }
802
803 rec->offset = runtime->dma_addr;
804 /* buffer and period sizes in frame */
805 rec->dma_size = runtime->buffer_size << rec->shift;
806 period_size = runtime->period_size << rec->shift;
807 if (runtime->channels > 2) {
808 /* multi-channels */
809 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
810 period_size = (period_size * runtime->channels) / 2;
811 }
812
813 spin_lock_irq(&cm->reg_lock);
814
815 /* set buffer address */
816 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
817 snd_cmipci_write(cm, reg, rec->offset);
818 /* program sample counts */
819 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
820 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
821 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
822
823 /* set adc/dac flag */
824 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
825 if (rec->is_dac)
826 cm->ctrl &= ~val;
827 else
828 cm->ctrl |= val;
829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
831
832 /* set sample rate */
833 freq = snd_cmipci_rate_freq(runtime->rate);
834 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
835 if (rec->ch) {
836 val &= ~CM_DSFC_MASK;
837 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
838 } else {
839 val &= ~CM_ASFC_MASK;
840 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
841 }
842 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
843 //snd_printd("cmipci: functrl1 = %08x\n", val);
844
845 /* set format */
846 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
847 if (rec->ch) {
848 val &= ~CM_CH1FMT_MASK;
849 val |= rec->fmt << CM_CH1FMT_SHIFT;
850 } else {
851 val &= ~CM_CH0FMT_MASK;
852 val |= rec->fmt << CM_CH0FMT_SHIFT;
853 }
854 if (cm->chip_version == 68) {
855 if (runtime->rate == 88200)
856 val |= CM_CH0_SRATE_88K << (rec->ch * 2);
857 else
858 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
859 if (runtime->rate == 96000)
860 val |= CM_CH0_SRATE_96K << (rec->ch * 2);
861 else
862 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
863 }
864 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
865 //snd_printd("cmipci: chformat = %08x\n", val);
866
867 rec->running = 0;
868 spin_unlock_irq(&cm->reg_lock);
869
870 return 0;
871 }
872
873 /*
874 * PCM trigger/stop
875 */
876 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
877 int cmd)
878 {
879 unsigned int inthld, chen, reset, pause;
880 int result = 0;
881
882 inthld = CM_CH0_INT_EN << rec->ch;
883 chen = CM_CHEN0 << rec->ch;
884 reset = CM_RST_CH0 << rec->ch;
885 pause = CM_PAUSE0 << rec->ch;
886
887 spin_lock(&cm->reg_lock);
888 switch (cmd) {
889 case SNDRV_PCM_TRIGGER_START:
890 rec->running = 1;
891 /* set interrupt */
892 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
893 cm->ctrl |= chen;
894 /* enable channel */
895 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
896 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
897 break;
898 case SNDRV_PCM_TRIGGER_STOP:
899 rec->running = 0;
900 /* disable interrupt */
901 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
902 /* reset */
903 cm->ctrl &= ~chen;
904 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
905 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
906 break;
907 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
908 case SNDRV_PCM_TRIGGER_SUSPEND:
909 cm->ctrl |= pause;
910 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
911 break;
912 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
913 case SNDRV_PCM_TRIGGER_RESUME:
914 cm->ctrl &= ~pause;
915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
916 break;
917 default:
918 result = -EINVAL;
919 break;
920 }
921 spin_unlock(&cm->reg_lock);
922 return result;
923 }
924
925 /*
926 * return the current pointer
927 */
928 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
929 struct snd_pcm_substream *substream)
930 {
931 size_t ptr;
932 unsigned int reg;
933 if (!rec->running)
934 return 0;
935 #if 1 // this seems better..
936 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
937 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
938 ptr >>= rec->shift;
939 #else
940 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
941 ptr = snd_cmipci_read(cm, reg) - rec->offset;
942 ptr = bytes_to_frames(substream->runtime, ptr);
943 #endif
944 if (substream->runtime->channels > 2)
945 ptr = (ptr * 2) / substream->runtime->channels;
946 return ptr;
947 }
948
949 /*
950 * playback
951 */
952
953 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
954 int cmd)
955 {
956 struct cmipci *cm = snd_pcm_substream_chip(substream);
957 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
958 }
959
960 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
961 {
962 struct cmipci *cm = snd_pcm_substream_chip(substream);
963 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
964 }
965
966
967
968 /*
969 * capture
970 */
971
972 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
973 int cmd)
974 {
975 struct cmipci *cm = snd_pcm_substream_chip(substream);
976 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
977 }
978
979 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
980 {
981 struct cmipci *cm = snd_pcm_substream_chip(substream);
982 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
983 }
984
985
986 /*
987 * hw preparation for spdif
988 */
989
990 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
991 struct snd_ctl_elem_info *uinfo)
992 {
993 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
994 uinfo->count = 1;
995 return 0;
996 }
997
998 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
999 struct snd_ctl_elem_value *ucontrol)
1000 {
1001 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1002 int i;
1003
1004 spin_lock_irq(&chip->reg_lock);
1005 for (i = 0; i < 4; i++)
1006 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1007 spin_unlock_irq(&chip->reg_lock);
1008 return 0;
1009 }
1010
1011 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_value *ucontrol)
1013 {
1014 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1015 int i, change;
1016 unsigned int val;
1017
1018 val = 0;
1019 spin_lock_irq(&chip->reg_lock);
1020 for (i = 0; i < 4; i++)
1021 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1022 change = val != chip->dig_status;
1023 chip->dig_status = val;
1024 spin_unlock_irq(&chip->reg_lock);
1025 return change;
1026 }
1027
1028 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1029 {
1030 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1031 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1032 .info = snd_cmipci_spdif_default_info,
1033 .get = snd_cmipci_spdif_default_get,
1034 .put = snd_cmipci_spdif_default_put
1035 };
1036
1037 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1038 struct snd_ctl_elem_info *uinfo)
1039 {
1040 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1041 uinfo->count = 1;
1042 return 0;
1043 }
1044
1045 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1046 struct snd_ctl_elem_value *ucontrol)
1047 {
1048 ucontrol->value.iec958.status[0] = 0xff;
1049 ucontrol->value.iec958.status[1] = 0xff;
1050 ucontrol->value.iec958.status[2] = 0xff;
1051 ucontrol->value.iec958.status[3] = 0xff;
1052 return 0;
1053 }
1054
1055 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1056 {
1057 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1058 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1059 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1060 .info = snd_cmipci_spdif_mask_info,
1061 .get = snd_cmipci_spdif_mask_get,
1062 };
1063
1064 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1065 struct snd_ctl_elem_info *uinfo)
1066 {
1067 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1068 uinfo->count = 1;
1069 return 0;
1070 }
1071
1072 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1074 {
1075 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1076 int i;
1077
1078 spin_lock_irq(&chip->reg_lock);
1079 for (i = 0; i < 4; i++)
1080 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1081 spin_unlock_irq(&chip->reg_lock);
1082 return 0;
1083 }
1084
1085 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1087 {
1088 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1089 int i, change;
1090 unsigned int val;
1091
1092 val = 0;
1093 spin_lock_irq(&chip->reg_lock);
1094 for (i = 0; i < 4; i++)
1095 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1096 change = val != chip->dig_pcm_status;
1097 chip->dig_pcm_status = val;
1098 spin_unlock_irq(&chip->reg_lock);
1099 return change;
1100 }
1101
1102 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1103 {
1104 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1105 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1106 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1107 .info = snd_cmipci_spdif_stream_info,
1108 .get = snd_cmipci_spdif_stream_get,
1109 .put = snd_cmipci_spdif_stream_put
1110 };
1111
1112 /*
1113 */
1114
1115 /* save mixer setting and mute for AC3 playback */
1116 static int save_mixer_state(struct cmipci *cm)
1117 {
1118 if (! cm->mixer_insensitive) {
1119 struct snd_ctl_elem_value *val;
1120 unsigned int i;
1121
1122 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1123 if (!val)
1124 return -ENOMEM;
1125 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1126 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1127 if (ctl) {
1128 int event;
1129 memset(val, 0, sizeof(*val));
1130 ctl->get(ctl, val);
1131 cm->mixer_res_status[i] = val->value.integer.value[0];
1132 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1133 event = SNDRV_CTL_EVENT_MASK_INFO;
1134 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1135 ctl->put(ctl, val); /* toggle */
1136 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1137 }
1138 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1139 snd_ctl_notify(cm->card, event, &ctl->id);
1140 }
1141 }
1142 kfree(val);
1143 cm->mixer_insensitive = 1;
1144 }
1145 return 0;
1146 }
1147
1148
1149 /* restore the previously saved mixer status */
1150 static void restore_mixer_state(struct cmipci *cm)
1151 {
1152 if (cm->mixer_insensitive) {
1153 struct snd_ctl_elem_value *val;
1154 unsigned int i;
1155
1156 val = kmalloc(sizeof(*val), GFP_KERNEL);
1157 if (!val)
1158 return;
1159 cm->mixer_insensitive = 0; /* at first clear this;
1160 otherwise the changes will be ignored */
1161 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1162 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1163 if (ctl) {
1164 int event;
1165
1166 memset(val, 0, sizeof(*val));
1167 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1168 ctl->get(ctl, val);
1169 event = SNDRV_CTL_EVENT_MASK_INFO;
1170 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1171 val->value.integer.value[0] = cm->mixer_res_status[i];
1172 ctl->put(ctl, val);
1173 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1174 }
1175 snd_ctl_notify(cm->card, event, &ctl->id);
1176 }
1177 }
1178 kfree(val);
1179 }
1180 }
1181
1182 /* spinlock held! */
1183 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1184 {
1185 if (do_ac3) {
1186 /* AC3EN for 037 */
1187 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1188 /* AC3EN for 039 */
1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1190
1191 if (cm->can_ac3_hw) {
1192 /* SPD24SEL for 037, 0x02 */
1193 /* SPD24SEL for 039, 0x20, but cannot be set */
1194 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1195 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1196 } else { /* can_ac3_sw */
1197 /* SPD32SEL for 037 & 039, 0x20 */
1198 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1199 /* set 176K sample rate to fix 033 HW bug */
1200 if (cm->chip_version == 33) {
1201 if (rate >= 48000) {
1202 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1203 } else {
1204 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1205 }
1206 }
1207 }
1208
1209 } else {
1210 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1211 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1212
1213 if (cm->can_ac3_hw) {
1214 /* chip model >= 37 */
1215 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1216 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1217 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1218 } else {
1219 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1220 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1221 }
1222 } else {
1223 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1224 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1225 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1226 }
1227 }
1228 }
1229
1230 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1231 {
1232 int rate, err;
1233
1234 rate = subs->runtime->rate;
1235
1236 if (up && do_ac3)
1237 if ((err = save_mixer_state(cm)) < 0)
1238 return err;
1239
1240 spin_lock_irq(&cm->reg_lock);
1241 cm->spdif_playback_avail = up;
1242 if (up) {
1243 /* they are controlled via "IEC958 Output Switch" */
1244 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1245 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1246 if (cm->spdif_playback_enabled)
1247 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1248 setup_ac3(cm, subs, do_ac3, rate);
1249
1250 if (rate == 48000 || rate == 96000)
1251 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1252 else
1253 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1254 if (rate > 48000)
1255 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1256 else
1257 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1258 } else {
1259 /* they are controlled via "IEC958 Output Switch" */
1260 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1261 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1262 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1263 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1264 setup_ac3(cm, subs, 0, 0);
1265 }
1266 spin_unlock_irq(&cm->reg_lock);
1267 return 0;
1268 }
1269
1270
1271 /*
1272 * preparation
1273 */
1274
1275 /* playback - enable spdif only on the certain condition */
1276 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1277 {
1278 struct cmipci *cm = snd_pcm_substream_chip(substream);
1279 int rate = substream->runtime->rate;
1280 int err, do_spdif, do_ac3 = 0;
1281
1282 do_spdif = (rate >= 44100 &&
1283 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1284 substream->runtime->channels == 2);
1285 if (do_spdif && cm->can_ac3_hw)
1286 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1287 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1288 return err;
1289 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1290 }
1291
1292 /* playback (via device #2) - enable spdif always */
1293 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1294 {
1295 struct cmipci *cm = snd_pcm_substream_chip(substream);
1296 int err, do_ac3;
1297
1298 if (cm->can_ac3_hw)
1299 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1300 else
1301 do_ac3 = 1; /* doesn't matter */
1302 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1303 return err;
1304 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1305 }
1306
1307 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1308 {
1309 struct cmipci *cm = snd_pcm_substream_chip(substream);
1310 setup_spdif_playback(cm, substream, 0, 0);
1311 restore_mixer_state(cm);
1312 return snd_cmipci_hw_free(substream);
1313 }
1314
1315 /* capture */
1316 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1317 {
1318 struct cmipci *cm = snd_pcm_substream_chip(substream);
1319 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1320 }
1321
1322 /* capture with spdif (via device #2) */
1323 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1324 {
1325 struct cmipci *cm = snd_pcm_substream_chip(substream);
1326
1327 spin_lock_irq(&cm->reg_lock);
1328 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1329 spin_unlock_irq(&cm->reg_lock);
1330
1331 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1332 }
1333
1334 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1335 {
1336 struct cmipci *cm = snd_pcm_substream_chip(subs);
1337
1338 spin_lock_irq(&cm->reg_lock);
1339 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1340 spin_unlock_irq(&cm->reg_lock);
1341
1342 return snd_cmipci_hw_free(subs);
1343 }
1344
1345
1346 /*
1347 * interrupt handler
1348 */
1349 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1350 {
1351 struct cmipci *cm = dev_id;
1352 unsigned int status, mask = 0;
1353
1354 /* fastpath out, to ease interrupt sharing */
1355 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1356 if (!(status & CM_INTR))
1357 return IRQ_NONE;
1358
1359 /* acknowledge interrupt */
1360 spin_lock(&cm->reg_lock);
1361 if (status & CM_CHINT0)
1362 mask |= CM_CH0_INT_EN;
1363 if (status & CM_CHINT1)
1364 mask |= CM_CH1_INT_EN;
1365 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1366 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1367 spin_unlock(&cm->reg_lock);
1368
1369 if (cm->rmidi && (status & CM_UARTINT))
1370 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1371
1372 if (cm->pcm) {
1373 if ((status & CM_CHINT0) && cm->channel[0].running)
1374 snd_pcm_period_elapsed(cm->channel[0].substream);
1375 if ((status & CM_CHINT1) && cm->channel[1].running)
1376 snd_pcm_period_elapsed(cm->channel[1].substream);
1377 }
1378 return IRQ_HANDLED;
1379 }
1380
1381 /*
1382 * h/w infos
1383 */
1384
1385 /* playback on channel A */
1386 static struct snd_pcm_hardware snd_cmipci_playback =
1387 {
1388 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1389 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1390 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1391 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1392 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1393 .rate_min = 5512,
1394 .rate_max = 48000,
1395 .channels_min = 1,
1396 .channels_max = 2,
1397 .buffer_bytes_max = (128*1024),
1398 .period_bytes_min = 64,
1399 .period_bytes_max = (128*1024),
1400 .periods_min = 2,
1401 .periods_max = 1024,
1402 .fifo_size = 0,
1403 };
1404
1405 /* capture on channel B */
1406 static struct snd_pcm_hardware snd_cmipci_capture =
1407 {
1408 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1409 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1410 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1411 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1412 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1413 .rate_min = 5512,
1414 .rate_max = 48000,
1415 .channels_min = 1,
1416 .channels_max = 2,
1417 .buffer_bytes_max = (128*1024),
1418 .period_bytes_min = 64,
1419 .period_bytes_max = (128*1024),
1420 .periods_min = 2,
1421 .periods_max = 1024,
1422 .fifo_size = 0,
1423 };
1424
1425 /* playback on channel B - stereo 16bit only? */
1426 static struct snd_pcm_hardware snd_cmipci_playback2 =
1427 {
1428 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1429 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1430 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1431 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1432 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1433 .rate_min = 5512,
1434 .rate_max = 48000,
1435 .channels_min = 2,
1436 .channels_max = 2,
1437 .buffer_bytes_max = (128*1024),
1438 .period_bytes_min = 64,
1439 .period_bytes_max = (128*1024),
1440 .periods_min = 2,
1441 .periods_max = 1024,
1442 .fifo_size = 0,
1443 };
1444
1445 /* spdif playback on channel A */
1446 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1447 {
1448 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1449 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1450 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1451 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1452 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1453 .rate_min = 44100,
1454 .rate_max = 48000,
1455 .channels_min = 2,
1456 .channels_max = 2,
1457 .buffer_bytes_max = (128*1024),
1458 .period_bytes_min = 64,
1459 .period_bytes_max = (128*1024),
1460 .periods_min = 2,
1461 .periods_max = 1024,
1462 .fifo_size = 0,
1463 };
1464
1465 /* spdif playback on channel A (32bit, IEC958 subframes) */
1466 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1467 {
1468 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1469 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1470 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1471 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1472 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1473 .rate_min = 44100,
1474 .rate_max = 48000,
1475 .channels_min = 2,
1476 .channels_max = 2,
1477 .buffer_bytes_max = (128*1024),
1478 .period_bytes_min = 64,
1479 .period_bytes_max = (128*1024),
1480 .periods_min = 2,
1481 .periods_max = 1024,
1482 .fifo_size = 0,
1483 };
1484
1485 /* spdif capture on channel B */
1486 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1487 {
1488 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1489 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1490 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1491 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1492 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1493 .rate_min = 44100,
1494 .rate_max = 48000,
1495 .channels_min = 2,
1496 .channels_max = 2,
1497 .buffer_bytes_max = (128*1024),
1498 .period_bytes_min = 64,
1499 .period_bytes_max = (128*1024),
1500 .periods_min = 2,
1501 .periods_max = 1024,
1502 .fifo_size = 0,
1503 };
1504
1505 /*
1506 * check device open/close
1507 */
1508 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1509 {
1510 int ch = mode & CM_OPEN_CH_MASK;
1511
1512 /* FIXME: a file should wait until the device becomes free
1513 * when it's opened on blocking mode. however, since the current
1514 * pcm framework doesn't pass file pointer before actually opened,
1515 * we can't know whether blocking mode or not in open callback..
1516 */
1517 mutex_lock(&cm->open_mutex);
1518 if (cm->opened[ch]) {
1519 mutex_unlock(&cm->open_mutex);
1520 return -EBUSY;
1521 }
1522 cm->opened[ch] = mode;
1523 cm->channel[ch].substream = subs;
1524 if (! (mode & CM_OPEN_DAC)) {
1525 /* disable dual DAC mode */
1526 cm->channel[ch].is_dac = 0;
1527 spin_lock_irq(&cm->reg_lock);
1528 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1529 spin_unlock_irq(&cm->reg_lock);
1530 }
1531 mutex_unlock(&cm->open_mutex);
1532 return 0;
1533 }
1534
1535 static void close_device_check(struct cmipci *cm, int mode)
1536 {
1537 int ch = mode & CM_OPEN_CH_MASK;
1538
1539 mutex_lock(&cm->open_mutex);
1540 if (cm->opened[ch] == mode) {
1541 if (cm->channel[ch].substream) {
1542 snd_cmipci_ch_reset(cm, ch);
1543 cm->channel[ch].running = 0;
1544 cm->channel[ch].substream = NULL;
1545 }
1546 cm->opened[ch] = 0;
1547 if (! cm->channel[ch].is_dac) {
1548 /* enable dual DAC mode again */
1549 cm->channel[ch].is_dac = 1;
1550 spin_lock_irq(&cm->reg_lock);
1551 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1552 spin_unlock_irq(&cm->reg_lock);
1553 }
1554 }
1555 mutex_unlock(&cm->open_mutex);
1556 }
1557
1558 /*
1559 */
1560
1561 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1562 {
1563 struct cmipci *cm = snd_pcm_substream_chip(substream);
1564 struct snd_pcm_runtime *runtime = substream->runtime;
1565 int err;
1566
1567 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1568 return err;
1569 runtime->hw = snd_cmipci_playback;
1570 if (cm->chip_version == 68) {
1571 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1572 SNDRV_PCM_RATE_96000;
1573 runtime->hw.rate_max = 96000;
1574 }
1575 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1576 cm->dig_pcm_status = cm->dig_status;
1577 return 0;
1578 }
1579
1580 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1581 {
1582 struct cmipci *cm = snd_pcm_substream_chip(substream);
1583 struct snd_pcm_runtime *runtime = substream->runtime;
1584 int err;
1585
1586 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1587 return err;
1588 runtime->hw = snd_cmipci_capture;
1589 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1590 runtime->hw.rate_min = 41000;
1591 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1592 }
1593 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1594 return 0;
1595 }
1596
1597 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1598 {
1599 struct cmipci *cm = snd_pcm_substream_chip(substream);
1600 struct snd_pcm_runtime *runtime = substream->runtime;
1601 int err;
1602
1603 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1604 return err;
1605 runtime->hw = snd_cmipci_playback2;
1606 mutex_lock(&cm->open_mutex);
1607 if (! cm->opened[CM_CH_PLAY]) {
1608 if (cm->can_multi_ch) {
1609 runtime->hw.channels_max = cm->max_channels;
1610 if (cm->max_channels == 4)
1611 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1612 else if (cm->max_channels == 6)
1613 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1614 else if (cm->max_channels == 8)
1615 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1616 }
1617 }
1618 mutex_unlock(&cm->open_mutex);
1619 if (cm->chip_version == 68) {
1620 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1621 SNDRV_PCM_RATE_96000;
1622 runtime->hw.rate_max = 96000;
1623 }
1624 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1625 return 0;
1626 }
1627
1628 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1629 {
1630 struct cmipci *cm = snd_pcm_substream_chip(substream);
1631 struct snd_pcm_runtime *runtime = substream->runtime;
1632 int err;
1633
1634 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1635 return err;
1636 if (cm->can_ac3_hw) {
1637 runtime->hw = snd_cmipci_playback_spdif;
1638 if (cm->chip_version >= 37) {
1639 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1640 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1641 }
1642 if (cm->chip_version == 68) {
1643 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1644 SNDRV_PCM_RATE_96000;
1645 runtime->hw.rate_max = 96000;
1646 }
1647 } else {
1648 runtime->hw = snd_cmipci_playback_iec958_subframe;
1649 }
1650 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1651 cm->dig_pcm_status = cm->dig_status;
1652 return 0;
1653 }
1654
1655 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1656 {
1657 struct cmipci *cm = snd_pcm_substream_chip(substream);
1658 struct snd_pcm_runtime *runtime = substream->runtime;
1659 int err;
1660
1661 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1662 return err;
1663 runtime->hw = snd_cmipci_capture_spdif;
1664 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1665 return 0;
1666 }
1667
1668
1669 /*
1670 */
1671
1672 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1673 {
1674 struct cmipci *cm = snd_pcm_substream_chip(substream);
1675 close_device_check(cm, CM_OPEN_PLAYBACK);
1676 return 0;
1677 }
1678
1679 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1680 {
1681 struct cmipci *cm = snd_pcm_substream_chip(substream);
1682 close_device_check(cm, CM_OPEN_CAPTURE);
1683 return 0;
1684 }
1685
1686 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1687 {
1688 struct cmipci *cm = snd_pcm_substream_chip(substream);
1689 close_device_check(cm, CM_OPEN_PLAYBACK2);
1690 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1691 return 0;
1692 }
1693
1694 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1695 {
1696 struct cmipci *cm = snd_pcm_substream_chip(substream);
1697 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1698 return 0;
1699 }
1700
1701 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1702 {
1703 struct cmipci *cm = snd_pcm_substream_chip(substream);
1704 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1705 return 0;
1706 }
1707
1708
1709 /*
1710 */
1711
1712 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1713 .open = snd_cmipci_playback_open,
1714 .close = snd_cmipci_playback_close,
1715 .ioctl = snd_pcm_lib_ioctl,
1716 .hw_params = snd_cmipci_hw_params,
1717 .hw_free = snd_cmipci_playback_hw_free,
1718 .prepare = snd_cmipci_playback_prepare,
1719 .trigger = snd_cmipci_playback_trigger,
1720 .pointer = snd_cmipci_playback_pointer,
1721 };
1722
1723 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1724 .open = snd_cmipci_capture_open,
1725 .close = snd_cmipci_capture_close,
1726 .ioctl = snd_pcm_lib_ioctl,
1727 .hw_params = snd_cmipci_hw_params,
1728 .hw_free = snd_cmipci_hw_free,
1729 .prepare = snd_cmipci_capture_prepare,
1730 .trigger = snd_cmipci_capture_trigger,
1731 .pointer = snd_cmipci_capture_pointer,
1732 };
1733
1734 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1735 .open = snd_cmipci_playback2_open,
1736 .close = snd_cmipci_playback2_close,
1737 .ioctl = snd_pcm_lib_ioctl,
1738 .hw_params = snd_cmipci_playback2_hw_params,
1739 .hw_free = snd_cmipci_hw_free,
1740 .prepare = snd_cmipci_capture_prepare, /* channel B */
1741 .trigger = snd_cmipci_capture_trigger, /* channel B */
1742 .pointer = snd_cmipci_capture_pointer, /* channel B */
1743 };
1744
1745 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1746 .open = snd_cmipci_playback_spdif_open,
1747 .close = snd_cmipci_playback_spdif_close,
1748 .ioctl = snd_pcm_lib_ioctl,
1749 .hw_params = snd_cmipci_hw_params,
1750 .hw_free = snd_cmipci_playback_hw_free,
1751 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1752 .trigger = snd_cmipci_playback_trigger,
1753 .pointer = snd_cmipci_playback_pointer,
1754 };
1755
1756 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1757 .open = snd_cmipci_capture_spdif_open,
1758 .close = snd_cmipci_capture_spdif_close,
1759 .ioctl = snd_pcm_lib_ioctl,
1760 .hw_params = snd_cmipci_hw_params,
1761 .hw_free = snd_cmipci_capture_spdif_hw_free,
1762 .prepare = snd_cmipci_capture_spdif_prepare,
1763 .trigger = snd_cmipci_capture_trigger,
1764 .pointer = snd_cmipci_capture_pointer,
1765 };
1766
1767
1768 /*
1769 */
1770
1771 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1772 {
1773 struct snd_pcm *pcm;
1774 int err;
1775
1776 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1777 if (err < 0)
1778 return err;
1779
1780 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1781 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1782
1783 pcm->private_data = cm;
1784 pcm->info_flags = 0;
1785 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1786 cm->pcm = pcm;
1787
1788 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1789 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1790
1791 return 0;
1792 }
1793
1794 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1795 {
1796 struct snd_pcm *pcm;
1797 int err;
1798
1799 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1800 if (err < 0)
1801 return err;
1802
1803 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1804
1805 pcm->private_data = cm;
1806 pcm->info_flags = 0;
1807 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1808 cm->pcm2 = pcm;
1809
1810 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1811 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1812
1813 return 0;
1814 }
1815
1816 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1817 {
1818 struct snd_pcm *pcm;
1819 int err;
1820
1821 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1822 if (err < 0)
1823 return err;
1824
1825 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1826 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1827
1828 pcm->private_data = cm;
1829 pcm->info_flags = 0;
1830 strcpy(pcm->name, "C-Media PCI IEC958");
1831 cm->pcm_spdif = pcm;
1832
1833 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1834 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1835
1836 return 0;
1837 }
1838
1839 /*
1840 * mixer interface:
1841 * - CM8338/8738 has a compatible mixer interface with SB16, but
1842 * lack of some elements like tone control, i/o gain and AGC.
1843 * - Access to native registers:
1844 * - A 3D switch
1845 * - Output mute switches
1846 */
1847
1848 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1849 {
1850 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1851 outb(data, s->iobase + CM_REG_SB16_DATA);
1852 }
1853
1854 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1855 {
1856 unsigned char v;
1857
1858 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1859 v = inb(s->iobase + CM_REG_SB16_DATA);
1860 return v;
1861 }
1862
1863 /*
1864 * general mixer element
1865 */
1866 struct cmipci_sb_reg {
1867 unsigned int left_reg, right_reg;
1868 unsigned int left_shift, right_shift;
1869 unsigned int mask;
1870 unsigned int invert: 1;
1871 unsigned int stereo: 1;
1872 };
1873
1874 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1875 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1876
1877 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1878 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1879 .info = snd_cmipci_info_volume, \
1880 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1881 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1882 }
1883
1884 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1885 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1886 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1887 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1888
1889 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1890 {
1891 r->left_reg = val & 0xff;
1892 r->right_reg = (val >> 8) & 0xff;
1893 r->left_shift = (val >> 16) & 0x07;
1894 r->right_shift = (val >> 19) & 0x07;
1895 r->invert = (val >> 22) & 1;
1896 r->stereo = (val >> 23) & 1;
1897 r->mask = (val >> 24) & 0xff;
1898 }
1899
1900 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1901 struct snd_ctl_elem_info *uinfo)
1902 {
1903 struct cmipci_sb_reg reg;
1904
1905 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1906 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1907 uinfo->count = reg.stereo + 1;
1908 uinfo->value.integer.min = 0;
1909 uinfo->value.integer.max = reg.mask;
1910 return 0;
1911 }
1912
1913 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1914 struct snd_ctl_elem_value *ucontrol)
1915 {
1916 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1917 struct cmipci_sb_reg reg;
1918 int val;
1919
1920 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1921 spin_lock_irq(&cm->reg_lock);
1922 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1923 if (reg.invert)
1924 val = reg.mask - val;
1925 ucontrol->value.integer.value[0] = val;
1926 if (reg.stereo) {
1927 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1928 if (reg.invert)
1929 val = reg.mask - val;
1930 ucontrol->value.integer.value[1] = val;
1931 }
1932 spin_unlock_irq(&cm->reg_lock);
1933 return 0;
1934 }
1935
1936 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1937 struct snd_ctl_elem_value *ucontrol)
1938 {
1939 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1940 struct cmipci_sb_reg reg;
1941 int change;
1942 int left, right, oleft, oright;
1943
1944 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1945 left = ucontrol->value.integer.value[0] & reg.mask;
1946 if (reg.invert)
1947 left = reg.mask - left;
1948 left <<= reg.left_shift;
1949 if (reg.stereo) {
1950 right = ucontrol->value.integer.value[1] & reg.mask;
1951 if (reg.invert)
1952 right = reg.mask - right;
1953 right <<= reg.right_shift;
1954 } else
1955 right = 0;
1956 spin_lock_irq(&cm->reg_lock);
1957 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1958 left |= oleft & ~(reg.mask << reg.left_shift);
1959 change = left != oleft;
1960 if (reg.stereo) {
1961 if (reg.left_reg != reg.right_reg) {
1962 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1963 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1964 } else
1965 oright = left;
1966 right |= oright & ~(reg.mask << reg.right_shift);
1967 change |= right != oright;
1968 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1969 } else
1970 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1971 spin_unlock_irq(&cm->reg_lock);
1972 return change;
1973 }
1974
1975 /*
1976 * input route (left,right) -> (left,right)
1977 */
1978 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1979 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1980 .info = snd_cmipci_info_input_sw, \
1981 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1982 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1983 }
1984
1985 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1986 struct snd_ctl_elem_info *uinfo)
1987 {
1988 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1989 uinfo->count = 4;
1990 uinfo->value.integer.min = 0;
1991 uinfo->value.integer.max = 1;
1992 return 0;
1993 }
1994
1995 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
1996 struct snd_ctl_elem_value *ucontrol)
1997 {
1998 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1999 struct cmipci_sb_reg reg;
2000 int val1, val2;
2001
2002 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2003 spin_lock_irq(&cm->reg_lock);
2004 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2005 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2006 spin_unlock_irq(&cm->reg_lock);
2007 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2008 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2009 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2010 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2011 return 0;
2012 }
2013
2014 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2015 struct snd_ctl_elem_value *ucontrol)
2016 {
2017 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2018 struct cmipci_sb_reg reg;
2019 int change;
2020 int val1, val2, oval1, oval2;
2021
2022 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2023 spin_lock_irq(&cm->reg_lock);
2024 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2025 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2026 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2027 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2028 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2029 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2030 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2031 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2032 change = val1 != oval1 || val2 != oval2;
2033 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2034 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2035 spin_unlock_irq(&cm->reg_lock);
2036 return change;
2037 }
2038
2039 /*
2040 * native mixer switches/volumes
2041 */
2042
2043 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2044 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2045 .info = snd_cmipci_info_native_mixer, \
2046 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2047 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2048 }
2049
2050 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2051 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2052 .info = snd_cmipci_info_native_mixer, \
2053 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2054 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2055 }
2056
2057 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2058 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2059 .info = snd_cmipci_info_native_mixer, \
2060 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2061 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2062 }
2063
2064 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2065 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2066 .info = snd_cmipci_info_native_mixer, \
2067 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2068 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2069 }
2070
2071 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2072 struct snd_ctl_elem_info *uinfo)
2073 {
2074 struct cmipci_sb_reg reg;
2075
2076 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2077 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2078 uinfo->count = reg.stereo + 1;
2079 uinfo->value.integer.min = 0;
2080 uinfo->value.integer.max = reg.mask;
2081 return 0;
2082
2083 }
2084
2085 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2086 struct snd_ctl_elem_value *ucontrol)
2087 {
2088 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2089 struct cmipci_sb_reg reg;
2090 unsigned char oreg, val;
2091
2092 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2093 spin_lock_irq(&cm->reg_lock);
2094 oreg = inb(cm->iobase + reg.left_reg);
2095 val = (oreg >> reg.left_shift) & reg.mask;
2096 if (reg.invert)
2097 val = reg.mask - val;
2098 ucontrol->value.integer.value[0] = val;
2099 if (reg.stereo) {
2100 val = (oreg >> reg.right_shift) & reg.mask;
2101 if (reg.invert)
2102 val = reg.mask - val;
2103 ucontrol->value.integer.value[1] = val;
2104 }
2105 spin_unlock_irq(&cm->reg_lock);
2106 return 0;
2107 }
2108
2109 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2110 struct snd_ctl_elem_value *ucontrol)
2111 {
2112 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2113 struct cmipci_sb_reg reg;
2114 unsigned char oreg, nreg, val;
2115
2116 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2117 spin_lock_irq(&cm->reg_lock);
2118 oreg = inb(cm->iobase + reg.left_reg);
2119 val = ucontrol->value.integer.value[0] & reg.mask;
2120 if (reg.invert)
2121 val = reg.mask - val;
2122 nreg = oreg & ~(reg.mask << reg.left_shift);
2123 nreg |= (val << reg.left_shift);
2124 if (reg.stereo) {
2125 val = ucontrol->value.integer.value[1] & reg.mask;
2126 if (reg.invert)
2127 val = reg.mask - val;
2128 nreg &= ~(reg.mask << reg.right_shift);
2129 nreg |= (val << reg.right_shift);
2130 }
2131 outb(nreg, cm->iobase + reg.left_reg);
2132 spin_unlock_irq(&cm->reg_lock);
2133 return (nreg != oreg);
2134 }
2135
2136 /*
2137 * special case - check mixer sensitivity
2138 */
2139 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2140 struct snd_ctl_elem_value *ucontrol)
2141 {
2142 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2143 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2144 }
2145
2146 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2147 struct snd_ctl_elem_value *ucontrol)
2148 {
2149 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2150 if (cm->mixer_insensitive) {
2151 /* ignored */
2152 return 0;
2153 }
2154 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2155 }
2156
2157
2158 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2159 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2160 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2161 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2162 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2163 { /* switch with sensitivity */
2164 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2165 .name = "PCM Playback Switch",
2166 .info = snd_cmipci_info_native_mixer,
2167 .get = snd_cmipci_get_native_mixer_sensitive,
2168 .put = snd_cmipci_put_native_mixer_sensitive,
2169 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2170 },
2171 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2172 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2173 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2174 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2175 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2176 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2177 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2178 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2179 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2180 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2181 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2182 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2183 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2184 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2185 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2186 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2187 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2188 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2189 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2190 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2191 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2192 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2193 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2194 };
2195
2196 /*
2197 * other switches
2198 */
2199
2200 struct cmipci_switch_args {
2201 int reg; /* register index */
2202 unsigned int mask; /* mask bits */
2203 unsigned int mask_on; /* mask bits to turn on */
2204 unsigned int is_byte: 1; /* byte access? */
2205 unsigned int ac3_sensitive: 1; /* access forbidden during
2206 * non-audio operation?
2207 */
2208 };
2209
2210 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2211
2212 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2213 struct snd_ctl_elem_value *ucontrol,
2214 struct cmipci_switch_args *args)
2215 {
2216 unsigned int val;
2217 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2218
2219 spin_lock_irq(&cm->reg_lock);
2220 if (args->ac3_sensitive && cm->mixer_insensitive) {
2221 ucontrol->value.integer.value[0] = 0;
2222 spin_unlock_irq(&cm->reg_lock);
2223 return 0;
2224 }
2225 if (args->is_byte)
2226 val = inb(cm->iobase + args->reg);
2227 else
2228 val = snd_cmipci_read(cm, args->reg);
2229 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2230 spin_unlock_irq(&cm->reg_lock);
2231 return 0;
2232 }
2233
2234 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2235 struct snd_ctl_elem_value *ucontrol)
2236 {
2237 struct cmipci_switch_args *args;
2238 args = (struct cmipci_switch_args *)kcontrol->private_value;
2239 snd_assert(args != NULL, return -EINVAL);
2240 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2241 }
2242
2243 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol,
2245 struct cmipci_switch_args *args)
2246 {
2247 unsigned int val;
2248 int change;
2249 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2250
2251 spin_lock_irq(&cm->reg_lock);
2252 if (args->ac3_sensitive && cm->mixer_insensitive) {
2253 /* ignored */
2254 spin_unlock_irq(&cm->reg_lock);
2255 return 0;
2256 }
2257 if (args->is_byte)
2258 val = inb(cm->iobase + args->reg);
2259 else
2260 val = snd_cmipci_read(cm, args->reg);
2261 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2262 args->mask_on : (args->mask & ~args->mask_on));
2263 if (change) {
2264 val &= ~args->mask;
2265 if (ucontrol->value.integer.value[0])
2266 val |= args->mask_on;
2267 else
2268 val |= (args->mask & ~args->mask_on);
2269 if (args->is_byte)
2270 outb((unsigned char)val, cm->iobase + args->reg);
2271 else
2272 snd_cmipci_write(cm, args->reg, val);
2273 }
2274 spin_unlock_irq(&cm->reg_lock);
2275 return change;
2276 }
2277
2278 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2279 struct snd_ctl_elem_value *ucontrol)
2280 {
2281 struct cmipci_switch_args *args;
2282 args = (struct cmipci_switch_args *)kcontrol->private_value;
2283 snd_assert(args != NULL, return -EINVAL);
2284 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2285 }
2286
2287 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2288 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2289 .reg = xreg, \
2290 .mask = xmask, \
2291 .mask_on = xmask_on, \
2292 .is_byte = xis_byte, \
2293 .ac3_sensitive = xac3, \
2294 }
2295
2296 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2297 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2298
2299 #if 0 /* these will be controlled in pcm device */
2300 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2301 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2302 #endif
2303 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2304 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2305 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2306 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2307 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2308 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2309 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2310 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2311 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2312 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2313 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2314 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2315 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2316 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2317 #if CM_CH_PLAY == 1
2318 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2319 #else
2320 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2321 #endif
2322 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2323 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2324 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2325 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2326 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2327
2328 #define DEFINE_SWITCH(sname, stype, sarg) \
2329 { .name = sname, \
2330 .iface = stype, \
2331 .info = snd_cmipci_uswitch_info, \
2332 .get = snd_cmipci_uswitch_get, \
2333 .put = snd_cmipci_uswitch_put, \
2334 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2335 }
2336
2337 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2338 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2339
2340
2341 /*
2342 * callbacks for spdif output switch
2343 * needs toggle two registers..
2344 */
2345 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2346 struct snd_ctl_elem_value *ucontrol)
2347 {
2348 int changed;
2349 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2350 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2351 return changed;
2352 }
2353
2354 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2355 struct snd_ctl_elem_value *ucontrol)
2356 {
2357 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2358 int changed;
2359 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2360 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2361 if (changed) {
2362 if (ucontrol->value.integer.value[0]) {
2363 if (chip->spdif_playback_avail)
2364 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2365 } else {
2366 if (chip->spdif_playback_avail)
2367 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2368 }
2369 }
2370 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2371 return changed;
2372 }
2373
2374
2375 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2376 struct snd_ctl_elem_info *uinfo)
2377 {
2378 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2379 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2380 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2381 uinfo->count = 1;
2382 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2383 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2384 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2385 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2386 return 0;
2387 }
2388
2389 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2390 {
2391 unsigned int val;
2392 if (cm->chip_version >= 39) {
2393 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2394 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2395 return 2;
2396 }
2397 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2398 if (val & CM_REAR2LIN)
2399 return 1;
2400 return 0;
2401 }
2402
2403 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2404 struct snd_ctl_elem_value *ucontrol)
2405 {
2406 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2407
2408 spin_lock_irq(&cm->reg_lock);
2409 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2410 spin_unlock_irq(&cm->reg_lock);
2411 return 0;
2412 }
2413
2414 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2415 struct snd_ctl_elem_value *ucontrol)
2416 {
2417 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2418 int change;
2419
2420 spin_lock_irq(&cm->reg_lock);
2421 if (ucontrol->value.enumerated.item[0] == 2)
2422 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2423 else
2424 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2425 if (ucontrol->value.enumerated.item[0] == 1)
2426 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2427 else
2428 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2429 spin_unlock_irq(&cm->reg_lock);
2430 return change;
2431 }
2432
2433 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2434 struct snd_ctl_elem_info *uinfo)
2435 {
2436 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2437 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2438 uinfo->count = 1;
2439 uinfo->value.enumerated.items = 2;
2440 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2441 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2442 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2443 return 0;
2444 }
2445
2446 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2447 struct snd_ctl_elem_value *ucontrol)
2448 {
2449 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2450 /* same bit as spdi_phase */
2451 spin_lock_irq(&cm->reg_lock);
2452 ucontrol->value.enumerated.item[0] =
2453 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2454 spin_unlock_irq(&cm->reg_lock);
2455 return 0;
2456 }
2457
2458 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2459 struct snd_ctl_elem_value *ucontrol)
2460 {
2461 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2462 int change;
2463
2464 spin_lock_irq(&cm->reg_lock);
2465 if (ucontrol->value.enumerated.item[0])
2466 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2467 else
2468 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2469 spin_unlock_irq(&cm->reg_lock);
2470 return change;
2471 }
2472
2473 /* both for CM8338/8738 */
2474 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2475 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2476 {
2477 .name = "Line-In Mode",
2478 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2479 .info = snd_cmipci_line_in_mode_info,
2480 .get = snd_cmipci_line_in_mode_get,
2481 .put = snd_cmipci_line_in_mode_put,
2482 },
2483 };
2484
2485 /* for non-multichannel chips */
2486 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2487 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2488
2489 /* only for CM8738 */
2490 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2491 #if 0 /* controlled in pcm device */
2492 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2493 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2494 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2495 #endif
2496 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2497 { .name = "IEC958 Output Switch",
2498 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2499 .info = snd_cmipci_uswitch_info,
2500 .get = snd_cmipci_spdout_enable_get,
2501 .put = snd_cmipci_spdout_enable_put,
2502 },
2503 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2504 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2505 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2506 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2507 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2508 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2509 };
2510
2511 /* only for model 033/037 */
2512 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2513 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2514 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2515 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2516 };
2517
2518 /* only for model 039 or later */
2519 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2520 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2521 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2522 {
2523 .name = "Mic-In Mode",
2524 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2525 .info = snd_cmipci_mic_in_mode_info,
2526 .get = snd_cmipci_mic_in_mode_get,
2527 .put = snd_cmipci_mic_in_mode_put,
2528 }
2529 };
2530
2531 /* card control switches */
2532 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2533 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2534 DEFINE_CARD_SWITCH("Modem", modem),
2535 };
2536
2537
2538 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2539 {
2540 struct snd_card *card;
2541 struct snd_kcontrol_new *sw;
2542 struct snd_kcontrol *kctl;
2543 unsigned int idx;
2544 int err;
2545
2546 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2547
2548 card = cm->card;
2549
2550 strcpy(card->mixername, "CMedia PCI");
2551
2552 spin_lock_irq(&cm->reg_lock);
2553 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2554 spin_unlock_irq(&cm->reg_lock);
2555
2556 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2557 if (cm->chip_version == 68) { // 8768 has no PCM volume
2558 if (!strcmp(snd_cmipci_mixers[idx].name,
2559 "PCM Playback Volume"))
2560 continue;
2561 }
2562 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2563 return err;
2564 }
2565
2566 /* mixer switches */
2567 sw = snd_cmipci_mixer_switches;
2568 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2569 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2570 if (err < 0)
2571 return err;
2572 }
2573 if (! cm->can_multi_ch) {
2574 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2575 if (err < 0)
2576 return err;
2577 }
2578 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2579 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2580 sw = snd_cmipci_8738_mixer_switches;
2581 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2582 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2583 if (err < 0)
2584 return err;
2585 }
2586 if (cm->can_ac3_hw) {
2587 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2588 return err;
2589 kctl->id.device = pcm_spdif_device;
2590 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2591 return err;
2592 kctl->id.device = pcm_spdif_device;
2593 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2594 return err;
2595 kctl->id.device = pcm_spdif_device;
2596 }
2597 if (cm->chip_version <= 37) {
2598 sw = snd_cmipci_old_mixer_switches;
2599 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2600 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2601 if (err < 0)
2602 return err;
2603 }
2604 }
2605 }
2606 if (cm->chip_version >= 39) {
2607 sw = snd_cmipci_extra_mixer_switches;
2608 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2609 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2610 if (err < 0)
2611 return err;
2612 }
2613 }
2614
2615 /* card switches */
2616 sw = snd_cmipci_control_switches;
2617 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2618 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2619 if (err < 0)
2620 return err;
2621 }
2622
2623 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2624 struct snd_ctl_elem_id id;
2625 struct snd_kcontrol *ctl;
2626 memset(&id, 0, sizeof(id));
2627 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2628 strcpy(id.name, cm_saved_mixer[idx].name);
2629 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2630 cm->mixer_res_ctl[idx] = ctl;
2631 }
2632
2633 return 0;
2634 }
2635
2636
2637 /*
2638 * proc interface
2639 */
2640
2641 #ifdef CONFIG_PROC_FS
2642 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2643 struct snd_info_buffer *buffer)
2644 {
2645 struct cmipci *cm = entry->private_data;
2646 int i, v;
2647
2648 snd_iprintf(buffer, "%s\n", cm->card->longname);
2649 for (i = 0; i < 0x94; i++) {
2650 if (i == 0x28)
2651 i = 0x90;
2652 v = inb(cm->iobase + i);
2653 if (i % 4 == 0)
2654 snd_iprintf(buffer, "\n%02x:", i);
2655 snd_iprintf(buffer, " %02x", v);
2656 }
2657 snd_iprintf(buffer, "\n");
2658 }
2659
2660 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2661 {
2662 struct snd_info_entry *entry;
2663
2664 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2665 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2666 }
2667 #else /* !CONFIG_PROC_FS */
2668 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2669 #endif
2670
2671
2672 static struct pci_device_id snd_cmipci_ids[] = {
2673 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2674 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2675 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2676 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2677 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2678 {0,},
2679 };
2680
2681
2682 /*
2683 * check chip version and capabilities
2684 * driver name is modified according to the chip model
2685 */
2686 static void __devinit query_chip(struct cmipci *cm)
2687 {
2688 unsigned int detect;
2689
2690 /* check reg 0Ch, bit 24-31 */
2691 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2692 if (! detect) {
2693 /* check reg 08h, bit 24-28 */
2694 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2695 switch (detect) {
2696 case 0:
2697 cm->chip_version = 33;
2698 if (cm->do_soft_ac3)
2699 cm->can_ac3_sw = 1;
2700 else
2701 cm->can_ac3_hw = 1;
2702 break;
2703 case CM_CHIP_037:
2704 cm->chip_version = 37;
2705 cm->can_ac3_hw = 1;
2706 break;
2707 default:
2708 cm->chip_version = 39;
2709 cm->can_ac3_hw = 1;
2710 break;
2711 }
2712 cm->max_channels = 2;
2713 } else {
2714 if (detect & CM_CHIP_039) {
2715 cm->chip_version = 39;
2716 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2717 cm->max_channels = 6;
2718 else
2719 cm->max_channels = 4;
2720 } else if (detect & CM_CHIP_8768) {
2721 cm->chip_version = 68;
2722 cm->max_channels = 8;
2723 } else {
2724 cm->chip_version = 55;
2725 cm->max_channels = 6;
2726 }
2727 cm->can_ac3_hw = 1;
2728 cm->can_multi_ch = 1;
2729 }
2730 }
2731
2732 #ifdef SUPPORT_JOYSTICK
2733 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2734 {
2735 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2736 struct gameport *gp;
2737 struct resource *r = NULL;
2738 int i, io_port = 0;
2739
2740 if (joystick_port[dev] == 0)
2741 return -ENODEV;
2742
2743 if (joystick_port[dev] == 1) { /* auto-detect */
2744 for (i = 0; ports[i]; i++) {
2745 io_port = ports[i];
2746 r = request_region(io_port, 1, "CMIPCI gameport");
2747 if (r)
2748 break;
2749 }
2750 } else {
2751 io_port = joystick_port[dev];
2752 r = request_region(io_port, 1, "CMIPCI gameport");
2753 }
2754
2755 if (!r) {
2756 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2757 return -EBUSY;
2758 }
2759
2760 cm->gameport = gp = gameport_allocate_port();
2761 if (!gp) {
2762 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2763 release_and_free_resource(r);
2764 return -ENOMEM;
2765 }
2766 gameport_set_name(gp, "C-Media Gameport");
2767 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2768 gameport_set_dev_parent(gp, &cm->pci->dev);
2769 gp->io = io_port;
2770 gameport_set_port_data(gp, r);
2771
2772 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2773
2774 gameport_register_port(cm->gameport);
2775
2776 return 0;
2777 }
2778
2779 static void snd_cmipci_free_gameport(struct cmipci *cm)
2780 {
2781 if (cm->gameport) {
2782 struct resource *r = gameport_get_port_data(cm->gameport);
2783
2784 gameport_unregister_port(cm->gameport);
2785 cm->gameport = NULL;
2786
2787 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2788 release_and_free_resource(r);
2789 }
2790 }
2791 #else
2792 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2793 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2794 #endif
2795
2796 static int snd_cmipci_free(struct cmipci *cm)
2797 {
2798 if (cm->irq >= 0) {
2799 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2800 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2801 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2802 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2803 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2804 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2805 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2806
2807 /* reset mixer */
2808 snd_cmipci_mixer_write(cm, 0, 0);
2809
2810 synchronize_irq(cm->irq);
2811
2812 free_irq(cm->irq, cm);
2813 }
2814
2815 snd_cmipci_free_gameport(cm);
2816 pci_release_regions(cm->pci);
2817 pci_disable_device(cm->pci);
2818 kfree(cm);
2819 return 0;
2820 }
2821
2822 static int snd_cmipci_dev_free(struct snd_device *device)
2823 {
2824 struct cmipci *cm = device->device_data;
2825 return snd_cmipci_free(cm);
2826 }
2827
2828 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2829 {
2830 long iosynth;
2831 unsigned int val;
2832 struct snd_opl3 *opl3;
2833 int err;
2834
2835 if (!fm_port)
2836 goto disable_fm;
2837
2838 if (cm->chip_version >= 39) {
2839 /* first try FM regs in PCI port range */
2840 iosynth = cm->iobase + CM_REG_FM_PCI;
2841 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2842 OPL3_HW_OPL3, 1, &opl3);
2843 } else {
2844 err = -EIO;
2845 }
2846 if (err < 0) {
2847 /* then try legacy ports */
2848 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2849 iosynth = fm_port;
2850 switch (iosynth) {
2851 case 0x3E8: val |= CM_FMSEL_3E8; break;
2852 case 0x3E0: val |= CM_FMSEL_3E0; break;
2853 case 0x3C8: val |= CM_FMSEL_3C8; break;
2854 case 0x388: val |= CM_FMSEL_388; break;
2855 default:
2856 goto disable_fm;
2857 }
2858 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2859 /* enable FM */
2860 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2861
2862 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2863 OPL3_HW_OPL3, 0, &opl3) < 0) {
2864 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2865 "skipping...\n", iosynth);
2866 goto disable_fm;
2867 }
2868 }
2869 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2870 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2871 return err;
2872 }
2873 return 0;
2874
2875 disable_fm:
2876 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2877 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2878 return 0;
2879 }
2880
2881 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2882 int dev, struct cmipci **rcmipci)
2883 {
2884 struct cmipci *cm;
2885 int err;
2886 static struct snd_device_ops ops = {
2887 .dev_free = snd_cmipci_dev_free,
2888 };
2889 unsigned int val;
2890 long iomidi;
2891 int integrated_midi = 0;
2892 char modelstr[16];
2893 int pcm_index, pcm_spdif_index;
2894 static struct pci_device_id intel_82437vx[] = {
2895 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2896 { },
2897 };
2898
2899 *rcmipci = NULL;
2900
2901 if ((err = pci_enable_device(pci)) < 0)
2902 return err;
2903
2904 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2905 if (cm == NULL) {
2906 pci_disable_device(pci);
2907 return -ENOMEM;
2908 }
2909
2910 spin_lock_init(&cm->reg_lock);
2911 mutex_init(&cm->open_mutex);
2912 cm->device = pci->device;
2913 cm->card = card;
2914 cm->pci = pci;
2915 cm->irq = -1;
2916 cm->channel[0].ch = 0;
2917 cm->channel[1].ch = 1;
2918 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2919
2920 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2921 kfree(cm);
2922 pci_disable_device(pci);
2923 return err;
2924 }
2925 cm->iobase = pci_resource_start(pci, 0);
2926
2927 if (request_irq(pci->irq, snd_cmipci_interrupt,
2928 IRQF_SHARED, card->driver, cm)) {
2929 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2930 snd_cmipci_free(cm);
2931 return -EBUSY;
2932 }
2933 cm->irq = pci->irq;
2934
2935 pci_set_master(cm->pci);
2936
2937 /*
2938 * check chip version, max channels and capabilities
2939 */
2940
2941 cm->chip_version = 0;
2942 cm->max_channels = 2;
2943 cm->do_soft_ac3 = soft_ac3[dev];
2944
2945 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2946 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2947 query_chip(cm);
2948 /* added -MCx suffix for chip supporting multi-channels */
2949 if (cm->can_multi_ch)
2950 sprintf(cm->card->driver + strlen(cm->card->driver),
2951 "-MC%d", cm->max_channels);
2952 else if (cm->can_ac3_sw)
2953 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2954
2955 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2956 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2957
2958 #if CM_CH_PLAY == 1
2959 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2960 #else
2961 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2962 #endif
2963
2964 /* initialize codec registers */
2965 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
2966 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
2967 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2968 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2969 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2970 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2971 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2972
2973 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2974 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2975 #if CM_CH_PLAY == 1
2976 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2977 #else
2978 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2979 #endif
2980 if (cm->chip_version) {
2981 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
2982 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
2983 }
2984 /* Set Bus Master Request */
2985 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2986
2987 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2988 switch (pci->device) {
2989 case PCI_DEVICE_ID_CMEDIA_CM8738:
2990 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2991 if (!pci_dev_present(intel_82437vx))
2992 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2993 break;
2994 default:
2995 break;
2996 }
2997
2998 if (cm->chip_version < 68) {
2999 val = pci->device < 0x110 ? 8338 : 8738;
3000 } else {
3001 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3002 case 0:
3003 val = 8769;
3004 break;
3005 case 2:
3006 val = 8762;
3007 break;
3008 default:
3009 switch ((pci->subsystem_vendor << 16) |
3010 pci->subsystem_device) {
3011 case 0x13f69761:
3012 case 0x584d3741:
3013 case 0x584d3751:
3014 case 0x584d3761:
3015 case 0x584d3771:
3016 case 0x72848384:
3017 val = 8770;
3018 break;
3019 default:
3020 val = 8768;
3021 break;
3022 }
3023 }
3024 }
3025 sprintf(card->shortname, "C-Media CMI%d", val);
3026 if (cm->chip_version < 68)
3027 sprintf(modelstr, " (model %d)", cm->chip_version);
3028 else
3029 modelstr[0] = '\0';
3030 sprintf(card->longname, "%s%s at %#lx, irq %i",
3031 card->shortname, modelstr, cm->iobase, cm->irq);
3032
3033 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3034 snd_cmipci_free(cm);
3035 return err;
3036 }
3037
3038 if (cm->chip_version >= 39) {
3039 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3040 if (val != 0x00 && val != 0xff) {
3041 iomidi = cm->iobase + CM_REG_MPU_PCI;
3042 integrated_midi = 1;
3043 }
3044 }
3045 if (!integrated_midi) {
3046 val = 0;
3047 iomidi = mpu_port[dev];
3048 switch (iomidi) {
3049 case 0x320: val = CM_VMPU_320; break;
3050 case 0x310: val = CM_VMPU_310; break;
3051 case 0x300: val = CM_VMPU_300; break;
3052 case 0x330: val = CM_VMPU_330; break;
3053 default:
3054 iomidi = 0; break;
3055 }
3056 if (iomidi > 0) {
3057 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3058 /* enable UART */
3059 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3060 if (inb(iomidi + 1) == 0xff) {
3061 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3062 " at %#lx\n", iomidi);
3063 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3064 CM_UART_EN);
3065 iomidi = 0;
3066 }
3067 }
3068 }
3069
3070 if (cm->chip_version < 68) {
3071 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3072 if (err < 0)
3073 return err;
3074 }
3075
3076 /* reset mixer */
3077 snd_cmipci_mixer_write(cm, 0, 0);
3078
3079 snd_cmipci_proc_init(cm);
3080
3081 /* create pcm devices */
3082 pcm_index = pcm_spdif_index = 0;
3083 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3084 return err;
3085 pcm_index++;
3086 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3087 return err;
3088 pcm_index++;
3089 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3090 pcm_spdif_index = pcm_index;
3091 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3092 return err;
3093 }
3094
3095 /* create mixer interface & switches */
3096 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3097 return err;
3098
3099 if (iomidi > 0) {
3100 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3101 iomidi,
3102 (integrated_midi ?
3103 MPU401_INFO_INTEGRATED : 0),
3104 cm->irq, 0, &cm->rmidi)) < 0) {
3105 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3106 }
3107 }
3108
3109 #ifdef USE_VAR48KRATE
3110 for (val = 0; val < ARRAY_SIZE(rates); val++)
3111 snd_cmipci_set_pll(cm, rates[val], val);
3112
3113 /*
3114 * (Re-)Enable external switch spdo_48k
3115 */
3116 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3117 #endif /* USE_VAR48KRATE */
3118
3119 if (snd_cmipci_create_gameport(cm, dev) < 0)
3120 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3121
3122 snd_card_set_dev(card, &pci->dev);
3123
3124 *rcmipci = cm;
3125 return 0;
3126 }
3127
3128 /*
3129 */
3130
3131 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3132
3133 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3134 const struct pci_device_id *pci_id)
3135 {
3136 static int dev;
3137 struct snd_card *card;
3138 struct cmipci *cm;
3139 int err;
3140
3141 if (dev >= SNDRV_CARDS)
3142 return -ENODEV;
3143 if (! enable[dev]) {
3144 dev++;
3145 return -ENOENT;
3146 }
3147
3148 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3149 if (card == NULL)
3150 return -ENOMEM;
3151
3152 switch (pci->device) {
3153 case PCI_DEVICE_ID_CMEDIA_CM8738:
3154 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3155 strcpy(card->driver, "CMI8738");
3156 break;
3157 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3158 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3159 strcpy(card->driver, "CMI8338");
3160 break;
3161 default:
3162 strcpy(card->driver, "CMIPCI");
3163 break;
3164 }
3165
3166 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3167 snd_card_free(card);
3168 return err;
3169 }
3170 card->private_data = cm;
3171
3172 if ((err = snd_card_register(card)) < 0) {
3173 snd_card_free(card);
3174 return err;
3175 }
3176 pci_set_drvdata(pci, card);
3177 dev++;
3178 return 0;
3179
3180 }
3181
3182 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3183 {
3184 snd_card_free(pci_get_drvdata(pci));
3185 pci_set_drvdata(pci, NULL);
3186 }
3187
3188
3189 #ifdef CONFIG_PM
3190 /*
3191 * power management
3192 */
3193 static unsigned char saved_regs[] = {
3194 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3195 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3196 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3197 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3198 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3199 };
3200
3201 static unsigned char saved_mixers[] = {
3202 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3203 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3204 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3205 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3206 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3207 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3208 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3209 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3210 };
3211
3212 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3213 {
3214 struct snd_card *card = pci_get_drvdata(pci);
3215 struct cmipci *cm = card->private_data;
3216 int i;
3217
3218 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3219
3220 snd_pcm_suspend_all(cm->pcm);
3221 snd_pcm_suspend_all(cm->pcm2);
3222 snd_pcm_suspend_all(cm->pcm_spdif);
3223
3224 /* save registers */
3225 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3226 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3227 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3228 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3229
3230 /* disable ints */
3231 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3232
3233 pci_disable_device(pci);
3234 pci_save_state(pci);
3235 pci_set_power_state(pci, pci_choose_state(pci, state));
3236 return 0;
3237 }
3238
3239 static int snd_cmipci_resume(struct pci_dev *pci)
3240 {
3241 struct snd_card *card = pci_get_drvdata(pci);
3242 struct cmipci *cm = card->private_data;
3243 int i;
3244
3245 pci_set_power_state(pci, PCI_D0);
3246 pci_restore_state(pci);
3247 if (pci_enable_device(pci) < 0) {
3248 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3249 "disabling device\n");
3250 snd_card_disconnect(card);
3251 return -EIO;
3252 }
3253 pci_set_master(pci);
3254
3255 /* reset / initialize to a sane state */
3256 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3257 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3258 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3259 snd_cmipci_mixer_write(cm, 0, 0);
3260
3261 /* restore registers */
3262 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3263 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3264 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3265 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3266
3267 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3268 return 0;
3269 }
3270 #endif /* CONFIG_PM */
3271
3272 static struct pci_driver driver = {
3273 .name = "C-Media PCI",
3274 .id_table = snd_cmipci_ids,
3275 .probe = snd_cmipci_probe,
3276 .remove = __devexit_p(snd_cmipci_remove),
3277 #ifdef CONFIG_PM
3278 .suspend = snd_cmipci_suspend,
3279 .resume = snd_cmipci_resume,
3280 #endif
3281 };
3282
3283 static int __init alsa_card_cmipci_init(void)
3284 {
3285 return pci_register_driver(&driver);
3286 }
3287
3288 static void __exit alsa_card_cmipci_exit(void)
3289 {
3290 pci_unregister_driver(&driver);
3291 }
3292
3293 module_init(alsa_card_cmipci_init)
3294 module_exit(alsa_card_cmipci_exit)
Linux kernel - Deliverables
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