2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
5 * Routines for control of Cirrus Logic CS461x chips
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer control.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #include <linux/delay.h>
49 #include <linux/pci.h>
51 #include <linux/init.h>
52 #include <linux/interrupt.h>
53 #include <linux/slab.h>
54 #include <linux/gameport.h>
55 #include <linux/mutex.h>
56 #include <linux/export.h>
57 #include <linux/module.h>
58 #include <linux/firmware.h>
59 #include <linux/vmalloc.h>
61 #include <sound/core.h>
62 #include <sound/control.h>
63 #include <sound/info.h>
64 #include <sound/pcm.h>
65 #include <sound/pcm_params.h>
70 #include "cs46xx_lib.h"
73 static void amp_voyetra(struct snd_cs46xx
*chip
, int change
);
75 #ifdef CONFIG_SND_CS46XX_NEW_DSP
76 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops
;
77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops
;
78 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops
;
79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops
;
80 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops
;
81 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops
;
84 static struct snd_pcm_ops snd_cs46xx_playback_ops
;
85 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops
;
86 static struct snd_pcm_ops snd_cs46xx_capture_ops
;
87 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops
;
89 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx
*chip
,
94 unsigned short result
,tmp
;
97 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
98 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
101 chip
->active_ctrl(chip
, 1);
103 if (codec_index
== CS46XX_SECONDARY_CODEC_INDEX
)
104 offset
= CS46XX_SECONDARY_CODEC_OFFSET
;
107 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
108 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
109 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
110 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
111 * 5. if DCV not cleared, break and return error
112 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
115 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
117 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
118 if ((tmp
& ACCTL_VFRM
) == 0) {
119 snd_printk(KERN_WARNING
"cs46xx: ACCTL_VFRM not set 0x%x\n",tmp
);
120 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, (tmp
& (~ACCTL_ESYN
)) | ACCTL_VFRM
);
122 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
+ offset
);
123 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, tmp
| ACCTL_ESYN
| ACCTL_VFRM
);
128 * Setup the AC97 control registers on the CS461x to send the
129 * appropriate command to the AC97 to perform the read.
130 * ACCAD = Command Address Register = 46Ch
131 * ACCDA = Command Data Register = 470h
132 * ACCTL = Control Register = 460h
133 * set DCV - will clear when process completed
134 * set CRW - Read command
135 * set VFRM - valid frame enabled
136 * set ESYN - ASYNC generation enabled
137 * set RSTN - ARST# inactive, AC97 codec not reset
140 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
141 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, 0);
142 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
143 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
,/* clear ACCTL_DCV */ ACCTL_CRW
|
144 ACCTL_VFRM
| ACCTL_ESYN
|
146 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_CRW
|
147 ACCTL_VFRM
| ACCTL_ESYN
|
150 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
151 ACCTL_CRW
| ACCTL_VFRM
| ACCTL_ESYN
|
156 * Wait for the read to occur.
158 for (count
= 0; count
< 1000; count
++) {
160 * First, we want to wait for a short time.
164 * Now, check to see if the read has completed.
165 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
167 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
))
171 snd_printk(KERN_ERR
"AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg
);
177 * Wait for the valid status bit to go active.
179 for (count
= 0; count
< 100; count
++) {
181 * Read the AC97 status register.
182 * ACSTS = Status Register = 464h
183 * VSTS - Valid Status
185 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
+ offset
) & ACSTS_VSTS
)
190 snd_printk(KERN_ERR
"AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index
, reg
);
196 * Read the data returned from the AC97 register.
197 * ACSDA = Status Data Register = 474h
200 printk(KERN_DEBUG
"e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg
,
201 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
),
202 snd_cs46xx_peekBA0(chip
, BA0_ACCAD
));
205 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
206 result
= snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
208 chip
->active_ctrl(chip
, -1);
212 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97
* ac97
,
215 struct snd_cs46xx
*chip
= ac97
->private_data
;
217 int codec_index
= ac97
->num
;
219 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
220 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
223 val
= snd_cs46xx_codec_read(chip
, reg
, codec_index
);
229 static void snd_cs46xx_codec_write(struct snd_cs46xx
*chip
,
236 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
237 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
240 chip
->active_ctrl(chip
, 1);
243 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
244 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
245 * 3. Write ACCTL = Control Register = 460h for initiating the write
246 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
247 * 5. if DCV not cleared, break and return error
251 * Setup the AC97 control registers on the CS461x to send the
252 * appropriate command to the AC97 to perform the read.
253 * ACCAD = Command Address Register = 46Ch
254 * ACCDA = Command Data Register = 470h
255 * ACCTL = Control Register = 460h
256 * set DCV - will clear when process completed
257 * reset CRW - Write command
258 * set VFRM - valid frame enabled
259 * set ESYN - ASYNC generation enabled
260 * set RSTN - ARST# inactive, AC97 codec not reset
262 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
263 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, val
);
264 snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
266 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
267 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, /* clear ACCTL_DCV */ ACCTL_VFRM
|
268 ACCTL_ESYN
| ACCTL_RSTN
);
269 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_VFRM
|
270 ACCTL_ESYN
| ACCTL_RSTN
);
272 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
273 ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
276 for (count
= 0; count
< 4000; count
++) {
278 * First, we want to wait for a short time.
282 * Now, check to see if the write has completed.
283 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
285 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
)) {
289 snd_printk(KERN_ERR
"AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index
, reg
, val
);
291 chip
->active_ctrl(chip
, -1);
294 static void snd_cs46xx_ac97_write(struct snd_ac97
*ac97
,
298 struct snd_cs46xx
*chip
= ac97
->private_data
;
299 int codec_index
= ac97
->num
;
301 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
302 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
305 snd_cs46xx_codec_write(chip
, reg
, val
, codec_index
);
310 * Chip initialization
313 int snd_cs46xx_download(struct snd_cs46xx
*chip
,
315 unsigned long offset
,
319 unsigned int bank
= offset
>> 16;
320 offset
= offset
& 0xffff;
322 if (snd_BUG_ON((offset
& 3) || (len
& 3)))
324 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
327 /* writel already converts 32-bit value to right endianess */
335 static inline void memcpy_le32(void *dst
, const void *src
, unsigned int len
)
337 #ifdef __LITTLE_ENDIAN
338 memcpy(dst
, src
, len
);
341 const __le32
*_src
= src
;
344 *_dst
++ = le32_to_cpu(*_src
++);
348 #ifdef CONFIG_SND_CS46XX_NEW_DSP
350 static const char *module_names
[CS46XX_DSP_MODULES
] = {
351 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
354 MODULE_FIRMWARE("cs46xx/cwc4630");
355 MODULE_FIRMWARE("cs46xx/cwcasync");
356 MODULE_FIRMWARE("cs46xx/cwcsnoop");
357 MODULE_FIRMWARE("cs46xx/cwcbinhack");
358 MODULE_FIRMWARE("cs46xx/cwcdma");
360 static void free_module_desc(struct dsp_module_desc
*module
)
364 kfree(module
->module_name
);
365 kfree(module
->symbol_table
.symbols
);
366 if (module
->segments
) {
368 for (i
= 0; i
< module
->nsegments
; i
++)
369 kfree(module
->segments
[i
].data
);
370 kfree(module
->segments
);
374 /* firmware binary format:
378 * char symbol_name[DSP_MAX_SYMBOL_NAME];
380 * } symbols[nsymbols];
387 * } segments[nsegments];
390 static int load_firmware(struct snd_cs46xx
*chip
,
391 struct dsp_module_desc
**module_ret
,
395 unsigned int nums
, fwlen
, fwsize
;
397 struct dsp_module_desc
*module
= NULL
;
398 const struct firmware
*fw
;
401 sprintf(fw_path
, "cs46xx/%s", fw_name
);
402 err
= request_firmware(&fw
, fw_path
, &chip
->pci
->dev
);
405 fwsize
= fw
->size
/ 4;
412 module
= kzalloc(sizeof(*module
), GFP_KERNEL
);
415 module
->module_name
= kstrdup(fw_name
, GFP_KERNEL
);
416 if (!module
->module_name
)
420 fwdat
= (const __le32
*)fw
->data
;
421 nums
= module
->symbol_table
.nsymbols
= le32_to_cpu(fwdat
[fwlen
++]);
424 module
->symbol_table
.symbols
=
425 kcalloc(nums
, sizeof(struct dsp_symbol_entry
), GFP_KERNEL
);
426 if (!module
->symbol_table
.symbols
)
428 for (i
= 0; i
< nums
; i
++) {
429 struct dsp_symbol_entry
*entry
=
430 &module
->symbol_table
.symbols
[i
];
431 if (fwlen
+ 2 + DSP_MAX_SYMBOL_NAME
/ 4 > fwsize
)
433 entry
->address
= le32_to_cpu(fwdat
[fwlen
++]);
434 memcpy(entry
->symbol_name
, &fwdat
[fwlen
], DSP_MAX_SYMBOL_NAME
- 1);
435 fwlen
+= DSP_MAX_SYMBOL_NAME
/ 4;
436 entry
->symbol_type
= le32_to_cpu(fwdat
[fwlen
++]);
441 nums
= module
->nsegments
= le32_to_cpu(fwdat
[fwlen
++]);
445 kcalloc(nums
, sizeof(struct dsp_segment_desc
), GFP_KERNEL
);
446 if (!module
->segments
)
448 for (i
= 0; i
< nums
; i
++) {
449 struct dsp_segment_desc
*entry
= &module
->segments
[i
];
450 if (fwlen
+ 3 > fwsize
)
452 entry
->segment_type
= le32_to_cpu(fwdat
[fwlen
++]);
453 entry
->offset
= le32_to_cpu(fwdat
[fwlen
++]);
454 entry
->size
= le32_to_cpu(fwdat
[fwlen
++]);
455 if (fwlen
+ entry
->size
> fwsize
)
457 entry
->data
= kmalloc(entry
->size
* 4, GFP_KERNEL
);
460 memcpy_le32(entry
->data
, &fwdat
[fwlen
], entry
->size
* 4);
461 fwlen
+= entry
->size
;
464 *module_ret
= module
;
465 release_firmware(fw
);
471 free_module_desc(module
);
472 release_firmware(fw
);
476 int snd_cs46xx_clear_BA1(struct snd_cs46xx
*chip
,
477 unsigned long offset
,
481 unsigned int bank
= offset
>> 16;
482 offset
= offset
& 0xffff;
484 if (snd_BUG_ON((offset
& 3) || (len
& 3)))
486 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
489 /* writel already converts 32-bit value to right endianess */
497 #else /* old DSP image */
503 } memory
[BA1_MEMORY_COUNT
];
504 u32 map
[BA1_DWORD_SIZE
];
507 MODULE_FIRMWARE("cs46xx/ba1");
509 static int load_firmware(struct snd_cs46xx
*chip
)
511 const struct firmware
*fw
;
514 err
= request_firmware(&fw
, "cs46xx/ba1", &chip
->pci
->dev
);
517 if (fw
->size
!= sizeof(*chip
->ba1
)) {
522 chip
->ba1
= vmalloc(sizeof(*chip
->ba1
));
528 memcpy_le32(chip
->ba1
, fw
->data
, sizeof(*chip
->ba1
));
532 for (i
= 0; i
< BA1_MEMORY_COUNT
; i
++)
533 size
+= chip
->ba1
->memory
[i
].size
;
534 if (size
> BA1_DWORD_SIZE
* 4)
538 release_firmware(fw
);
542 int snd_cs46xx_download_image(struct snd_cs46xx
*chip
)
545 unsigned int offset
= 0;
546 struct ba1_struct
*ba1
= chip
->ba1
;
548 for (idx
= 0; idx
< BA1_MEMORY_COUNT
; idx
++) {
549 err
= snd_cs46xx_download(chip
,
551 ba1
->memory
[idx
].offset
,
552 ba1
->memory
[idx
].size
);
555 offset
+= ba1
->memory
[idx
].size
>> 2;
559 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
565 static void snd_cs46xx_reset(struct snd_cs46xx
*chip
)
570 * Write the reset bit of the SP control register.
572 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RSTSP
);
575 * Write the control register.
577 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_DRQEN
);
580 * Clear the trap registers.
582 for (idx
= 0; idx
< 8; idx
++) {
583 snd_cs46xx_poke(chip
, BA1_DREG
, DREG_REGID_TRAP_SELECT
+ idx
);
584 snd_cs46xx_poke(chip
, BA1_TWPR
, 0xFFFF);
586 snd_cs46xx_poke(chip
, BA1_DREG
, 0);
589 * Set the frame timer to reflect the number of cycles per frame.
591 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
594 static int cs46xx_wait_for_fifo(struct snd_cs46xx
* chip
,int retry_timeout
)
598 * Make sure the previous FIFO write operation has completed.
600 for(i
= 0; i
< 50; i
++){
601 status
= snd_cs46xx_peekBA0(chip
, BA0_SERBST
);
603 if( !(status
& SERBST_WBSY
) )
606 mdelay(retry_timeout
);
609 if(status
& SERBST_WBSY
) {
610 snd_printk(KERN_ERR
"cs46xx: failure waiting for "
611 "FIFO command to complete\n");
618 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx
*chip
)
620 int idx
, powerdown
= 0;
624 * See if the devices are powered down. If so, we must power them up first
625 * or they will not respond.
627 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
628 if (!(tmp
& CLKCR1_SWCE
)) {
629 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
634 * We want to clear out the serial port FIFOs so we don't end up playing
635 * whatever random garbage happens to be in them. We fill the sample FIFOS
636 * with zero (silence).
638 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0);
641 * Fill all 256 sample FIFO locations.
643 for (idx
= 0; idx
< 0xFF; idx
++) {
645 * Make sure the previous FIFO write operation has completed.
647 if (cs46xx_wait_for_fifo(chip
,1)) {
648 snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx
);
651 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
656 * Write the serial port FIFO index.
658 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
660 * Tell the serial port to load the new value into the FIFO location.
662 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
665 * Now, if we powered up the devices, then power them back down again.
666 * This is kinda ugly, but should never happen.
669 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
672 static void snd_cs46xx_proc_start(struct snd_cs46xx
*chip
)
677 * Set the frame timer to reflect the number of cycles per frame.
679 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
681 * Turn on the run, run at frame, and DMA enable bits in the local copy of
682 * the SP control register.
684 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RUN
| SPCR_RUNFR
| SPCR_DRQEN
);
686 * Wait until the run at frame bit resets itself in the SP control
689 for (cnt
= 0; cnt
< 25; cnt
++) {
691 if (!(snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
))
695 if (snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
)
696 snd_printk(KERN_ERR
"SPCR_RUNFR never reset\n");
699 static void snd_cs46xx_proc_stop(struct snd_cs46xx
*chip
)
702 * Turn off the run, run at frame, and DMA enable bits in the local copy of
703 * the SP control register.
705 snd_cs46xx_poke(chip
, BA1_SPCR
, 0);
709 * Sample rate routines
712 #define GOF_PER_SEC 200
714 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx
*chip
, unsigned int rate
)
717 unsigned int tmp1
, tmp2
;
718 unsigned int phiIncr
;
719 unsigned int correctionPerGOF
, correctionPerSec
;
722 * Compute the values used to drive the actual sample rate conversion.
723 * The following formulas are being computed, using inline assembly
724 * since we need to use 64 bit arithmetic to compute the values:
726 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
727 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
729 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
730 * GOF_PER_SEC * correctionPerGOF
734 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
735 * correctionPerGOF:correctionPerSec =
736 * dividend:remainder(ulOther / GOF_PER_SEC)
739 phiIncr
= tmp1
/ 48000;
740 tmp1
-= phiIncr
* 48000;
745 tmp1
-= tmp2
* 48000;
746 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
747 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
748 correctionPerSec
= tmp1
;
751 * Fill in the SampleRateConverter control block.
753 spin_lock_irqsave(&chip
->reg_lock
, flags
);
754 snd_cs46xx_poke(chip
, BA1_PSRC
,
755 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
756 snd_cs46xx_poke(chip
, BA1_PPI
, phiIncr
);
757 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
760 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx
*chip
, unsigned int rate
)
763 unsigned int phiIncr
, coeffIncr
, tmp1
, tmp2
;
764 unsigned int correctionPerGOF
, correctionPerSec
, initialDelay
;
765 unsigned int frameGroupLength
, cnt
;
768 * We can only decimate by up to a factor of 1/9th the hardware rate.
769 * Correct the value if an attempt is made to stray outside that limit.
771 if ((rate
* 9) < 48000)
775 * We can not capture at at rate greater than the Input Rate (48000).
776 * Return an error if an attempt is made to stray outside that limit.
782 * Compute the values used to drive the actual sample rate conversion.
783 * The following formulas are being computed, using inline assembly
784 * since we need to use 64 bit arithmetic to compute the values:
786 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
787 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
788 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
790 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
791 * GOF_PER_SEC * correctionPerGOF
792 * initialDelay = ceil((24 * Fs,in) / Fs,out)
796 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
797 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
798 * correctionPerGOF:correctionPerSec =
799 * dividend:remainder(ulOther / GOF_PER_SEC)
800 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
804 coeffIncr
= tmp1
/ 48000;
805 tmp1
-= coeffIncr
* 48000;
808 coeffIncr
+= tmp1
/ 48000;
809 coeffIncr
^= 0xFFFFFFFF;
812 phiIncr
= tmp1
/ rate
;
813 tmp1
-= phiIncr
* rate
;
819 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
820 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
821 correctionPerSec
= tmp1
;
822 initialDelay
= ((48000 * 24) + rate
- 1) / rate
;
825 * Fill in the VariDecimate control block.
827 spin_lock_irqsave(&chip
->reg_lock
, flags
);
828 snd_cs46xx_poke(chip
, BA1_CSRC
,
829 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
830 snd_cs46xx_poke(chip
, BA1_CCI
, coeffIncr
);
831 snd_cs46xx_poke(chip
, BA1_CD
,
832 (((BA1_VARIDEC_BUF_1
+ (initialDelay
<< 2)) << 16) & 0xFFFF0000) | 0x80);
833 snd_cs46xx_poke(chip
, BA1_CPI
, phiIncr
);
834 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
837 * Figure out the frame group length for the write back task. Basically,
838 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
839 * the output sample rate.
841 frameGroupLength
= 1;
842 for (cnt
= 2; cnt
<= 64; cnt
*= 2) {
843 if (((rate
/ cnt
) * cnt
) != rate
)
844 frameGroupLength
*= 2;
846 if (((rate
/ 3) * 3) != rate
) {
847 frameGroupLength
*= 3;
849 for (cnt
= 5; cnt
<= 125; cnt
*= 5) {
850 if (((rate
/ cnt
) * cnt
) != rate
)
851 frameGroupLength
*= 5;
855 * Fill in the WriteBack control block.
857 spin_lock_irqsave(&chip
->reg_lock
, flags
);
858 snd_cs46xx_poke(chip
, BA1_CFG1
, frameGroupLength
);
859 snd_cs46xx_poke(chip
, BA1_CFG2
, (0x00800000 | frameGroupLength
));
860 snd_cs46xx_poke(chip
, BA1_CCST
, 0x0000FFFF);
861 snd_cs46xx_poke(chip
, BA1_CSPB
, ((65536 * rate
) / 24000));
862 snd_cs46xx_poke(chip
, (BA1_CSPB
+ 4), 0x0000FFFF);
863 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
870 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream
*substream
,
871 struct snd_pcm_indirect
*rec
, size_t bytes
)
873 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
874 struct snd_cs46xx_pcm
* cpcm
= runtime
->private_data
;
875 memcpy(cpcm
->hw_buf
.area
+ rec
->hw_data
, runtime
->dma_area
+ rec
->sw_data
, bytes
);
878 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream
*substream
)
880 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
881 struct snd_cs46xx_pcm
* cpcm
= runtime
->private_data
;
882 snd_pcm_indirect_playback_transfer(substream
, &cpcm
->pcm_rec
, snd_cs46xx_pb_trans_copy
);
886 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream
*substream
,
887 struct snd_pcm_indirect
*rec
, size_t bytes
)
889 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
890 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
891 memcpy(runtime
->dma_area
+ rec
->sw_data
,
892 chip
->capt
.hw_buf
.area
+ rec
->hw_data
, bytes
);
895 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream
*substream
)
897 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
898 snd_pcm_indirect_capture_transfer(substream
, &chip
->capt
.pcm_rec
, snd_cs46xx_cp_trans_copy
);
902 static snd_pcm_uframes_t
snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream
*substream
)
904 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
906 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
908 if (snd_BUG_ON(!cpcm
->pcm_channel
))
911 #ifdef CONFIG_SND_CS46XX_NEW_DSP
912 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
914 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
916 ptr
-= cpcm
->hw_buf
.addr
;
917 return ptr
>> cpcm
->shift
;
920 static snd_pcm_uframes_t
snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream
*substream
)
922 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
924 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
926 #ifdef CONFIG_SND_CS46XX_NEW_DSP
927 if (snd_BUG_ON(!cpcm
->pcm_channel
))
929 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
931 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
933 ptr
-= cpcm
->hw_buf
.addr
;
934 return snd_pcm_indirect_playback_pointer(substream
, &cpcm
->pcm_rec
, ptr
);
937 static snd_pcm_uframes_t
snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream
*substream
)
939 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
940 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
941 return ptr
>> chip
->capt
.shift
;
944 static snd_pcm_uframes_t
snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream
*substream
)
946 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
947 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
948 return snd_pcm_indirect_capture_pointer(substream
, &chip
->capt
.pcm_rec
, ptr
);
951 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream
*substream
,
954 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
955 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
958 #ifdef CONFIG_SND_CS46XX_NEW_DSP
959 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
960 if (! cpcm
->pcm_channel
) {
965 case SNDRV_PCM_TRIGGER_START
:
966 case SNDRV_PCM_TRIGGER_RESUME
:
967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
968 /* magic value to unmute PCM stream playback volume */
969 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
970 SCBVolumeCtrl
) << 2, 0x80008000);
972 if (cpcm
->pcm_channel
->unlinked
)
973 cs46xx_dsp_pcm_link(chip
,cpcm
->pcm_channel
);
975 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
976 snd_cs46xx_playback_transfer(substream
);
978 spin_lock(&chip
->reg_lock
);
979 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
980 snd_cs46xx_playback_transfer(substream
);
982 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
984 snd_cs46xx_poke(chip
, BA1_PCTL
, chip
->play_ctl
| tmp
);
986 spin_unlock(&chip
->reg_lock
);
989 case SNDRV_PCM_TRIGGER_STOP
:
990 case SNDRV_PCM_TRIGGER_SUSPEND
:
991 #ifdef CONFIG_SND_CS46XX_NEW_DSP
992 /* magic mute channel */
993 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
994 SCBVolumeCtrl
) << 2, 0xffffffff);
996 if (!cpcm
->pcm_channel
->unlinked
)
997 cs46xx_dsp_pcm_unlink(chip
,cpcm
->pcm_channel
);
999 spin_lock(&chip
->reg_lock
);
1001 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
1003 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
);
1005 spin_unlock(&chip
->reg_lock
);
1016 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream
*substream
,
1019 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1023 spin_lock(&chip
->reg_lock
);
1025 case SNDRV_PCM_TRIGGER_START
:
1026 case SNDRV_PCM_TRIGGER_RESUME
:
1027 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
1029 snd_cs46xx_poke(chip
, BA1_CCTL
, chip
->capt
.ctl
| tmp
);
1031 case SNDRV_PCM_TRIGGER_STOP
:
1032 case SNDRV_PCM_TRIGGER_SUSPEND
:
1033 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
1035 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
);
1041 spin_unlock(&chip
->reg_lock
);
1046 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1047 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx
*chip
, struct snd_cs46xx_pcm
*cpcm
,
1051 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1052 if ( cpcm
->pcm_channel
== NULL
) {
1053 cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
,
1054 cpcm
, cpcm
->hw_buf
.addr
,cpcm
->pcm_channel_id
);
1055 if (cpcm
->pcm_channel
== NULL
) {
1056 snd_printk(KERN_ERR
"cs46xx: failed to create virtual PCM channel\n");
1059 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
1061 /* if sample rate is changed */
1062 if ((int)cpcm
->pcm_channel
->sample_rate
!= sample_rate
) {
1063 int unlinked
= cpcm
->pcm_channel
->unlinked
;
1064 cs46xx_dsp_destroy_pcm_channel (chip
,cpcm
->pcm_channel
);
1066 if ( (cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
, cpcm
,
1068 cpcm
->pcm_channel_id
)) == NULL
) {
1069 snd_printk(KERN_ERR
"cs46xx: failed to re-create virtual PCM channel\n");
1073 if (!unlinked
) cs46xx_dsp_pcm_link (chip
,cpcm
->pcm_channel
);
1074 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
1082 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream
*substream
,
1083 struct snd_pcm_hw_params
*hw_params
)
1085 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1086 struct snd_cs46xx_pcm
*cpcm
;
1088 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1089 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1090 int sample_rate
= params_rate(hw_params
);
1091 int period_size
= params_period_bytes(hw_params
);
1093 cpcm
= runtime
->private_data
;
1095 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1096 if (snd_BUG_ON(!sample_rate
))
1099 mutex_lock(&chip
->spos_mutex
);
1101 if (_cs46xx_adjust_sample_rate (chip
,cpcm
,sample_rate
)) {
1102 mutex_unlock(&chip
->spos_mutex
);
1106 snd_BUG_ON(!cpcm
->pcm_channel
);
1107 if (!cpcm
->pcm_channel
) {
1108 mutex_unlock(&chip
->spos_mutex
);
1113 if (cs46xx_dsp_pcm_channel_set_period (chip
,cpcm
->pcm_channel
,period_size
)) {
1114 mutex_unlock(&chip
->spos_mutex
);
1118 snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
1119 period_size
, params_periods(hw_params
),
1120 params_buffer_bytes(hw_params
));
1123 if (params_periods(hw_params
) == CS46XX_FRAGS
) {
1124 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
1125 snd_pcm_lib_free_pages(substream
);
1126 runtime
->dma_area
= cpcm
->hw_buf
.area
;
1127 runtime
->dma_addr
= cpcm
->hw_buf
.addr
;
1128 runtime
->dma_bytes
= cpcm
->hw_buf
.bytes
;
1131 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1132 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
1133 substream
->ops
= &snd_cs46xx_playback_ops
;
1134 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
1135 substream
->ops
= &snd_cs46xx_playback_rear_ops
;
1136 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
1137 substream
->ops
= &snd_cs46xx_playback_clfe_ops
;
1138 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
1139 substream
->ops
= &snd_cs46xx_playback_iec958_ops
;
1144 substream
->ops
= &snd_cs46xx_playback_ops
;
1148 if (runtime
->dma_area
== cpcm
->hw_buf
.area
) {
1149 runtime
->dma_area
= NULL
;
1150 runtime
->dma_addr
= 0;
1151 runtime
->dma_bytes
= 0;
1153 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0) {
1154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1155 mutex_unlock(&chip
->spos_mutex
);
1160 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1161 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
1162 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
1163 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
1164 substream
->ops
= &snd_cs46xx_playback_indirect_rear_ops
;
1165 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
1166 substream
->ops
= &snd_cs46xx_playback_indirect_clfe_ops
;
1167 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
1168 substream
->ops
= &snd_cs46xx_playback_indirect_iec958_ops
;
1173 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
1178 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1179 mutex_unlock(&chip
->spos_mutex
);
1185 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream
*substream
)
1187 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1188 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1189 struct snd_cs46xx_pcm
*cpcm
;
1191 cpcm
= runtime
->private_data
;
1193 /* if play_back open fails, then this function
1194 is called and cpcm can actually be NULL here */
1195 if (!cpcm
) return -ENXIO
;
1197 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
1198 snd_pcm_lib_free_pages(substream
);
1200 runtime
->dma_area
= NULL
;
1201 runtime
->dma_addr
= 0;
1202 runtime
->dma_bytes
= 0;
1207 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream
*substream
)
1211 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1212 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1213 struct snd_cs46xx_pcm
*cpcm
;
1215 cpcm
= runtime
->private_data
;
1217 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1218 if (snd_BUG_ON(!cpcm
->pcm_channel
))
1221 pfie
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2 );
1222 pfie
&= ~0x0000f03f;
1225 pfie
= snd_cs46xx_peek(chip
, BA1_PFIE
);
1226 pfie
&= ~0x0000f03f;
1230 /* if to convert from stereo to mono */
1231 if (runtime
->channels
== 1) {
1235 /* if to convert from 8 bit to 16 bit */
1236 if (snd_pcm_format_width(runtime
->format
) == 8) {
1240 /* if to convert to unsigned */
1241 if (snd_pcm_format_unsigned(runtime
->format
))
1244 /* Never convert byte order when sample stream is 8 bit */
1245 if (snd_pcm_format_width(runtime
->format
) != 8) {
1246 /* convert from big endian to little endian */
1247 if (snd_pcm_format_big_endian(runtime
->format
))
1251 memset(&cpcm
->pcm_rec
, 0, sizeof(cpcm
->pcm_rec
));
1252 cpcm
->pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1253 cpcm
->pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< cpcm
->shift
;
1255 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1257 tmp
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2);
1259 tmp
|= (4 << cpcm
->shift
) - 1;
1260 /* playback transaction count register */
1261 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2, tmp
);
1263 /* playback format && interrupt enable */
1264 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2, pfie
| cpcm
->pcm_channel
->pcm_slot
);
1266 snd_cs46xx_poke(chip
, BA1_PBA
, cpcm
->hw_buf
.addr
);
1267 tmp
= snd_cs46xx_peek(chip
, BA1_PDTC
);
1269 tmp
|= (4 << cpcm
->shift
) - 1;
1270 snd_cs46xx_poke(chip
, BA1_PDTC
, tmp
);
1271 snd_cs46xx_poke(chip
, BA1_PFIE
, pfie
);
1272 snd_cs46xx_set_play_sample_rate(chip
, runtime
->rate
);
1278 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream
*substream
,
1279 struct snd_pcm_hw_params
*hw_params
)
1281 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1282 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1285 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1286 cs46xx_dsp_pcm_ostream_set_period (chip
, params_period_bytes(hw_params
));
1288 if (runtime
->periods
== CS46XX_FRAGS
) {
1289 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1290 snd_pcm_lib_free_pages(substream
);
1291 runtime
->dma_area
= chip
->capt
.hw_buf
.area
;
1292 runtime
->dma_addr
= chip
->capt
.hw_buf
.addr
;
1293 runtime
->dma_bytes
= chip
->capt
.hw_buf
.bytes
;
1294 substream
->ops
= &snd_cs46xx_capture_ops
;
1296 if (runtime
->dma_area
== chip
->capt
.hw_buf
.area
) {
1297 runtime
->dma_area
= NULL
;
1298 runtime
->dma_addr
= 0;
1299 runtime
->dma_bytes
= 0;
1301 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0)
1303 substream
->ops
= &snd_cs46xx_capture_indirect_ops
;
1309 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream
*substream
)
1311 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1312 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1314 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1315 snd_pcm_lib_free_pages(substream
);
1316 runtime
->dma_area
= NULL
;
1317 runtime
->dma_addr
= 0;
1318 runtime
->dma_bytes
= 0;
1323 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream
*substream
)
1325 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1326 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1328 snd_cs46xx_poke(chip
, BA1_CBA
, chip
->capt
.hw_buf
.addr
);
1329 chip
->capt
.shift
= 2;
1330 memset(&chip
->capt
.pcm_rec
, 0, sizeof(chip
->capt
.pcm_rec
));
1331 chip
->capt
.pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1332 chip
->capt
.pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< 2;
1333 snd_cs46xx_set_capture_sample_rate(chip
, runtime
->rate
);
1338 static irqreturn_t
snd_cs46xx_interrupt(int irq
, void *dev_id
)
1340 struct snd_cs46xx
*chip
= dev_id
;
1342 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1343 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
1346 struct snd_cs46xx_pcm
*cpcm
= NULL
;
1350 * Read the Interrupt Status Register to clear the interrupt
1352 status1
= snd_cs46xx_peekBA0(chip
, BA0_HISR
);
1353 if ((status1
& 0x7fffffff) == 0) {
1354 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1358 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1359 status2
= snd_cs46xx_peekBA0(chip
, BA0_HSR0
);
1361 for (i
= 0; i
< DSP_MAX_PCM_CHANNELS
; ++i
) {
1363 if ( status1
& (1 << i
) ) {
1364 if (i
== CS46XX_DSP_CAPTURE_CHANNEL
) {
1365 if (chip
->capt
.substream
)
1366 snd_pcm_period_elapsed(chip
->capt
.substream
);
1368 if (ins
->pcm_channels
[i
].active
&&
1369 ins
->pcm_channels
[i
].private_data
&&
1370 !ins
->pcm_channels
[i
].unlinked
) {
1371 cpcm
= ins
->pcm_channels
[i
].private_data
;
1372 snd_pcm_period_elapsed(cpcm
->substream
);
1377 if ( status2
& (1 << (i
- 16))) {
1378 if (ins
->pcm_channels
[i
].active
&&
1379 ins
->pcm_channels
[i
].private_data
&&
1380 !ins
->pcm_channels
[i
].unlinked
) {
1381 cpcm
= ins
->pcm_channels
[i
].private_data
;
1382 snd_pcm_period_elapsed(cpcm
->substream
);
1390 if ((status1
& HISR_VC0
) && chip
->playback_pcm
) {
1391 if (chip
->playback_pcm
->substream
)
1392 snd_pcm_period_elapsed(chip
->playback_pcm
->substream
);
1394 if ((status1
& HISR_VC1
) && chip
->pcm
) {
1395 if (chip
->capt
.substream
)
1396 snd_pcm_period_elapsed(chip
->capt
.substream
);
1400 if ((status1
& HISR_MIDI
) && chip
->rmidi
) {
1403 spin_lock(&chip
->reg_lock
);
1404 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_RBE
) == 0) {
1405 c
= snd_cs46xx_peekBA0(chip
, BA0_MIDRP
);
1406 if ((chip
->midcr
& MIDCR_RIE
) == 0)
1408 snd_rawmidi_receive(chip
->midi_input
, &c
, 1);
1410 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
1411 if ((chip
->midcr
& MIDCR_TIE
) == 0)
1413 if (snd_rawmidi_transmit(chip
->midi_output
, &c
, 1) != 1) {
1414 chip
->midcr
&= ~MIDCR_TIE
;
1415 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
1418 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, c
);
1420 spin_unlock(&chip
->reg_lock
);
1423 * EOI to the PCI part....reenables interrupts
1425 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1430 static struct snd_pcm_hardware snd_cs46xx_playback
=
1432 .info
= (SNDRV_PCM_INFO_MMAP
|
1433 SNDRV_PCM_INFO_INTERLEAVED
|
1434 SNDRV_PCM_INFO_BLOCK_TRANSFER
/*|*/
1435 /*SNDRV_PCM_INFO_RESUME*/),
1436 .formats
= (SNDRV_PCM_FMTBIT_S8
| SNDRV_PCM_FMTBIT_U8
|
1437 SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S16_BE
|
1438 SNDRV_PCM_FMTBIT_U16_LE
| SNDRV_PCM_FMTBIT_U16_BE
),
1439 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1444 .buffer_bytes_max
= (256 * 1024),
1445 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1446 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1447 .periods_min
= CS46XX_FRAGS
,
1448 .periods_max
= 1024,
1452 static struct snd_pcm_hardware snd_cs46xx_capture
=
1454 .info
= (SNDRV_PCM_INFO_MMAP
|
1455 SNDRV_PCM_INFO_INTERLEAVED
|
1456 SNDRV_PCM_INFO_BLOCK_TRANSFER
/*|*/
1457 /*SNDRV_PCM_INFO_RESUME*/),
1458 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1459 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1464 .buffer_bytes_max
= (256 * 1024),
1465 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1466 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1467 .periods_min
= CS46XX_FRAGS
,
1468 .periods_max
= 1024,
1472 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1474 static unsigned int period_sizes
[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1476 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes
= {
1477 .count
= ARRAY_SIZE(period_sizes
),
1478 .list
= period_sizes
,
1484 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime
*runtime
)
1486 kfree(runtime
->private_data
);
1489 static int _cs46xx_playback_open_channel (struct snd_pcm_substream
*substream
,int pcm_channel_id
)
1491 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1492 struct snd_cs46xx_pcm
* cpcm
;
1493 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1495 cpcm
= kzalloc(sizeof(*cpcm
), GFP_KERNEL
);
1498 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1499 PAGE_SIZE
, &cpcm
->hw_buf
) < 0) {
1504 runtime
->hw
= snd_cs46xx_playback
;
1505 runtime
->private_data
= cpcm
;
1506 runtime
->private_free
= snd_cs46xx_pcm_free_substream
;
1508 cpcm
->substream
= substream
;
1509 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1510 mutex_lock(&chip
->spos_mutex
);
1511 cpcm
->pcm_channel
= NULL
;
1512 cpcm
->pcm_channel_id
= pcm_channel_id
;
1515 snd_pcm_hw_constraint_list(runtime
, 0,
1516 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1517 &hw_constraints_period_sizes
);
1519 mutex_unlock(&chip
->spos_mutex
);
1521 chip
->playback_pcm
= cpcm
; /* HACK */
1524 if (chip
->accept_valid
)
1525 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1526 chip
->active_ctrl(chip
, 1);
1531 static int snd_cs46xx_playback_open(struct snd_pcm_substream
*substream
)
1533 snd_printdd("open front channel\n");
1534 return _cs46xx_playback_open_channel(substream
,DSP_PCM_MAIN_CHANNEL
);
1537 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1538 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream
*substream
)
1540 snd_printdd("open rear channel\n");
1542 return _cs46xx_playback_open_channel(substream
,DSP_PCM_REAR_CHANNEL
);
1545 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream
*substream
)
1547 snd_printdd("open center - LFE channel\n");
1549 return _cs46xx_playback_open_channel(substream
,DSP_PCM_CENTER_LFE_CHANNEL
);
1552 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream
*substream
)
1554 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1556 snd_printdd("open raw iec958 channel\n");
1558 mutex_lock(&chip
->spos_mutex
);
1559 cs46xx_iec958_pre_open (chip
);
1560 mutex_unlock(&chip
->spos_mutex
);
1562 return _cs46xx_playback_open_channel(substream
,DSP_IEC958_CHANNEL
);
1565 static int snd_cs46xx_playback_close(struct snd_pcm_substream
*substream
);
1567 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream
*substream
)
1570 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1572 snd_printdd("close raw iec958 channel\n");
1574 err
= snd_cs46xx_playback_close(substream
);
1576 mutex_lock(&chip
->spos_mutex
);
1577 cs46xx_iec958_post_close (chip
);
1578 mutex_unlock(&chip
->spos_mutex
);
1584 static int snd_cs46xx_capture_open(struct snd_pcm_substream
*substream
)
1586 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1588 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1589 PAGE_SIZE
, &chip
->capt
.hw_buf
) < 0)
1591 chip
->capt
.substream
= substream
;
1592 substream
->runtime
->hw
= snd_cs46xx_capture
;
1594 if (chip
->accept_valid
)
1595 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1597 chip
->active_ctrl(chip
, 1);
1599 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1600 snd_pcm_hw_constraint_list(substream
->runtime
, 0,
1601 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1602 &hw_constraints_period_sizes
);
1607 static int snd_cs46xx_playback_close(struct snd_pcm_substream
*substream
)
1609 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1610 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1611 struct snd_cs46xx_pcm
* cpcm
;
1613 cpcm
= runtime
->private_data
;
1615 /* when playback_open fails, then cpcm can be NULL */
1616 if (!cpcm
) return -ENXIO
;
1618 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1619 mutex_lock(&chip
->spos_mutex
);
1620 if (cpcm
->pcm_channel
) {
1621 cs46xx_dsp_destroy_pcm_channel(chip
,cpcm
->pcm_channel
);
1622 cpcm
->pcm_channel
= NULL
;
1624 mutex_unlock(&chip
->spos_mutex
);
1626 chip
->playback_pcm
= NULL
;
1629 cpcm
->substream
= NULL
;
1630 snd_dma_free_pages(&cpcm
->hw_buf
);
1631 chip
->active_ctrl(chip
, -1);
1636 static int snd_cs46xx_capture_close(struct snd_pcm_substream
*substream
)
1638 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1640 chip
->capt
.substream
= NULL
;
1641 snd_dma_free_pages(&chip
->capt
.hw_buf
);
1642 chip
->active_ctrl(chip
, -1);
1647 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1648 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops
= {
1649 .open
= snd_cs46xx_playback_open_rear
,
1650 .close
= snd_cs46xx_playback_close
,
1651 .ioctl
= snd_pcm_lib_ioctl
,
1652 .hw_params
= snd_cs46xx_playback_hw_params
,
1653 .hw_free
= snd_cs46xx_playback_hw_free
,
1654 .prepare
= snd_cs46xx_playback_prepare
,
1655 .trigger
= snd_cs46xx_playback_trigger
,
1656 .pointer
= snd_cs46xx_playback_direct_pointer
,
1659 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops
= {
1660 .open
= snd_cs46xx_playback_open_rear
,
1661 .close
= snd_cs46xx_playback_close
,
1662 .ioctl
= snd_pcm_lib_ioctl
,
1663 .hw_params
= snd_cs46xx_playback_hw_params
,
1664 .hw_free
= snd_cs46xx_playback_hw_free
,
1665 .prepare
= snd_cs46xx_playback_prepare
,
1666 .trigger
= snd_cs46xx_playback_trigger
,
1667 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1668 .ack
= snd_cs46xx_playback_transfer
,
1671 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops
= {
1672 .open
= snd_cs46xx_playback_open_clfe
,
1673 .close
= snd_cs46xx_playback_close
,
1674 .ioctl
= snd_pcm_lib_ioctl
,
1675 .hw_params
= snd_cs46xx_playback_hw_params
,
1676 .hw_free
= snd_cs46xx_playback_hw_free
,
1677 .prepare
= snd_cs46xx_playback_prepare
,
1678 .trigger
= snd_cs46xx_playback_trigger
,
1679 .pointer
= snd_cs46xx_playback_direct_pointer
,
1682 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops
= {
1683 .open
= snd_cs46xx_playback_open_clfe
,
1684 .close
= snd_cs46xx_playback_close
,
1685 .ioctl
= snd_pcm_lib_ioctl
,
1686 .hw_params
= snd_cs46xx_playback_hw_params
,
1687 .hw_free
= snd_cs46xx_playback_hw_free
,
1688 .prepare
= snd_cs46xx_playback_prepare
,
1689 .trigger
= snd_cs46xx_playback_trigger
,
1690 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1691 .ack
= snd_cs46xx_playback_transfer
,
1694 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops
= {
1695 .open
= snd_cs46xx_playback_open_iec958
,
1696 .close
= snd_cs46xx_playback_close_iec958
,
1697 .ioctl
= snd_pcm_lib_ioctl
,
1698 .hw_params
= snd_cs46xx_playback_hw_params
,
1699 .hw_free
= snd_cs46xx_playback_hw_free
,
1700 .prepare
= snd_cs46xx_playback_prepare
,
1701 .trigger
= snd_cs46xx_playback_trigger
,
1702 .pointer
= snd_cs46xx_playback_direct_pointer
,
1705 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops
= {
1706 .open
= snd_cs46xx_playback_open_iec958
,
1707 .close
= snd_cs46xx_playback_close_iec958
,
1708 .ioctl
= snd_pcm_lib_ioctl
,
1709 .hw_params
= snd_cs46xx_playback_hw_params
,
1710 .hw_free
= snd_cs46xx_playback_hw_free
,
1711 .prepare
= snd_cs46xx_playback_prepare
,
1712 .trigger
= snd_cs46xx_playback_trigger
,
1713 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1714 .ack
= snd_cs46xx_playback_transfer
,
1719 static struct snd_pcm_ops snd_cs46xx_playback_ops
= {
1720 .open
= snd_cs46xx_playback_open
,
1721 .close
= snd_cs46xx_playback_close
,
1722 .ioctl
= snd_pcm_lib_ioctl
,
1723 .hw_params
= snd_cs46xx_playback_hw_params
,
1724 .hw_free
= snd_cs46xx_playback_hw_free
,
1725 .prepare
= snd_cs46xx_playback_prepare
,
1726 .trigger
= snd_cs46xx_playback_trigger
,
1727 .pointer
= snd_cs46xx_playback_direct_pointer
,
1730 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops
= {
1731 .open
= snd_cs46xx_playback_open
,
1732 .close
= snd_cs46xx_playback_close
,
1733 .ioctl
= snd_pcm_lib_ioctl
,
1734 .hw_params
= snd_cs46xx_playback_hw_params
,
1735 .hw_free
= snd_cs46xx_playback_hw_free
,
1736 .prepare
= snd_cs46xx_playback_prepare
,
1737 .trigger
= snd_cs46xx_playback_trigger
,
1738 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1739 .ack
= snd_cs46xx_playback_transfer
,
1742 static struct snd_pcm_ops snd_cs46xx_capture_ops
= {
1743 .open
= snd_cs46xx_capture_open
,
1744 .close
= snd_cs46xx_capture_close
,
1745 .ioctl
= snd_pcm_lib_ioctl
,
1746 .hw_params
= snd_cs46xx_capture_hw_params
,
1747 .hw_free
= snd_cs46xx_capture_hw_free
,
1748 .prepare
= snd_cs46xx_capture_prepare
,
1749 .trigger
= snd_cs46xx_capture_trigger
,
1750 .pointer
= snd_cs46xx_capture_direct_pointer
,
1753 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops
= {
1754 .open
= snd_cs46xx_capture_open
,
1755 .close
= snd_cs46xx_capture_close
,
1756 .ioctl
= snd_pcm_lib_ioctl
,
1757 .hw_params
= snd_cs46xx_capture_hw_params
,
1758 .hw_free
= snd_cs46xx_capture_hw_free
,
1759 .prepare
= snd_cs46xx_capture_prepare
,
1760 .trigger
= snd_cs46xx_capture_trigger
,
1761 .pointer
= snd_cs46xx_capture_indirect_pointer
,
1762 .ack
= snd_cs46xx_capture_transfer
,
1765 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1766 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1768 #define MAX_PLAYBACK_CHANNELS 1
1771 int snd_cs46xx_pcm(struct snd_cs46xx
*chip
, int device
, struct snd_pcm
**rpcm
)
1773 struct snd_pcm
*pcm
;
1778 if ((err
= snd_pcm_new(chip
->card
, "CS46xx", device
, MAX_PLAYBACK_CHANNELS
, 1, &pcm
)) < 0)
1781 pcm
->private_data
= chip
;
1783 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_ops
);
1784 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cs46xx_capture_ops
);
1787 pcm
->info_flags
= 0;
1788 strcpy(pcm
->name
, "CS46xx");
1791 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1792 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1801 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1802 int snd_cs46xx_pcm_rear(struct snd_cs46xx
*chip
, int device
,
1803 struct snd_pcm
**rpcm
)
1805 struct snd_pcm
*pcm
;
1811 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Rear", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1814 pcm
->private_data
= chip
;
1816 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_rear_ops
);
1819 pcm
->info_flags
= 0;
1820 strcpy(pcm
->name
, "CS46xx - Rear");
1821 chip
->pcm_rear
= pcm
;
1823 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1824 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1832 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx
*chip
, int device
,
1833 struct snd_pcm
**rpcm
)
1835 struct snd_pcm
*pcm
;
1841 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Center LFE", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1844 pcm
->private_data
= chip
;
1846 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_clfe_ops
);
1849 pcm
->info_flags
= 0;
1850 strcpy(pcm
->name
, "CS46xx - Center LFE");
1851 chip
->pcm_center_lfe
= pcm
;
1853 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1854 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1862 int snd_cs46xx_pcm_iec958(struct snd_cs46xx
*chip
, int device
,
1863 struct snd_pcm
**rpcm
)
1865 struct snd_pcm
*pcm
;
1871 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - IEC958", device
, 1, 0, &pcm
)) < 0)
1874 pcm
->private_data
= chip
;
1876 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_iec958_ops
);
1879 pcm
->info_flags
= 0;
1880 strcpy(pcm
->name
, "CS46xx - IEC958");
1881 chip
->pcm_rear
= pcm
;
1883 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1884 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1896 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus
*bus
)
1898 struct snd_cs46xx
*chip
= bus
->private_data
;
1900 chip
->ac97_bus
= NULL
;
1903 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97
*ac97
)
1905 struct snd_cs46xx
*chip
= ac97
->private_data
;
1907 if (snd_BUG_ON(ac97
!= chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
] &&
1908 ac97
!= chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]))
1911 if (ac97
== chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]) {
1912 chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
] = NULL
;
1913 chip
->eapd_switch
= NULL
;
1916 chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
] = NULL
;
1919 static int snd_cs46xx_vol_info(struct snd_kcontrol
*kcontrol
,
1920 struct snd_ctl_elem_info
*uinfo
)
1922 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
1924 uinfo
->value
.integer
.min
= 0;
1925 uinfo
->value
.integer
.max
= 0x7fff;
1929 static int snd_cs46xx_vol_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1931 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1932 int reg
= kcontrol
->private_value
;
1933 unsigned int val
= snd_cs46xx_peek(chip
, reg
);
1934 ucontrol
->value
.integer
.value
[0] = 0xffff - (val
>> 16);
1935 ucontrol
->value
.integer
.value
[1] = 0xffff - (val
& 0xffff);
1939 static int snd_cs46xx_vol_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1941 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1942 int reg
= kcontrol
->private_value
;
1943 unsigned int val
= ((0xffff - ucontrol
->value
.integer
.value
[0]) << 16 |
1944 (0xffff - ucontrol
->value
.integer
.value
[1]));
1945 unsigned int old
= snd_cs46xx_peek(chip
, reg
);
1946 int change
= (old
!= val
);
1949 snd_cs46xx_poke(chip
, reg
, val
);
1955 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1957 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1959 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1961 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->dac_volume_left
;
1962 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->dac_volume_right
;
1967 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1969 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1972 if (chip
->dsp_spos_instance
->dac_volume_right
!= ucontrol
->value
.integer
.value
[0] ||
1973 chip
->dsp_spos_instance
->dac_volume_left
!= ucontrol
->value
.integer
.value
[1]) {
1974 cs46xx_dsp_set_dac_volume(chip
,
1975 ucontrol
->value
.integer
.value
[0],
1976 ucontrol
->value
.integer
.value
[1]);
1984 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1986 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1988 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_input_volume_left
;
1989 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->spdif_input_volume_right
;
1993 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1995 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1998 if (chip
->dsp_spos_instance
->spdif_input_volume_left
!= ucontrol
->value
.integer
.value
[0] ||
1999 chip
->dsp_spos_instance
->spdif_input_volume_right
!= ucontrol
->value
.integer
.value
[1]) {
2000 cs46xx_dsp_set_iec958_volume (chip
,
2001 ucontrol
->value
.integer
.value
[0],
2002 ucontrol
->value
.integer
.value
[1]);
2010 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
2012 static int snd_cs46xx_iec958_get(struct snd_kcontrol
*kcontrol
,
2013 struct snd_ctl_elem_value
*ucontrol
)
2015 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2016 int reg
= kcontrol
->private_value
;
2018 if (reg
== CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
)
2019 ucontrol
->value
.integer
.value
[0] = (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
2021 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_status_in
;
2026 static int snd_cs46xx_iec958_put(struct snd_kcontrol
*kcontrol
,
2027 struct snd_ctl_elem_value
*ucontrol
)
2029 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2032 switch (kcontrol
->private_value
) {
2033 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
:
2034 mutex_lock(&chip
->spos_mutex
);
2035 change
= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
2036 if (ucontrol
->value
.integer
.value
[0] && !change
)
2037 cs46xx_dsp_enable_spdif_out(chip
);
2038 else if (change
&& !ucontrol
->value
.integer
.value
[0])
2039 cs46xx_dsp_disable_spdif_out(chip
);
2041 res
= (change
!= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
));
2042 mutex_unlock(&chip
->spos_mutex
);
2044 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT
:
2045 change
= chip
->dsp_spos_instance
->spdif_status_in
;
2046 if (ucontrol
->value
.integer
.value
[0] && !change
) {
2047 cs46xx_dsp_enable_spdif_in(chip
);
2048 /* restore volume */
2050 else if (change
&& !ucontrol
->value
.integer
.value
[0])
2051 cs46xx_dsp_disable_spdif_in(chip
);
2053 res
= (change
!= chip
->dsp_spos_instance
->spdif_status_in
);
2057 snd_BUG(); /* should never happen ... */
2063 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol
*kcontrol
,
2064 struct snd_ctl_elem_value
*ucontrol
)
2066 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2067 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2069 if (ins
->adc_input
!= NULL
)
2070 ucontrol
->value
.integer
.value
[0] = 1;
2072 ucontrol
->value
.integer
.value
[0] = 0;
2077 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol
*kcontrol
,
2078 struct snd_ctl_elem_value
*ucontrol
)
2080 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2081 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2084 if (ucontrol
->value
.integer
.value
[0] && !ins
->adc_input
) {
2085 cs46xx_dsp_enable_adc_capture(chip
);
2087 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->adc_input
) {
2088 cs46xx_dsp_disable_adc_capture(chip
);
2094 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol
*kcontrol
,
2095 struct snd_ctl_elem_value
*ucontrol
)
2097 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2098 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2100 if (ins
->pcm_input
!= NULL
)
2101 ucontrol
->value
.integer
.value
[0] = 1;
2103 ucontrol
->value
.integer
.value
[0] = 0;
2109 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol
*kcontrol
,
2110 struct snd_ctl_elem_value
*ucontrol
)
2112 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2113 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2116 if (ucontrol
->value
.integer
.value
[0] && !ins
->pcm_input
) {
2117 cs46xx_dsp_enable_pcm_capture(chip
);
2119 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->pcm_input
) {
2120 cs46xx_dsp_disable_pcm_capture(chip
);
2127 static int snd_herc_spdif_select_get(struct snd_kcontrol
*kcontrol
,
2128 struct snd_ctl_elem_value
*ucontrol
)
2130 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2132 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
2134 if (val1
& EGPIODR_GPOE0
)
2135 ucontrol
->value
.integer
.value
[0] = 1;
2137 ucontrol
->value
.integer
.value
[0] = 0;
2143 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2145 static int snd_herc_spdif_select_put(struct snd_kcontrol
*kcontrol
,
2146 struct snd_ctl_elem_value
*ucontrol
)
2148 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2149 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
2150 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
2152 if (ucontrol
->value
.integer
.value
[0]) {
2153 /* optical is default */
2154 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
2155 EGPIODR_GPOE0
| val1
); /* enable EGPIO0 output */
2156 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
2157 EGPIOPTR_GPPT0
| val2
); /* open-drain on output */
2160 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE0
); /* disable */
2161 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT0
); /* disable */
2164 /* checking diff from the EGPIO direction register
2166 return (val1
!= (int)snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
));
2170 static int snd_cs46xx_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2172 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2177 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol
*kcontrol
,
2178 struct snd_ctl_elem_value
*ucontrol
)
2180 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2181 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2183 mutex_lock(&chip
->spos_mutex
);
2184 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_default
>> 24) & 0xff);
2185 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_default
>> 16) & 0xff);
2186 ucontrol
->value
.iec958
.status
[2] = 0;
2187 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_default
) & 0xff);
2188 mutex_unlock(&chip
->spos_mutex
);
2193 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol
*kcontrol
,
2194 struct snd_ctl_elem_value
*ucontrol
)
2196 struct snd_cs46xx
* chip
= snd_kcontrol_chip(kcontrol
);
2197 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2201 mutex_lock(&chip
->spos_mutex
);
2202 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2203 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[2]) << 16) |
2204 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2205 /* left and right validity bit */
2206 (1 << 13) | (1 << 12);
2209 change
= (unsigned int)ins
->spdif_csuv_default
!= val
;
2210 ins
->spdif_csuv_default
= val
;
2212 if ( !(ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
) )
2213 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2215 mutex_unlock(&chip
->spos_mutex
);
2220 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol
*kcontrol
,
2221 struct snd_ctl_elem_value
*ucontrol
)
2223 ucontrol
->value
.iec958
.status
[0] = 0xff;
2224 ucontrol
->value
.iec958
.status
[1] = 0xff;
2225 ucontrol
->value
.iec958
.status
[2] = 0x00;
2226 ucontrol
->value
.iec958
.status
[3] = 0xff;
2230 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol
*kcontrol
,
2231 struct snd_ctl_elem_value
*ucontrol
)
2233 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2234 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2236 mutex_lock(&chip
->spos_mutex
);
2237 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 24) & 0xff);
2238 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 16) & 0xff);
2239 ucontrol
->value
.iec958
.status
[2] = 0;
2240 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_stream
) & 0xff);
2241 mutex_unlock(&chip
->spos_mutex
);
2246 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol
*kcontrol
,
2247 struct snd_ctl_elem_value
*ucontrol
)
2249 struct snd_cs46xx
* chip
= snd_kcontrol_chip(kcontrol
);
2250 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2254 mutex_lock(&chip
->spos_mutex
);
2255 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2256 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[1]) << 16) |
2257 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2258 /* left and right validity bit */
2259 (1 << 13) | (1 << 12);
2262 change
= ins
->spdif_csuv_stream
!= val
;
2263 ins
->spdif_csuv_stream
= val
;
2265 if ( ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
)
2266 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2268 mutex_unlock(&chip
->spos_mutex
);
2273 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2276 static struct snd_kcontrol_new snd_cs46xx_controls
[] = {
2278 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2279 .name
= "DAC Volume",
2280 .info
= snd_cs46xx_vol_info
,
2281 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2282 .get
= snd_cs46xx_vol_get
,
2283 .put
= snd_cs46xx_vol_put
,
2284 .private_value
= BA1_PVOL
,
2286 .get
= snd_cs46xx_vol_dac_get
,
2287 .put
= snd_cs46xx_vol_dac_put
,
2292 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2293 .name
= "ADC Volume",
2294 .info
= snd_cs46xx_vol_info
,
2295 .get
= snd_cs46xx_vol_get
,
2296 .put
= snd_cs46xx_vol_put
,
2297 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2298 .private_value
= BA1_CVOL
,
2300 .private_value
= (VARIDECIMATE_SCB_ADDR
+ 0xE) << 2,
2303 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2305 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2306 .name
= "ADC Capture Switch",
2307 .info
= snd_mixer_boolean_info
,
2308 .get
= snd_cs46xx_adc_capture_get
,
2309 .put
= snd_cs46xx_adc_capture_put
2312 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2313 .name
= "DAC Capture Switch",
2314 .info
= snd_mixer_boolean_info
,
2315 .get
= snd_cs46xx_pcm_capture_get
,
2316 .put
= snd_cs46xx_pcm_capture_put
2319 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2320 .name
= SNDRV_CTL_NAME_IEC958("Output ",NONE
,SWITCH
),
2321 .info
= snd_mixer_boolean_info
,
2322 .get
= snd_cs46xx_iec958_get
,
2323 .put
= snd_cs46xx_iec958_put
,
2324 .private_value
= CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
,
2327 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2328 .name
= SNDRV_CTL_NAME_IEC958("Input ",NONE
,SWITCH
),
2329 .info
= snd_mixer_boolean_info
,
2330 .get
= snd_cs46xx_iec958_get
,
2331 .put
= snd_cs46xx_iec958_put
,
2332 .private_value
= CS46XX_MIXER_SPDIF_INPUT_ELEMENT
,
2335 /* Input IEC958 volume does not work for the moment. (Benny) */
2337 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2338 .name
= SNDRV_CTL_NAME_IEC958("Input ",NONE
,VOLUME
),
2339 .info
= snd_cs46xx_vol_info
,
2340 .get
= snd_cs46xx_vol_iec958_get
,
2341 .put
= snd_cs46xx_vol_iec958_put
,
2342 .private_value
= (ASYNCRX_SCB_ADDR
+ 0xE) << 2,
2346 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2347 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2348 .info
= snd_cs46xx_spdif_info
,
2349 .get
= snd_cs46xx_spdif_default_get
,
2350 .put
= snd_cs46xx_spdif_default_put
,
2353 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2354 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,MASK
),
2355 .info
= snd_cs46xx_spdif_info
,
2356 .get
= snd_cs46xx_spdif_mask_get
,
2357 .access
= SNDRV_CTL_ELEM_ACCESS_READ
2360 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2361 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2362 .info
= snd_cs46xx_spdif_info
,
2363 .get
= snd_cs46xx_spdif_stream_get
,
2364 .put
= snd_cs46xx_spdif_stream_put
2370 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2371 /* set primary cs4294 codec into Extended Audio Mode */
2372 static int snd_cs46xx_front_dup_get(struct snd_kcontrol
*kcontrol
,
2373 struct snd_ctl_elem_value
*ucontrol
)
2375 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2377 val
= snd_ac97_read(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
], AC97_CSR_ACMODE
);
2378 ucontrol
->value
.integer
.value
[0] = (val
& 0x200) ? 0 : 1;
2382 static int snd_cs46xx_front_dup_put(struct snd_kcontrol
*kcontrol
,
2383 struct snd_ctl_elem_value
*ucontrol
)
2385 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2386 return snd_ac97_update_bits(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2387 AC97_CSR_ACMODE
, 0x200,
2388 ucontrol
->value
.integer
.value
[0] ? 0 : 0x200);
2391 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl
= {
2392 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2393 .name
= "Duplicate Front",
2394 .info
= snd_mixer_boolean_info
,
2395 .get
= snd_cs46xx_front_dup_get
,
2396 .put
= snd_cs46xx_front_dup_put
,
2400 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2401 /* Only available on the Hercules Game Theater XP soundcard */
2402 static struct snd_kcontrol_new snd_hercules_controls
[] = {
2404 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2405 .name
= "Optical/Coaxial SPDIF Input Switch",
2406 .info
= snd_mixer_boolean_info
,
2407 .get
= snd_herc_spdif_select_get
,
2408 .put
= snd_herc_spdif_select_put
,
2413 static void snd_cs46xx_codec_reset (struct snd_ac97
* ac97
)
2415 unsigned long end_time
;
2418 /* reset to defaults */
2419 snd_ac97_write(ac97
, AC97_RESET
, 0);
2421 /* set the desired CODEC mode */
2422 if (ac97
->num
== CS46XX_PRIMARY_CODEC_INDEX
) {
2423 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0);
2424 snd_cs46xx_ac97_write(ac97
, AC97_CSR_ACMODE
, 0x0);
2425 } else if (ac97
->num
== CS46XX_SECONDARY_CODEC_INDEX
) {
2426 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3);
2427 snd_cs46xx_ac97_write(ac97
, AC97_CSR_ACMODE
, 0x3);
2429 snd_BUG(); /* should never happen ... */
2434 /* it's necessary to wait awhile until registers are accessible after RESET */
2435 /* because the PCM or MASTER volume registers can be modified, */
2436 /* the REC_GAIN register is used for tests */
2437 end_time
= jiffies
+ HZ
;
2439 unsigned short ext_mid
;
2441 /* use preliminary reads to settle the communication */
2442 snd_ac97_read(ac97
, AC97_RESET
);
2443 snd_ac97_read(ac97
, AC97_VENDOR_ID1
);
2444 snd_ac97_read(ac97
, AC97_VENDOR_ID2
);
2446 ext_mid
= snd_ac97_read(ac97
, AC97_EXTENDED_MID
);
2447 if (ext_mid
!= 0xffff && (ext_mid
& 1) != 0)
2450 /* test if we can write to the record gain volume register */
2451 snd_ac97_write(ac97
, AC97_REC_GAIN
, 0x8a05);
2452 if ((err
= snd_ac97_read(ac97
, AC97_REC_GAIN
)) == 0x8a05)
2456 } while (time_after_eq(end_time
, jiffies
));
2458 snd_printk(KERN_ERR
"CS46xx secondary codec doesn't respond!\n");
2462 static int cs46xx_detect_codec(struct snd_cs46xx
*chip
, int codec
)
2465 struct snd_ac97_template ac97
;
2467 memset(&ac97
, 0, sizeof(ac97
));
2468 ac97
.private_data
= chip
;
2469 ac97
.private_free
= snd_cs46xx_mixer_free_ac97
;
2471 if (chip
->amplifier_ctrl
== amp_voyetra
)
2472 ac97
.scaps
= AC97_SCAP_INV_EAPD
;
2474 if (codec
== CS46XX_SECONDARY_CODEC_INDEX
) {
2475 snd_cs46xx_codec_write(chip
, AC97_RESET
, 0, codec
);
2477 if (snd_cs46xx_codec_read(chip
, AC97_RESET
, codec
) & 0x8000) {
2478 snd_printdd("snd_cs46xx: seconadry codec not present\n");
2483 snd_cs46xx_codec_write(chip
, AC97_MASTER
, 0x8000, codec
);
2484 for (idx
= 0; idx
< 100; ++idx
) {
2485 if (snd_cs46xx_codec_read(chip
, AC97_MASTER
, codec
) == 0x8000) {
2486 err
= snd_ac97_mixer(chip
->ac97_bus
, &ac97
, &chip
->ac97
[codec
]);
2491 snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec
);
2495 int snd_cs46xx_mixer(struct snd_cs46xx
*chip
, int spdif_device
)
2497 struct snd_card
*card
= chip
->card
;
2498 struct snd_ctl_elem_id id
;
2501 static struct snd_ac97_bus_ops ops
= {
2502 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2503 .reset
= snd_cs46xx_codec_reset
,
2505 .write
= snd_cs46xx_ac97_write
,
2506 .read
= snd_cs46xx_ac97_read
,
2509 /* detect primary codec */
2510 chip
->nr_ac97_codecs
= 0;
2511 snd_printdd("snd_cs46xx: detecting primary codec\n");
2512 if ((err
= snd_ac97_bus(card
, 0, &ops
, chip
, &chip
->ac97_bus
)) < 0)
2514 chip
->ac97_bus
->private_free
= snd_cs46xx_mixer_free_ac97_bus
;
2516 if (cs46xx_detect_codec(chip
, CS46XX_PRIMARY_CODEC_INDEX
) < 0)
2518 chip
->nr_ac97_codecs
= 1;
2520 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2521 snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2522 /* try detect a secondary codec */
2523 if (! cs46xx_detect_codec(chip
, CS46XX_SECONDARY_CODEC_INDEX
))
2524 chip
->nr_ac97_codecs
= 2;
2525 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2527 /* add cs4630 mixer controls */
2528 for (idx
= 0; idx
< ARRAY_SIZE(snd_cs46xx_controls
); idx
++) {
2529 struct snd_kcontrol
*kctl
;
2530 kctl
= snd_ctl_new1(&snd_cs46xx_controls
[idx
], chip
);
2531 if (kctl
&& kctl
->id
.iface
== SNDRV_CTL_ELEM_IFACE_PCM
)
2532 kctl
->id
.device
= spdif_device
;
2533 if ((err
= snd_ctl_add(card
, kctl
)) < 0)
2537 /* get EAPD mixer switch (for voyetra hack) */
2538 memset(&id
, 0, sizeof(id
));
2539 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2540 strcpy(id
.name
, "External Amplifier");
2541 chip
->eapd_switch
= snd_ctl_find_id(chip
->card
, &id
);
2543 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2544 if (chip
->nr_ac97_codecs
== 1) {
2545 unsigned int id2
= chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]->id
& 0xffff;
2546 if (id2
== 0x592b || id2
== 0x592d) {
2547 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cs46xx_front_dup_ctl
, chip
));
2550 snd_ac97_write_cache(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2551 AC97_CSR_ACMODE
, 0x200);
2554 /* do soundcard specific mixer setup */
2555 if (chip
->mixer_init
) {
2556 snd_printdd ("calling chip->mixer_init(chip);\n");
2557 chip
->mixer_init(chip
);
2561 /* turn on amplifier */
2562 chip
->amplifier_ctrl(chip
, 1);
2571 static void snd_cs46xx_midi_reset(struct snd_cs46xx
*chip
)
2573 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, MIDCR_MRST
);
2575 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2578 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream
*substream
)
2580 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2582 chip
->active_ctrl(chip
, 1);
2583 spin_lock_irq(&chip
->reg_lock
);
2584 chip
->uartm
|= CS46XX_MODE_INPUT
;
2585 chip
->midcr
|= MIDCR_RXE
;
2586 chip
->midi_input
= substream
;
2587 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2588 snd_cs46xx_midi_reset(chip
);
2590 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2592 spin_unlock_irq(&chip
->reg_lock
);
2596 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream
*substream
)
2598 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2600 spin_lock_irq(&chip
->reg_lock
);
2601 chip
->midcr
&= ~(MIDCR_RXE
| MIDCR_RIE
);
2602 chip
->midi_input
= NULL
;
2603 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2604 snd_cs46xx_midi_reset(chip
);
2606 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2608 chip
->uartm
&= ~CS46XX_MODE_INPUT
;
2609 spin_unlock_irq(&chip
->reg_lock
);
2610 chip
->active_ctrl(chip
, -1);
2614 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream
*substream
)
2616 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2618 chip
->active_ctrl(chip
, 1);
2620 spin_lock_irq(&chip
->reg_lock
);
2621 chip
->uartm
|= CS46XX_MODE_OUTPUT
;
2622 chip
->midcr
|= MIDCR_TXE
;
2623 chip
->midi_output
= substream
;
2624 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2625 snd_cs46xx_midi_reset(chip
);
2627 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2629 spin_unlock_irq(&chip
->reg_lock
);
2633 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream
*substream
)
2635 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2637 spin_lock_irq(&chip
->reg_lock
);
2638 chip
->midcr
&= ~(MIDCR_TXE
| MIDCR_TIE
);
2639 chip
->midi_output
= NULL
;
2640 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2641 snd_cs46xx_midi_reset(chip
);
2643 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2645 chip
->uartm
&= ~CS46XX_MODE_OUTPUT
;
2646 spin_unlock_irq(&chip
->reg_lock
);
2647 chip
->active_ctrl(chip
, -1);
2651 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2653 unsigned long flags
;
2654 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2656 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2658 if ((chip
->midcr
& MIDCR_RIE
) == 0) {
2659 chip
->midcr
|= MIDCR_RIE
;
2660 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2663 if (chip
->midcr
& MIDCR_RIE
) {
2664 chip
->midcr
&= ~MIDCR_RIE
;
2665 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2668 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2671 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2673 unsigned long flags
;
2674 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2677 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2679 if ((chip
->midcr
& MIDCR_TIE
) == 0) {
2680 chip
->midcr
|= MIDCR_TIE
;
2681 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2682 while ((chip
->midcr
& MIDCR_TIE
) &&
2683 (snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
2684 if (snd_rawmidi_transmit(substream
, &byte
, 1) != 1) {
2685 chip
->midcr
&= ~MIDCR_TIE
;
2687 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, byte
);
2690 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2693 if (chip
->midcr
& MIDCR_TIE
) {
2694 chip
->midcr
&= ~MIDCR_TIE
;
2695 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2698 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2701 static struct snd_rawmidi_ops snd_cs46xx_midi_output
=
2703 .open
= snd_cs46xx_midi_output_open
,
2704 .close
= snd_cs46xx_midi_output_close
,
2705 .trigger
= snd_cs46xx_midi_output_trigger
,
2708 static struct snd_rawmidi_ops snd_cs46xx_midi_input
=
2710 .open
= snd_cs46xx_midi_input_open
,
2711 .close
= snd_cs46xx_midi_input_close
,
2712 .trigger
= snd_cs46xx_midi_input_trigger
,
2715 int snd_cs46xx_midi(struct snd_cs46xx
*chip
, int device
, struct snd_rawmidi
**rrawmidi
)
2717 struct snd_rawmidi
*rmidi
;
2722 if ((err
= snd_rawmidi_new(chip
->card
, "CS46XX", device
, 1, 1, &rmidi
)) < 0)
2724 strcpy(rmidi
->name
, "CS46XX");
2725 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_OUTPUT
, &snd_cs46xx_midi_output
);
2726 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_INPUT
, &snd_cs46xx_midi_input
);
2727 rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_OUTPUT
| SNDRV_RAWMIDI_INFO_INPUT
| SNDRV_RAWMIDI_INFO_DUPLEX
;
2728 rmidi
->private_data
= chip
;
2729 chip
->rmidi
= rmidi
;
2737 * gameport interface
2740 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2742 static void snd_cs46xx_gameport_trigger(struct gameport
*gameport
)
2744 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2746 if (snd_BUG_ON(!chip
))
2748 snd_cs46xx_pokeBA0(chip
, BA0_JSPT
, 0xFF); //outb(gameport->io, 0xFF);
2751 static unsigned char snd_cs46xx_gameport_read(struct gameport
*gameport
)
2753 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2755 if (snd_BUG_ON(!chip
))
2757 return snd_cs46xx_peekBA0(chip
, BA0_JSPT
); //inb(gameport->io);
2760 static int snd_cs46xx_gameport_cooked_read(struct gameport
*gameport
, int *axes
, int *buttons
)
2762 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2763 unsigned js1
, js2
, jst
;
2765 if (snd_BUG_ON(!chip
))
2768 js1
= snd_cs46xx_peekBA0(chip
, BA0_JSC1
);
2769 js2
= snd_cs46xx_peekBA0(chip
, BA0_JSC2
);
2770 jst
= snd_cs46xx_peekBA0(chip
, BA0_JSPT
);
2772 *buttons
= (~jst
>> 4) & 0x0F;
2774 axes
[0] = ((js1
& JSC1_Y1V_MASK
) >> JSC1_Y1V_SHIFT
) & 0xFFFF;
2775 axes
[1] = ((js1
& JSC1_X1V_MASK
) >> JSC1_X1V_SHIFT
) & 0xFFFF;
2776 axes
[2] = ((js2
& JSC2_Y2V_MASK
) >> JSC2_Y2V_SHIFT
) & 0xFFFF;
2777 axes
[3] = ((js2
& JSC2_X2V_MASK
) >> JSC2_X2V_SHIFT
) & 0xFFFF;
2779 for(jst
=0;jst
<4;++jst
)
2780 if(axes
[jst
]==0xFFFF) axes
[jst
] = -1;
2784 static int snd_cs46xx_gameport_open(struct gameport
*gameport
, int mode
)
2787 case GAMEPORT_MODE_COOKED
:
2789 case GAMEPORT_MODE_RAW
:
2797 int snd_cs46xx_gameport(struct snd_cs46xx
*chip
)
2799 struct gameport
*gp
;
2801 chip
->gameport
= gp
= gameport_allocate_port();
2803 printk(KERN_ERR
"cs46xx: cannot allocate memory for gameport\n");
2807 gameport_set_name(gp
, "CS46xx Gameport");
2808 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(chip
->pci
));
2809 gameport_set_dev_parent(gp
, &chip
->pci
->dev
);
2810 gameport_set_port_data(gp
, chip
);
2812 gp
->open
= snd_cs46xx_gameport_open
;
2813 gp
->read
= snd_cs46xx_gameport_read
;
2814 gp
->trigger
= snd_cs46xx_gameport_trigger
;
2815 gp
->cooked_read
= snd_cs46xx_gameport_cooked_read
;
2817 snd_cs46xx_pokeBA0(chip
, BA0_JSIO
, 0xFF); // ?
2818 snd_cs46xx_pokeBA0(chip
, BA0_JSCTL
, JSCTL_SP_MEDIUM_SLOW
);
2820 gameport_register_port(gp
);
2825 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx
*chip
)
2827 if (chip
->gameport
) {
2828 gameport_unregister_port(chip
->gameport
);
2829 chip
->gameport
= NULL
;
2833 int snd_cs46xx_gameport(struct snd_cs46xx
*chip
) { return -ENOSYS
; }
2834 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx
*chip
) { }
2835 #endif /* CONFIG_GAMEPORT */
2837 #ifdef CONFIG_PROC_FS
2842 static ssize_t
snd_cs46xx_io_read(struct snd_info_entry
*entry
,
2843 void *file_private_data
,
2844 struct file
*file
, char __user
*buf
,
2845 size_t count
, loff_t pos
)
2847 struct snd_cs46xx_region
*region
= entry
->private_data
;
2849 if (copy_to_user_fromio(buf
, region
->remap_addr
+ pos
, count
))
2854 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops
= {
2855 .read
= snd_cs46xx_io_read
,
2858 static int snd_cs46xx_proc_init(struct snd_card
*card
, struct snd_cs46xx
*chip
)
2860 struct snd_info_entry
*entry
;
2863 for (idx
= 0; idx
< 5; idx
++) {
2864 struct snd_cs46xx_region
*region
= &chip
->region
.idx
[idx
];
2865 if (! snd_card_proc_new(card
, region
->name
, &entry
)) {
2866 entry
->content
= SNDRV_INFO_CONTENT_DATA
;
2867 entry
->private_data
= chip
;
2868 entry
->c
.ops
= &snd_cs46xx_proc_io_ops
;
2869 entry
->size
= region
->size
;
2870 entry
->mode
= S_IFREG
| S_IRUSR
;
2873 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2874 cs46xx_dsp_proc_init(card
, chip
);
2879 static int snd_cs46xx_proc_done(struct snd_cs46xx
*chip
)
2881 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2882 cs46xx_dsp_proc_done(chip
);
2886 #else /* !CONFIG_PROC_FS */
2887 #define snd_cs46xx_proc_init(card, chip)
2888 #define snd_cs46xx_proc_done(chip)
2894 static void snd_cs46xx_hw_stop(struct snd_cs46xx
*chip
)
2898 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
2901 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt disable */
2903 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
2906 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt disable */
2909 * Stop playback DMA.
2911 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
2912 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
2917 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
2918 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
2921 * Reset the processor.
2923 snd_cs46xx_reset(chip
);
2925 snd_cs46xx_proc_stop(chip
);
2928 * Power down the PLL.
2930 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
2933 * Turn off the Processor by turning off the software clock enable flag in
2934 * the clock control register.
2936 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
) & ~CLKCR1_SWCE
;
2937 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
2941 static int snd_cs46xx_free(struct snd_cs46xx
*chip
)
2945 if (snd_BUG_ON(!chip
))
2948 if (chip
->active_ctrl
)
2949 chip
->active_ctrl(chip
, 1);
2951 snd_cs46xx_remove_gameport(chip
);
2953 if (chip
->amplifier_ctrl
)
2954 chip
->amplifier_ctrl(chip
, -chip
->amplifier
); /* force to off */
2956 snd_cs46xx_proc_done(chip
);
2958 if (chip
->region
.idx
[0].resource
)
2959 snd_cs46xx_hw_stop(chip
);
2962 free_irq(chip
->irq
, chip
);
2964 if (chip
->active_ctrl
)
2965 chip
->active_ctrl(chip
, -chip
->amplifier
);
2967 for (idx
= 0; idx
< 5; idx
++) {
2968 struct snd_cs46xx_region
*region
= &chip
->region
.idx
[idx
];
2969 if (region
->remap_addr
)
2970 iounmap(region
->remap_addr
);
2971 release_and_free_resource(region
->resource
);
2974 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2975 if (chip
->dsp_spos_instance
) {
2976 cs46xx_dsp_spos_destroy(chip
);
2977 chip
->dsp_spos_instance
= NULL
;
2979 for (idx
= 0; idx
< CS46XX_DSP_MODULES
; idx
++)
2980 free_module_desc(chip
->modules
[idx
]);
2985 #ifdef CONFIG_PM_SLEEP
2986 kfree(chip
->saved_regs
);
2989 pci_disable_device(chip
->pci
);
2994 static int snd_cs46xx_dev_free(struct snd_device
*device
)
2996 struct snd_cs46xx
*chip
= device
->device_data
;
2997 return snd_cs46xx_free(chip
);
3003 static int snd_cs46xx_chip_init(struct snd_cs46xx
*chip
)
3008 * First, blast the clock control register to zero so that the PLL starts
3009 * out in a known state, and blast the master serial port control register
3010 * to zero so that the serial ports also start out in a known state.
3012 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
3013 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, 0);
3016 * If we are in AC97 mode, then we must set the part to a host controlled
3017 * AC-link. Otherwise, we won't be able to bring up the link.
3019 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3020 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_2_0
|
3021 SERACC_TWO_CODECS
); /* 2.00 dual codecs */
3022 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3024 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_1_03
); /* 1.03 codec */
3028 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3029 * spec) and then drive it high. This is done for non AC97 modes since
3030 * there might be logic external to the CS461x that uses the ARST# line
3033 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, 0);
3034 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3035 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, 0);
3038 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_RSTN
);
3039 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3040 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_RSTN
);
3044 * The first thing we do here is to enable sync generation. As soon
3045 * as we start receiving bit clock, we'll start producing the SYNC
3048 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_ESYN
| ACCTL_RSTN
);
3049 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3050 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_ESYN
| ACCTL_RSTN
);
3054 * Now wait for a short while to allow the AC97 part to start
3055 * generating bit clock (so we don't try to start the PLL without an
3061 * Set the serial port timing configuration, so that
3062 * the clock control circuit gets its clock from the correct place.
3064 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
);
3067 * Write the selected clock control setup to the hardware. Do not turn on
3068 * SWCE yet (if requested), so that the devices clocked by the output of
3069 * PLL are not clocked until the PLL is stable.
3071 snd_cs46xx_pokeBA0(chip
, BA0_PLLCC
, PLLCC_LPF_1050_2780_KHZ
| PLLCC_CDR_73_104_MHZ
);
3072 snd_cs46xx_pokeBA0(chip
, BA0_PLLM
, 0x3a);
3073 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR2
, CLKCR2_PDIVS_8
);
3078 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
);
3081 * Wait until the PLL has stabilized.
3086 * Turn on clocking of the core so that we can setup the serial ports.
3088 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
| CLKCR1_SWCE
);
3091 * Enable FIFO Host Bypass
3093 snd_cs46xx_pokeBA0(chip
, BA0_SERBCF
, SERBCF_HBP
);
3096 * Fill the serial port FIFOs with silence.
3098 snd_cs46xx_clear_serial_FIFOs(chip
);
3101 * Set the serial port FIFO pointer to the first sample in the FIFO.
3103 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3106 * Write the serial port configuration to the part. The master
3107 * enable bit is not set until all other values have been written.
3109 snd_cs46xx_pokeBA0(chip
, BA0_SERC1
, SERC1_SO1F_AC97
| SERC1_SO1EN
);
3110 snd_cs46xx_pokeBA0(chip
, BA0_SERC2
, SERC2_SI1F_AC97
| SERC1_SO1EN
);
3111 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
| SERMC1_MSPE
);
3114 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3115 snd_cs46xx_pokeBA0(chip
, BA0_SERC7
, SERC7_ASDI2EN
);
3116 snd_cs46xx_pokeBA0(chip
, BA0_SERC3
, 0);
3117 snd_cs46xx_pokeBA0(chip
, BA0_SERC4
, 0);
3118 snd_cs46xx_pokeBA0(chip
, BA0_SERC5
, 0);
3119 snd_cs46xx_pokeBA0(chip
, BA0_SERC6
, 1);
3126 * Wait for the codec ready signal from the AC97 codec.
3129 while (timeout
-- > 0) {
3131 * Read the AC97 status register to see if we've seen a CODEC READY
3132 * signal from the AC97 codec.
3134 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
) & ACSTS_CRDY
)
3140 snd_printk(KERN_ERR
"create - never read codec ready from AC'97\n");
3141 snd_printk(KERN_ERR
"it is not probably bug, try to use CS4236 driver\n");
3144 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3147 for (count
= 0; count
< 150; count
++) {
3148 /* First, we want to wait for a short time. */
3151 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
)
3156 * Make sure CODEC is READY.
3158 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
))
3159 snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
3164 * Assert the vaid frame signal so that we can start sending commands
3165 * to the AC97 codec.
3167 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3168 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3169 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3174 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3175 * the codec is pumping ADC data across the AC-link.
3178 while (timeout
-- > 0) {
3180 * Read the input slot valid register and see if input slots 3 and
3183 if ((snd_cs46xx_peekBA0(chip
, BA0_ACISV
) & (ACISV_ISV3
| ACISV_ISV4
)) == (ACISV_ISV3
| ACISV_ISV4
))
3188 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3189 snd_printk(KERN_ERR
"create - never read ISV3 & ISV4 from AC'97\n");
3192 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3193 Reloading the driver may help, if there's other soundcards
3194 with the same problem I would like to know. (Benny) */
3196 snd_printk(KERN_ERR
"ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3197 snd_printk(KERN_ERR
" Try reloading the ALSA driver, if you find something\n");
3198 snd_printk(KERN_ERR
" broken or not working on your soundcard upon\n");
3199 snd_printk(KERN_ERR
" this message please report to alsa-devel@alsa-project.org\n");
3206 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3207 * commense the transfer of digital audio data to the AC97 codec.
3210 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, ACOSV_SLV3
| ACOSV_SLV4
);
3214 * Power down the DAC and ADC. We will power them up (if) when we need
3217 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3220 * Turn off the Processor by turning off the software clock enable flag in
3221 * the clock control register.
3223 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3224 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3230 * start and load DSP
3233 static void cs46xx_enable_stream_irqs(struct snd_cs46xx
*chip
)
3237 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_IEV
| HICR_CHGM
);
3239 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
3241 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt enable */
3243 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
3246 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt enable */
3249 int snd_cs46xx_start_dsp(struct snd_cs46xx
*chip
)
3252 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3258 * Reset the processor.
3260 snd_cs46xx_reset(chip
);
3262 * Download the image to the processor.
3264 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3265 for (i
= 0; i
< CS46XX_DSP_MODULES
; i
++) {
3266 err
= load_firmware(chip
, &chip
->modules
[i
], module_names
[i
]);
3268 snd_printk(KERN_ERR
"firmware load error [%s]\n",
3272 err
= cs46xx_dsp_load_module(chip
, chip
->modules
[i
]);
3274 snd_printk(KERN_ERR
"image download error [%s]\n",
3280 if (cs46xx_dsp_scb_and_task_init(chip
) < 0)
3283 err
= load_firmware(chip
);
3288 err
= snd_cs46xx_download_image(chip
);
3290 snd_printk(KERN_ERR
"image download error\n");
3295 * Stop playback DMA.
3297 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
3298 chip
->play_ctl
= tmp
& 0xffff0000;
3299 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
3305 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
3306 chip
->capt
.ctl
= tmp
& 0x0000ffff;
3307 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
3311 snd_cs46xx_set_play_sample_rate(chip
, 8000);
3312 snd_cs46xx_set_capture_sample_rate(chip
, 8000);
3314 snd_cs46xx_proc_start(chip
);
3316 cs46xx_enable_stream_irqs(chip
);
3318 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3319 /* set the attenuation to 0dB */
3320 snd_cs46xx_poke(chip
, BA1_PVOL
, 0x80008000);
3321 snd_cs46xx_poke(chip
, BA1_CVOL
, 0x80008000);
3329 * AMP control - null AMP
3332 static void amp_none(struct snd_cs46xx
*chip
, int change
)
3336 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3337 static int voyetra_setup_eapd_slot(struct snd_cs46xx
*chip
)
3340 u32 idx
, valid_slots
,tmp
,powerdown
= 0;
3341 u16 modem_power
,pin_config
,logic_type
;
3343 snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3346 * See if the devices are powered down. If so, we must power them up first
3347 * or they will not respond.
3349 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
3351 if (!(tmp
& CLKCR1_SWCE
)) {
3352 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
3357 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3360 if(chip
->nr_ac97_codecs
!= 2) {
3361 snd_printk (KERN_ERR
"cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3365 modem_power
= snd_cs46xx_codec_read (chip
,
3366 AC97_EXTENDED_MSTATUS
,
3367 CS46XX_SECONDARY_CODEC_INDEX
);
3368 modem_power
&=0xFEFF;
3370 snd_cs46xx_codec_write(chip
,
3371 AC97_EXTENDED_MSTATUS
, modem_power
,
3372 CS46XX_SECONDARY_CODEC_INDEX
);
3375 * Set GPIO pin's 7 and 8 so that they are configured for output.
3377 pin_config
= snd_cs46xx_codec_read (chip
,
3379 CS46XX_SECONDARY_CODEC_INDEX
);
3382 snd_cs46xx_codec_write(chip
,
3383 AC97_GPIO_CFG
, pin_config
,
3384 CS46XX_SECONDARY_CODEC_INDEX
);
3387 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3390 logic_type
= snd_cs46xx_codec_read(chip
, AC97_GPIO_POLARITY
,
3391 CS46XX_SECONDARY_CODEC_INDEX
);
3394 snd_cs46xx_codec_write (chip
, AC97_GPIO_POLARITY
, logic_type
,
3395 CS46XX_SECONDARY_CODEC_INDEX
);
3397 valid_slots
= snd_cs46xx_peekBA0(chip
, BA0_ACOSV
);
3398 valid_slots
|= 0x200;
3399 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, valid_slots
);
3401 if ( cs46xx_wait_for_fifo(chip
,1) ) {
3402 snd_printdd("FIFO is busy\n");
3408 * Fill slots 12 with the correct value for the GPIO pins.
3410 for(idx
= 0x90; idx
<= 0x9F; idx
++) {
3412 * Initialize the fifo so that bits 7 and 8 are on.
3414 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3415 * the left. 0x1800 corresponds to bits 7 and 8.
3417 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0x1800);
3420 * Wait for command to complete
3422 if ( cs46xx_wait_for_fifo(chip
,200) ) {
3423 snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx
);
3429 * Write the serial port FIFO index.
3431 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
3434 * Tell the serial port to load the new value into the FIFO location.
3436 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
3439 /* wait for last command to complete */
3440 cs46xx_wait_for_fifo(chip
,200);
3443 * Now, if we powered up the devices, then power them back down again.
3444 * This is kinda ugly, but should never happen.
3447 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
3457 static void amp_voyetra(struct snd_cs46xx
*chip
, int change
)
3459 /* Manage the EAPD bit on the Crystal 4297
3460 and the Analog AD1885 */
3462 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3463 int old
= chip
->amplifier
;
3467 chip
->amplifier
+= change
;
3468 oval
= snd_cs46xx_codec_read(chip
, AC97_POWERDOWN
,
3469 CS46XX_PRIMARY_CODEC_INDEX
);
3471 if (chip
->amplifier
) {
3472 /* Turn the EAPD amp on */
3475 /* Turn the EAPD amp off */
3479 snd_cs46xx_codec_write(chip
, AC97_POWERDOWN
, val
,
3480 CS46XX_PRIMARY_CODEC_INDEX
);
3481 if (chip
->eapd_switch
)
3482 snd_ctl_notify(chip
->card
, SNDRV_CTL_EVENT_MASK_VALUE
,
3483 &chip
->eapd_switch
->id
);
3486 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3487 if (chip
->amplifier
&& !old
) {
3488 voyetra_setup_eapd_slot(chip
);
3493 static void hercules_init(struct snd_cs46xx
*chip
)
3495 /* default: AMP off, and SPDIF input optical */
3496 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3497 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3502 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3504 static void amp_hercules(struct snd_cs46xx
*chip
, int change
)
3506 int old
= chip
->amplifier
;
3507 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
3508 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
3510 chip
->amplifier
+= change
;
3511 if (chip
->amplifier
&& !old
) {
3512 snd_printdd ("Hercules amplifier ON\n");
3514 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
3515 EGPIODR_GPOE2
| val1
); /* enable EGPIO2 output */
3516 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
3517 EGPIOPTR_GPPT2
| val2
); /* open-drain on output */
3518 } else if (old
&& !chip
->amplifier
) {
3519 snd_printdd ("Hercules amplifier OFF\n");
3520 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE2
); /* disable */
3521 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT2
); /* disable */
3525 static void voyetra_mixer_init (struct snd_cs46xx
*chip
)
3527 snd_printdd ("initializing Voyetra mixer\n");
3529 /* Enable SPDIF out */
3530 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3531 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3534 static void hercules_mixer_init (struct snd_cs46xx
*chip
)
3536 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3539 struct snd_card
*card
= chip
->card
;
3542 /* set EGPIO to default */
3543 hercules_init(chip
);
3545 snd_printdd ("initializing Hercules mixer\n");
3547 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3548 if (chip
->in_suspend
)
3551 for (idx
= 0 ; idx
< ARRAY_SIZE(snd_hercules_controls
); idx
++) {
3552 struct snd_kcontrol
*kctl
;
3554 kctl
= snd_ctl_new1(&snd_hercules_controls
[idx
], chip
);
3555 if ((err
= snd_ctl_add(card
, kctl
)) < 0) {
3556 printk (KERN_ERR
"cs46xx: failed to initialize Hercules mixer (%d)\n",err
);
3569 static void amp_voyetra_4294(struct snd_cs46xx
*chip
, int change
)
3571 chip
->amplifier
+= change
;
3573 if (chip
->amplifier
) {
3574 /* Switch the GPIO pins 7 and 8 to open drain */
3575 snd_cs46xx_codec_write(chip
, 0x4C,
3576 snd_cs46xx_codec_read(chip
, 0x4C) & 0xFE7F);
3577 snd_cs46xx_codec_write(chip
, 0x4E,
3578 snd_cs46xx_codec_read(chip
, 0x4E) | 0x0180);
3579 /* Now wake the AMP (this might be backwards) */
3580 snd_cs46xx_codec_write(chip
, 0x54,
3581 snd_cs46xx_codec_read(chip
, 0x54) & ~0x0180);
3583 snd_cs46xx_codec_write(chip
, 0x54,
3584 snd_cs46xx_codec_read(chip
, 0x54) | 0x0180);
3591 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3592 * whenever we need to beat on the chip.
3594 * The original idea and code for this hack comes from David Kaiser at
3595 * Linuxcare. Perhaps one day Crystal will document their chips well
3596 * enough to make them useful.
3599 static void clkrun_hack(struct snd_cs46xx
*chip
, int change
)
3603 if (!chip
->acpi_port
)
3606 chip
->amplifier
+= change
;
3608 /* Read ACPI port */
3609 nval
= control
= inw(chip
->acpi_port
+ 0x10);
3611 /* Flip CLKRUN off while running */
3612 if (! chip
->amplifier
)
3616 if (nval
!= control
)
3617 outw(nval
, chip
->acpi_port
+ 0x10);
3622 * detect intel piix4
3624 static void clkrun_init(struct snd_cs46xx
*chip
)
3626 struct pci_dev
*pdev
;
3629 chip
->acpi_port
= 0;
3631 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
3632 PCI_DEVICE_ID_INTEL_82371AB_3
, NULL
);
3634 return; /* Not a thinkpad thats for sure */
3636 /* Find the control port */
3637 pci_read_config_byte(pdev
, 0x41, &pp
);
3638 chip
->acpi_port
= pp
<< 8;
3652 void (*init
)(struct snd_cs46xx
*);
3653 void (*amp
)(struct snd_cs46xx
*, int);
3654 void (*active
)(struct snd_cs46xx
*, int);
3655 void (*mixer_init
)(struct snd_cs46xx
*);
3658 static struct cs_card_type cards
[] = {
3662 .name
= "Genius Soundmaker 128 value",
3663 /* nothing special */
3670 .mixer_init
= voyetra_mixer_init
,
3675 .name
= "Mitac MI6020/21",
3678 /* Hercules Game Theatre XP */
3680 .vendor
= 0x14af, /* Guillemot Corporation */
3682 .name
= "Hercules Game Theatre XP",
3683 .amp
= amp_hercules
,
3684 .mixer_init
= hercules_mixer_init
,
3689 .name
= "Hercules Game Theatre XP",
3690 .amp
= amp_hercules
,
3691 .mixer_init
= hercules_mixer_init
,
3696 .name
= "Hercules Game Theatre XP",
3697 .amp
= amp_hercules
,
3698 .mixer_init
= hercules_mixer_init
,
3704 .name
= "Hercules Game Theatre XP",
3705 .amp
= amp_hercules
,
3706 .mixer_init
= hercules_mixer_init
,
3711 .name
= "Hercules Game Theatre XP",
3712 .amp
= amp_hercules
,
3713 .mixer_init
= hercules_mixer_init
,
3718 .name
= "Hercules Game Theatre XP",
3719 .amp
= amp_hercules
,
3720 .mixer_init
= hercules_mixer_init
,
3722 /* Herculess Fortissimo */
3726 .name
= "Hercules Gamesurround Fortissimo II",
3731 .name
= "Hercules Gamesurround Fortissimo III 7.1",
3737 .name
= "Terratec DMX XFire 1024",
3742 .name
= "Terratec SiXPack 5.1",
3744 /* Not sure if the 570 needs the clkrun hack */
3746 .vendor
= PCI_VENDOR_ID_IBM
,
3748 .name
= "Thinkpad 570",
3749 .init
= clkrun_init
,
3750 .active
= clkrun_hack
,
3753 .vendor
= PCI_VENDOR_ID_IBM
,
3755 .name
= "Thinkpad 600X/A20/T20",
3756 .init
= clkrun_init
,
3757 .active
= clkrun_hack
,
3760 .vendor
= PCI_VENDOR_ID_IBM
,
3762 .name
= "Thinkpad 600E (unsupported)",
3771 #ifdef CONFIG_PM_SLEEP
3772 static unsigned int saved_regs
[] = {
3780 static int snd_cs46xx_suspend(struct device
*dev
)
3782 struct pci_dev
*pci
= to_pci_dev(dev
);
3783 struct snd_card
*card
= dev_get_drvdata(dev
);
3784 struct snd_cs46xx
*chip
= card
->private_data
;
3787 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
3788 chip
->in_suspend
= 1;
3789 snd_pcm_suspend_all(chip
->pcm
);
3790 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3791 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3793 snd_ac97_suspend(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3794 snd_ac97_suspend(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3796 /* save some registers */
3797 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3798 chip
->saved_regs
[i
] = snd_cs46xx_peekBA0(chip
, saved_regs
[i
]);
3800 amp_saved
= chip
->amplifier
;
3802 chip
->amplifier_ctrl(chip
, -chip
->amplifier
);
3803 snd_cs46xx_hw_stop(chip
);
3804 /* disable CLKRUN */
3805 chip
->active_ctrl(chip
, -chip
->amplifier
);
3806 chip
->amplifier
= amp_saved
; /* restore the status */
3808 pci_disable_device(pci
);
3809 pci_save_state(pci
);
3810 pci_set_power_state(pci
, PCI_D3hot
);
3814 static int snd_cs46xx_resume(struct device
*dev
)
3816 struct pci_dev
*pci
= to_pci_dev(dev
);
3817 struct snd_card
*card
= dev_get_drvdata(dev
);
3818 struct snd_cs46xx
*chip
= card
->private_data
;
3820 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3825 pci_set_power_state(pci
, PCI_D0
);
3826 pci_restore_state(pci
);
3827 if (pci_enable_device(pci
) < 0) {
3828 printk(KERN_ERR
"cs46xx: pci_enable_device failed, "
3829 "disabling device\n");
3830 snd_card_disconnect(card
);
3833 pci_set_master(pci
);
3835 amp_saved
= chip
->amplifier
;
3836 chip
->amplifier
= 0;
3837 chip
->active_ctrl(chip
, 1); /* force to on */
3839 snd_cs46xx_chip_init(chip
);
3841 snd_cs46xx_reset(chip
);
3842 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3843 cs46xx_dsp_resume(chip
);
3844 /* restore some registers */
3845 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3846 snd_cs46xx_pokeBA0(chip
, saved_regs
[i
], chip
->saved_regs
[i
]);
3848 snd_cs46xx_download_image(chip
);
3852 snd_cs46xx_codec_write(chip
, BA0_AC97_GENERAL_PURPOSE
,
3853 chip
->ac97_general_purpose
);
3854 snd_cs46xx_codec_write(chip
, AC97_POWER_CONTROL
,
3855 chip
->ac97_powerdown
);
3857 snd_cs46xx_codec_write(chip
, BA0_AC97_POWERDOWN
,
3858 chip
->ac97_powerdown
);
3862 snd_ac97_resume(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3863 snd_ac97_resume(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3868 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
3869 chip
->capt
.ctl
= tmp
& 0x0000ffff;
3870 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
3874 /* reset playback/capture */
3875 snd_cs46xx_set_play_sample_rate(chip
, 8000);
3876 snd_cs46xx_set_capture_sample_rate(chip
, 8000);
3877 snd_cs46xx_proc_start(chip
);
3879 cs46xx_enable_stream_irqs(chip
);
3882 chip
->amplifier_ctrl(chip
, 1); /* turn amp on */
3884 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */
3885 chip
->amplifier
= amp_saved
;
3886 chip
->in_suspend
= 0;
3887 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
3891 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm
, snd_cs46xx_suspend
, snd_cs46xx_resume
);
3892 #endif /* CONFIG_PM_SLEEP */
3898 int snd_cs46xx_create(struct snd_card
*card
,
3899 struct pci_dev
*pci
,
3900 int external_amp
, int thinkpad
,
3901 struct snd_cs46xx
**rchip
)
3903 struct snd_cs46xx
*chip
;
3905 struct snd_cs46xx_region
*region
;
3906 struct cs_card_type
*cp
;
3907 u16 ss_card
, ss_vendor
;
3908 static struct snd_device_ops ops
= {
3909 .dev_free
= snd_cs46xx_dev_free
,
3914 /* enable PCI device */
3915 if ((err
= pci_enable_device(pci
)) < 0)
3918 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
3920 pci_disable_device(pci
);
3923 spin_lock_init(&chip
->reg_lock
);
3924 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3925 mutex_init(&chip
->spos_mutex
);
3930 chip
->ba0_addr
= pci_resource_start(pci
, 0);
3931 chip
->ba1_addr
= pci_resource_start(pci
, 1);
3932 if (chip
->ba0_addr
== 0 || chip
->ba0_addr
== (unsigned long)~0 ||
3933 chip
->ba1_addr
== 0 || chip
->ba1_addr
== (unsigned long)~0) {
3934 snd_printk(KERN_ERR
"wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3935 chip
->ba0_addr
, chip
->ba1_addr
);
3936 snd_cs46xx_free(chip
);
3940 region
= &chip
->region
.name
.ba0
;
3941 strcpy(region
->name
, "CS46xx_BA0");
3942 region
->base
= chip
->ba0_addr
;
3943 region
->size
= CS46XX_BA0_SIZE
;
3945 region
= &chip
->region
.name
.data0
;
3946 strcpy(region
->name
, "CS46xx_BA1_data0");
3947 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM0
;
3948 region
->size
= CS46XX_BA1_DATA0_SIZE
;
3950 region
= &chip
->region
.name
.data1
;
3951 strcpy(region
->name
, "CS46xx_BA1_data1");
3952 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM1
;
3953 region
->size
= CS46XX_BA1_DATA1_SIZE
;
3955 region
= &chip
->region
.name
.pmem
;
3956 strcpy(region
->name
, "CS46xx_BA1_pmem");
3957 region
->base
= chip
->ba1_addr
+ BA1_SP_PMEM
;
3958 region
->size
= CS46XX_BA1_PRG_SIZE
;
3960 region
= &chip
->region
.name
.reg
;
3961 strcpy(region
->name
, "CS46xx_BA1_reg");
3962 region
->base
= chip
->ba1_addr
+ BA1_SP_REG
;
3963 region
->size
= CS46XX_BA1_REG_SIZE
;
3965 /* set up amp and clkrun hack */
3966 pci_read_config_word(pci
, PCI_SUBSYSTEM_VENDOR_ID
, &ss_vendor
);
3967 pci_read_config_word(pci
, PCI_SUBSYSTEM_ID
, &ss_card
);
3969 for (cp
= &cards
[0]; cp
->name
; cp
++) {
3970 if (cp
->vendor
== ss_vendor
&& cp
->id
== ss_card
) {
3971 snd_printdd ("hack for %s enabled\n", cp
->name
);
3973 chip
->amplifier_ctrl
= cp
->amp
;
3974 chip
->active_ctrl
= cp
->active
;
3975 chip
->mixer_init
= cp
->mixer_init
;
3984 snd_printk(KERN_INFO
"Crystal EAPD support forced on.\n");
3985 chip
->amplifier_ctrl
= amp_voyetra
;
3989 snd_printk(KERN_INFO
"Activating CLKRUN hack for Thinkpad.\n");
3990 chip
->active_ctrl
= clkrun_hack
;
3994 if (chip
->amplifier_ctrl
== NULL
)
3995 chip
->amplifier_ctrl
= amp_none
;
3996 if (chip
->active_ctrl
== NULL
)
3997 chip
->active_ctrl
= amp_none
;
3999 chip
->active_ctrl(chip
, 1); /* enable CLKRUN */
4001 pci_set_master(pci
);
4003 for (idx
= 0; idx
< 5; idx
++) {
4004 region
= &chip
->region
.idx
[idx
];
4005 if ((region
->resource
= request_mem_region(region
->base
, region
->size
,
4006 region
->name
)) == NULL
) {
4007 snd_printk(KERN_ERR
"unable to request memory region 0x%lx-0x%lx\n",
4008 region
->base
, region
->base
+ region
->size
- 1);
4009 snd_cs46xx_free(chip
);
4012 region
->remap_addr
= ioremap_nocache(region
->base
, region
->size
);
4013 if (region
->remap_addr
== NULL
) {
4014 snd_printk(KERN_ERR
"%s ioremap problem\n", region
->name
);
4015 snd_cs46xx_free(chip
);
4020 if (request_irq(pci
->irq
, snd_cs46xx_interrupt
, IRQF_SHARED
,
4021 KBUILD_MODNAME
, chip
)) {
4022 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
4023 snd_cs46xx_free(chip
);
4026 chip
->irq
= pci
->irq
;
4028 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4029 chip
->dsp_spos_instance
= cs46xx_dsp_spos_create(chip
);
4030 if (chip
->dsp_spos_instance
== NULL
) {
4031 snd_cs46xx_free(chip
);
4036 err
= snd_cs46xx_chip_init(chip
);
4038 snd_cs46xx_free(chip
);
4042 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) < 0) {
4043 snd_cs46xx_free(chip
);
4047 snd_cs46xx_proc_init(card
, chip
);
4049 #ifdef CONFIG_PM_SLEEP
4050 chip
->saved_regs
= kmalloc(sizeof(*chip
->saved_regs
) *
4051 ARRAY_SIZE(saved_regs
), GFP_KERNEL
);
4052 if (!chip
->saved_regs
) {
4053 snd_cs46xx_free(chip
);
4058 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */
4060 snd_card_set_dev(card
, &pci
->dev
);