sound/pci/echoaudio/layla24_dsp.c

   1 /****************************************************************************
   2
   3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   4    All rights reserved
   5    www.echoaudio.com
   6
   7    This file is part of Echo Digital Audio's generic driver library.
   8
   9    Echo Digital Audio's generic driver library is free software;
  10    you can redistribute it and/or modify it under the terms of
  11    the GNU General Public License as published by the Free Software Foundation.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  21    MA  02111-1307, USA.
  22
  23    *************************************************************************
  24
  25  Translation from C++ and adaptation for use in ALSA-Driver
  26  were made by Giuliano Pochini <pochini@shiny.it>
  27
  28 ****************************************************************************/
  29
  30
  31 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
  32 static int set_input_clock(struct echoaudio *chip, u16 clock);
  33 static int set_professional_spdif(struct echoaudio *chip, char prof);
  34 static int set_digital_mode(struct echoaudio *chip, u8 mode);
  35 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic);
  36 static int check_asic_status(struct echoaudio *chip);
  37
  38
  39 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
  40 {
  41         int err;
  42
  43         dev_dbg(chip->card->dev, "init_hw() - Layla24\n");
  44         if (snd_BUG_ON((subdevice_id & 0xfff0) != LAYLA24))
  45                 return -ENODEV;
  46
  47         if ((err = init_dsp_comm_page(chip))) {
  48                 dev_err(chip->card->dev,
  49                         "init_hw - could not initialize DSP comm page\n");
  50                 return err;
  51         }
  52
  53         chip->device_id = device_id;
  54         chip->subdevice_id = subdevice_id;
  55         chip->bad_board = TRUE;
  56         chip->has_midi = TRUE;
  57         chip->dsp_code_to_load = FW_LAYLA24_DSP;
  58         chip->input_clock_types =
  59                 ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
  60                 ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
  61         chip->digital_modes =
  62                 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
  63                 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
  64                 ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
  65
  66         if ((err = load_firmware(chip)) < 0)
  67                 return err;
  68         chip->bad_board = FALSE;
  69
  70         if ((err = init_line_levels(chip)) < 0)
  71                 return err;
  72
  73         dev_dbg(chip->card->dev, "init_hw done\n");
  74         return err;
  75 }
  76
  77
  78
  79 static int set_mixer_defaults(struct echoaudio *chip)
  80 {
  81         chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
  82         chip->professional_spdif = FALSE;
  83         chip->digital_in_automute = TRUE;
  84         return init_line_levels(chip);
  85 }
  86
  87
  88
  89 static u32 detect_input_clocks(const struct echoaudio *chip)
  90 {
  91         u32 clocks_from_dsp, clock_bits;
  92
  93         /* Map the DSP clock detect bits to the generic driver clock detect bits */
  94         clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
  95
  96         clock_bits = ECHO_CLOCK_BIT_INTERNAL;
  97
  98         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
  99                 clock_bits |= ECHO_CLOCK_BIT_SPDIF;
 100
 101         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
 102                 clock_bits |= ECHO_CLOCK_BIT_ADAT;
 103
 104         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
 105                 clock_bits |= ECHO_CLOCK_BIT_WORD;
 106
 107         return clock_bits;
 108 }
 109
 110
 111
 112 /* Layla24 has an ASIC on the PCI card and another ASIC in the external box;
 113 both need to be loaded. */
 114 static int load_asic(struct echoaudio *chip)
 115 {
 116         int err;
 117
 118         if (chip->asic_loaded)
 119                 return 1;
 120
 121         dev_dbg(chip->card->dev, "load_asic\n");
 122
 123         /* Give the DSP a few milliseconds to settle down */
 124         mdelay(10);
 125
 126         /* Load the ASIC for the PCI card */
 127         err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC,
 128                                 FW_LAYLA24_1_ASIC);
 129         if (err < 0)
 130                 return err;
 131
 132         chip->asic_code = FW_LAYLA24_2S_ASIC;
 133
 134         /* Now give the new ASIC a little time to set up */
 135         mdelay(10);
 136
 137         /* Do the external one */
 138         err = load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
 139                                 FW_LAYLA24_2S_ASIC);
 140         if (err < 0)
 141                 return FALSE;
 142
 143         /* Now give the external ASIC a little time to set up */
 144         mdelay(10);
 145
 146         /* See if it worked */
 147         err = check_asic_status(chip);
 148
 149         /* Set up the control register if the load succeeded -
 150            48 kHz, internal clock, S/PDIF RCA mode */
 151         if (!err)
 152                 err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ,
 153                                         TRUE);
 154
 155         dev_dbg(chip->card->dev, "load_asic() done\n");
 156         return err;
 157 }
 158
 159
 160
 161 static int set_sample_rate(struct echoaudio *chip, u32 rate)
 162 {
 163         u32 control_reg, clock, base_rate;
 164
 165         if (snd_BUG_ON(rate >= 50000 &&
 166                        chip->digital_mode == DIGITAL_MODE_ADAT))
 167                 return -EINVAL;
 168
 169         /* Only set the clock for internal mode. */
 170         if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
 171                 dev_warn(chip->card->dev,
 172                          "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n");
 173                 /* Save the rate anyhow */
 174                 chip->comm_page->sample_rate = cpu_to_le32(rate);
 175                 chip->sample_rate = rate;
 176                 return 0;
 177         }
 178
 179         /* Get the control register & clear the appropriate bits */
 180         control_reg = le32_to_cpu(chip->comm_page->control_register);
 181         control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
 182
 183         clock = 0;
 184
 185         switch (rate) {
 186         case 96000:
 187                 clock = GML_96KHZ;
 188                 break;
 189         case 88200:
 190                 clock = GML_88KHZ;
 191                 break;
 192         case 48000:
 193                 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
 194                 break;
 195         case 44100:
 196                 clock = GML_44KHZ;
 197                 /* Professional mode */
 198                 if (control_reg & GML_SPDIF_PRO_MODE)
 199                         clock |= GML_SPDIF_SAMPLE_RATE0;
 200                 break;
 201         case 32000:
 202                 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
 203                         GML_SPDIF_SAMPLE_RATE1;
 204                 break;
 205         case 22050:
 206                 clock = GML_22KHZ;
 207                 break;
 208         case 16000:
 209                 clock = GML_16KHZ;
 210                 break;
 211         case 11025:
 212                 clock = GML_11KHZ;
 213                 break;
 214         case 8000:
 215                 clock = GML_8KHZ;
 216                 break;
 217         default:
 218                 /* If this is a non-standard rate, then the driver needs to
 219                 use Layla24's special "continuous frequency" mode */
 220                 clock = LAYLA24_CONTINUOUS_CLOCK;
 221                 if (rate > 50000) {
 222                         base_rate = rate >> 1;
 223                         control_reg |= GML_DOUBLE_SPEED_MODE;
 224                 } else {
 225                         base_rate = rate;
 226                 }
 227
 228                 if (base_rate < 25000)
 229                         base_rate = 25000;
 230
 231                 if (wait_handshake(chip))
 232                         return -EIO;
 233
 234                 chip->comm_page->sample_rate =
 235                         cpu_to_le32(LAYLA24_MAGIC_NUMBER / base_rate - 2);
 236
 237                 clear_handshake(chip);
 238                 send_vector(chip, DSP_VC_SET_LAYLA24_FREQUENCY_REG);
 239         }
 240
 241         control_reg |= clock;
 242
 243         chip->comm_page->sample_rate = cpu_to_le32(rate);       /* ignored by the DSP ? */
 244         chip->sample_rate = rate;
 245         dev_dbg(chip->card->dev,
 246                 "set_sample_rate: %d clock %d\n", rate, control_reg);
 247
 248         return write_control_reg(chip, control_reg, FALSE);
 249 }
 250
 251
 252
 253 static int set_input_clock(struct echoaudio *chip, u16 clock)
 254 {
 255         u32 control_reg, clocks_from_dsp;
 256
 257         /* Mask off the clock select bits */
 258         control_reg = le32_to_cpu(chip->comm_page->control_register) &
 259                 GML_CLOCK_CLEAR_MASK;
 260         clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
 261
 262         /* Pick the new clock */
 263         switch (clock) {
 264         case ECHO_CLOCK_INTERNAL:
 265                 dev_dbg(chip->card->dev, "Set Layla24 clock to INTERNAL\n");
 266                 chip->input_clock = ECHO_CLOCK_INTERNAL;
 267                 return set_sample_rate(chip, chip->sample_rate);
 268         case ECHO_CLOCK_SPDIF:
 269                 if (chip->digital_mode == DIGITAL_MODE_ADAT)
 270                         return -EAGAIN;
 271                 control_reg |= GML_SPDIF_CLOCK;
 272                 /* Layla24 doesn't support 96KHz S/PDIF */
 273                 control_reg &= ~GML_DOUBLE_SPEED_MODE;
 274                 dev_dbg(chip->card->dev, "Set Layla24 clock to SPDIF\n");
 275                 break;
 276         case ECHO_CLOCK_WORD:
 277                 control_reg |= GML_WORD_CLOCK;
 278                 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
 279                         control_reg |= GML_DOUBLE_SPEED_MODE;
 280                 else
 281                         control_reg &= ~GML_DOUBLE_SPEED_MODE;
 282                 dev_dbg(chip->card->dev, "Set Layla24 clock to WORD\n");
 283                 break;
 284         case ECHO_CLOCK_ADAT:
 285                 if (chip->digital_mode != DIGITAL_MODE_ADAT)
 286                         return -EAGAIN;
 287                 control_reg |= GML_ADAT_CLOCK;
 288                 control_reg &= ~GML_DOUBLE_SPEED_MODE;
 289                 dev_dbg(chip->card->dev, "Set Layla24 clock to ADAT\n");
 290                 break;
 291         default:
 292                 dev_err(chip->card->dev,
 293                         "Input clock 0x%x not supported for Layla24\n", clock);
 294                 return -EINVAL;
 295         }
 296
 297         chip->input_clock = clock;
 298         return write_control_reg(chip, control_reg, TRUE);
 299 }
 300
 301
 302
 303 /* Depending on what digital mode you want, Layla24 needs different ASICs
 304 loaded.  This function checks the ASIC needed for the new mode and sees
 305 if it matches the one already loaded. */
 306 static int switch_asic(struct echoaudio *chip, short asic)
 307 {
 308         s8 *monitors;
 309
 310         /*  Check to see if this is already loaded */
 311         if (asic != chip->asic_code) {
 312                 monitors = kmemdup(chip->comm_page->monitors,
 313                                         MONITOR_ARRAY_SIZE, GFP_KERNEL);
 314                 if (! monitors)
 315                         return -ENOMEM;
 316
 317                 memset(chip->comm_page->monitors, ECHOGAIN_MUTED,
 318                        MONITOR_ARRAY_SIZE);
 319
 320                 /* Load the desired ASIC */
 321                 if (load_asic_generic(chip, DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC,
 322                                       asic) < 0) {
 323                         memcpy(chip->comm_page->monitors, monitors,
 324                                MONITOR_ARRAY_SIZE);
 325                         kfree(monitors);
 326                         return -EIO;
 327                 }
 328                 chip->asic_code = asic;
 329                 memcpy(chip->comm_page->monitors, monitors, MONITOR_ARRAY_SIZE);
 330                 kfree(monitors);
 331         }
 332
 333         return 0;
 334 }
 335
 336
 337
 338 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
 339 {
 340         u32 control_reg;
 341         int err, incompatible_clock;
 342         short asic;
 343
 344         /* Set clock to "internal" if it's not compatible with the new mode */
 345         incompatible_clock = FALSE;
 346         switch (mode) {
 347         case DIGITAL_MODE_SPDIF_OPTICAL:
 348         case DIGITAL_MODE_SPDIF_RCA:
 349                 if (chip->input_clock == ECHO_CLOCK_ADAT)
 350                         incompatible_clock = TRUE;
 351                 asic = FW_LAYLA24_2S_ASIC;
 352                 break;
 353         case DIGITAL_MODE_ADAT:
 354                 if (chip->input_clock == ECHO_CLOCK_SPDIF)
 355                         incompatible_clock = TRUE;
 356                 asic = FW_LAYLA24_2A_ASIC;
 357                 break;
 358         default:
 359                 dev_err(chip->card->dev,
 360                         "Digital mode not supported: %d\n", mode);
 361                 return -EINVAL;
 362         }
 363
 364         if (incompatible_clock) {       /* Switch to 48KHz, internal */
 365                 chip->sample_rate = 48000;
 366                 spin_lock_irq(&chip->lock);
 367                 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
 368                 spin_unlock_irq(&chip->lock);
 369         }
 370
 371         /* switch_asic() can sleep */
 372         if (switch_asic(chip, asic) < 0)
 373                 return -EIO;
 374
 375         spin_lock_irq(&chip->lock);
 376
 377         /* Tweak the control register */
 378         control_reg = le32_to_cpu(chip->comm_page->control_register);
 379         control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
 380
 381         switch (mode) {
 382         case DIGITAL_MODE_SPDIF_OPTICAL:
 383                 control_reg |= GML_SPDIF_OPTICAL_MODE;
 384                 break;
 385         case DIGITAL_MODE_SPDIF_RCA:
 386                 /* GML_SPDIF_OPTICAL_MODE bit cleared */
 387                 break;
 388         case DIGITAL_MODE_ADAT:
 389                 control_reg |= GML_ADAT_MODE;
 390                 control_reg &= ~GML_DOUBLE_SPEED_MODE;
 391                 break;
 392         }
 393
 394         err = write_control_reg(chip, control_reg, TRUE);
 395         spin_unlock_irq(&chip->lock);
 396         if (err < 0)
 397                 return err;
 398         chip->digital_mode = mode;
 399
 400         dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode);
 401         return incompatible_clock;
 402 }