3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index
= SNDRV_DEFAULT_IDX1
;
53 static char *id
= SNDRV_DEFAULT_STR1
;
55 static int position_fix
;
56 static int probe_mask
= -1;
57 static int single_cmd
;
59 module_param(index
, int, 0444);
60 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
61 module_param(id
, charp
, 0444);
62 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
63 module_param(model
, charp
, 0444);
64 MODULE_PARM_DESC(model
, "Use the given board model.");
65 module_param(position_fix
, int, 0444);
66 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
67 module_param(probe_mask
, int, 0444);
68 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
69 module_param(single_cmd
, bool, 0444);
70 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs (for debugging only).");
73 /* just for backward compatibility */
75 module_param(enable
, bool, 0444);
77 MODULE_LICENSE("GPL");
78 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
88 MODULE_DESCRIPTION("Intel HDA driver");
90 #define SFX "hda-intel: "
95 #define ICH6_REG_GCAP 0x00
96 #define ICH6_REG_VMIN 0x02
97 #define ICH6_REG_VMAJ 0x03
98 #define ICH6_REG_OUTPAY 0x04
99 #define ICH6_REG_INPAY 0x06
100 #define ICH6_REG_GCTL 0x08
101 #define ICH6_REG_WAKEEN 0x0c
102 #define ICH6_REG_STATESTS 0x0e
103 #define ICH6_REG_GSTS 0x10
104 #define ICH6_REG_INTCTL 0x20
105 #define ICH6_REG_INTSTS 0x24
106 #define ICH6_REG_WALCLK 0x30
107 #define ICH6_REG_SYNC 0x34
108 #define ICH6_REG_CORBLBASE 0x40
109 #define ICH6_REG_CORBUBASE 0x44
110 #define ICH6_REG_CORBWP 0x48
111 #define ICH6_REG_CORBRP 0x4A
112 #define ICH6_REG_CORBCTL 0x4c
113 #define ICH6_REG_CORBSTS 0x4d
114 #define ICH6_REG_CORBSIZE 0x4e
116 #define ICH6_REG_RIRBLBASE 0x50
117 #define ICH6_REG_RIRBUBASE 0x54
118 #define ICH6_REG_RIRBWP 0x58
119 #define ICH6_REG_RINTCNT 0x5a
120 #define ICH6_REG_RIRBCTL 0x5c
121 #define ICH6_REG_RIRBSTS 0x5d
122 #define ICH6_REG_RIRBSIZE 0x5e
124 #define ICH6_REG_IC 0x60
125 #define ICH6_REG_IR 0x64
126 #define ICH6_REG_IRS 0x68
127 #define ICH6_IRS_VALID (1<<1)
128 #define ICH6_IRS_BUSY (1<<0)
130 #define ICH6_REG_DPLBASE 0x70
131 #define ICH6_REG_DPUBASE 0x74
132 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
134 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
135 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
137 /* stream register offsets from stream base */
138 #define ICH6_REG_SD_CTL 0x00
139 #define ICH6_REG_SD_STS 0x03
140 #define ICH6_REG_SD_LPIB 0x04
141 #define ICH6_REG_SD_CBL 0x08
142 #define ICH6_REG_SD_LVI 0x0c
143 #define ICH6_REG_SD_FIFOW 0x0e
144 #define ICH6_REG_SD_FIFOSIZE 0x10
145 #define ICH6_REG_SD_FORMAT 0x12
146 #define ICH6_REG_SD_BDLPL 0x18
147 #define ICH6_REG_SD_BDLPU 0x1c
150 #define ICH6_PCIREG_TCSEL 0x44
156 /* max number of SDs */
157 /* ICH, ATI and VIA have 4 playback and 4 capture */
158 #define ICH6_CAPTURE_INDEX 0
159 #define ICH6_NUM_CAPTURE 4
160 #define ICH6_PLAYBACK_INDEX 4
161 #define ICH6_NUM_PLAYBACK 4
163 /* ULI has 6 playback and 5 capture */
164 #define ULI_CAPTURE_INDEX 0
165 #define ULI_NUM_CAPTURE 5
166 #define ULI_PLAYBACK_INDEX 5
167 #define ULI_NUM_PLAYBACK 6
169 /* this number is statically defined for simplicity */
170 #define MAX_AZX_DEV 16
172 /* max number of fragments - we may use more if allocating more pages for BDL */
173 #define BDL_SIZE PAGE_ALIGN(8192)
174 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
175 /* max buffer size - no h/w limit, you can increase as you like */
176 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
177 /* max number of PCM devics per card */
178 #define AZX_MAX_AUDIO_PCMS 6
179 #define AZX_MAX_MODEM_PCMS 2
180 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
182 /* RIRB int mask: overrun[2], response[0] */
183 #define RIRB_INT_RESPONSE 0x01
184 #define RIRB_INT_OVERRUN 0x04
185 #define RIRB_INT_MASK 0x05
187 /* STATESTS int mask: SD2,SD1,SD0 */
188 #define STATESTS_INT_MASK 0x07
189 #define AZX_MAX_CODECS 4
192 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
193 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
194 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
195 #define SD_CTL_STREAM_TAG_SHIFT 20
197 /* SD_CTL and SD_STS */
198 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
199 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
200 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
201 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
204 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
206 /* INTCTL and INTSTS */
207 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
208 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
209 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
211 /* GCTL unsolicited response enable bit */
212 #define ICH6_GCTL_UREN (1<<8)
215 #define ICH6_GCTL_RESET (1<<0)
217 /* CORB/RIRB control, read/write pointer */
218 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
219 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
220 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
221 /* below are so far hardcoded - should read registers in future */
222 #define ICH6_MAX_CORB_ENTRIES 256
223 #define ICH6_MAX_RIRB_ENTRIES 256
225 /* position fix mode */
233 /* Defines for ATI HD Audio support in SB450 south bridge */
234 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
235 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
237 /* Defines for Nvidia HDA support */
238 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
239 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
245 u32
*bdl
; /* virtual address of the BDL */
246 dma_addr_t bdl_addr
; /* physical address of the BDL */
247 volatile u32
*posbuf
; /* position buffer pointer */
249 unsigned int bufsize
; /* size of the play buffer in bytes */
250 unsigned int fragsize
; /* size of each period in bytes */
251 unsigned int frags
; /* number for period in the play buffer */
252 unsigned int fifo_size
; /* FIFO size */
253 unsigned int last_pos
; /* last updated period position */
255 void __iomem
*sd_addr
; /* stream descriptor pointer */
257 u32 sd_int_sta_mask
; /* stream int status mask */
260 struct snd_pcm_substream
*substream
; /* assigned substream, set in PCM open */
261 unsigned int format_val
; /* format value to be set in the controller and the codec */
262 unsigned char stream_tag
; /* assigned stream */
263 unsigned char index
; /* stream index */
265 unsigned int opened
: 1;
266 unsigned int running
: 1;
267 unsigned int period_updating
: 1;
272 u32
*buf
; /* CORB/RIRB buffer
273 * Each CORB entry is 4byte, RIRB is 8byte
275 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
277 unsigned short rp
, wp
; /* read/write pointers */
278 int cmds
; /* number of pending requests */
279 u32 res
; /* last read value */
283 struct snd_card
*card
;
286 /* chip type specific */
288 int playback_streams
;
289 int playback_index_offset
;
291 int capture_index_offset
;
296 void __iomem
*remap_addr
;
301 struct mutex open_mutex
;
303 /* streams (x num_streams) */
304 struct azx_dev
*azx_dev
;
307 unsigned int pcm_devs
;
308 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
311 unsigned short codec_mask
;
318 /* BDL, CORB/RIRB and position buffers */
319 struct snd_dma_buffer bdl
;
320 struct snd_dma_buffer rb
;
321 struct snd_dma_buffer posbuf
;
325 unsigned int initialized
: 1;
326 unsigned int single_cmd
: 1;
339 static char *driver_short_names
[] __devinitdata
= {
340 [AZX_DRIVER_ICH
] = "HDA Intel",
341 [AZX_DRIVER_ATI
] = "HDA ATI SB",
342 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
343 [AZX_DRIVER_SIS
] = "HDA SIS966",
344 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
345 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
349 * macros for easy use
351 #define azx_writel(chip,reg,value) \
352 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
353 #define azx_readl(chip,reg) \
354 readl((chip)->remap_addr + ICH6_REG_##reg)
355 #define azx_writew(chip,reg,value) \
356 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
357 #define azx_readw(chip,reg) \
358 readw((chip)->remap_addr + ICH6_REG_##reg)
359 #define azx_writeb(chip,reg,value) \
360 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
361 #define azx_readb(chip,reg) \
362 readb((chip)->remap_addr + ICH6_REG_##reg)
364 #define azx_sd_writel(dev,reg,value) \
365 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
366 #define azx_sd_readl(dev,reg) \
367 readl((dev)->sd_addr + ICH6_REG_##reg)
368 #define azx_sd_writew(dev,reg,value) \
369 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
370 #define azx_sd_readw(dev,reg) \
371 readw((dev)->sd_addr + ICH6_REG_##reg)
372 #define azx_sd_writeb(dev,reg,value) \
373 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
374 #define azx_sd_readb(dev,reg) \
375 readb((dev)->sd_addr + ICH6_REG_##reg)
377 /* for pcm support */
378 #define get_azx_dev(substream) (substream->runtime->private_data)
380 /* Get the upper 32bit of the given dma_addr_t
381 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
383 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
387 * Interface for HD codec
391 * CORB / RIRB interface
393 static int azx_alloc_cmd_io(struct azx
*chip
)
397 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
398 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
399 PAGE_SIZE
, &chip
->rb
);
401 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
407 static void azx_init_cmd_io(struct azx
*chip
)
410 chip
->corb
.addr
= chip
->rb
.addr
;
411 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
412 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
413 azx_writel(chip
, CORBUBASE
, upper_32bit(chip
->corb
.addr
));
415 /* set the corb size to 256 entries (ULI requires explicitly) */
416 azx_writeb(chip
, CORBSIZE
, 0x02);
417 /* set the corb write pointer to 0 */
418 azx_writew(chip
, CORBWP
, 0);
419 /* reset the corb hw read pointer */
420 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
421 /* enable corb dma */
422 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
425 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
426 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
427 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
428 azx_writel(chip
, RIRBUBASE
, upper_32bit(chip
->rirb
.addr
));
430 /* set the rirb size to 256 entries (ULI requires explicitly) */
431 azx_writeb(chip
, RIRBSIZE
, 0x02);
432 /* reset the rirb hw write pointer */
433 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
434 /* set N=1, get RIRB response interrupt for new entry */
435 azx_writew(chip
, RINTCNT
, 1);
436 /* enable rirb dma and response irq */
437 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
438 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
441 static void azx_free_cmd_io(struct azx
*chip
)
443 /* disable ringbuffer DMAs */
444 azx_writeb(chip
, RIRBCTL
, 0);
445 azx_writeb(chip
, CORBCTL
, 0);
449 static int azx_corb_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
, int direct
,
450 unsigned int verb
, unsigned int para
)
452 struct azx
*chip
= codec
->bus
->private_data
;
456 val
= (u32
)(codec
->addr
& 0x0f) << 28;
457 val
|= (u32
)direct
<< 27;
458 val
|= (u32
)nid
<< 20;
462 /* add command to corb */
463 wp
= azx_readb(chip
, CORBWP
);
465 wp
%= ICH6_MAX_CORB_ENTRIES
;
467 spin_lock_irq(&chip
->reg_lock
);
469 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
470 azx_writel(chip
, CORBWP
, wp
);
471 spin_unlock_irq(&chip
->reg_lock
);
476 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
478 /* retrieve RIRB entry - called from interrupt handler */
479 static void azx_update_rirb(struct azx
*chip
)
484 wp
= azx_readb(chip
, RIRBWP
);
485 if (wp
== chip
->rirb
.wp
)
489 while (chip
->rirb
.rp
!= wp
) {
491 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
493 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
494 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
495 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
496 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
497 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
498 else if (chip
->rirb
.cmds
) {
500 chip
->rirb
.res
= res
;
505 /* receive a response */
506 static unsigned int azx_rirb_get_response(struct hda_codec
*codec
)
508 struct azx
*chip
= codec
->bus
->private_data
;
511 while (chip
->rirb
.cmds
) {
514 "hda_intel: azx_get_response timeout, "
515 "switching to single_cmd mode...\n");
516 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
518 /* switch to single_cmd mode */
519 chip
->single_cmd
= 1;
520 azx_free_cmd_io(chip
);
525 return chip
->rirb
.res
; /* the last value */
529 * Use the single immediate command instead of CORB/RIRB for simplicity
531 * Note: according to Intel, this is not preferred use. The command was
532 * intended for the BIOS only, and may get confused with unsolicited
533 * responses. So, we shouldn't use it for normal operation from the
535 * I left the codes, however, for debugging/testing purposes.
539 static int azx_single_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
540 int direct
, unsigned int verb
,
543 struct azx
*chip
= codec
->bus
->private_data
;
547 val
= (u32
)(codec
->addr
& 0x0f) << 28;
548 val
|= (u32
)direct
<< 27;
549 val
|= (u32
)nid
<< 20;
554 /* check ICB busy bit */
555 if (! (azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
)) {
556 /* Clear IRV valid bit */
557 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_VALID
);
558 azx_writel(chip
, IC
, val
);
559 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_BUSY
);
564 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip
, IRS
), val
);
568 /* receive a response */
569 static unsigned int azx_single_get_response(struct hda_codec
*codec
)
571 struct azx
*chip
= codec
->bus
->private_data
;
575 /* check IRV busy bit */
576 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
577 return azx_readl(chip
, IR
);
580 snd_printd(SFX
"get_response timeout: IRS=0x%x\n", azx_readw(chip
, IRS
));
581 return (unsigned int)-1;
585 * The below are the main callbacks from hda_codec.
587 * They are just the skeleton to call sub-callbacks according to the
588 * current setting of chip->single_cmd.
592 static int azx_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
593 int direct
, unsigned int verb
,
596 struct azx
*chip
= codec
->bus
->private_data
;
597 if (chip
->single_cmd
)
598 return azx_single_send_cmd(codec
, nid
, direct
, verb
, para
);
600 return azx_corb_send_cmd(codec
, nid
, direct
, verb
, para
);
604 static unsigned int azx_get_response(struct hda_codec
*codec
)
606 struct azx
*chip
= codec
->bus
->private_data
;
607 if (chip
->single_cmd
)
608 return azx_single_get_response(codec
);
610 return azx_rirb_get_response(codec
);
614 /* reset codec link */
615 static int azx_reset(struct azx
*chip
)
619 /* reset controller */
620 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
623 while (azx_readb(chip
, GCTL
) && --count
)
626 /* delay for >= 100us for codec PLL to settle per spec
627 * Rev 0.9 section 5.5.1
631 /* Bring controller out of reset */
632 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
635 while (! azx_readb(chip
, GCTL
) && --count
)
638 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
641 /* check to see if controller is ready */
642 if (! azx_readb(chip
, GCTL
)) {
643 snd_printd("azx_reset: controller not ready!\n");
647 /* Accept unsolicited responses */
648 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
651 if (! chip
->codec_mask
) {
652 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
653 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
664 /* enable interrupts */
665 static void azx_int_enable(struct azx
*chip
)
667 /* enable controller CIE and GIE */
668 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
669 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
672 /* disable interrupts */
673 static void azx_int_disable(struct azx
*chip
)
677 /* disable interrupts in stream descriptor */
678 for (i
= 0; i
< chip
->num_streams
; i
++) {
679 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
680 azx_sd_writeb(azx_dev
, SD_CTL
,
681 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
684 /* disable SIE for all streams */
685 azx_writeb(chip
, INTCTL
, 0);
687 /* disable controller CIE and GIE */
688 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
689 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
692 /* clear interrupts */
693 static void azx_int_clear(struct azx
*chip
)
697 /* clear stream status */
698 for (i
= 0; i
< chip
->num_streams
; i
++) {
699 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
700 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
704 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
706 /* clear rirb status */
707 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
709 /* clear int status */
710 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
714 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
717 azx_writeb(chip
, INTCTL
,
718 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
719 /* set DMA start and interrupt mask */
720 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
721 SD_CTL_DMA_START
| SD_INT_MASK
);
725 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
728 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
729 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
730 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
732 azx_writeb(chip
, INTCTL
,
733 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
738 * initialize the chip
740 static void azx_init_chip(struct azx
*chip
)
744 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
745 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
746 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
748 pci_read_config_byte (chip
->pci
, ICH6_PCIREG_TCSEL
, ®
);
749 pci_write_config_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, reg
& 0xf8);
751 /* reset controller */
754 /* initialize interrupts */
756 azx_int_enable(chip
);
758 /* initialize the codec command I/O */
759 if (! chip
->single_cmd
)
760 azx_init_cmd_io(chip
);
762 /* program the position buffer */
763 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
764 azx_writel(chip
, DPUBASE
, upper_32bit(chip
->posbuf
.addr
));
766 switch (chip
->driver_type
) {
768 /* For ATI SB450 azalia HD audio, we need to enable snoop */
769 pci_read_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
771 pci_write_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
772 (reg
& 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
774 case AZX_DRIVER_NVIDIA
:
775 /* For NVIDIA HDA, enable snoop */
776 pci_read_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
, ®
);
777 pci_write_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
,
778 (reg
& 0xf0) | NVIDIA_HDA_ENABLE_COHBITS
);
787 static irqreturn_t
azx_interrupt(int irq
, void* dev_id
, struct pt_regs
*regs
)
789 struct azx
*chip
= dev_id
;
790 struct azx_dev
*azx_dev
;
794 spin_lock(&chip
->reg_lock
);
796 status
= azx_readl(chip
, INTSTS
);
798 spin_unlock(&chip
->reg_lock
);
802 for (i
= 0; i
< chip
->num_streams
; i
++) {
803 azx_dev
= &chip
->azx_dev
[i
];
804 if (status
& azx_dev
->sd_int_sta_mask
) {
805 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
806 if (azx_dev
->substream
&& azx_dev
->running
) {
807 azx_dev
->period_updating
= 1;
808 spin_unlock(&chip
->reg_lock
);
809 snd_pcm_period_elapsed(azx_dev
->substream
);
810 spin_lock(&chip
->reg_lock
);
811 azx_dev
->period_updating
= 0;
817 status
= azx_readb(chip
, RIRBSTS
);
818 if (status
& RIRB_INT_MASK
) {
819 if (! chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
820 azx_update_rirb(chip
);
821 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
825 /* clear state status int */
826 if (azx_readb(chip
, STATESTS
) & 0x04)
827 azx_writeb(chip
, STATESTS
, 0x04);
829 spin_unlock(&chip
->reg_lock
);
838 static void azx_setup_periods(struct azx_dev
*azx_dev
)
840 u32
*bdl
= azx_dev
->bdl
;
841 dma_addr_t dma_addr
= azx_dev
->substream
->runtime
->dma_addr
;
844 /* reset BDL address */
845 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
846 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
848 /* program the initial BDL entries */
849 for (idx
= 0; idx
< azx_dev
->frags
; idx
++) {
850 unsigned int off
= idx
<< 2; /* 4 dword step */
851 dma_addr_t addr
= dma_addr
+ idx
* azx_dev
->fragsize
;
852 /* program the address field of the BDL entry */
853 bdl
[off
] = cpu_to_le32((u32
)addr
);
854 bdl
[off
+1] = cpu_to_le32(upper_32bit(addr
));
856 /* program the size field of the BDL entry */
857 bdl
[off
+2] = cpu_to_le32(azx_dev
->fragsize
);
859 /* program the IOC to enable interrupt when buffer completes */
860 bdl
[off
+3] = cpu_to_le32(0x01);
865 * set up the SD for streaming
867 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
872 /* make sure the run bit is zero for SD */
873 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_CTL_DMA_START
);
875 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) | SD_CTL_STREAM_RESET
);
878 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
881 val
&= ~SD_CTL_STREAM_RESET
;
882 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
886 /* waiting for hardware to report that the stream is out of reset */
887 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
891 /* program the stream_tag */
892 azx_sd_writel(azx_dev
, SD_CTL
,
893 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
) |
894 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
896 /* program the length of samples in cyclic buffer */
897 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
899 /* program the stream format */
900 /* this value needs to be the same as the one programmed */
901 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
903 /* program the stream LVI (last valid index) of the BDL */
904 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
906 /* program the BDL address */
907 /* lower BDL address */
908 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl_addr
);
909 /* upper BDL address */
910 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32bit(azx_dev
->bdl_addr
));
912 /* enable the position buffer */
913 if (! (azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
914 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
916 /* set the interrupt enable bits in the descriptor control register */
917 azx_sd_writel(azx_dev
, SD_CTL
, azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
924 * Codec initialization
927 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
929 struct hda_bus_template bus_temp
;
932 memset(&bus_temp
, 0, sizeof(bus_temp
));
933 bus_temp
.private_data
= chip
;
934 bus_temp
.modelname
= model
;
935 bus_temp
.pci
= chip
->pci
;
936 bus_temp
.ops
.command
= azx_send_cmd
;
937 bus_temp
.ops
.get_response
= azx_get_response
;
939 if ((err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
)) < 0)
943 for (c
= 0; c
< AZX_MAX_CODECS
; c
++) {
944 if ((chip
->codec_mask
& (1 << c
)) & probe_mask
) {
945 err
= snd_hda_codec_new(chip
->bus
, c
, NULL
);
952 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
964 /* assign a stream for the PCM */
965 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
968 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
969 dev
= chip
->playback_index_offset
;
970 nums
= chip
->playback_streams
;
972 dev
= chip
->capture_index_offset
;
973 nums
= chip
->capture_streams
;
975 for (i
= 0; i
< nums
; i
++, dev
++)
976 if (! chip
->azx_dev
[dev
].opened
) {
977 chip
->azx_dev
[dev
].opened
= 1;
978 return &chip
->azx_dev
[dev
];
983 /* release the assigned stream */
984 static inline void azx_release_device(struct azx_dev
*azx_dev
)
989 static struct snd_pcm_hardware azx_pcm_hw
= {
990 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
991 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
992 SNDRV_PCM_INFO_MMAP_VALID
|
993 SNDRV_PCM_INFO_PAUSE
/*|*/
994 /*SNDRV_PCM_INFO_RESUME*/),
995 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
996 .rates
= SNDRV_PCM_RATE_48000
,
1001 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1002 .period_bytes_min
= 128,
1003 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1005 .periods_max
= AZX_MAX_FRAG
,
1011 struct hda_codec
*codec
;
1012 struct hda_pcm_stream
*hinfo
[2];
1015 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1017 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1018 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1019 struct azx
*chip
= apcm
->chip
;
1020 struct azx_dev
*azx_dev
;
1021 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1022 unsigned long flags
;
1025 mutex_lock(&chip
->open_mutex
);
1026 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1027 if (azx_dev
== NULL
) {
1028 mutex_unlock(&chip
->open_mutex
);
1031 runtime
->hw
= azx_pcm_hw
;
1032 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1033 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1034 runtime
->hw
.formats
= hinfo
->formats
;
1035 runtime
->hw
.rates
= hinfo
->rates
;
1036 snd_pcm_limit_hw_rates(runtime
);
1037 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1038 if ((err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
)) < 0) {
1039 azx_release_device(azx_dev
);
1040 mutex_unlock(&chip
->open_mutex
);
1043 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1044 azx_dev
->substream
= substream
;
1045 azx_dev
->running
= 0;
1046 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1048 runtime
->private_data
= azx_dev
;
1049 mutex_unlock(&chip
->open_mutex
);
1053 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1055 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1056 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1057 struct azx
*chip
= apcm
->chip
;
1058 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1059 unsigned long flags
;
1061 mutex_lock(&chip
->open_mutex
);
1062 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1063 azx_dev
->substream
= NULL
;
1064 azx_dev
->running
= 0;
1065 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1066 azx_release_device(azx_dev
);
1067 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1068 mutex_unlock(&chip
->open_mutex
);
1072 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
, struct snd_pcm_hw_params
*hw_params
)
1074 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
1077 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1079 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1080 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1081 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1083 /* reset BDL address */
1084 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1085 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1086 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1088 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1090 return snd_pcm_lib_free_pages(substream
);
1093 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1095 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1096 struct azx
*chip
= apcm
->chip
;
1097 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1098 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1099 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1101 azx_dev
->bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1102 azx_dev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
1103 azx_dev
->frags
= azx_dev
->bufsize
/ azx_dev
->fragsize
;
1104 azx_dev
->format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1108 if (! azx_dev
->format_val
) {
1109 snd_printk(KERN_ERR SFX
"invalid format_val, rate=%d, ch=%d, format=%d\n",
1110 runtime
->rate
, runtime
->channels
, runtime
->format
);
1114 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1115 azx_dev
->bufsize
, azx_dev
->fragsize
, azx_dev
->format_val
);
1116 azx_setup_periods(azx_dev
);
1117 azx_setup_controller(chip
, azx_dev
);
1118 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1119 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1121 azx_dev
->fifo_size
= 0;
1122 azx_dev
->last_pos
= 0;
1124 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1125 azx_dev
->format_val
, substream
);
1128 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1130 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1131 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1132 struct azx
*chip
= apcm
->chip
;
1135 spin_lock(&chip
->reg_lock
);
1137 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1138 case SNDRV_PCM_TRIGGER_RESUME
:
1139 case SNDRV_PCM_TRIGGER_START
:
1140 azx_stream_start(chip
, azx_dev
);
1141 azx_dev
->running
= 1;
1143 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1144 case SNDRV_PCM_TRIGGER_SUSPEND
:
1145 case SNDRV_PCM_TRIGGER_STOP
:
1146 azx_stream_stop(chip
, azx_dev
);
1147 azx_dev
->running
= 0;
1152 spin_unlock(&chip
->reg_lock
);
1153 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
||
1154 cmd
== SNDRV_PCM_TRIGGER_SUSPEND
||
1155 cmd
== SNDRV_PCM_TRIGGER_STOP
) {
1157 while (azx_sd_readb(azx_dev
, SD_CTL
) & SD_CTL_DMA_START
&& --timeout
)
1163 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1165 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1166 struct azx
*chip
= apcm
->chip
;
1167 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1170 if (chip
->position_fix
== POS_FIX_POSBUF
) {
1171 /* use the position buffer */
1172 pos
= *azx_dev
->posbuf
;
1175 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1176 if (chip
->position_fix
== POS_FIX_FIFO
)
1177 pos
+= azx_dev
->fifo_size
;
1179 if (pos
>= azx_dev
->bufsize
)
1181 return bytes_to_frames(substream
->runtime
, pos
);
1184 static struct snd_pcm_ops azx_pcm_ops
= {
1185 .open
= azx_pcm_open
,
1186 .close
= azx_pcm_close
,
1187 .ioctl
= snd_pcm_lib_ioctl
,
1188 .hw_params
= azx_pcm_hw_params
,
1189 .hw_free
= azx_pcm_hw_free
,
1190 .prepare
= azx_pcm_prepare
,
1191 .trigger
= azx_pcm_trigger
,
1192 .pointer
= azx_pcm_pointer
,
1195 static void azx_pcm_free(struct snd_pcm
*pcm
)
1197 kfree(pcm
->private_data
);
1200 static int __devinit
create_codec_pcm(struct azx
*chip
, struct hda_codec
*codec
,
1201 struct hda_pcm
*cpcm
, int pcm_dev
)
1204 struct snd_pcm
*pcm
;
1205 struct azx_pcm
*apcm
;
1207 snd_assert(cpcm
->stream
[0].substreams
|| cpcm
->stream
[1].substreams
, return -EINVAL
);
1208 snd_assert(cpcm
->name
, return -EINVAL
);
1210 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1211 cpcm
->stream
[0].substreams
, cpcm
->stream
[1].substreams
,
1215 strcpy(pcm
->name
, cpcm
->name
);
1216 apcm
= kmalloc(sizeof(*apcm
), GFP_KERNEL
);
1220 apcm
->codec
= codec
;
1221 apcm
->hinfo
[0] = &cpcm
->stream
[0];
1222 apcm
->hinfo
[1] = &cpcm
->stream
[1];
1223 pcm
->private_data
= apcm
;
1224 pcm
->private_free
= azx_pcm_free
;
1225 if (cpcm
->stream
[0].substreams
)
1226 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &azx_pcm_ops
);
1227 if (cpcm
->stream
[1].substreams
)
1228 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &azx_pcm_ops
);
1229 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1230 snd_dma_pci_data(chip
->pci
),
1231 1024 * 64, 1024 * 128);
1232 chip
->pcm
[pcm_dev
] = pcm
;
1233 chip
->pcm_devs
= pcm_dev
+ 1;
1238 static int __devinit
azx_pcm_create(struct azx
*chip
)
1240 struct list_head
*p
;
1241 struct hda_codec
*codec
;
1245 if ((err
= snd_hda_build_pcms(chip
->bus
)) < 0)
1248 /* create audio PCMs */
1250 list_for_each(p
, &chip
->bus
->codec_list
) {
1251 codec
= list_entry(p
, struct hda_codec
, list
);
1252 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1253 if (codec
->pcm_info
[c
].is_modem
)
1254 continue; /* create later */
1255 if (pcm_dev
>= AZX_MAX_AUDIO_PCMS
) {
1256 snd_printk(KERN_ERR SFX
"Too many audio PCMs\n");
1259 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1266 /* create modem PCMs */
1267 pcm_dev
= AZX_MAX_AUDIO_PCMS
;
1268 list_for_each(p
, &chip
->bus
->codec_list
) {
1269 codec
= list_entry(p
, struct hda_codec
, list
);
1270 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1271 if (! codec
->pcm_info
[c
].is_modem
)
1272 continue; /* already created */
1273 if (pcm_dev
>= AZX_MAX_PCMS
) {
1274 snd_printk(KERN_ERR SFX
"Too many modem PCMs\n");
1277 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1280 chip
->pcm
[pcm_dev
]->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1288 * mixer creation - all stuff is implemented in hda module
1290 static int __devinit
azx_mixer_create(struct azx
*chip
)
1292 return snd_hda_build_controls(chip
->bus
);
1297 * initialize SD streams
1299 static int __devinit
azx_init_stream(struct azx
*chip
)
1303 /* initialize each stream (aka device)
1304 * assign the starting bdl address to each stream (device) and initialize
1306 for (i
= 0; i
< chip
->num_streams
; i
++) {
1307 unsigned int off
= sizeof(u32
) * (i
* AZX_MAX_FRAG
* 4);
1308 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1309 azx_dev
->bdl
= (u32
*)(chip
->bdl
.area
+ off
);
1310 azx_dev
->bdl_addr
= chip
->bdl
.addr
+ off
;
1311 azx_dev
->posbuf
= (volatile u32
*)(chip
->posbuf
.area
+ i
* 8);
1312 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1313 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1314 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1315 azx_dev
->sd_int_sta_mask
= 1 << i
;
1316 /* stream tag: must be non-zero and unique */
1318 azx_dev
->stream_tag
= i
+ 1;
1329 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1331 struct snd_card
*card
= pci_get_drvdata(pci
);
1332 struct azx
*chip
= card
->private_data
;
1335 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1336 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1337 snd_pcm_suspend_all(chip
->pcm
[i
]);
1338 snd_hda_suspend(chip
->bus
, state
);
1339 azx_free_cmd_io(chip
);
1340 pci_disable_device(pci
);
1341 pci_save_state(pci
);
1345 static int azx_resume(struct pci_dev
*pci
)
1347 struct snd_card
*card
= pci_get_drvdata(pci
);
1348 struct azx
*chip
= card
->private_data
;
1350 pci_restore_state(pci
);
1351 pci_enable_device(pci
);
1352 pci_set_master(pci
);
1353 azx_init_chip(chip
);
1354 snd_hda_resume(chip
->bus
);
1355 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1358 #endif /* CONFIG_PM */
1364 static int azx_free(struct azx
*chip
)
1366 if (chip
->initialized
) {
1369 for (i
= 0; i
< chip
->num_streams
; i
++)
1370 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
1372 /* disable interrupts */
1373 azx_int_disable(chip
);
1374 azx_int_clear(chip
);
1376 /* disable CORB/RIRB */
1377 azx_free_cmd_io(chip
);
1379 /* disable position buffer */
1380 azx_writel(chip
, DPLBASE
, 0);
1381 azx_writel(chip
, DPUBASE
, 0);
1383 /* wait a little for interrupts to finish */
1387 if (chip
->remap_addr
)
1388 iounmap(chip
->remap_addr
);
1390 free_irq(chip
->irq
, (void*)chip
);
1393 snd_dma_free_pages(&chip
->bdl
);
1395 snd_dma_free_pages(&chip
->rb
);
1396 if (chip
->posbuf
.area
)
1397 snd_dma_free_pages(&chip
->posbuf
);
1398 pci_release_regions(chip
->pci
);
1399 pci_disable_device(chip
->pci
);
1400 kfree(chip
->azx_dev
);
1406 static int azx_dev_free(struct snd_device
*device
)
1408 return azx_free(device
->device_data
);
1414 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1420 static struct snd_device_ops ops
= {
1421 .dev_free
= azx_dev_free
,
1426 if ((err
= pci_enable_device(pci
)) < 0)
1429 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1432 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
1433 pci_disable_device(pci
);
1437 spin_lock_init(&chip
->reg_lock
);
1438 mutex_init(&chip
->open_mutex
);
1442 chip
->driver_type
= driver_type
;
1444 chip
->position_fix
= position_fix
? position_fix
: POS_FIX_POSBUF
;
1445 chip
->single_cmd
= single_cmd
;
1447 #if BITS_PER_LONG != 64
1448 /* Fix up base address on ULI M5461 */
1449 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1451 pci_read_config_word(pci
, 0x40, &tmp3
);
1452 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1453 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1457 if ((err
= pci_request_regions(pci
, "ICH HD audio")) < 0) {
1459 pci_disable_device(pci
);
1463 chip
->addr
= pci_resource_start(pci
,0);
1464 chip
->remap_addr
= ioremap_nocache(chip
->addr
, pci_resource_len(pci
,0));
1465 if (chip
->remap_addr
== NULL
) {
1466 snd_printk(KERN_ERR SFX
"ioremap error\n");
1471 if (request_irq(pci
->irq
, azx_interrupt
, SA_INTERRUPT
|SA_SHIRQ
,
1472 "HDA Intel", (void*)chip
)) {
1473 snd_printk(KERN_ERR SFX
"unable to grab IRQ %d\n", pci
->irq
);
1477 chip
->irq
= pci
->irq
;
1479 pci_set_master(pci
);
1480 synchronize_irq(chip
->irq
);
1482 switch (chip
->driver_type
) {
1483 case AZX_DRIVER_ULI
:
1484 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1485 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1486 chip
->playback_index_offset
= ULI_PLAYBACK_INDEX
;
1487 chip
->capture_index_offset
= ULI_CAPTURE_INDEX
;
1490 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1491 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1492 chip
->playback_index_offset
= ICH6_PLAYBACK_INDEX
;
1493 chip
->capture_index_offset
= ICH6_CAPTURE_INDEX
;
1496 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1497 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
), GFP_KERNEL
);
1498 if (! chip
->azx_dev
) {
1499 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
1503 /* allocate memory for the BDL for each stream */
1504 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1505 BDL_SIZE
, &chip
->bdl
)) < 0) {
1506 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
1509 /* allocate memory for the position buffer */
1510 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1511 chip
->num_streams
* 8, &chip
->posbuf
)) < 0) {
1512 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
1515 /* allocate CORB/RIRB */
1516 if (! chip
->single_cmd
)
1517 if ((err
= azx_alloc_cmd_io(chip
)) < 0)
1520 /* initialize streams */
1521 azx_init_stream(chip
);
1523 /* initialize chip */
1524 azx_init_chip(chip
);
1526 chip
->initialized
= 1;
1528 /* codec detection */
1529 if (! chip
->codec_mask
) {
1530 snd_printk(KERN_ERR SFX
"no codecs found!\n");
1535 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) <0) {
1536 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
1540 strcpy(card
->driver
, "HDA-Intel");
1541 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
1542 sprintf(card
->longname
, "%s at 0x%lx irq %i", card
->shortname
, chip
->addr
, chip
->irq
);
1552 static int __devinit
azx_probe(struct pci_dev
*pci
, const struct pci_device_id
*pci_id
)
1554 struct snd_card
*card
;
1558 card
= snd_card_new(index
, id
, THIS_MODULE
, 0);
1560 snd_printk(KERN_ERR SFX
"Error creating card!\n");
1564 if ((err
= azx_create(card
, pci
, pci_id
->driver_data
,
1566 snd_card_free(card
);
1569 card
->private_data
= chip
;
1571 /* create codec instances */
1572 if ((err
= azx_codec_create(chip
, model
)) < 0) {
1573 snd_card_free(card
);
1577 /* create PCM streams */
1578 if ((err
= azx_pcm_create(chip
)) < 0) {
1579 snd_card_free(card
);
1583 /* create mixer controls */
1584 if ((err
= azx_mixer_create(chip
)) < 0) {
1585 snd_card_free(card
);
1589 snd_card_set_dev(card
, &pci
->dev
);
1591 if ((err
= snd_card_register(card
)) < 0) {
1592 snd_card_free(card
);
1596 pci_set_drvdata(pci
, card
);
1601 static void __devexit
azx_remove(struct pci_dev
*pci
)
1603 snd_card_free(pci_get_drvdata(pci
));
1604 pci_set_drvdata(pci
, NULL
);
1608 static struct pci_device_id azx_ids
[] = {
1609 { 0x8086, 0x2668, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH6 */
1610 { 0x8086, 0x27d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH7 */
1611 { 0x8086, 0x269a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ESB2 */
1612 { 0x8086, 0x284b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH8 */
1613 { 0x1002, 0x437b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB450 */
1614 { 0x1106, 0x3288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_VIA
}, /* VIA VT8251/VT8237A */
1615 { 0x1039, 0x7502, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_SIS
}, /* SIS966 */
1616 { 0x10b9, 0x5461, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ULI
}, /* ULI M5461 */
1617 { 0x10de, 0x026c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 026c */
1618 { 0x10de, 0x0371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 0371 */
1621 MODULE_DEVICE_TABLE(pci
, azx_ids
);
1623 /* pci_driver definition */
1624 static struct pci_driver driver
= {
1625 .name
= "HDA Intel",
1626 .id_table
= azx_ids
,
1628 .remove
= __devexit_p(azx_remove
),
1630 .suspend
= azx_suspend
,
1631 .resume
= azx_resume
,
1635 static int __init
alsa_card_azx_init(void)
1637 return pci_register_driver(&driver
);
1640 static void __exit
alsa_card_azx_exit(void)
1642 pci_unregister_driver(&driver
);
1645 module_init(alsa_card_azx_init
)
1646 module_exit(alsa_card_azx_exit
)