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Merge branch 'fix/hda' into topic/hda
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82 "(0 = auto, 1 = none, 2 = POSBUF).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, int, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 "{Intel, ICH6M},"
122 "{Intel, ICH7},"
123 "{Intel, ESB2},"
124 "{Intel, ICH8},"
125 "{Intel, ICH9},"
126 "{Intel, ICH10},"
127 "{Intel, PCH},"
128 "{Intel, CPT},"
129 "{Intel, SCH},"
130 "{ATI, SB450},"
131 "{ATI, SB600},"
132 "{ATI, RS600},"
133 "{ATI, RS690},"
134 "{ATI, RS780},"
135 "{ATI, R600},"
136 "{ATI, RV630},"
137 "{ATI, RV610},"
138 "{ATI, RV670},"
139 "{ATI, RV635},"
140 "{ATI, RV620},"
141 "{ATI, RV770},"
142 "{VIA, VT8251},"
143 "{VIA, VT8237A},"
144 "{SiS, SIS966},"
145 "{ULI, M5461}}");
146 MODULE_DESCRIPTION("Intel HDA driver");
147
148 #ifdef CONFIG_SND_VERBOSE_PRINTK
149 #define SFX /* nop */
150 #else
151 #define SFX "hda-intel: "
152 #endif
153
154 /*
155 * registers
156 */
157 #define ICH6_REG_GCAP 0x00
158 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
163 #define ICH6_REG_VMIN 0x02
164 #define ICH6_REG_VMAJ 0x03
165 #define ICH6_REG_OUTPAY 0x04
166 #define ICH6_REG_INPAY 0x06
167 #define ICH6_REG_GCTL 0x08
168 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
169 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
171 #define ICH6_REG_WAKEEN 0x0c
172 #define ICH6_REG_STATESTS 0x0e
173 #define ICH6_REG_GSTS 0x10
174 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
175 #define ICH6_REG_INTCTL 0x20
176 #define ICH6_REG_INTSTS 0x24
177 #define ICH6_REG_WALCLK 0x30
178 #define ICH6_REG_SYNC 0x34
179 #define ICH6_REG_CORBLBASE 0x40
180 #define ICH6_REG_CORBUBASE 0x44
181 #define ICH6_REG_CORBWP 0x48
182 #define ICH6_REG_CORBRP 0x4a
183 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
184 #define ICH6_REG_CORBCTL 0x4c
185 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
187 #define ICH6_REG_CORBSTS 0x4d
188 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
189 #define ICH6_REG_CORBSIZE 0x4e
190
191 #define ICH6_REG_RIRBLBASE 0x50
192 #define ICH6_REG_RIRBUBASE 0x54
193 #define ICH6_REG_RIRBWP 0x58
194 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
195 #define ICH6_REG_RINTCNT 0x5a
196 #define ICH6_REG_RIRBCTL 0x5c
197 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
200 #define ICH6_REG_RIRBSTS 0x5d
201 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
203 #define ICH6_REG_RIRBSIZE 0x5e
204
205 #define ICH6_REG_IC 0x60
206 #define ICH6_REG_IR 0x64
207 #define ICH6_REG_IRS 0x68
208 #define ICH6_IRS_VALID (1<<1)
209 #define ICH6_IRS_BUSY (1<<0)
210
211 #define ICH6_REG_DPLBASE 0x70
212 #define ICH6_REG_DPUBASE 0x74
213 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
214
215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
217
218 /* stream register offsets from stream base */
219 #define ICH6_REG_SD_CTL 0x00
220 #define ICH6_REG_SD_STS 0x03
221 #define ICH6_REG_SD_LPIB 0x04
222 #define ICH6_REG_SD_CBL 0x08
223 #define ICH6_REG_SD_LVI 0x0c
224 #define ICH6_REG_SD_FIFOW 0x0e
225 #define ICH6_REG_SD_FIFOSIZE 0x10
226 #define ICH6_REG_SD_FORMAT 0x12
227 #define ICH6_REG_SD_BDLPL 0x18
228 #define ICH6_REG_SD_BDLPU 0x1c
229
230 /* PCI space */
231 #define ICH6_PCIREG_TCSEL 0x44
232
233 /*
234 * other constants
235 */
236
237 /* max number of SDs */
238 /* ICH, ATI and VIA have 4 playback and 4 capture */
239 #define ICH6_NUM_CAPTURE 4
240 #define ICH6_NUM_PLAYBACK 4
241
242 /* ULI has 6 playback and 5 capture */
243 #define ULI_NUM_CAPTURE 5
244 #define ULI_NUM_PLAYBACK 6
245
246 /* ATI HDMI has 1 playback and 0 capture */
247 #define ATIHDMI_NUM_CAPTURE 0
248 #define ATIHDMI_NUM_PLAYBACK 1
249
250 /* TERA has 4 playback and 3 capture */
251 #define TERA_NUM_CAPTURE 3
252 #define TERA_NUM_PLAYBACK 4
253
254 /* this number is statically defined for simplicity */
255 #define MAX_AZX_DEV 16
256
257 /* max number of fragments - we may use more if allocating more pages for BDL */
258 #define BDL_SIZE 4096
259 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260 #define AZX_MAX_FRAG 32
261 /* max buffer size - no h/w limit, you can increase as you like */
262 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
263
264 /* RIRB int mask: overrun[2], response[0] */
265 #define RIRB_INT_RESPONSE 0x01
266 #define RIRB_INT_OVERRUN 0x04
267 #define RIRB_INT_MASK 0x05
268
269 /* STATESTS int mask: S3,SD2,SD1,SD0 */
270 #define AZX_MAX_CODECS 8
271 #define AZX_DEFAULT_CODECS 4
272 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
273
274 /* SD_CTL bits */
275 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
276 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
277 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
278 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
279 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
280 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
281 #define SD_CTL_STREAM_TAG_SHIFT 20
282
283 /* SD_CTL and SD_STS */
284 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
285 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
286 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
287 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
288 SD_INT_COMPLETE)
289
290 /* SD_STS */
291 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
292
293 /* INTCTL and INTSTS */
294 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
295 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
296 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
297
298 /* below are so far hardcoded - should read registers in future */
299 #define ICH6_MAX_CORB_ENTRIES 256
300 #define ICH6_MAX_RIRB_ENTRIES 256
301
302 /* position fix mode */
303 enum {
304 POS_FIX_AUTO,
305 POS_FIX_LPIB,
306 POS_FIX_POSBUF,
307 };
308
309 /* Defines for ATI HD Audio support in SB450 south bridge */
310 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
311 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
312
313 /* Defines for Nvidia HDA support */
314 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
315 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
316 #define NVIDIA_HDA_ISTRM_COH 0x4d
317 #define NVIDIA_HDA_OSTRM_COH 0x4c
318 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
319
320 /* Defines for Intel SCH HDA snoop control */
321 #define INTEL_SCH_HDA_DEVC 0x78
322 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
323
324 /* Define IN stream 0 FIFO size offset in VIA controller */
325 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
326 /* Define VIA HD Audio Device ID*/
327 #define VIA_HDAC_DEVICE_ID 0x3288
328
329 /* HD Audio class code */
330 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
331
332 /*
333 */
334
335 struct azx_dev {
336 struct snd_dma_buffer bdl; /* BDL buffer */
337 u32 *posbuf; /* position buffer pointer */
338
339 unsigned int bufsize; /* size of the play buffer in bytes */
340 unsigned int period_bytes; /* size of the period in bytes */
341 unsigned int frags; /* number for period in the play buffer */
342 unsigned int fifo_size; /* FIFO size */
343 unsigned long start_jiffies; /* start + minimum jiffies */
344 unsigned long min_jiffies; /* minimum jiffies before position is valid */
345
346 void __iomem *sd_addr; /* stream descriptor pointer */
347
348 u32 sd_int_sta_mask; /* stream int status mask */
349
350 /* pcm support */
351 struct snd_pcm_substream *substream; /* assigned substream,
352 * set in PCM open
353 */
354 unsigned int format_val; /* format value to be set in the
355 * controller and the codec
356 */
357 unsigned char stream_tag; /* assigned stream */
358 unsigned char index; /* stream index */
359 int device; /* last device number assigned to */
360
361 unsigned int opened :1;
362 unsigned int running :1;
363 unsigned int irq_pending :1;
364 unsigned int start_flag: 1; /* stream full start flag */
365 /*
366 * For VIA:
367 * A flag to ensure DMA position is 0
368 * when link position is not greater than FIFO size
369 */
370 unsigned int insufficient :1;
371 };
372
373 /* CORB/RIRB */
374 struct azx_rb {
375 u32 *buf; /* CORB/RIRB buffer
376 * Each CORB entry is 4byte, RIRB is 8byte
377 */
378 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
379 /* for RIRB */
380 unsigned short rp, wp; /* read/write pointers */
381 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
382 u32 res[AZX_MAX_CODECS]; /* last read value */
383 };
384
385 struct azx {
386 struct snd_card *card;
387 struct pci_dev *pci;
388 int dev_index;
389
390 /* chip type specific */
391 int driver_type;
392 int playback_streams;
393 int playback_index_offset;
394 int capture_streams;
395 int capture_index_offset;
396 int num_streams;
397
398 /* pci resources */
399 unsigned long addr;
400 void __iomem *remap_addr;
401 int irq;
402
403 /* locks */
404 spinlock_t reg_lock;
405 struct mutex open_mutex;
406
407 /* streams (x num_streams) */
408 struct azx_dev *azx_dev;
409
410 /* PCM */
411 struct snd_pcm *pcm[HDA_MAX_PCMS];
412
413 /* HD codec */
414 unsigned short codec_mask;
415 int codec_probe_mask; /* copied from probe_mask option */
416 struct hda_bus *bus;
417 unsigned int beep_mode;
418
419 /* CORB/RIRB */
420 struct azx_rb corb;
421 struct azx_rb rirb;
422
423 /* CORB/RIRB and position buffers */
424 struct snd_dma_buffer rb;
425 struct snd_dma_buffer posbuf;
426
427 /* flags */
428 int position_fix;
429 int poll_count;
430 unsigned int running :1;
431 unsigned int initialized :1;
432 unsigned int single_cmd :1;
433 unsigned int polling_mode :1;
434 unsigned int msi :1;
435 unsigned int irq_pending_warned :1;
436 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
437 unsigned int probing :1; /* codec probing phase */
438
439 /* for debugging */
440 unsigned int last_cmd[AZX_MAX_CODECS];
441
442 /* for pending irqs */
443 struct work_struct irq_pending_work;
444
445 /* reboot notifier (for mysterious hangup problem at power-down) */
446 struct notifier_block reboot_notifier;
447 };
448
449 /* driver types */
450 enum {
451 AZX_DRIVER_ICH,
452 AZX_DRIVER_PCH,
453 AZX_DRIVER_SCH,
454 AZX_DRIVER_ATI,
455 AZX_DRIVER_ATIHDMI,
456 AZX_DRIVER_VIA,
457 AZX_DRIVER_SIS,
458 AZX_DRIVER_ULI,
459 AZX_DRIVER_NVIDIA,
460 AZX_DRIVER_TERA,
461 AZX_DRIVER_GENERIC,
462 AZX_NUM_DRIVERS, /* keep this as last entry */
463 };
464
465 static char *driver_short_names[] __devinitdata = {
466 [AZX_DRIVER_ICH] = "HDA Intel",
467 [AZX_DRIVER_PCH] = "HDA Intel PCH",
468 [AZX_DRIVER_SCH] = "HDA Intel MID",
469 [AZX_DRIVER_ATI] = "HDA ATI SB",
470 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
471 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
472 [AZX_DRIVER_SIS] = "HDA SIS966",
473 [AZX_DRIVER_ULI] = "HDA ULI M5461",
474 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
475 [AZX_DRIVER_TERA] = "HDA Teradici",
476 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
477 };
478
479 /*
480 * macros for easy use
481 */
482 #define azx_writel(chip,reg,value) \
483 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
484 #define azx_readl(chip,reg) \
485 readl((chip)->remap_addr + ICH6_REG_##reg)
486 #define azx_writew(chip,reg,value) \
487 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
488 #define azx_readw(chip,reg) \
489 readw((chip)->remap_addr + ICH6_REG_##reg)
490 #define azx_writeb(chip,reg,value) \
491 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
492 #define azx_readb(chip,reg) \
493 readb((chip)->remap_addr + ICH6_REG_##reg)
494
495 #define azx_sd_writel(dev,reg,value) \
496 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
497 #define azx_sd_readl(dev,reg) \
498 readl((dev)->sd_addr + ICH6_REG_##reg)
499 #define azx_sd_writew(dev,reg,value) \
500 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
501 #define azx_sd_readw(dev,reg) \
502 readw((dev)->sd_addr + ICH6_REG_##reg)
503 #define azx_sd_writeb(dev,reg,value) \
504 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
505 #define azx_sd_readb(dev,reg) \
506 readb((dev)->sd_addr + ICH6_REG_##reg)
507
508 /* for pcm support */
509 #define get_azx_dev(substream) (substream->runtime->private_data)
510
511 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
512 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
513 /*
514 * Interface for HD codec
515 */
516
517 /*
518 * CORB / RIRB interface
519 */
520 static int azx_alloc_cmd_io(struct azx *chip)
521 {
522 int err;
523
524 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
525 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
526 snd_dma_pci_data(chip->pci),
527 PAGE_SIZE, &chip->rb);
528 if (err < 0) {
529 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
530 return err;
531 }
532 return 0;
533 }
534
535 static void azx_init_cmd_io(struct azx *chip)
536 {
537 spin_lock_irq(&chip->reg_lock);
538 /* CORB set up */
539 chip->corb.addr = chip->rb.addr;
540 chip->corb.buf = (u32 *)chip->rb.area;
541 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
542 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
543
544 /* set the corb size to 256 entries (ULI requires explicitly) */
545 azx_writeb(chip, CORBSIZE, 0x02);
546 /* set the corb write pointer to 0 */
547 azx_writew(chip, CORBWP, 0);
548 /* reset the corb hw read pointer */
549 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
550 /* enable corb dma */
551 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
552
553 /* RIRB set up */
554 chip->rirb.addr = chip->rb.addr + 2048;
555 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
556 chip->rirb.wp = chip->rirb.rp = 0;
557 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
558 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
559 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
560
561 /* set the rirb size to 256 entries (ULI requires explicitly) */
562 azx_writeb(chip, RIRBSIZE, 0x02);
563 /* reset the rirb hw write pointer */
564 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
565 /* set N=1, get RIRB response interrupt for new entry */
566 azx_writew(chip, RINTCNT, 1);
567 /* enable rirb dma and response irq */
568 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
569 spin_unlock_irq(&chip->reg_lock);
570 }
571
572 static void azx_free_cmd_io(struct azx *chip)
573 {
574 spin_lock_irq(&chip->reg_lock);
575 /* disable ringbuffer DMAs */
576 azx_writeb(chip, RIRBCTL, 0);
577 azx_writeb(chip, CORBCTL, 0);
578 spin_unlock_irq(&chip->reg_lock);
579 }
580
581 static unsigned int azx_command_addr(u32 cmd)
582 {
583 unsigned int addr = cmd >> 28;
584
585 if (addr >= AZX_MAX_CODECS) {
586 snd_BUG();
587 addr = 0;
588 }
589
590 return addr;
591 }
592
593 static unsigned int azx_response_addr(u32 res)
594 {
595 unsigned int addr = res & 0xf;
596
597 if (addr >= AZX_MAX_CODECS) {
598 snd_BUG();
599 addr = 0;
600 }
601
602 return addr;
603 }
604
605 /* send a command */
606 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
607 {
608 struct azx *chip = bus->private_data;
609 unsigned int addr = azx_command_addr(val);
610 unsigned int wp;
611
612 spin_lock_irq(&chip->reg_lock);
613
614 /* add command to corb */
615 wp = azx_readb(chip, CORBWP);
616 wp++;
617 wp %= ICH6_MAX_CORB_ENTRIES;
618
619 chip->rirb.cmds[addr]++;
620 chip->corb.buf[wp] = cpu_to_le32(val);
621 azx_writel(chip, CORBWP, wp);
622
623 spin_unlock_irq(&chip->reg_lock);
624
625 return 0;
626 }
627
628 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
629
630 /* retrieve RIRB entry - called from interrupt handler */
631 static void azx_update_rirb(struct azx *chip)
632 {
633 unsigned int rp, wp;
634 unsigned int addr;
635 u32 res, res_ex;
636
637 wp = azx_readb(chip, RIRBWP);
638 if (wp == chip->rirb.wp)
639 return;
640 chip->rirb.wp = wp;
641
642 while (chip->rirb.rp != wp) {
643 chip->rirb.rp++;
644 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
645
646 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
647 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
648 res = le32_to_cpu(chip->rirb.buf[rp]);
649 addr = azx_response_addr(res_ex);
650 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
651 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
652 else if (chip->rirb.cmds[addr]) {
653 chip->rirb.res[addr] = res;
654 smp_wmb();
655 chip->rirb.cmds[addr]--;
656 } else
657 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
658 "last cmd=%#08x\n",
659 res, res_ex,
660 chip->last_cmd[addr]);
661 }
662 }
663
664 /* receive a response */
665 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
666 unsigned int addr)
667 {
668 struct azx *chip = bus->private_data;
669 unsigned long timeout;
670 int do_poll = 0;
671
672 again:
673 timeout = jiffies + msecs_to_jiffies(1000);
674 for (;;) {
675 if (chip->polling_mode || do_poll) {
676 spin_lock_irq(&chip->reg_lock);
677 azx_update_rirb(chip);
678 spin_unlock_irq(&chip->reg_lock);
679 }
680 if (!chip->rirb.cmds[addr]) {
681 smp_rmb();
682 bus->rirb_error = 0;
683
684 if (!do_poll)
685 chip->poll_count = 0;
686 return chip->rirb.res[addr]; /* the last value */
687 }
688 if (time_after(jiffies, timeout))
689 break;
690 if (bus->needs_damn_long_delay)
691 msleep(2); /* temporary workaround */
692 else {
693 udelay(10);
694 cond_resched();
695 }
696 }
697
698 if (!chip->polling_mode && chip->poll_count < 2) {
699 snd_printdd(SFX "azx_get_response timeout, "
700 "polling the codec once: last cmd=0x%08x\n",
701 chip->last_cmd[addr]);
702 do_poll = 1;
703 chip->poll_count++;
704 goto again;
705 }
706
707
708 if (!chip->polling_mode) {
709 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
710 "switching to polling mode: last cmd=0x%08x\n",
711 chip->last_cmd[addr]);
712 chip->polling_mode = 1;
713 goto again;
714 }
715
716 if (chip->msi) {
717 snd_printk(KERN_WARNING SFX "No response from codec, "
718 "disabling MSI: last cmd=0x%08x\n",
719 chip->last_cmd[addr]);
720 free_irq(chip->irq, chip);
721 chip->irq = -1;
722 pci_disable_msi(chip->pci);
723 chip->msi = 0;
724 if (azx_acquire_irq(chip, 1) < 0) {
725 bus->rirb_error = 1;
726 return -1;
727 }
728 goto again;
729 }
730
731 if (chip->probing) {
732 /* If this critical timeout happens during the codec probing
733 * phase, this is likely an access to a non-existing codec
734 * slot. Better to return an error and reset the system.
735 */
736 return -1;
737 }
738
739 /* a fatal communication error; need either to reset or to fallback
740 * to the single_cmd mode
741 */
742 bus->rirb_error = 1;
743 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
744 bus->response_reset = 1;
745 return -1; /* give a chance to retry */
746 }
747
748 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
749 "switching to single_cmd mode: last cmd=0x%08x\n",
750 chip->last_cmd[addr]);
751 chip->single_cmd = 1;
752 bus->response_reset = 0;
753 /* release CORB/RIRB */
754 azx_free_cmd_io(chip);
755 /* disable unsolicited responses */
756 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
757 return -1;
758 }
759
760 /*
761 * Use the single immediate command instead of CORB/RIRB for simplicity
762 *
763 * Note: according to Intel, this is not preferred use. The command was
764 * intended for the BIOS only, and may get confused with unsolicited
765 * responses. So, we shouldn't use it for normal operation from the
766 * driver.
767 * I left the codes, however, for debugging/testing purposes.
768 */
769
770 /* receive a response */
771 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
772 {
773 int timeout = 50;
774
775 while (timeout--) {
776 /* check IRV busy bit */
777 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
778 /* reuse rirb.res as the response return value */
779 chip->rirb.res[addr] = azx_readl(chip, IR);
780 return 0;
781 }
782 udelay(1);
783 }
784 if (printk_ratelimit())
785 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
786 azx_readw(chip, IRS));
787 chip->rirb.res[addr] = -1;
788 return -EIO;
789 }
790
791 /* send a command */
792 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
793 {
794 struct azx *chip = bus->private_data;
795 unsigned int addr = azx_command_addr(val);
796 int timeout = 50;
797
798 bus->rirb_error = 0;
799 while (timeout--) {
800 /* check ICB busy bit */
801 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
802 /* Clear IRV valid bit */
803 azx_writew(chip, IRS, azx_readw(chip, IRS) |
804 ICH6_IRS_VALID);
805 azx_writel(chip, IC, val);
806 azx_writew(chip, IRS, azx_readw(chip, IRS) |
807 ICH6_IRS_BUSY);
808 return azx_single_wait_for_response(chip, addr);
809 }
810 udelay(1);
811 }
812 if (printk_ratelimit())
813 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
814 azx_readw(chip, IRS), val);
815 return -EIO;
816 }
817
818 /* receive a response */
819 static unsigned int azx_single_get_response(struct hda_bus *bus,
820 unsigned int addr)
821 {
822 struct azx *chip = bus->private_data;
823 return chip->rirb.res[addr];
824 }
825
826 /*
827 * The below are the main callbacks from hda_codec.
828 *
829 * They are just the skeleton to call sub-callbacks according to the
830 * current setting of chip->single_cmd.
831 */
832
833 /* send a command */
834 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
835 {
836 struct azx *chip = bus->private_data;
837
838 chip->last_cmd[azx_command_addr(val)] = val;
839 if (chip->single_cmd)
840 return azx_single_send_cmd(bus, val);
841 else
842 return azx_corb_send_cmd(bus, val);
843 }
844
845 /* get a response */
846 static unsigned int azx_get_response(struct hda_bus *bus,
847 unsigned int addr)
848 {
849 struct azx *chip = bus->private_data;
850 if (chip->single_cmd)
851 return azx_single_get_response(bus, addr);
852 else
853 return azx_rirb_get_response(bus, addr);
854 }
855
856 #ifdef CONFIG_SND_HDA_POWER_SAVE
857 static void azx_power_notify(struct hda_bus *bus);
858 #endif
859
860 /* reset codec link */
861 static int azx_reset(struct azx *chip, int full_reset)
862 {
863 int count;
864
865 if (!full_reset)
866 goto __skip;
867
868 /* clear STATESTS */
869 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
870
871 /* reset controller */
872 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
873
874 count = 50;
875 while (azx_readb(chip, GCTL) && --count)
876 msleep(1);
877
878 /* delay for >= 100us for codec PLL to settle per spec
879 * Rev 0.9 section 5.5.1
880 */
881 msleep(1);
882
883 /* Bring controller out of reset */
884 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
885
886 count = 50;
887 while (!azx_readb(chip, GCTL) && --count)
888 msleep(1);
889
890 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
891 msleep(1);
892
893 __skip:
894 /* check to see if controller is ready */
895 if (!azx_readb(chip, GCTL)) {
896 snd_printd(SFX "azx_reset: controller not ready!\n");
897 return -EBUSY;
898 }
899
900 /* Accept unsolicited responses */
901 if (!chip->single_cmd)
902 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
903 ICH6_GCTL_UNSOL);
904
905 /* detect codecs */
906 if (!chip->codec_mask) {
907 chip->codec_mask = azx_readw(chip, STATESTS);
908 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
909 }
910
911 return 0;
912 }
913
914
915 /*
916 * Lowlevel interface
917 */
918
919 /* enable interrupts */
920 static void azx_int_enable(struct azx *chip)
921 {
922 /* enable controller CIE and GIE */
923 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
924 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
925 }
926
927 /* disable interrupts */
928 static void azx_int_disable(struct azx *chip)
929 {
930 int i;
931
932 /* disable interrupts in stream descriptor */
933 for (i = 0; i < chip->num_streams; i++) {
934 struct azx_dev *azx_dev = &chip->azx_dev[i];
935 azx_sd_writeb(azx_dev, SD_CTL,
936 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
937 }
938
939 /* disable SIE for all streams */
940 azx_writeb(chip, INTCTL, 0);
941
942 /* disable controller CIE and GIE */
943 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
944 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
945 }
946
947 /* clear interrupts */
948 static void azx_int_clear(struct azx *chip)
949 {
950 int i;
951
952 /* clear stream status */
953 for (i = 0; i < chip->num_streams; i++) {
954 struct azx_dev *azx_dev = &chip->azx_dev[i];
955 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
956 }
957
958 /* clear STATESTS */
959 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
960
961 /* clear rirb status */
962 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
963
964 /* clear int status */
965 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
966 }
967
968 /* start a stream */
969 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
970 {
971 /*
972 * Before stream start, initialize parameter
973 */
974 azx_dev->insufficient = 1;
975
976 /* enable SIE */
977 azx_writel(chip, INTCTL,
978 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
979 /* set DMA start and interrupt mask */
980 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
981 SD_CTL_DMA_START | SD_INT_MASK);
982 }
983
984 /* stop DMA */
985 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
986 {
987 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
988 ~(SD_CTL_DMA_START | SD_INT_MASK));
989 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
990 }
991
992 /* stop a stream */
993 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
994 {
995 azx_stream_clear(chip, azx_dev);
996 /* disable SIE */
997 azx_writel(chip, INTCTL,
998 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
999 }
1000
1001
1002 /*
1003 * reset and start the controller registers
1004 */
1005 static void azx_init_chip(struct azx *chip, int full_reset)
1006 {
1007 if (chip->initialized)
1008 return;
1009
1010 /* reset controller */
1011 azx_reset(chip, full_reset);
1012
1013 /* initialize interrupts */
1014 azx_int_clear(chip);
1015 azx_int_enable(chip);
1016
1017 /* initialize the codec command I/O */
1018 if (!chip->single_cmd)
1019 azx_init_cmd_io(chip);
1020
1021 /* program the position buffer */
1022 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1023 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1024
1025 chip->initialized = 1;
1026 }
1027
1028 /*
1029 * initialize the PCI registers
1030 */
1031 /* update bits in a PCI register byte */
1032 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1033 unsigned char mask, unsigned char val)
1034 {
1035 unsigned char data;
1036
1037 pci_read_config_byte(pci, reg, &data);
1038 data &= ~mask;
1039 data |= (val & mask);
1040 pci_write_config_byte(pci, reg, data);
1041 }
1042
1043 static void azx_init_pci(struct azx *chip)
1044 {
1045 unsigned short snoop;
1046
1047 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1048 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1049 * Ensuring these bits are 0 clears playback static on some HD Audio
1050 * codecs
1051 */
1052 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1053
1054 switch (chip->driver_type) {
1055 case AZX_DRIVER_ATI:
1056 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1057 update_pci_byte(chip->pci,
1058 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1059 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1060 break;
1061 case AZX_DRIVER_NVIDIA:
1062 /* For NVIDIA HDA, enable snoop */
1063 update_pci_byte(chip->pci,
1064 NVIDIA_HDA_TRANSREG_ADDR,
1065 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1066 update_pci_byte(chip->pci,
1067 NVIDIA_HDA_ISTRM_COH,
1068 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1069 update_pci_byte(chip->pci,
1070 NVIDIA_HDA_OSTRM_COH,
1071 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1072 break;
1073 case AZX_DRIVER_SCH:
1074 case AZX_DRIVER_PCH:
1075 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1076 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1077 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1078 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1079 pci_read_config_word(chip->pci,
1080 INTEL_SCH_HDA_DEVC, &snoop);
1081 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1082 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1083 ? "Failed" : "OK");
1084 }
1085 break;
1086
1087 }
1088 }
1089
1090
1091 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1092
1093 /*
1094 * interrupt handler
1095 */
1096 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1097 {
1098 struct azx *chip = dev_id;
1099 struct azx_dev *azx_dev;
1100 u32 status;
1101 int i, ok;
1102
1103 spin_lock(&chip->reg_lock);
1104
1105 status = azx_readl(chip, INTSTS);
1106 if (status == 0) {
1107 spin_unlock(&chip->reg_lock);
1108 return IRQ_NONE;
1109 }
1110
1111 for (i = 0; i < chip->num_streams; i++) {
1112 azx_dev = &chip->azx_dev[i];
1113 if (status & azx_dev->sd_int_sta_mask) {
1114 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1115 if (!azx_dev->substream || !azx_dev->running)
1116 continue;
1117 /* check whether this IRQ is really acceptable */
1118 ok = azx_position_ok(chip, azx_dev);
1119 if (ok == 1) {
1120 azx_dev->irq_pending = 0;
1121 spin_unlock(&chip->reg_lock);
1122 snd_pcm_period_elapsed(azx_dev->substream);
1123 spin_lock(&chip->reg_lock);
1124 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1125 /* bogus IRQ, process it later */
1126 azx_dev->irq_pending = 1;
1127 queue_work(chip->bus->workq,
1128 &chip->irq_pending_work);
1129 }
1130 }
1131 }
1132
1133 /* clear rirb int */
1134 status = azx_readb(chip, RIRBSTS);
1135 if (status & RIRB_INT_MASK) {
1136 if (status & RIRB_INT_RESPONSE)
1137 azx_update_rirb(chip);
1138 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1139 }
1140
1141 #if 0
1142 /* clear state status int */
1143 if (azx_readb(chip, STATESTS) & 0x04)
1144 azx_writeb(chip, STATESTS, 0x04);
1145 #endif
1146 spin_unlock(&chip->reg_lock);
1147
1148 return IRQ_HANDLED;
1149 }
1150
1151
1152 /*
1153 * set up a BDL entry
1154 */
1155 static int setup_bdle(struct snd_pcm_substream *substream,
1156 struct azx_dev *azx_dev, u32 **bdlp,
1157 int ofs, int size, int with_ioc)
1158 {
1159 u32 *bdl = *bdlp;
1160
1161 while (size > 0) {
1162 dma_addr_t addr;
1163 int chunk;
1164
1165 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1166 return -EINVAL;
1167
1168 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1169 /* program the address field of the BDL entry */
1170 bdl[0] = cpu_to_le32((u32)addr);
1171 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1172 /* program the size field of the BDL entry */
1173 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1174 bdl[2] = cpu_to_le32(chunk);
1175 /* program the IOC to enable interrupt
1176 * only when the whole fragment is processed
1177 */
1178 size -= chunk;
1179 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1180 bdl += 4;
1181 azx_dev->frags++;
1182 ofs += chunk;
1183 }
1184 *bdlp = bdl;
1185 return ofs;
1186 }
1187
1188 /*
1189 * set up BDL entries
1190 */
1191 static int azx_setup_periods(struct azx *chip,
1192 struct snd_pcm_substream *substream,
1193 struct azx_dev *azx_dev)
1194 {
1195 u32 *bdl;
1196 int i, ofs, periods, period_bytes;
1197 int pos_adj;
1198
1199 /* reset BDL address */
1200 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1201 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1202
1203 period_bytes = azx_dev->period_bytes;
1204 periods = azx_dev->bufsize / period_bytes;
1205
1206 /* program the initial BDL entries */
1207 bdl = (u32 *)azx_dev->bdl.area;
1208 ofs = 0;
1209 azx_dev->frags = 0;
1210 pos_adj = bdl_pos_adj[chip->dev_index];
1211 if (pos_adj > 0) {
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pos_align = pos_adj;
1214 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1215 if (!pos_adj)
1216 pos_adj = pos_align;
1217 else
1218 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1219 pos_align;
1220 pos_adj = frames_to_bytes(runtime, pos_adj);
1221 if (pos_adj >= period_bytes) {
1222 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1223 bdl_pos_adj[chip->dev_index]);
1224 pos_adj = 0;
1225 } else {
1226 ofs = setup_bdle(substream, azx_dev,
1227 &bdl, ofs, pos_adj, 1);
1228 if (ofs < 0)
1229 goto error;
1230 }
1231 } else
1232 pos_adj = 0;
1233 for (i = 0; i < periods; i++) {
1234 if (i == periods - 1 && pos_adj)
1235 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1236 period_bytes - pos_adj, 0);
1237 else
1238 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1239 period_bytes, 1);
1240 if (ofs < 0)
1241 goto error;
1242 }
1243 return 0;
1244
1245 error:
1246 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1247 azx_dev->bufsize, period_bytes);
1248 return -EINVAL;
1249 }
1250
1251 /* reset stream */
1252 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1253 {
1254 unsigned char val;
1255 int timeout;
1256
1257 azx_stream_clear(chip, azx_dev);
1258
1259 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1260 SD_CTL_STREAM_RESET);
1261 udelay(3);
1262 timeout = 300;
1263 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1264 --timeout)
1265 ;
1266 val &= ~SD_CTL_STREAM_RESET;
1267 azx_sd_writeb(azx_dev, SD_CTL, val);
1268 udelay(3);
1269
1270 timeout = 300;
1271 /* waiting for hardware to report that the stream is out of reset */
1272 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1273 --timeout)
1274 ;
1275
1276 /* reset first position - may not be synced with hw at this time */
1277 *azx_dev->posbuf = 0;
1278 }
1279
1280 /*
1281 * set up the SD for streaming
1282 */
1283 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1284 {
1285 /* make sure the run bit is zero for SD */
1286 azx_stream_clear(chip, azx_dev);
1287 /* program the stream_tag */
1288 azx_sd_writel(azx_dev, SD_CTL,
1289 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1290 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1291
1292 /* program the length of samples in cyclic buffer */
1293 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1294
1295 /* program the stream format */
1296 /* this value needs to be the same as the one programmed */
1297 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1298
1299 /* program the stream LVI (last valid index) of the BDL */
1300 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1301
1302 /* program the BDL address */
1303 /* lower BDL address */
1304 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1305 /* upper BDL address */
1306 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1307
1308 /* enable the position buffer */
1309 if (chip->position_fix == POS_FIX_POSBUF ||
1310 chip->position_fix == POS_FIX_AUTO ||
1311 chip->via_dmapos_patch) {
1312 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1313 azx_writel(chip, DPLBASE,
1314 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1315 }
1316
1317 /* set the interrupt enable bits in the descriptor control register */
1318 azx_sd_writel(azx_dev, SD_CTL,
1319 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1320
1321 return 0;
1322 }
1323
1324 /*
1325 * Probe the given codec address
1326 */
1327 static int probe_codec(struct azx *chip, int addr)
1328 {
1329 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1330 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1331 unsigned int res;
1332
1333 mutex_lock(&chip->bus->cmd_mutex);
1334 chip->probing = 1;
1335 azx_send_cmd(chip->bus, cmd);
1336 res = azx_get_response(chip->bus, addr);
1337 chip->probing = 0;
1338 mutex_unlock(&chip->bus->cmd_mutex);
1339 if (res == -1)
1340 return -EIO;
1341 snd_printdd(SFX "codec #%d probed OK\n", addr);
1342 return 0;
1343 }
1344
1345 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1346 struct hda_pcm *cpcm);
1347 static void azx_stop_chip(struct azx *chip);
1348
1349 static void azx_bus_reset(struct hda_bus *bus)
1350 {
1351 struct azx *chip = bus->private_data;
1352
1353 bus->in_reset = 1;
1354 azx_stop_chip(chip);
1355 azx_init_chip(chip, 1);
1356 #ifdef CONFIG_PM
1357 if (chip->initialized) {
1358 int i;
1359
1360 for (i = 0; i < HDA_MAX_PCMS; i++)
1361 snd_pcm_suspend_all(chip->pcm[i]);
1362 snd_hda_suspend(chip->bus);
1363 snd_hda_resume(chip->bus);
1364 }
1365 #endif
1366 bus->in_reset = 0;
1367 }
1368
1369 /*
1370 * Codec initialization
1371 */
1372
1373 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1374 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1375 [AZX_DRIVER_NVIDIA] = 8,
1376 [AZX_DRIVER_TERA] = 1,
1377 };
1378
1379 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1380 {
1381 struct hda_bus_template bus_temp;
1382 int c, codecs, err;
1383 int max_slots;
1384
1385 memset(&bus_temp, 0, sizeof(bus_temp));
1386 bus_temp.private_data = chip;
1387 bus_temp.modelname = model;
1388 bus_temp.pci = chip->pci;
1389 bus_temp.ops.command = azx_send_cmd;
1390 bus_temp.ops.get_response = azx_get_response;
1391 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1392 bus_temp.ops.bus_reset = azx_bus_reset;
1393 #ifdef CONFIG_SND_HDA_POWER_SAVE
1394 bus_temp.power_save = &power_save;
1395 bus_temp.ops.pm_notify = azx_power_notify;
1396 #endif
1397
1398 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1399 if (err < 0)
1400 return err;
1401
1402 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1403 chip->bus->needs_damn_long_delay = 1;
1404
1405 codecs = 0;
1406 max_slots = azx_max_codecs[chip->driver_type];
1407 if (!max_slots)
1408 max_slots = AZX_DEFAULT_CODECS;
1409
1410 /* First try to probe all given codec slots */
1411 for (c = 0; c < max_slots; c++) {
1412 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1413 if (probe_codec(chip, c) < 0) {
1414 /* Some BIOSen give you wrong codec addresses
1415 * that don't exist
1416 */
1417 snd_printk(KERN_WARNING SFX
1418 "Codec #%d probe error; "
1419 "disabling it...\n", c);
1420 chip->codec_mask &= ~(1 << c);
1421 /* More badly, accessing to a non-existing
1422 * codec often screws up the controller chip,
1423 * and disturbs the further communications.
1424 * Thus if an error occurs during probing,
1425 * better to reset the controller chip to
1426 * get back to the sanity state.
1427 */
1428 azx_stop_chip(chip);
1429 azx_init_chip(chip, 1);
1430 }
1431 }
1432 }
1433
1434 /* Then create codec instances */
1435 for (c = 0; c < max_slots; c++) {
1436 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1437 struct hda_codec *codec;
1438 err = snd_hda_codec_new(chip->bus, c, &codec);
1439 if (err < 0)
1440 continue;
1441 codec->beep_mode = chip->beep_mode;
1442 codecs++;
1443 }
1444 }
1445 if (!codecs) {
1446 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1447 return -ENXIO;
1448 }
1449 return 0;
1450 }
1451
1452 /* configure each codec instance */
1453 static int __devinit azx_codec_configure(struct azx *chip)
1454 {
1455 struct hda_codec *codec;
1456 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1457 snd_hda_codec_configure(codec);
1458 }
1459 return 0;
1460 }
1461
1462
1463 /*
1464 * PCM support
1465 */
1466
1467 /* assign a stream for the PCM */
1468 static inline struct azx_dev *
1469 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1470 {
1471 int dev, i, nums;
1472 struct azx_dev *res = NULL;
1473
1474 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1475 dev = chip->playback_index_offset;
1476 nums = chip->playback_streams;
1477 } else {
1478 dev = chip->capture_index_offset;
1479 nums = chip->capture_streams;
1480 }
1481 for (i = 0; i < nums; i++, dev++)
1482 if (!chip->azx_dev[dev].opened) {
1483 res = &chip->azx_dev[dev];
1484 if (res->device == substream->pcm->device)
1485 break;
1486 }
1487 if (res) {
1488 res->opened = 1;
1489 res->device = substream->pcm->device;
1490 }
1491 return res;
1492 }
1493
1494 /* release the assigned stream */
1495 static inline void azx_release_device(struct azx_dev *azx_dev)
1496 {
1497 azx_dev->opened = 0;
1498 }
1499
1500 static struct snd_pcm_hardware azx_pcm_hw = {
1501 .info = (SNDRV_PCM_INFO_MMAP |
1502 SNDRV_PCM_INFO_INTERLEAVED |
1503 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1504 SNDRV_PCM_INFO_MMAP_VALID |
1505 /* No full-resume yet implemented */
1506 /* SNDRV_PCM_INFO_RESUME |*/
1507 SNDRV_PCM_INFO_PAUSE |
1508 SNDRV_PCM_INFO_SYNC_START),
1509 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1510 .rates = SNDRV_PCM_RATE_48000,
1511 .rate_min = 48000,
1512 .rate_max = 48000,
1513 .channels_min = 2,
1514 .channels_max = 2,
1515 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1516 .period_bytes_min = 128,
1517 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1518 .periods_min = 2,
1519 .periods_max = AZX_MAX_FRAG,
1520 .fifo_size = 0,
1521 };
1522
1523 struct azx_pcm {
1524 struct azx *chip;
1525 struct hda_codec *codec;
1526 struct hda_pcm_stream *hinfo[2];
1527 };
1528
1529 static int azx_pcm_open(struct snd_pcm_substream *substream)
1530 {
1531 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1532 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1533 struct azx *chip = apcm->chip;
1534 struct azx_dev *azx_dev;
1535 struct snd_pcm_runtime *runtime = substream->runtime;
1536 unsigned long flags;
1537 int err;
1538
1539 mutex_lock(&chip->open_mutex);
1540 azx_dev = azx_assign_device(chip, substream);
1541 if (azx_dev == NULL) {
1542 mutex_unlock(&chip->open_mutex);
1543 return -EBUSY;
1544 }
1545 runtime->hw = azx_pcm_hw;
1546 runtime->hw.channels_min = hinfo->channels_min;
1547 runtime->hw.channels_max = hinfo->channels_max;
1548 runtime->hw.formats = hinfo->formats;
1549 runtime->hw.rates = hinfo->rates;
1550 snd_pcm_limit_hw_rates(runtime);
1551 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1552 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1553 128);
1554 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1555 128);
1556 snd_hda_power_up(apcm->codec);
1557 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1558 if (err < 0) {
1559 azx_release_device(azx_dev);
1560 snd_hda_power_down(apcm->codec);
1561 mutex_unlock(&chip->open_mutex);
1562 return err;
1563 }
1564 snd_pcm_limit_hw_rates(runtime);
1565 /* sanity check */
1566 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1567 snd_BUG_ON(!runtime->hw.channels_max) ||
1568 snd_BUG_ON(!runtime->hw.formats) ||
1569 snd_BUG_ON(!runtime->hw.rates)) {
1570 azx_release_device(azx_dev);
1571 hinfo->ops.close(hinfo, apcm->codec, substream);
1572 snd_hda_power_down(apcm->codec);
1573 mutex_unlock(&chip->open_mutex);
1574 return -EINVAL;
1575 }
1576 spin_lock_irqsave(&chip->reg_lock, flags);
1577 azx_dev->substream = substream;
1578 azx_dev->running = 0;
1579 spin_unlock_irqrestore(&chip->reg_lock, flags);
1580
1581 runtime->private_data = azx_dev;
1582 snd_pcm_set_sync(substream);
1583 mutex_unlock(&chip->open_mutex);
1584 return 0;
1585 }
1586
1587 static int azx_pcm_close(struct snd_pcm_substream *substream)
1588 {
1589 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1590 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1591 struct azx *chip = apcm->chip;
1592 struct azx_dev *azx_dev = get_azx_dev(substream);
1593 unsigned long flags;
1594
1595 mutex_lock(&chip->open_mutex);
1596 spin_lock_irqsave(&chip->reg_lock, flags);
1597 azx_dev->substream = NULL;
1598 azx_dev->running = 0;
1599 spin_unlock_irqrestore(&chip->reg_lock, flags);
1600 azx_release_device(azx_dev);
1601 hinfo->ops.close(hinfo, apcm->codec, substream);
1602 snd_hda_power_down(apcm->codec);
1603 mutex_unlock(&chip->open_mutex);
1604 return 0;
1605 }
1606
1607 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1608 struct snd_pcm_hw_params *hw_params)
1609 {
1610 struct azx_dev *azx_dev = get_azx_dev(substream);
1611
1612 azx_dev->bufsize = 0;
1613 azx_dev->period_bytes = 0;
1614 azx_dev->format_val = 0;
1615 return snd_pcm_lib_malloc_pages(substream,
1616 params_buffer_bytes(hw_params));
1617 }
1618
1619 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1620 {
1621 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1622 struct azx_dev *azx_dev = get_azx_dev(substream);
1623 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1624
1625 /* reset BDL address */
1626 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1627 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1628 azx_sd_writel(azx_dev, SD_CTL, 0);
1629 azx_dev->bufsize = 0;
1630 azx_dev->period_bytes = 0;
1631 azx_dev->format_val = 0;
1632
1633 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1634
1635 return snd_pcm_lib_free_pages(substream);
1636 }
1637
1638 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1639 {
1640 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1641 struct azx *chip = apcm->chip;
1642 struct azx_dev *azx_dev = get_azx_dev(substream);
1643 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1644 struct snd_pcm_runtime *runtime = substream->runtime;
1645 unsigned int bufsize, period_bytes, format_val;
1646 int err;
1647
1648 azx_stream_reset(chip, azx_dev);
1649 format_val = snd_hda_calc_stream_format(runtime->rate,
1650 runtime->channels,
1651 runtime->format,
1652 hinfo->maxbps);
1653 if (!format_val) {
1654 snd_printk(KERN_ERR SFX
1655 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1656 runtime->rate, runtime->channels, runtime->format);
1657 return -EINVAL;
1658 }
1659
1660 bufsize = snd_pcm_lib_buffer_bytes(substream);
1661 period_bytes = snd_pcm_lib_period_bytes(substream);
1662
1663 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1664 bufsize, format_val);
1665
1666 if (bufsize != azx_dev->bufsize ||
1667 period_bytes != azx_dev->period_bytes ||
1668 format_val != azx_dev->format_val) {
1669 azx_dev->bufsize = bufsize;
1670 azx_dev->period_bytes = period_bytes;
1671 azx_dev->format_val = format_val;
1672 err = azx_setup_periods(chip, substream, azx_dev);
1673 if (err < 0)
1674 return err;
1675 }
1676
1677 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1678 (runtime->rate * 2);
1679 azx_setup_controller(chip, azx_dev);
1680 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1681 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1682 else
1683 azx_dev->fifo_size = 0;
1684
1685 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1686 azx_dev->format_val, substream);
1687 }
1688
1689 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1690 {
1691 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1692 struct azx *chip = apcm->chip;
1693 struct azx_dev *azx_dev;
1694 struct snd_pcm_substream *s;
1695 int rstart = 0, start, nsync = 0, sbits = 0;
1696 int nwait, timeout;
1697
1698 switch (cmd) {
1699 case SNDRV_PCM_TRIGGER_START:
1700 rstart = 1;
1701 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1702 case SNDRV_PCM_TRIGGER_RESUME:
1703 start = 1;
1704 break;
1705 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1706 case SNDRV_PCM_TRIGGER_SUSPEND:
1707 case SNDRV_PCM_TRIGGER_STOP:
1708 start = 0;
1709 break;
1710 default:
1711 return -EINVAL;
1712 }
1713
1714 snd_pcm_group_for_each_entry(s, substream) {
1715 if (s->pcm->card != substream->pcm->card)
1716 continue;
1717 azx_dev = get_azx_dev(s);
1718 sbits |= 1 << azx_dev->index;
1719 nsync++;
1720 snd_pcm_trigger_done(s, substream);
1721 }
1722
1723 spin_lock(&chip->reg_lock);
1724 if (nsync > 1) {
1725 /* first, set SYNC bits of corresponding streams */
1726 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1727 }
1728 snd_pcm_group_for_each_entry(s, substream) {
1729 if (s->pcm->card != substream->pcm->card)
1730 continue;
1731 azx_dev = get_azx_dev(s);
1732 if (rstart) {
1733 azx_dev->start_flag = 1;
1734 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1735 }
1736 if (start)
1737 azx_stream_start(chip, azx_dev);
1738 else
1739 azx_stream_stop(chip, azx_dev);
1740 azx_dev->running = start;
1741 }
1742 spin_unlock(&chip->reg_lock);
1743 if (start) {
1744 if (nsync == 1)
1745 return 0;
1746 /* wait until all FIFOs get ready */
1747 for (timeout = 5000; timeout; timeout--) {
1748 nwait = 0;
1749 snd_pcm_group_for_each_entry(s, substream) {
1750 if (s->pcm->card != substream->pcm->card)
1751 continue;
1752 azx_dev = get_azx_dev(s);
1753 if (!(azx_sd_readb(azx_dev, SD_STS) &
1754 SD_STS_FIFO_READY))
1755 nwait++;
1756 }
1757 if (!nwait)
1758 break;
1759 cpu_relax();
1760 }
1761 } else {
1762 /* wait until all RUN bits are cleared */
1763 for (timeout = 5000; timeout; timeout--) {
1764 nwait = 0;
1765 snd_pcm_group_for_each_entry(s, substream) {
1766 if (s->pcm->card != substream->pcm->card)
1767 continue;
1768 azx_dev = get_azx_dev(s);
1769 if (azx_sd_readb(azx_dev, SD_CTL) &
1770 SD_CTL_DMA_START)
1771 nwait++;
1772 }
1773 if (!nwait)
1774 break;
1775 cpu_relax();
1776 }
1777 }
1778 if (nsync > 1) {
1779 spin_lock(&chip->reg_lock);
1780 /* reset SYNC bits */
1781 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1782 spin_unlock(&chip->reg_lock);
1783 }
1784 return 0;
1785 }
1786
1787 /* get the current DMA position with correction on VIA chips */
1788 static unsigned int azx_via_get_position(struct azx *chip,
1789 struct azx_dev *azx_dev)
1790 {
1791 unsigned int link_pos, mini_pos, bound_pos;
1792 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1793 unsigned int fifo_size;
1794
1795 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1796 if (azx_dev->index >= 4) {
1797 /* Playback, no problem using link position */
1798 return link_pos;
1799 }
1800
1801 /* Capture */
1802 /* For new chipset,
1803 * use mod to get the DMA position just like old chipset
1804 */
1805 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1806 mod_dma_pos %= azx_dev->period_bytes;
1807
1808 /* azx_dev->fifo_size can't get FIFO size of in stream.
1809 * Get from base address + offset.
1810 */
1811 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1812
1813 if (azx_dev->insufficient) {
1814 /* Link position never gather than FIFO size */
1815 if (link_pos <= fifo_size)
1816 return 0;
1817
1818 azx_dev->insufficient = 0;
1819 }
1820
1821 if (link_pos <= fifo_size)
1822 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1823 else
1824 mini_pos = link_pos - fifo_size;
1825
1826 /* Find nearest previous boudary */
1827 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1828 mod_link_pos = link_pos % azx_dev->period_bytes;
1829 if (mod_link_pos >= fifo_size)
1830 bound_pos = link_pos - mod_link_pos;
1831 else if (mod_dma_pos >= mod_mini_pos)
1832 bound_pos = mini_pos - mod_mini_pos;
1833 else {
1834 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1835 if (bound_pos >= azx_dev->bufsize)
1836 bound_pos = 0;
1837 }
1838
1839 /* Calculate real DMA position we want */
1840 return bound_pos + mod_dma_pos;
1841 }
1842
1843 static unsigned int azx_get_position(struct azx *chip,
1844 struct azx_dev *azx_dev)
1845 {
1846 unsigned int pos;
1847
1848 if (chip->via_dmapos_patch)
1849 pos = azx_via_get_position(chip, azx_dev);
1850 else if (chip->position_fix == POS_FIX_POSBUF ||
1851 chip->position_fix == POS_FIX_AUTO) {
1852 /* use the position buffer */
1853 pos = le32_to_cpu(*azx_dev->posbuf);
1854 } else {
1855 /* read LPIB */
1856 pos = azx_sd_readl(azx_dev, SD_LPIB);
1857 }
1858 if (pos >= azx_dev->bufsize)
1859 pos = 0;
1860 return pos;
1861 }
1862
1863 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1864 {
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1866 struct azx *chip = apcm->chip;
1867 struct azx_dev *azx_dev = get_azx_dev(substream);
1868 return bytes_to_frames(substream->runtime,
1869 azx_get_position(chip, azx_dev));
1870 }
1871
1872 /*
1873 * Check whether the current DMA position is acceptable for updating
1874 * periods. Returns non-zero if it's OK.
1875 *
1876 * Many HD-audio controllers appear pretty inaccurate about
1877 * the update-IRQ timing. The IRQ is issued before actually the
1878 * data is processed. So, we need to process it afterwords in a
1879 * workqueue.
1880 */
1881 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1882 {
1883 unsigned int pos;
1884
1885 if (azx_dev->start_flag &&
1886 time_before_eq(jiffies, azx_dev->start_jiffies))
1887 return -1; /* bogus (too early) interrupt */
1888 azx_dev->start_flag = 0;
1889
1890 pos = azx_get_position(chip, azx_dev);
1891 if (chip->position_fix == POS_FIX_AUTO) {
1892 if (!pos) {
1893 printk(KERN_WARNING
1894 "hda-intel: Invalid position buffer, "
1895 "using LPIB read method instead.\n");
1896 chip->position_fix = POS_FIX_LPIB;
1897 pos = azx_get_position(chip, azx_dev);
1898 } else
1899 chip->position_fix = POS_FIX_POSBUF;
1900 }
1901
1902 if (!bdl_pos_adj[chip->dev_index])
1903 return 1; /* no delayed ack */
1904 if (WARN_ONCE(!azx_dev->period_bytes,
1905 "hda-intel: zero azx_dev->period_bytes"))
1906 return 0; /* this shouldn't happen! */
1907 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1908 return 0; /* NG - it's below the period boundary */
1909 return 1; /* OK, it's fine */
1910 }
1911
1912 /*
1913 * The work for pending PCM period updates.
1914 */
1915 static void azx_irq_pending_work(struct work_struct *work)
1916 {
1917 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1918 int i, pending;
1919
1920 if (!chip->irq_pending_warned) {
1921 printk(KERN_WARNING
1922 "hda-intel: IRQ timing workaround is activated "
1923 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1924 chip->card->number);
1925 chip->irq_pending_warned = 1;
1926 }
1927
1928 for (;;) {
1929 pending = 0;
1930 spin_lock_irq(&chip->reg_lock);
1931 for (i = 0; i < chip->num_streams; i++) {
1932 struct azx_dev *azx_dev = &chip->azx_dev[i];
1933 if (!azx_dev->irq_pending ||
1934 !azx_dev->substream ||
1935 !azx_dev->running)
1936 continue;
1937 if (azx_position_ok(chip, azx_dev)) {
1938 azx_dev->irq_pending = 0;
1939 spin_unlock(&chip->reg_lock);
1940 snd_pcm_period_elapsed(azx_dev->substream);
1941 spin_lock(&chip->reg_lock);
1942 } else
1943 pending++;
1944 }
1945 spin_unlock_irq(&chip->reg_lock);
1946 if (!pending)
1947 return;
1948 cond_resched();
1949 }
1950 }
1951
1952 /* clear irq_pending flags and assure no on-going workq */
1953 static void azx_clear_irq_pending(struct azx *chip)
1954 {
1955 int i;
1956
1957 spin_lock_irq(&chip->reg_lock);
1958 for (i = 0; i < chip->num_streams; i++)
1959 chip->azx_dev[i].irq_pending = 0;
1960 spin_unlock_irq(&chip->reg_lock);
1961 }
1962
1963 static struct snd_pcm_ops azx_pcm_ops = {
1964 .open = azx_pcm_open,
1965 .close = azx_pcm_close,
1966 .ioctl = snd_pcm_lib_ioctl,
1967 .hw_params = azx_pcm_hw_params,
1968 .hw_free = azx_pcm_hw_free,
1969 .prepare = azx_pcm_prepare,
1970 .trigger = azx_pcm_trigger,
1971 .pointer = azx_pcm_pointer,
1972 .page = snd_pcm_sgbuf_ops_page,
1973 };
1974
1975 static void azx_pcm_free(struct snd_pcm *pcm)
1976 {
1977 struct azx_pcm *apcm = pcm->private_data;
1978 if (apcm) {
1979 apcm->chip->pcm[pcm->device] = NULL;
1980 kfree(apcm);
1981 }
1982 }
1983
1984 static int
1985 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1986 struct hda_pcm *cpcm)
1987 {
1988 struct azx *chip = bus->private_data;
1989 struct snd_pcm *pcm;
1990 struct azx_pcm *apcm;
1991 int pcm_dev = cpcm->device;
1992 int s, err;
1993
1994 if (pcm_dev >= HDA_MAX_PCMS) {
1995 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1996 pcm_dev);
1997 return -EINVAL;
1998 }
1999 if (chip->pcm[pcm_dev]) {
2000 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2001 return -EBUSY;
2002 }
2003 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2004 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2005 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2006 &pcm);
2007 if (err < 0)
2008 return err;
2009 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2010 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2011 if (apcm == NULL)
2012 return -ENOMEM;
2013 apcm->chip = chip;
2014 apcm->codec = codec;
2015 pcm->private_data = apcm;
2016 pcm->private_free = azx_pcm_free;
2017 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2018 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2019 chip->pcm[pcm_dev] = pcm;
2020 cpcm->pcm = pcm;
2021 for (s = 0; s < 2; s++) {
2022 apcm->hinfo[s] = &cpcm->stream[s];
2023 if (cpcm->stream[s].substreams)
2024 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2025 }
2026 /* buffer pre-allocation */
2027 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2028 snd_dma_pci_data(chip->pci),
2029 1024 * 64, 32 * 1024 * 1024);
2030 return 0;
2031 }
2032
2033 /*
2034 * mixer creation - all stuff is implemented in hda module
2035 */
2036 static int __devinit azx_mixer_create(struct azx *chip)
2037 {
2038 return snd_hda_build_controls(chip->bus);
2039 }
2040
2041
2042 /*
2043 * initialize SD streams
2044 */
2045 static int __devinit azx_init_stream(struct azx *chip)
2046 {
2047 int i;
2048
2049 /* initialize each stream (aka device)
2050 * assign the starting bdl address to each stream (device)
2051 * and initialize
2052 */
2053 for (i = 0; i < chip->num_streams; i++) {
2054 struct azx_dev *azx_dev = &chip->azx_dev[i];
2055 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2056 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2057 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2058 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2059 azx_dev->sd_int_sta_mask = 1 << i;
2060 /* stream tag: must be non-zero and unique */
2061 azx_dev->index = i;
2062 azx_dev->stream_tag = i + 1;
2063 }
2064
2065 return 0;
2066 }
2067
2068 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2069 {
2070 if (request_irq(chip->pci->irq, azx_interrupt,
2071 chip->msi ? 0 : IRQF_SHARED,
2072 "hda_intel", chip)) {
2073 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2074 "disabling device\n", chip->pci->irq);
2075 if (do_disconnect)
2076 snd_card_disconnect(chip->card);
2077 return -1;
2078 }
2079 chip->irq = chip->pci->irq;
2080 pci_intx(chip->pci, !chip->msi);
2081 return 0;
2082 }
2083
2084
2085 static void azx_stop_chip(struct azx *chip)
2086 {
2087 if (!chip->initialized)
2088 return;
2089
2090 /* disable interrupts */
2091 azx_int_disable(chip);
2092 azx_int_clear(chip);
2093
2094 /* disable CORB/RIRB */
2095 azx_free_cmd_io(chip);
2096
2097 /* disable position buffer */
2098 azx_writel(chip, DPLBASE, 0);
2099 azx_writel(chip, DPUBASE, 0);
2100
2101 chip->initialized = 0;
2102 }
2103
2104 #ifdef CONFIG_SND_HDA_POWER_SAVE
2105 /* power-up/down the controller */
2106 static void azx_power_notify(struct hda_bus *bus)
2107 {
2108 struct azx *chip = bus->private_data;
2109 struct hda_codec *c;
2110 int power_on = 0;
2111
2112 list_for_each_entry(c, &bus->codec_list, list) {
2113 if (c->power_on) {
2114 power_on = 1;
2115 break;
2116 }
2117 }
2118 if (power_on)
2119 azx_init_chip(chip, 1);
2120 else if (chip->running && power_save_controller &&
2121 !bus->power_keep_link_on)
2122 azx_stop_chip(chip);
2123 }
2124 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2125
2126 #ifdef CONFIG_PM
2127 /*
2128 * power management
2129 */
2130
2131 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2132 {
2133 struct hda_codec *codec;
2134
2135 list_for_each_entry(codec, &bus->codec_list, list) {
2136 if (snd_hda_codec_needs_resume(codec))
2137 return 1;
2138 }
2139 return 0;
2140 }
2141
2142 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2143 {
2144 struct snd_card *card = pci_get_drvdata(pci);
2145 struct azx *chip = card->private_data;
2146 int i;
2147
2148 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2149 azx_clear_irq_pending(chip);
2150 for (i = 0; i < HDA_MAX_PCMS; i++)
2151 snd_pcm_suspend_all(chip->pcm[i]);
2152 if (chip->initialized)
2153 snd_hda_suspend(chip->bus);
2154 azx_stop_chip(chip);
2155 if (chip->irq >= 0) {
2156 free_irq(chip->irq, chip);
2157 chip->irq = -1;
2158 }
2159 if (chip->msi)
2160 pci_disable_msi(chip->pci);
2161 pci_disable_device(pci);
2162 pci_save_state(pci);
2163 pci_set_power_state(pci, pci_choose_state(pci, state));
2164 return 0;
2165 }
2166
2167 static int azx_resume(struct pci_dev *pci)
2168 {
2169 struct snd_card *card = pci_get_drvdata(pci);
2170 struct azx *chip = card->private_data;
2171
2172 pci_set_power_state(pci, PCI_D0);
2173 pci_restore_state(pci);
2174 if (pci_enable_device(pci) < 0) {
2175 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2176 "disabling device\n");
2177 snd_card_disconnect(card);
2178 return -EIO;
2179 }
2180 pci_set_master(pci);
2181 if (chip->msi)
2182 if (pci_enable_msi(pci) < 0)
2183 chip->msi = 0;
2184 if (azx_acquire_irq(chip, 1) < 0)
2185 return -EIO;
2186 azx_init_pci(chip);
2187
2188 if (snd_hda_codecs_inuse(chip->bus))
2189 azx_init_chip(chip, 1);
2190
2191 snd_hda_resume(chip->bus);
2192 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2193 return 0;
2194 }
2195 #endif /* CONFIG_PM */
2196
2197
2198 /*
2199 * reboot notifier for hang-up problem at power-down
2200 */
2201 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2202 {
2203 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2204 snd_hda_bus_reboot_notify(chip->bus);
2205 azx_stop_chip(chip);
2206 return NOTIFY_OK;
2207 }
2208
2209 static void azx_notifier_register(struct azx *chip)
2210 {
2211 chip->reboot_notifier.notifier_call = azx_halt;
2212 register_reboot_notifier(&chip->reboot_notifier);
2213 }
2214
2215 static void azx_notifier_unregister(struct azx *chip)
2216 {
2217 if (chip->reboot_notifier.notifier_call)
2218 unregister_reboot_notifier(&chip->reboot_notifier);
2219 }
2220
2221 /*
2222 * destructor
2223 */
2224 static int azx_free(struct azx *chip)
2225 {
2226 int i;
2227
2228 azx_notifier_unregister(chip);
2229
2230 if (chip->initialized) {
2231 azx_clear_irq_pending(chip);
2232 for (i = 0; i < chip->num_streams; i++)
2233 azx_stream_stop(chip, &chip->azx_dev[i]);
2234 azx_stop_chip(chip);
2235 }
2236
2237 if (chip->irq >= 0)
2238 free_irq(chip->irq, (void*)chip);
2239 if (chip->msi)
2240 pci_disable_msi(chip->pci);
2241 if (chip->remap_addr)
2242 iounmap(chip->remap_addr);
2243
2244 if (chip->azx_dev) {
2245 for (i = 0; i < chip->num_streams; i++)
2246 if (chip->azx_dev[i].bdl.area)
2247 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2248 }
2249 if (chip->rb.area)
2250 snd_dma_free_pages(&chip->rb);
2251 if (chip->posbuf.area)
2252 snd_dma_free_pages(&chip->posbuf);
2253 pci_release_regions(chip->pci);
2254 pci_disable_device(chip->pci);
2255 kfree(chip->azx_dev);
2256 kfree(chip);
2257
2258 return 0;
2259 }
2260
2261 static int azx_dev_free(struct snd_device *device)
2262 {
2263 return azx_free(device->device_data);
2264 }
2265
2266 /*
2267 * white/black-listing for position_fix
2268 */
2269 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2270 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2271 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2272 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2273 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2274 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2275 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2276 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2277 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2278 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2279 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2280 {}
2281 };
2282
2283 static int __devinit check_position_fix(struct azx *chip, int fix)
2284 {
2285 const struct snd_pci_quirk *q;
2286
2287 switch (fix) {
2288 case POS_FIX_LPIB:
2289 case POS_FIX_POSBUF:
2290 return fix;
2291 }
2292
2293 /* Check VIA/ATI HD Audio Controller exist */
2294 switch (chip->driver_type) {
2295 case AZX_DRIVER_VIA:
2296 case AZX_DRIVER_ATI:
2297 chip->via_dmapos_patch = 1;
2298 /* Use link position directly, avoid any transfer problem. */
2299 return POS_FIX_LPIB;
2300 }
2301 chip->via_dmapos_patch = 0;
2302
2303 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2304 if (q) {
2305 printk(KERN_INFO
2306 "hda_intel: position_fix set to %d "
2307 "for device %04x:%04x\n",
2308 q->value, q->subvendor, q->subdevice);
2309 return q->value;
2310 }
2311 return POS_FIX_AUTO;
2312 }
2313
2314 /*
2315 * black-lists for probe_mask
2316 */
2317 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2318 /* Thinkpad often breaks the controller communication when accessing
2319 * to the non-working (or non-existing) modem codec slot.
2320 */
2321 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2322 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2323 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2324 /* broken BIOS */
2325 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2326 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2327 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2328 /* forced codec slots */
2329 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2330 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2331 {}
2332 };
2333
2334 #define AZX_FORCE_CODEC_MASK 0x100
2335
2336 static void __devinit check_probe_mask(struct azx *chip, int dev)
2337 {
2338 const struct snd_pci_quirk *q;
2339
2340 chip->codec_probe_mask = probe_mask[dev];
2341 if (chip->codec_probe_mask == -1) {
2342 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2343 if (q) {
2344 printk(KERN_INFO
2345 "hda_intel: probe_mask set to 0x%x "
2346 "for device %04x:%04x\n",
2347 q->value, q->subvendor, q->subdevice);
2348 chip->codec_probe_mask = q->value;
2349 }
2350 }
2351
2352 /* check forced option */
2353 if (chip->codec_probe_mask != -1 &&
2354 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2355 chip->codec_mask = chip->codec_probe_mask & 0xff;
2356 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2357 chip->codec_mask);
2358 }
2359 }
2360
2361 /*
2362 * white/black-list for enable_msi
2363 */
2364 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2365 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2366 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2367 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2368 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2369 {}
2370 };
2371
2372 static void __devinit check_msi(struct azx *chip)
2373 {
2374 const struct snd_pci_quirk *q;
2375
2376 if (enable_msi >= 0) {
2377 chip->msi = !!enable_msi;
2378 return;
2379 }
2380 chip->msi = 1; /* enable MSI as default */
2381 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2382 if (q) {
2383 printk(KERN_INFO
2384 "hda_intel: msi for device %04x:%04x set to %d\n",
2385 q->subvendor, q->subdevice, q->value);
2386 chip->msi = q->value;
2387 return;
2388 }
2389
2390 /* NVidia chipsets seem to cause troubles with MSI */
2391 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2392 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2393 chip->msi = 0;
2394 }
2395 }
2396
2397
2398 /*
2399 * constructor
2400 */
2401 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2402 int dev, int driver_type,
2403 struct azx **rchip)
2404 {
2405 struct azx *chip;
2406 int i, err;
2407 unsigned short gcap;
2408 static struct snd_device_ops ops = {
2409 .dev_free = azx_dev_free,
2410 };
2411
2412 *rchip = NULL;
2413
2414 err = pci_enable_device(pci);
2415 if (err < 0)
2416 return err;
2417
2418 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2419 if (!chip) {
2420 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2421 pci_disable_device(pci);
2422 return -ENOMEM;
2423 }
2424
2425 spin_lock_init(&chip->reg_lock);
2426 mutex_init(&chip->open_mutex);
2427 chip->card = card;
2428 chip->pci = pci;
2429 chip->irq = -1;
2430 chip->driver_type = driver_type;
2431 check_msi(chip);
2432 chip->dev_index = dev;
2433 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2434
2435 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2436 check_probe_mask(chip, dev);
2437
2438 chip->single_cmd = single_cmd;
2439
2440 if (bdl_pos_adj[dev] < 0) {
2441 switch (chip->driver_type) {
2442 case AZX_DRIVER_ICH:
2443 case AZX_DRIVER_PCH:
2444 bdl_pos_adj[dev] = 1;
2445 break;
2446 default:
2447 bdl_pos_adj[dev] = 32;
2448 break;
2449 }
2450 }
2451
2452 #if BITS_PER_LONG != 64
2453 /* Fix up base address on ULI M5461 */
2454 if (chip->driver_type == AZX_DRIVER_ULI) {
2455 u16 tmp3;
2456 pci_read_config_word(pci, 0x40, &tmp3);
2457 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2458 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2459 }
2460 #endif
2461
2462 err = pci_request_regions(pci, "ICH HD audio");
2463 if (err < 0) {
2464 kfree(chip);
2465 pci_disable_device(pci);
2466 return err;
2467 }
2468
2469 chip->addr = pci_resource_start(pci, 0);
2470 chip->remap_addr = pci_ioremap_bar(pci, 0);
2471 if (chip->remap_addr == NULL) {
2472 snd_printk(KERN_ERR SFX "ioremap error\n");
2473 err = -ENXIO;
2474 goto errout;
2475 }
2476
2477 if (chip->msi)
2478 if (pci_enable_msi(pci) < 0)
2479 chip->msi = 0;
2480
2481 if (azx_acquire_irq(chip, 0) < 0) {
2482 err = -EBUSY;
2483 goto errout;
2484 }
2485
2486 pci_set_master(pci);
2487 synchronize_irq(chip->irq);
2488
2489 gcap = azx_readw(chip, GCAP);
2490 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2491
2492 /* disable SB600 64bit support for safety */
2493 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2494 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2495 struct pci_dev *p_smbus;
2496 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2497 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2498 NULL);
2499 if (p_smbus) {
2500 if (p_smbus->revision < 0x30)
2501 gcap &= ~ICH6_GCAP_64OK;
2502 pci_dev_put(p_smbus);
2503 }
2504 }
2505
2506 /* disable 64bit DMA address for Teradici */
2507 /* it does not work with device 6549:1200 subsys e4a2:040b */
2508 if (chip->driver_type == AZX_DRIVER_TERA)
2509 gcap &= ~ICH6_GCAP_64OK;
2510
2511 /* allow 64bit DMA address if supported by H/W */
2512 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2513 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2514 else {
2515 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2516 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2517 }
2518
2519 /* read number of streams from GCAP register instead of using
2520 * hardcoded value
2521 */
2522 chip->capture_streams = (gcap >> 8) & 0x0f;
2523 chip->playback_streams = (gcap >> 12) & 0x0f;
2524 if (!chip->playback_streams && !chip->capture_streams) {
2525 /* gcap didn't give any info, switching to old method */
2526
2527 switch (chip->driver_type) {
2528 case AZX_DRIVER_ULI:
2529 chip->playback_streams = ULI_NUM_PLAYBACK;
2530 chip->capture_streams = ULI_NUM_CAPTURE;
2531 break;
2532 case AZX_DRIVER_ATIHDMI:
2533 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2534 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2535 break;
2536 case AZX_DRIVER_GENERIC:
2537 default:
2538 chip->playback_streams = ICH6_NUM_PLAYBACK;
2539 chip->capture_streams = ICH6_NUM_CAPTURE;
2540 break;
2541 }
2542 }
2543 chip->capture_index_offset = 0;
2544 chip->playback_index_offset = chip->capture_streams;
2545 chip->num_streams = chip->playback_streams + chip->capture_streams;
2546 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2547 GFP_KERNEL);
2548 if (!chip->azx_dev) {
2549 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2550 goto errout;
2551 }
2552
2553 for (i = 0; i < chip->num_streams; i++) {
2554 /* allocate memory for the BDL for each stream */
2555 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2556 snd_dma_pci_data(chip->pci),
2557 BDL_SIZE, &chip->azx_dev[i].bdl);
2558 if (err < 0) {
2559 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2560 goto errout;
2561 }
2562 }
2563 /* allocate memory for the position buffer */
2564 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2565 snd_dma_pci_data(chip->pci),
2566 chip->num_streams * 8, &chip->posbuf);
2567 if (err < 0) {
2568 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2569 goto errout;
2570 }
2571 /* allocate CORB/RIRB */
2572 err = azx_alloc_cmd_io(chip);
2573 if (err < 0)
2574 goto errout;
2575
2576 /* initialize streams */
2577 azx_init_stream(chip);
2578
2579 /* initialize chip */
2580 azx_init_pci(chip);
2581 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2582
2583 /* codec detection */
2584 if (!chip->codec_mask) {
2585 snd_printk(KERN_ERR SFX "no codecs found!\n");
2586 err = -ENODEV;
2587 goto errout;
2588 }
2589
2590 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2591 if (err <0) {
2592 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2593 goto errout;
2594 }
2595
2596 strcpy(card->driver, "HDA-Intel");
2597 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2598 sizeof(card->shortname));
2599 snprintf(card->longname, sizeof(card->longname),
2600 "%s at 0x%lx irq %i",
2601 card->shortname, chip->addr, chip->irq);
2602
2603 *rchip = chip;
2604 return 0;
2605
2606 errout:
2607 azx_free(chip);
2608 return err;
2609 }
2610
2611 static void power_down_all_codecs(struct azx *chip)
2612 {
2613 #ifdef CONFIG_SND_HDA_POWER_SAVE
2614 /* The codecs were powered up in snd_hda_codec_new().
2615 * Now all initialization done, so turn them down if possible
2616 */
2617 struct hda_codec *codec;
2618 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2619 snd_hda_power_down(codec);
2620 }
2621 #endif
2622 }
2623
2624 static int __devinit azx_probe(struct pci_dev *pci,
2625 const struct pci_device_id *pci_id)
2626 {
2627 static int dev;
2628 struct snd_card *card;
2629 struct azx *chip;
2630 int err;
2631
2632 if (dev >= SNDRV_CARDS)
2633 return -ENODEV;
2634 if (!enable[dev]) {
2635 dev++;
2636 return -ENOENT;
2637 }
2638
2639 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2640 if (err < 0) {
2641 snd_printk(KERN_ERR SFX "Error creating card!\n");
2642 return err;
2643 }
2644
2645 /* set this here since it's referred in snd_hda_load_patch() */
2646 snd_card_set_dev(card, &pci->dev);
2647
2648 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2649 if (err < 0)
2650 goto out_free;
2651 card->private_data = chip;
2652
2653 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2654 chip->beep_mode = beep_mode[dev];
2655 #endif
2656
2657 /* create codec instances */
2658 err = azx_codec_create(chip, model[dev]);
2659 if (err < 0)
2660 goto out_free;
2661 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2662 if (patch[dev]) {
2663 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2664 patch[dev]);
2665 err = snd_hda_load_patch(chip->bus, patch[dev]);
2666 if (err < 0)
2667 goto out_free;
2668 }
2669 #endif
2670 if ((probe_only[dev] & 1) == 0) {
2671 err = azx_codec_configure(chip);
2672 if (err < 0)
2673 goto out_free;
2674 }
2675
2676 /* create PCM streams */
2677 err = snd_hda_build_pcms(chip->bus);
2678 if (err < 0)
2679 goto out_free;
2680
2681 /* create mixer controls */
2682 err = azx_mixer_create(chip);
2683 if (err < 0)
2684 goto out_free;
2685
2686 err = snd_card_register(card);
2687 if (err < 0)
2688 goto out_free;
2689
2690 pci_set_drvdata(pci, card);
2691 chip->running = 1;
2692 power_down_all_codecs(chip);
2693 azx_notifier_register(chip);
2694
2695 dev++;
2696 return err;
2697 out_free:
2698 snd_card_free(card);
2699 return err;
2700 }
2701
2702 static void __devexit azx_remove(struct pci_dev *pci)
2703 {
2704 snd_card_free(pci_get_drvdata(pci));
2705 pci_set_drvdata(pci, NULL);
2706 }
2707
2708 /* PCI IDs */
2709 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2710 /* ICH 6..10 */
2711 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2712 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2713 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2714 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2715 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2716 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2717 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2718 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2719 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2720 /* PCH */
2721 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2722 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
2723 /* CPT */
2724 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2725 /* SCH */
2726 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2727 /* ATI SB 450/600 */
2728 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2729 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2730 /* ATI HDMI */
2731 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2732 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2733 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2734 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2735 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2736 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2737 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2738 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2739 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2740 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2741 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2742 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2743 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2744 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2745 /* VIA VT8251/VT8237A */
2746 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2747 /* SIS966 */
2748 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2749 /* ULI M5461 */
2750 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2751 /* NVIDIA MCP */
2752 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2753 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2754 .class_mask = 0xffffff,
2755 .driver_data = AZX_DRIVER_NVIDIA },
2756 /* Teradici */
2757 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2758 /* Creative X-Fi (CA0110-IBG) */
2759 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2760 /* the following entry conflicts with snd-ctxfi driver,
2761 * as ctxfi driver mutates from HD-audio to native mode with
2762 * a special command sequence.
2763 */
2764 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2765 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2766 .class_mask = 0xffffff,
2767 .driver_data = AZX_DRIVER_GENERIC },
2768 #else
2769 /* this entry seems still valid -- i.e. without emu20kx chip */
2770 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2771 #endif
2772 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2773 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2774 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2775 .class_mask = 0xffffff,
2776 .driver_data = AZX_DRIVER_GENERIC },
2777 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2778 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2779 .class_mask = 0xffffff,
2780 .driver_data = AZX_DRIVER_GENERIC },
2781 { 0, }
2782 };
2783 MODULE_DEVICE_TABLE(pci, azx_ids);
2784
2785 /* pci_driver definition */
2786 static struct pci_driver driver = {
2787 .name = "HDA Intel",
2788 .id_table = azx_ids,
2789 .probe = azx_probe,
2790 .remove = __devexit_p(azx_remove),
2791 #ifdef CONFIG_PM
2792 .suspend = azx_suspend,
2793 .resume = azx_resume,
2794 #endif
2795 };
2796
2797 static int __init alsa_card_azx_init(void)
2798 {
2799 return pci_register_driver(&driver);
2800 }
2801
2802 static void __exit alsa_card_azx_exit(void)
2803 {
2804 pci_unregister_driver(&driver);
2805 }
2806
2807 module_init(alsa_card_azx_init)
2808 module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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