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ced1406d777f3644ba3da58408db8805f9e21e78
[deliverable/linux.git] / sound / pci / rme9652 / hdspm.c
1 /*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
91
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
135
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
143
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
148
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
156
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
165
166
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
170
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
180
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
196
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
200
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
207
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233 * -- MADI ONLY
234 */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
239
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293 HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
311
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
333 for the AES32
334 */
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
338 * (like inp0)
339 */
340
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
363 * Interrupt
364 */
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
367
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
371
372
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0) /* not realy defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431 HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437 HDSPM_SelSyncRef2)
438
439 /*
440 For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446 HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /* status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
472 /*
473 Timecode
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475 AES i+1
476 bits 3210
477 0001 32kHz
478 0010 44.1kHz
479 0011 48kHz
480 0100 64kHz
481 0101 88.2kHz
482 0110 96kHz
483 0111 128kHz
484 1000 176.4kHz
485 1001 192kHz
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
497
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
501
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
508
509 /* the size of a substream (1 mono data stream) */
510 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
511 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
512
513 /* the size of the area we need to allocate for DMA transfers. the
514 size is the same regardless of the number of channels, and
515 also the latency to use.
516 for one direction !!!
517 */
518 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
519 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
520
521 /* revisions >= 230 indicate AES32 card */
522 #define HDSPM_MADI_REV 210
523 #define HDSPM_RAYDAT_REV 211
524 #define HDSPM_AIO_REV 212
525 #define HDSPM_MADIFACE_REV 213
526 #define HDSPM_AES_REV 240
527
528 /* speed factor modes */
529 #define HDSPM_SPEED_SINGLE 0
530 #define HDSPM_SPEED_DOUBLE 1
531 #define HDSPM_SPEED_QUAD 2
532
533 /* names for speed modes */
534 static char *hdspm_speed_names[] = { "single", "double", "quad" };
535
536 static char *texts_autosync_aes_tco[] = { "Word Clock",
537 "AES1", "AES2", "AES3", "AES4",
538 "AES5", "AES6", "AES7", "AES8",
539 "TCO" };
540 static char *texts_autosync_aes[] = { "Word Clock",
541 "AES1", "AES2", "AES3", "AES4",
542 "AES5", "AES6", "AES7", "AES8" };
543 static char *texts_autosync_madi_tco[] = { "Word Clock",
544 "MADI", "TCO", "Sync In" };
545 static char *texts_autosync_madi[] = { "Word Clock",
546 "MADI", "Sync In" };
547
548 static char *texts_autosync_raydat_tco[] = {
549 "Word Clock",
550 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
551 "AES", "SPDIF", "TCO", "Sync In"
552 };
553 static char *texts_autosync_raydat[] = {
554 "Word Clock",
555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556 "AES", "SPDIF", "Sync In"
557 };
558 static char *texts_autosync_aio_tco[] = {
559 "Word Clock",
560 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
561 };
562 static char *texts_autosync_aio[] = { "Word Clock",
563 "ADAT", "AES", "SPDIF", "Sync In" };
564
565 static char *texts_freq[] = {
566 "No Lock",
567 "32 kHz",
568 "44.1 kHz",
569 "48 kHz",
570 "64 kHz",
571 "88.2 kHz",
572 "96 kHz",
573 "128 kHz",
574 "176.4 kHz",
575 "192 kHz"
576 };
577
578 static char *texts_ports_madi[] = {
579 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
580 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
581 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
582 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
583 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
584 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
585 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
586 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
587 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
588 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
589 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
590 };
591
592
593 static char *texts_ports_raydat_ss[] = {
594 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
595 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
596 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
597 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
598 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
599 "ADAT4.7", "ADAT4.8",
600 "AES.L", "AES.R",
601 "SPDIF.L", "SPDIF.R"
602 };
603
604 static char *texts_ports_raydat_ds[] = {
605 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
606 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
607 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
608 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
609 "AES.L", "AES.R",
610 "SPDIF.L", "SPDIF.R"
611 };
612
613 static char *texts_ports_raydat_qs[] = {
614 "ADAT1.1", "ADAT1.2",
615 "ADAT2.1", "ADAT2.2",
616 "ADAT3.1", "ADAT3.2",
617 "ADAT4.1", "ADAT4.2",
618 "AES.L", "AES.R",
619 "SPDIF.L", "SPDIF.R"
620 };
621
622
623 static char *texts_ports_aio_in_ss[] = {
624 "Analogue.L", "Analogue.R",
625 "AES.L", "AES.R",
626 "SPDIF.L", "SPDIF.R",
627 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
628 "ADAT.7", "ADAT.8"
629 };
630
631 static char *texts_ports_aio_out_ss[] = {
632 "Analogue.L", "Analogue.R",
633 "AES.L", "AES.R",
634 "SPDIF.L", "SPDIF.R",
635 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
636 "ADAT.7", "ADAT.8",
637 "Phone.L", "Phone.R"
638 };
639
640 static char *texts_ports_aio_in_ds[] = {
641 "Analogue.L", "Analogue.R",
642 "AES.L", "AES.R",
643 "SPDIF.L", "SPDIF.R",
644 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
645 };
646
647 static char *texts_ports_aio_out_ds[] = {
648 "Analogue.L", "Analogue.R",
649 "AES.L", "AES.R",
650 "SPDIF.L", "SPDIF.R",
651 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
652 "Phone.L", "Phone.R"
653 };
654
655 static char *texts_ports_aio_in_qs[] = {
656 "Analogue.L", "Analogue.R",
657 "AES.L", "AES.R",
658 "SPDIF.L", "SPDIF.R",
659 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
660 };
661
662 static char *texts_ports_aio_out_qs[] = {
663 "Analogue.L", "Analogue.R",
664 "AES.L", "AES.R",
665 "SPDIF.L", "SPDIF.R",
666 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
667 "Phone.L", "Phone.R"
668 };
669
670 static char *texts_ports_aes32[] = {
671 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
672 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
673 "AES.15", "AES.16"
674 };
675
676 /* These tables map the ALSA channels 1..N to the channels that we
677 need to use in order to find the relevant channel buffer. RME
678 refers to this kind of mapping as between "the ADAT channel and
679 the DMA channel." We index it using the logical audio channel,
680 and the value is the DMA channel (i.e. channel buffer number)
681 where the data for that channel can be read/written from/to.
682 */
683
684 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
685 0, 1, 2, 3, 4, 5, 6, 7,
686 8, 9, 10, 11, 12, 13, 14, 15,
687 16, 17, 18, 19, 20, 21, 22, 23,
688 24, 25, 26, 27, 28, 29, 30, 31,
689 32, 33, 34, 35, 36, 37, 38, 39,
690 40, 41, 42, 43, 44, 45, 46, 47,
691 48, 49, 50, 51, 52, 53, 54, 55,
692 56, 57, 58, 59, 60, 61, 62, 63
693 };
694
695 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
696 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
697 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
698 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
699 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
700 0, 1, /* AES */
701 2, 3, /* SPDIF */
702 -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
705 -1, -1, -1, -1, -1, -1, -1, -1,
706 };
707
708 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
709 4, 5, 6, 7, /* ADAT 1 */
710 8, 9, 10, 11, /* ADAT 2 */
711 12, 13, 14, 15, /* ADAT 3 */
712 16, 17, 18, 19, /* ADAT 4 */
713 0, 1, /* AES */
714 2, 3, /* SPDIF */
715 -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
720 -1, -1, -1, -1, -1, -1, -1, -1,
721 };
722
723 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
724 4, 5, /* ADAT 1 */
725 6, 7, /* ADAT 2 */
726 8, 9, /* ADAT 3 */
727 10, 11, /* ADAT 4 */
728 0, 1, /* AES */
729 2, 3, /* SPDIF */
730 -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
736 -1, -1, -1, -1, -1, -1, -1, -1,
737 };
738
739 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
740 0, 1, /* line in */
741 8, 9, /* aes in, */
742 10, 11, /* spdif in */
743 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
744 -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
750 -1, -1, -1, -1, -1, -1, -1, -1,
751 };
752
753 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
754 0, 1, /* line out */
755 8, 9, /* aes out */
756 10, 11, /* spdif out */
757 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
758 6, 7, /* phone out */
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
764 -1, -1, -1, -1, -1, -1, -1, -1,
765 };
766
767 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
768 0, 1, /* line in */
769 8, 9, /* aes in */
770 10, 11, /* spdif in */
771 12, 14, 16, 18, /* adat in */
772 -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1,
778 -1, -1, -1, -1, -1, -1, -1, -1
779 };
780
781 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
782 0, 1, /* line out */
783 8, 9, /* aes out */
784 10, 11, /* spdif out */
785 12, 14, 16, 18, /* adat out */
786 6, 7, /* phone out */
787 -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1,
793 -1, -1, -1, -1, -1, -1, -1, -1
794 };
795
796 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
797 0, 1, /* line in */
798 8, 9, /* aes in */
799 10, 11, /* spdif in */
800 12, 16, /* adat in */
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1
808 };
809
810 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
811 0, 1, /* line out */
812 8, 9, /* aes out */
813 10, 11, /* spdif out */
814 12, 16, /* adat out */
815 6, 7, /* phone out */
816 -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1
823 };
824
825 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
826 0, 1, 2, 3, 4, 5, 6, 7,
827 8, 9, 10, 11, 12, 13, 14, 15,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1,
833 -1, -1, -1, -1, -1, -1, -1, -1
834 };
835
836 struct hdspm_midi {
837 struct hdspm *hdspm;
838 int id;
839 struct snd_rawmidi *rmidi;
840 struct snd_rawmidi_substream *input;
841 struct snd_rawmidi_substream *output;
842 char istimer; /* timer in use */
843 struct timer_list timer;
844 spinlock_t lock;
845 int pending;
846 int dataIn;
847 int statusIn;
848 int dataOut;
849 int statusOut;
850 int ie;
851 int irq;
852 };
853
854 struct hdspm_tco {
855 int input;
856 int framerate;
857 int wordclock;
858 int samplerate;
859 int pull;
860 int term; /* 0 = off, 1 = on */
861 };
862
863 struct hdspm {
864 spinlock_t lock;
865 /* only one playback and/or capture stream */
866 struct snd_pcm_substream *capture_substream;
867 struct snd_pcm_substream *playback_substream;
868
869 char *card_name; /* for procinfo */
870 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
871
872 uint8_t io_type;
873
874 int monitor_outs; /* set up monitoring outs init flag */
875
876 u32 control_register; /* cached value */
877 u32 control2_register; /* cached value */
878 u32 settings_register;
879
880 struct hdspm_midi midi[4];
881 struct tasklet_struct midi_tasklet;
882
883 size_t period_bytes;
884 unsigned char ss_in_channels;
885 unsigned char ds_in_channels;
886 unsigned char qs_in_channels;
887 unsigned char ss_out_channels;
888 unsigned char ds_out_channels;
889 unsigned char qs_out_channels;
890
891 unsigned char max_channels_in;
892 unsigned char max_channels_out;
893
894 char *channel_map_in;
895 char *channel_map_out;
896
897 char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
898 char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
899
900 char **port_names_in;
901 char **port_names_out;
902
903 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
904 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
905
906 unsigned char *playback_buffer; /* suitably aligned address */
907 unsigned char *capture_buffer; /* suitably aligned address */
908
909 pid_t capture_pid; /* process id which uses capture */
910 pid_t playback_pid; /* process id which uses capture */
911 int running; /* running status */
912
913 int last_external_sample_rate; /* samplerate mystic ... */
914 int last_internal_sample_rate;
915 int system_sample_rate;
916
917 int dev; /* Hardware vars... */
918 int irq;
919 unsigned long port;
920 void __iomem *iobase;
921
922 int irq_count; /* for debug */
923 int midiPorts;
924
925 struct snd_card *card; /* one card */
926 struct snd_pcm *pcm; /* has one pcm */
927 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
928 struct pci_dev *pci; /* and an pci info */
929
930 /* Mixer vars */
931 /* fast alsa mixer */
932 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
933 /* but input to much, so not used */
934 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
935 /* full mixer accessable over mixer ioctl or hwdep-device */
936 struct hdspm_mixer *mixer;
937
938 struct hdspm_tco *tco; /* NULL if no TCO detected */
939
940 char **texts_autosync;
941 int texts_autosync_items;
942
943 cycles_t last_interrupt;
944
945 struct hdspm_peak_rms peak_rms;
946 };
947
948
949 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
950 {
951 .vendor = PCI_VENDOR_ID_XILINX,
952 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
953 .subvendor = PCI_ANY_ID,
954 .subdevice = PCI_ANY_ID,
955 .class = 0,
956 .class_mask = 0,
957 .driver_data = 0},
958 {0,}
959 };
960
961 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
962
963 /* prototypes */
964 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
965 struct hdspm * hdspm);
966 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
967 struct hdspm * hdspm);
968
969 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
970 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
971 static int hdspm_autosync_ref(struct hdspm *hdspm);
972 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
973 static void hdspm_set_sgbuf(struct hdspm *hdspm,
974 struct snd_pcm_substream *substream,
975 unsigned int reg, int channels);
976
977 static inline int HDSPM_bit2freq(int n)
978 {
979 static const int bit2freq_tab[] = {
980 0, 32000, 44100, 48000, 64000, 88200,
981 96000, 128000, 176400, 192000 };
982 if (n < 1 || n > 9)
983 return 0;
984 return bit2freq_tab[n];
985 }
986
987 /* Write/read to/from HDSPM with Adresses in Bytes
988 not words but only 32Bit writes are allowed */
989
990 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
991 unsigned int val)
992 {
993 writel(val, hdspm->iobase + reg);
994 }
995
996 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
997 {
998 return readl(hdspm->iobase + reg);
999 }
1000
1001 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1002 mixer is write only on hardware so we have to cache him for read
1003 each fader is a u32, but uses only the first 16 bit */
1004
1005 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1006 unsigned int in)
1007 {
1008 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1009 return 0;
1010
1011 return hdspm->mixer->ch[chan].in[in];
1012 }
1013
1014 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1015 unsigned int pb)
1016 {
1017 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1018 return 0;
1019 return hdspm->mixer->ch[chan].pb[pb];
1020 }
1021
1022 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1023 unsigned int in, unsigned short data)
1024 {
1025 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1026 return -1;
1027
1028 hdspm_write(hdspm,
1029 HDSPM_MADI_mixerBase +
1030 ((in + 128 * chan) * sizeof(u32)),
1031 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1032 return 0;
1033 }
1034
1035 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1036 unsigned int pb, unsigned short data)
1037 {
1038 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1039 return -1;
1040
1041 hdspm_write(hdspm,
1042 HDSPM_MADI_mixerBase +
1043 ((64 + pb + 128 * chan) * sizeof(u32)),
1044 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1045 return 0;
1046 }
1047
1048
1049 /* enable DMA for specific channels, now available for DSP-MADI */
1050 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1051 {
1052 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1053 }
1054
1055 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1056 {
1057 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1058 }
1059
1060 /* check if same process is writing and reading */
1061 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1062 {
1063 unsigned long flags;
1064 int ret = 1;
1065
1066 spin_lock_irqsave(&hdspm->lock, flags);
1067 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1068 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1069 ret = 0;
1070 }
1071 spin_unlock_irqrestore(&hdspm->lock, flags);
1072 return ret;
1073 }
1074
1075 /* check for external sample rate */
1076 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1077 {
1078 unsigned int status, status2, timecode;
1079 int syncref, rate = 0, rate_bits;
1080
1081 switch (hdspm->io_type) {
1082 case AES32:
1083 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1084 status = hdspm_read(hdspm, HDSPM_statusRegister);
1085 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1086
1087 syncref = hdspm_autosync_ref(hdspm);
1088
1089 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1090 status & HDSPM_AES32_wcLock)
1091 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1092
1093 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1094 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1095 status2 & (HDSPM_LockAES >>
1096 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1097 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1098 return 0;
1099 break;
1100
1101 case MADIface:
1102 status = hdspm_read(hdspm, HDSPM_statusRegister);
1103
1104 if (!(status & HDSPM_madiLock)) {
1105 rate = 0; /* no lock */
1106 } else {
1107 switch (status & (HDSPM_status1_freqMask)) {
1108 case HDSPM_status1_F_0*1:
1109 rate = 32000; break;
1110 case HDSPM_status1_F_0*2:
1111 rate = 44100; break;
1112 case HDSPM_status1_F_0*3:
1113 rate = 48000; break;
1114 case HDSPM_status1_F_0*4:
1115 rate = 64000; break;
1116 case HDSPM_status1_F_0*5:
1117 rate = 88200; break;
1118 case HDSPM_status1_F_0*6:
1119 rate = 96000; break;
1120 case HDSPM_status1_F_0*7:
1121 rate = 128000; break;
1122 case HDSPM_status1_F_0*8:
1123 rate = 176400; break;
1124 case HDSPM_status1_F_0*9:
1125 rate = 192000; break;
1126 default:
1127 rate = 0; break;
1128 }
1129 }
1130
1131 break;
1132
1133 case MADI:
1134 case AIO:
1135 case RayDAT:
1136 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1137 status = hdspm_read(hdspm, HDSPM_statusRegister);
1138 rate = 0;
1139
1140 /* if wordclock has synced freq and wordclock is valid */
1141 if ((status2 & HDSPM_wcLock) != 0 &&
1142 (status & HDSPM_SelSyncRef0) == 0) {
1143
1144 rate_bits = status2 & HDSPM_wcFreqMask;
1145
1146
1147 switch (rate_bits) {
1148 case HDSPM_wcFreq32:
1149 rate = 32000;
1150 break;
1151 case HDSPM_wcFreq44_1:
1152 rate = 44100;
1153 break;
1154 case HDSPM_wcFreq48:
1155 rate = 48000;
1156 break;
1157 case HDSPM_wcFreq64:
1158 rate = 64000;
1159 break;
1160 case HDSPM_wcFreq88_2:
1161 rate = 88200;
1162 break;
1163 case HDSPM_wcFreq96:
1164 rate = 96000;
1165 break;
1166 default:
1167 rate = 0;
1168 break;
1169 }
1170 }
1171
1172 /* if rate detected and Syncref is Word than have it,
1173 * word has priority to MADI
1174 */
1175 if (rate != 0 &&
1176 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1177 return rate;
1178
1179 /* maybe a madi input (which is taken if sel sync is madi) */
1180 if (status & HDSPM_madiLock) {
1181 rate_bits = status & HDSPM_madiFreqMask;
1182
1183 switch (rate_bits) {
1184 case HDSPM_madiFreq32:
1185 rate = 32000;
1186 break;
1187 case HDSPM_madiFreq44_1:
1188 rate = 44100;
1189 break;
1190 case HDSPM_madiFreq48:
1191 rate = 48000;
1192 break;
1193 case HDSPM_madiFreq64:
1194 rate = 64000;
1195 break;
1196 case HDSPM_madiFreq88_2:
1197 rate = 88200;
1198 break;
1199 case HDSPM_madiFreq96:
1200 rate = 96000;
1201 break;
1202 case HDSPM_madiFreq128:
1203 rate = 128000;
1204 break;
1205 case HDSPM_madiFreq176_4:
1206 rate = 176400;
1207 break;
1208 case HDSPM_madiFreq192:
1209 rate = 192000;
1210 break;
1211 default:
1212 rate = 0;
1213 break;
1214 }
1215 }
1216 break;
1217 }
1218
1219 return rate;
1220 }
1221
1222 /* Latency function */
1223 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1224 {
1225 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1226 }
1227
1228
1229 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1230 {
1231 int position;
1232
1233 position = hdspm_read(hdspm, HDSPM_statusRegister);
1234
1235 switch (hdspm->io_type) {
1236 case RayDAT:
1237 case AIO:
1238 position &= HDSPM_BufferPositionMask;
1239 position /= 4; /* Bytes per sample */
1240 break;
1241 default:
1242 position = (position & HDSPM_BufferID) ?
1243 (hdspm->period_bytes / 4) : 0;
1244 }
1245
1246 return position;
1247 }
1248
1249
1250 static inline void hdspm_start_audio(struct hdspm * s)
1251 {
1252 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1253 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1254 }
1255
1256 static inline void hdspm_stop_audio(struct hdspm * s)
1257 {
1258 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1259 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1260 }
1261
1262 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1263 static void hdspm_silence_playback(struct hdspm *hdspm)
1264 {
1265 int i;
1266 int n = hdspm->period_bytes;
1267 void *buf = hdspm->playback_buffer;
1268
1269 if (buf == NULL)
1270 return;
1271
1272 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1273 memset(buf, 0, n);
1274 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1275 }
1276 }
1277
1278 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1279 {
1280 int n;
1281
1282 spin_lock_irq(&s->lock);
1283
1284 frames >>= 7;
1285 n = 0;
1286 while (frames) {
1287 n++;
1288 frames >>= 1;
1289 }
1290 s->control_register &= ~HDSPM_LatencyMask;
1291 s->control_register |= hdspm_encode_latency(n);
1292
1293 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1294
1295 hdspm_compute_period_size(s);
1296
1297 spin_unlock_irq(&s->lock);
1298
1299 return 0;
1300 }
1301
1302 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1303 {
1304 u64 freq_const;
1305
1306 if (period == 0)
1307 return 0;
1308
1309 switch (hdspm->io_type) {
1310 case MADI:
1311 case AES32:
1312 freq_const = 110069313433624ULL;
1313 break;
1314 case RayDAT:
1315 case AIO:
1316 freq_const = 104857600000000ULL;
1317 break;
1318 case MADIface:
1319 freq_const = 131072000000000ULL;
1320 }
1321
1322 return div_u64(freq_const, period);
1323 }
1324
1325
1326 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1327 {
1328 u64 n;
1329
1330 if (rate >= 112000)
1331 rate /= 4;
1332 else if (rate >= 56000)
1333 rate /= 2;
1334
1335 switch (hdspm->io_type) {
1336 case MADIface:
1337 n = 131072000000000ULL; /* 125 MHz */
1338 break;
1339 case MADI:
1340 case AES32:
1341 n = 110069313433624ULL; /* 105 MHz */
1342 break;
1343 case RayDAT:
1344 case AIO:
1345 n = 104857600000000ULL; /* 100 MHz */
1346 break;
1347 }
1348
1349 n = div_u64(n, rate);
1350 /* n should be less than 2^32 for being written to FREQ register */
1351 snd_BUG_ON(n >> 32);
1352 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1353 }
1354
1355 /* dummy set rate lets see what happens */
1356 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1357 {
1358 int current_rate;
1359 int rate_bits;
1360 int not_set = 0;
1361 int current_speed, target_speed;
1362
1363 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1364 it (e.g. during module initialization).
1365 */
1366
1367 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1368
1369 /* SLAVE --- */
1370 if (called_internally) {
1371
1372 /* request from ctl or card initialization
1373 just make a warning an remember setting
1374 for future master mode switching */
1375
1376 snd_printk(KERN_WARNING "HDSPM: "
1377 "Warning: device is not running "
1378 "as a clock master.\n");
1379 not_set = 1;
1380 } else {
1381
1382 /* hw_param request while in AutoSync mode */
1383 int external_freq =
1384 hdspm_external_sample_rate(hdspm);
1385
1386 if (hdspm_autosync_ref(hdspm) ==
1387 HDSPM_AUTOSYNC_FROM_NONE) {
1388
1389 snd_printk(KERN_WARNING "HDSPM: "
1390 "Detected no Externel Sync \n");
1391 not_set = 1;
1392
1393 } else if (rate != external_freq) {
1394
1395 snd_printk(KERN_WARNING "HDSPM: "
1396 "Warning: No AutoSync source for "
1397 "requested rate\n");
1398 not_set = 1;
1399 }
1400 }
1401 }
1402
1403 current_rate = hdspm->system_sample_rate;
1404
1405 /* Changing between Singe, Double and Quad speed is not
1406 allowed if any substreams are open. This is because such a change
1407 causes a shift in the location of the DMA buffers and a reduction
1408 in the number of available buffers.
1409
1410 Note that a similar but essentially insoluble problem exists for
1411 externally-driven rate changes. All we can do is to flag rate
1412 changes in the read/write routines.
1413 */
1414
1415 if (current_rate <= 48000)
1416 current_speed = HDSPM_SPEED_SINGLE;
1417 else if (current_rate <= 96000)
1418 current_speed = HDSPM_SPEED_DOUBLE;
1419 else
1420 current_speed = HDSPM_SPEED_QUAD;
1421
1422 if (rate <= 48000)
1423 target_speed = HDSPM_SPEED_SINGLE;
1424 else if (rate <= 96000)
1425 target_speed = HDSPM_SPEED_DOUBLE;
1426 else
1427 target_speed = HDSPM_SPEED_QUAD;
1428
1429 switch (rate) {
1430 case 32000:
1431 rate_bits = HDSPM_Frequency32KHz;
1432 break;
1433 case 44100:
1434 rate_bits = HDSPM_Frequency44_1KHz;
1435 break;
1436 case 48000:
1437 rate_bits = HDSPM_Frequency48KHz;
1438 break;
1439 case 64000:
1440 rate_bits = HDSPM_Frequency64KHz;
1441 break;
1442 case 88200:
1443 rate_bits = HDSPM_Frequency88_2KHz;
1444 break;
1445 case 96000:
1446 rate_bits = HDSPM_Frequency96KHz;
1447 break;
1448 case 128000:
1449 rate_bits = HDSPM_Frequency128KHz;
1450 break;
1451 case 176400:
1452 rate_bits = HDSPM_Frequency176_4KHz;
1453 break;
1454 case 192000:
1455 rate_bits = HDSPM_Frequency192KHz;
1456 break;
1457 default:
1458 return -EINVAL;
1459 }
1460
1461 if (current_speed != target_speed
1462 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1463 snd_printk
1464 (KERN_ERR "HDSPM: "
1465 "cannot change from %s speed to %s speed mode "
1466 "(capture PID = %d, playback PID = %d)\n",
1467 hdspm_speed_names[current_speed],
1468 hdspm_speed_names[target_speed],
1469 hdspm->capture_pid, hdspm->playback_pid);
1470 return -EBUSY;
1471 }
1472
1473 hdspm->control_register &= ~HDSPM_FrequencyMask;
1474 hdspm->control_register |= rate_bits;
1475 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1476
1477 /* For AES32, need to set DDS value in FREQ register
1478 For MADI, also apparently */
1479 hdspm_set_dds_value(hdspm, rate);
1480
1481 if (AES32 == hdspm->io_type && rate != current_rate)
1482 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1483
1484 hdspm->system_sample_rate = rate;
1485
1486 if (rate <= 48000) {
1487 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1488 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1489 hdspm->max_channels_in = hdspm->ss_in_channels;
1490 hdspm->max_channels_out = hdspm->ss_out_channels;
1491 hdspm->port_names_in = hdspm->port_names_in_ss;
1492 hdspm->port_names_out = hdspm->port_names_out_ss;
1493 } else if (rate <= 96000) {
1494 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1495 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1496 hdspm->max_channels_in = hdspm->ds_in_channels;
1497 hdspm->max_channels_out = hdspm->ds_out_channels;
1498 hdspm->port_names_in = hdspm->port_names_in_ds;
1499 hdspm->port_names_out = hdspm->port_names_out_ds;
1500 } else {
1501 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1502 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1503 hdspm->max_channels_in = hdspm->qs_in_channels;
1504 hdspm->max_channels_out = hdspm->qs_out_channels;
1505 hdspm->port_names_in = hdspm->port_names_in_qs;
1506 hdspm->port_names_out = hdspm->port_names_out_qs;
1507 }
1508
1509 if (not_set != 0)
1510 return -1;
1511
1512 return 0;
1513 }
1514
1515 /* mainly for init to 0 on load */
1516 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1517 {
1518 int i, j;
1519 unsigned int gain;
1520
1521 if (sgain > UNITY_GAIN)
1522 gain = UNITY_GAIN;
1523 else if (sgain < 0)
1524 gain = 0;
1525 else
1526 gain = sgain;
1527
1528 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1529 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1530 hdspm_write_in_gain(hdspm, i, j, gain);
1531 hdspm_write_pb_gain(hdspm, i, j, gain);
1532 }
1533 }
1534
1535 /*----------------------------------------------------------------------------
1536 MIDI
1537 ----------------------------------------------------------------------------*/
1538
1539 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1540 int id)
1541 {
1542 /* the hardware already does the relevant bit-mask with 0xff */
1543 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1544 }
1545
1546 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1547 int val)
1548 {
1549 /* the hardware already does the relevant bit-mask with 0xff */
1550 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1551 }
1552
1553 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1554 {
1555 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1556 }
1557
1558 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1559 {
1560 int fifo_bytes_used;
1561
1562 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1563
1564 if (fifo_bytes_used < 128)
1565 return 128 - fifo_bytes_used;
1566 else
1567 return 0;
1568 }
1569
1570 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1571 {
1572 while (snd_hdspm_midi_input_available (hdspm, id))
1573 snd_hdspm_midi_read_byte (hdspm, id);
1574 }
1575
1576 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1577 {
1578 unsigned long flags;
1579 int n_pending;
1580 int to_write;
1581 int i;
1582 unsigned char buf[128];
1583
1584 /* Output is not interrupt driven */
1585
1586 spin_lock_irqsave (&hmidi->lock, flags);
1587 if (hmidi->output &&
1588 !snd_rawmidi_transmit_empty (hmidi->output)) {
1589 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1590 hmidi->id);
1591 if (n_pending > 0) {
1592 if (n_pending > (int)sizeof (buf))
1593 n_pending = sizeof (buf);
1594
1595 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1596 n_pending);
1597 if (to_write > 0) {
1598 for (i = 0; i < to_write; ++i)
1599 snd_hdspm_midi_write_byte (hmidi->hdspm,
1600 hmidi->id,
1601 buf[i]);
1602 }
1603 }
1604 }
1605 spin_unlock_irqrestore (&hmidi->lock, flags);
1606 return 0;
1607 }
1608
1609 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1610 {
1611 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1612 * input FIFO size
1613 */
1614 unsigned long flags;
1615 int n_pending;
1616 int i;
1617
1618 spin_lock_irqsave (&hmidi->lock, flags);
1619 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1620 if (n_pending > 0) {
1621 if (hmidi->input) {
1622 if (n_pending > (int)sizeof (buf))
1623 n_pending = sizeof (buf);
1624 for (i = 0; i < n_pending; ++i)
1625 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1626 hmidi->id);
1627 if (n_pending)
1628 snd_rawmidi_receive (hmidi->input, buf,
1629 n_pending);
1630 } else {
1631 /* flush the MIDI input FIFO */
1632 while (n_pending--)
1633 snd_hdspm_midi_read_byte (hmidi->hdspm,
1634 hmidi->id);
1635 }
1636 }
1637 hmidi->pending = 0;
1638
1639 hmidi->hdspm->control_register |= hmidi->ie;
1640 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1641 hmidi->hdspm->control_register);
1642
1643 spin_unlock_irqrestore (&hmidi->lock, flags);
1644 return snd_hdspm_midi_output_write (hmidi);
1645 }
1646
1647 static void
1648 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1649 {
1650 struct hdspm *hdspm;
1651 struct hdspm_midi *hmidi;
1652 unsigned long flags;
1653
1654 hmidi = substream->rmidi->private_data;
1655 hdspm = hmidi->hdspm;
1656
1657 spin_lock_irqsave (&hdspm->lock, flags);
1658 if (up) {
1659 if (!(hdspm->control_register & hmidi->ie)) {
1660 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1661 hdspm->control_register |= hmidi->ie;
1662 }
1663 } else {
1664 hdspm->control_register &= ~hmidi->ie;
1665 }
1666
1667 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1668 spin_unlock_irqrestore (&hdspm->lock, flags);
1669 }
1670
1671 static void snd_hdspm_midi_output_timer(unsigned long data)
1672 {
1673 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1674 unsigned long flags;
1675
1676 snd_hdspm_midi_output_write(hmidi);
1677 spin_lock_irqsave (&hmidi->lock, flags);
1678
1679 /* this does not bump hmidi->istimer, because the
1680 kernel automatically removed the timer when it
1681 expired, and we are now adding it back, thus
1682 leaving istimer wherever it was set before.
1683 */
1684
1685 if (hmidi->istimer) {
1686 hmidi->timer.expires = 1 + jiffies;
1687 add_timer(&hmidi->timer);
1688 }
1689
1690 spin_unlock_irqrestore (&hmidi->lock, flags);
1691 }
1692
1693 static void
1694 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1695 {
1696 struct hdspm_midi *hmidi;
1697 unsigned long flags;
1698
1699 hmidi = substream->rmidi->private_data;
1700 spin_lock_irqsave (&hmidi->lock, flags);
1701 if (up) {
1702 if (!hmidi->istimer) {
1703 init_timer(&hmidi->timer);
1704 hmidi->timer.function = snd_hdspm_midi_output_timer;
1705 hmidi->timer.data = (unsigned long) hmidi;
1706 hmidi->timer.expires = 1 + jiffies;
1707 add_timer(&hmidi->timer);
1708 hmidi->istimer++;
1709 }
1710 } else {
1711 if (hmidi->istimer && --hmidi->istimer <= 0)
1712 del_timer (&hmidi->timer);
1713 }
1714 spin_unlock_irqrestore (&hmidi->lock, flags);
1715 if (up)
1716 snd_hdspm_midi_output_write(hmidi);
1717 }
1718
1719 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1720 {
1721 struct hdspm_midi *hmidi;
1722
1723 hmidi = substream->rmidi->private_data;
1724 spin_lock_irq (&hmidi->lock);
1725 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1726 hmidi->input = substream;
1727 spin_unlock_irq (&hmidi->lock);
1728
1729 return 0;
1730 }
1731
1732 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1733 {
1734 struct hdspm_midi *hmidi;
1735
1736 hmidi = substream->rmidi->private_data;
1737 spin_lock_irq (&hmidi->lock);
1738 hmidi->output = substream;
1739 spin_unlock_irq (&hmidi->lock);
1740
1741 return 0;
1742 }
1743
1744 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1745 {
1746 struct hdspm_midi *hmidi;
1747
1748 snd_hdspm_midi_input_trigger (substream, 0);
1749
1750 hmidi = substream->rmidi->private_data;
1751 spin_lock_irq (&hmidi->lock);
1752 hmidi->input = NULL;
1753 spin_unlock_irq (&hmidi->lock);
1754
1755 return 0;
1756 }
1757
1758 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1759 {
1760 struct hdspm_midi *hmidi;
1761
1762 snd_hdspm_midi_output_trigger (substream, 0);
1763
1764 hmidi = substream->rmidi->private_data;
1765 spin_lock_irq (&hmidi->lock);
1766 hmidi->output = NULL;
1767 spin_unlock_irq (&hmidi->lock);
1768
1769 return 0;
1770 }
1771
1772 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1773 {
1774 .open = snd_hdspm_midi_output_open,
1775 .close = snd_hdspm_midi_output_close,
1776 .trigger = snd_hdspm_midi_output_trigger,
1777 };
1778
1779 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1780 {
1781 .open = snd_hdspm_midi_input_open,
1782 .close = snd_hdspm_midi_input_close,
1783 .trigger = snd_hdspm_midi_input_trigger,
1784 };
1785
1786 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1787 struct hdspm *hdspm, int id)
1788 {
1789 int err;
1790 char buf[32];
1791
1792 hdspm->midi[id].id = id;
1793 hdspm->midi[id].hdspm = hdspm;
1794 spin_lock_init (&hdspm->midi[id].lock);
1795
1796 if (0 == id) {
1797 if (MADIface == hdspm->io_type) {
1798 /* MIDI-over-MADI on HDSPe MADIface */
1799 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1800 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1801 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1802 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1803 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1804 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1805 } else {
1806 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1807 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1808 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1809 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1810 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1811 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1812 }
1813 } else if (1 == id) {
1814 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1815 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1816 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1817 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1818 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1819 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1820 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1821 /* MIDI-over-MADI on HDSPe MADI */
1822 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1823 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1824 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1825 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1826 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1827 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1828 } else if (2 == id) {
1829 /* TCO MTC, read only */
1830 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1831 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1832 hdspm->midi[2].dataOut = -1;
1833 hdspm->midi[2].statusOut = -1;
1834 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1835 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1836 } else if (3 == id) {
1837 /* TCO MTC on HDSPe MADI */
1838 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1839 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1840 hdspm->midi[3].dataOut = -1;
1841 hdspm->midi[3].statusOut = -1;
1842 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1843 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1844 }
1845
1846 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1847 (MADIface == hdspm->io_type)))) {
1848 if ((id == 0) && (MADIface == hdspm->io_type)) {
1849 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1850 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1851 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1852 } else {
1853 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1854 }
1855 err = snd_rawmidi_new(card, buf, id, 1, 1,
1856 &hdspm->midi[id].rmidi);
1857 if (err < 0)
1858 return err;
1859
1860 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1861 card->id, id+1);
1862 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1863
1864 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1865 SNDRV_RAWMIDI_STREAM_OUTPUT,
1866 &snd_hdspm_midi_output);
1867 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1868 SNDRV_RAWMIDI_STREAM_INPUT,
1869 &snd_hdspm_midi_input);
1870
1871 hdspm->midi[id].rmidi->info_flags |=
1872 SNDRV_RAWMIDI_INFO_OUTPUT |
1873 SNDRV_RAWMIDI_INFO_INPUT |
1874 SNDRV_RAWMIDI_INFO_DUPLEX;
1875 } else {
1876 /* TCO MTC, read only */
1877 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1878 err = snd_rawmidi_new(card, buf, id, 1, 1,
1879 &hdspm->midi[id].rmidi);
1880 if (err < 0)
1881 return err;
1882
1883 sprintf(hdspm->midi[id].rmidi->name,
1884 "%s MTC %d", card->id, id+1);
1885 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1886
1887 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1888 SNDRV_RAWMIDI_STREAM_INPUT,
1889 &snd_hdspm_midi_input);
1890
1891 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1892 }
1893
1894 return 0;
1895 }
1896
1897
1898 static void hdspm_midi_tasklet(unsigned long arg)
1899 {
1900 struct hdspm *hdspm = (struct hdspm *)arg;
1901 int i = 0;
1902
1903 while (i < hdspm->midiPorts) {
1904 if (hdspm->midi[i].pending)
1905 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1906
1907 i++;
1908 }
1909 }
1910
1911
1912 /*-----------------------------------------------------------------------------
1913 Status Interface
1914 ----------------------------------------------------------------------------*/
1915
1916 /* get the system sample rate which is set */
1917
1918
1919 /**
1920 * Calculate the real sample rate from the
1921 * current DDS value.
1922 **/
1923 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1924 {
1925 unsigned int period, rate;
1926
1927 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1928 rate = hdspm_calc_dds_value(hdspm, period);
1929
1930 return rate;
1931 }
1932
1933
1934 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1935 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1936 .name = xname, \
1937 .index = xindex, \
1938 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1939 .info = snd_hdspm_info_system_sample_rate, \
1940 .get = snd_hdspm_get_system_sample_rate \
1941 }
1942
1943 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1944 struct snd_ctl_elem_info *uinfo)
1945 {
1946 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1947 uinfo->count = 1;
1948 uinfo->value.integer.min = 27000;
1949 uinfo->value.integer.max = 207000;
1950 uinfo->value.integer.step = 1;
1951 return 0;
1952 }
1953
1954
1955 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1956 struct snd_ctl_elem_value *
1957 ucontrol)
1958 {
1959 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1960
1961 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1962 return 0;
1963 }
1964
1965
1966 /**
1967 * Returns the WordClock sample rate class for the given card.
1968 **/
1969 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1970 {
1971 int status;
1972
1973 switch (hdspm->io_type) {
1974 case RayDAT:
1975 case AIO:
1976 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1977 return (status >> 16) & 0xF;
1978 break;
1979 default:
1980 break;
1981 }
1982
1983
1984 return 0;
1985 }
1986
1987
1988 /**
1989 * Returns the TCO sample rate class for the given card.
1990 **/
1991 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
1992 {
1993 int status;
1994
1995 if (hdspm->tco) {
1996 switch (hdspm->io_type) {
1997 case RayDAT:
1998 case AIO:
1999 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2000 return (status >> 20) & 0xF;
2001 break;
2002 default:
2003 break;
2004 }
2005 }
2006
2007 return 0;
2008 }
2009
2010
2011 /**
2012 * Returns the SYNC_IN sample rate class for the given card.
2013 **/
2014 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2015 {
2016 int status;
2017
2018 if (hdspm->tco) {
2019 switch (hdspm->io_type) {
2020 case RayDAT:
2021 case AIO:
2022 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2023 return (status >> 12) & 0xF;
2024 break;
2025 default:
2026 break;
2027 }
2028 }
2029
2030 return 0;
2031 }
2032
2033
2034 /**
2035 * Returns the sample rate class for input source <idx> for
2036 * 'new style' cards like the AIO and RayDAT.
2037 **/
2038 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2039 {
2040 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2041
2042 return (status >> (idx*4)) & 0xF;
2043 }
2044
2045
2046
2047 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2048 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2049 .name = xname, \
2050 .private_value = xindex, \
2051 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2052 .info = snd_hdspm_info_autosync_sample_rate, \
2053 .get = snd_hdspm_get_autosync_sample_rate \
2054 }
2055
2056
2057 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2058 struct snd_ctl_elem_info *uinfo)
2059 {
2060 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2061 uinfo->count = 1;
2062 uinfo->value.enumerated.items = 10;
2063
2064 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2065 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2066 strcpy(uinfo->value.enumerated.name,
2067 texts_freq[uinfo->value.enumerated.item]);
2068 return 0;
2069 }
2070
2071
2072 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2073 struct snd_ctl_elem_value *
2074 ucontrol)
2075 {
2076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2077
2078 switch (hdspm->io_type) {
2079 case RayDAT:
2080 switch (kcontrol->private_value) {
2081 case 0:
2082 ucontrol->value.enumerated.item[0] =
2083 hdspm_get_wc_sample_rate(hdspm);
2084 break;
2085 case 7:
2086 ucontrol->value.enumerated.item[0] =
2087 hdspm_get_tco_sample_rate(hdspm);
2088 break;
2089 case 8:
2090 ucontrol->value.enumerated.item[0] =
2091 hdspm_get_sync_in_sample_rate(hdspm);
2092 break;
2093 default:
2094 ucontrol->value.enumerated.item[0] =
2095 hdspm_get_s1_sample_rate(hdspm,
2096 kcontrol->private_value-1);
2097 }
2098
2099 case AIO:
2100 switch (kcontrol->private_value) {
2101 case 0: /* WC */
2102 ucontrol->value.enumerated.item[0] =
2103 hdspm_get_wc_sample_rate(hdspm);
2104 break;
2105 case 4: /* TCO */
2106 ucontrol->value.enumerated.item[0] =
2107 hdspm_get_tco_sample_rate(hdspm);
2108 break;
2109 case 5: /* SYNC_IN */
2110 ucontrol->value.enumerated.item[0] =
2111 hdspm_get_sync_in_sample_rate(hdspm);
2112 break;
2113 default:
2114 ucontrol->value.enumerated.item[0] =
2115 hdspm_get_s1_sample_rate(hdspm,
2116 ucontrol->id.index-1);
2117 }
2118
2119 case AES32:
2120
2121 switch (kcontrol->private_value) {
2122 case 0: /* WC */
2123 ucontrol->value.enumerated.item[0] =
2124 hdspm_get_wc_sample_rate(hdspm);
2125 break;
2126 case 9: /* TCO */
2127 ucontrol->value.enumerated.item[0] =
2128 hdspm_get_tco_sample_rate(hdspm);
2129 break;
2130 case 10: /* SYNC_IN */
2131 ucontrol->value.enumerated.item[0] =
2132 hdspm_get_sync_in_sample_rate(hdspm);
2133 break;
2134 default: /* AES1 to AES8 */
2135 ucontrol->value.enumerated.item[0] =
2136 hdspm_get_s1_sample_rate(hdspm,
2137 kcontrol->private_value-1);
2138 break;
2139
2140 }
2141 default:
2142 break;
2143 }
2144
2145 return 0;
2146 }
2147
2148
2149 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2150 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2151 .name = xname, \
2152 .index = xindex, \
2153 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2154 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2155 .info = snd_hdspm_info_system_clock_mode, \
2156 .get = snd_hdspm_get_system_clock_mode, \
2157 .put = snd_hdspm_put_system_clock_mode, \
2158 }
2159
2160
2161 /**
2162 * Returns the system clock mode for the given card.
2163 * @returns 0 - master, 1 - slave
2164 **/
2165 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2166 {
2167 switch (hdspm->io_type) {
2168 case AIO:
2169 case RayDAT:
2170 if (hdspm->settings_register & HDSPM_c0Master)
2171 return 0;
2172 break;
2173
2174 default:
2175 if (hdspm->control_register & HDSPM_ClockModeMaster)
2176 return 0;
2177 }
2178
2179 return 1;
2180 }
2181
2182
2183 /**
2184 * Sets the system clock mode.
2185 * @param mode 0 - master, 1 - slave
2186 **/
2187 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2188 {
2189 switch (hdspm->io_type) {
2190 case AIO:
2191 case RayDAT:
2192 if (0 == mode)
2193 hdspm->settings_register |= HDSPM_c0Master;
2194 else
2195 hdspm->settings_register &= ~HDSPM_c0Master;
2196
2197 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2198 break;
2199
2200 default:
2201 if (0 == mode)
2202 hdspm->control_register |= HDSPM_ClockModeMaster;
2203 else
2204 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2205
2206 hdspm_write(hdspm, HDSPM_controlRegister,
2207 hdspm->control_register);
2208 }
2209 }
2210
2211
2212 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2213 struct snd_ctl_elem_info *uinfo)
2214 {
2215 static char *texts[] = { "Master", "AutoSync" };
2216
2217 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2218 uinfo->count = 1;
2219 uinfo->value.enumerated.items = 2;
2220 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2221 uinfo->value.enumerated.item =
2222 uinfo->value.enumerated.items - 1;
2223 strcpy(uinfo->value.enumerated.name,
2224 texts[uinfo->value.enumerated.item]);
2225 return 0;
2226 }
2227
2228 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2229 struct snd_ctl_elem_value *ucontrol)
2230 {
2231 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2232
2233 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2234 return 0;
2235 }
2236
2237 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2238 struct snd_ctl_elem_value *ucontrol)
2239 {
2240 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2241 int val;
2242
2243 if (!snd_hdspm_use_is_exclusive(hdspm))
2244 return -EBUSY;
2245
2246 val = ucontrol->value.enumerated.item[0];
2247 if (val < 0)
2248 val = 0;
2249 else if (val > 1)
2250 val = 1;
2251
2252 hdspm_set_system_clock_mode(hdspm, val);
2253
2254 return 0;
2255 }
2256
2257
2258 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2259 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2260 .name = xname, \
2261 .index = xindex, \
2262 .info = snd_hdspm_info_clock_source, \
2263 .get = snd_hdspm_get_clock_source, \
2264 .put = snd_hdspm_put_clock_source \
2265 }
2266
2267
2268 static int hdspm_clock_source(struct hdspm * hdspm)
2269 {
2270 switch (hdspm->system_sample_rate) {
2271 case 32000: return 0;
2272 case 44100: return 1;
2273 case 48000: return 2;
2274 case 64000: return 3;
2275 case 88200: return 4;
2276 case 96000: return 5;
2277 case 128000: return 6;
2278 case 176400: return 7;
2279 case 192000: return 8;
2280 }
2281
2282 return -1;
2283 }
2284
2285 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2286 {
2287 int rate;
2288 switch (mode) {
2289 case 0:
2290 rate = 32000; break;
2291 case 1:
2292 rate = 44100; break;
2293 case 2:
2294 rate = 48000; break;
2295 case 3:
2296 rate = 64000; break;
2297 case 4:
2298 rate = 88200; break;
2299 case 5:
2300 rate = 96000; break;
2301 case 6:
2302 rate = 128000; break;
2303 case 7:
2304 rate = 176400; break;
2305 case 8:
2306 rate = 192000; break;
2307 default:
2308 rate = 48000;
2309 }
2310 hdspm_set_rate(hdspm, rate, 1);
2311 return 0;
2312 }
2313
2314 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2315 struct snd_ctl_elem_info *uinfo)
2316 {
2317 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2318 uinfo->count = 1;
2319 uinfo->value.enumerated.items = 9;
2320
2321 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2322 uinfo->value.enumerated.item =
2323 uinfo->value.enumerated.items - 1;
2324
2325 strcpy(uinfo->value.enumerated.name,
2326 texts_freq[uinfo->value.enumerated.item+1]);
2327
2328 return 0;
2329 }
2330
2331 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2332 struct snd_ctl_elem_value *ucontrol)
2333 {
2334 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2335
2336 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2337 return 0;
2338 }
2339
2340 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2341 struct snd_ctl_elem_value *ucontrol)
2342 {
2343 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2344 int change;
2345 int val;
2346
2347 if (!snd_hdspm_use_is_exclusive(hdspm))
2348 return -EBUSY;
2349 val = ucontrol->value.enumerated.item[0];
2350 if (val < 0)
2351 val = 0;
2352 if (val > 9)
2353 val = 9;
2354 spin_lock_irq(&hdspm->lock);
2355 if (val != hdspm_clock_source(hdspm))
2356 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2357 else
2358 change = 0;
2359 spin_unlock_irq(&hdspm->lock);
2360 return change;
2361 }
2362
2363
2364 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2365 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2366 .name = xname, \
2367 .index = xindex, \
2368 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2369 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2370 .info = snd_hdspm_info_pref_sync_ref, \
2371 .get = snd_hdspm_get_pref_sync_ref, \
2372 .put = snd_hdspm_put_pref_sync_ref \
2373 }
2374
2375
2376 /**
2377 * Returns the current preferred sync reference setting.
2378 * The semantics of the return value are depending on the
2379 * card, please see the comments for clarification.
2380 **/
2381 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2382 {
2383 switch (hdspm->io_type) {
2384 case AES32:
2385 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2386 case 0: return 0; /* WC */
2387 case HDSPM_SyncRef0: return 1; /* AES 1 */
2388 case HDSPM_SyncRef1: return 2; /* AES 2 */
2389 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2390 case HDSPM_SyncRef2: return 4; /* AES 4 */
2391 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2392 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2393 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2394 return 7; /* AES 7 */
2395 case HDSPM_SyncRef3: return 8; /* AES 8 */
2396 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2397 }
2398 break;
2399
2400 case MADI:
2401 case MADIface:
2402 if (hdspm->tco) {
2403 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2404 case 0: return 0; /* WC */
2405 case HDSPM_SyncRef0: return 1; /* MADI */
2406 case HDSPM_SyncRef1: return 2; /* TCO */
2407 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2408 return 3; /* SYNC_IN */
2409 }
2410 } else {
2411 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2412 case 0: return 0; /* WC */
2413 case HDSPM_SyncRef0: return 1; /* MADI */
2414 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2415 return 2; /* SYNC_IN */
2416 }
2417 }
2418 break;
2419
2420 case RayDAT:
2421 if (hdspm->tco) {
2422 switch ((hdspm->settings_register &
2423 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2424 case 0: return 0; /* WC */
2425 case 3: return 1; /* ADAT 1 */
2426 case 4: return 2; /* ADAT 2 */
2427 case 5: return 3; /* ADAT 3 */
2428 case 6: return 4; /* ADAT 4 */
2429 case 1: return 5; /* AES */
2430 case 2: return 6; /* SPDIF */
2431 case 9: return 7; /* TCO */
2432 case 10: return 8; /* SYNC_IN */
2433 }
2434 } else {
2435 switch ((hdspm->settings_register &
2436 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2437 case 0: return 0; /* WC */
2438 case 3: return 1; /* ADAT 1 */
2439 case 4: return 2; /* ADAT 2 */
2440 case 5: return 3; /* ADAT 3 */
2441 case 6: return 4; /* ADAT 4 */
2442 case 1: return 5; /* AES */
2443 case 2: return 6; /* SPDIF */
2444 case 10: return 7; /* SYNC_IN */
2445 }
2446 }
2447
2448 break;
2449
2450 case AIO:
2451 if (hdspm->tco) {
2452 switch ((hdspm->settings_register &
2453 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2454 case 0: return 0; /* WC */
2455 case 3: return 1; /* ADAT */
2456 case 1: return 2; /* AES */
2457 case 2: return 3; /* SPDIF */
2458 case 9: return 4; /* TCO */
2459 case 10: return 5; /* SYNC_IN */
2460 }
2461 } else {
2462 switch ((hdspm->settings_register &
2463 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2464 case 0: return 0; /* WC */
2465 case 3: return 1; /* ADAT */
2466 case 1: return 2; /* AES */
2467 case 2: return 3; /* SPDIF */
2468 case 10: return 4; /* SYNC_IN */
2469 }
2470 }
2471
2472 break;
2473 }
2474
2475 return -1;
2476 }
2477
2478
2479 /**
2480 * Set the preferred sync reference to <pref>. The semantics
2481 * of <pref> are depending on the card type, see the comments
2482 * for clarification.
2483 **/
2484 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2485 {
2486 int p = 0;
2487
2488 switch (hdspm->io_type) {
2489 case AES32:
2490 hdspm->control_register &= ~HDSPM_SyncRefMask;
2491 switch (pref) {
2492 case 0: /* WC */
2493 break;
2494 case 1: /* AES 1 */
2495 hdspm->control_register |= HDSPM_SyncRef0;
2496 break;
2497 case 2: /* AES 2 */
2498 hdspm->control_register |= HDSPM_SyncRef1;
2499 break;
2500 case 3: /* AES 3 */
2501 hdspm->control_register |=
2502 HDSPM_SyncRef1+HDSPM_SyncRef0;
2503 break;
2504 case 4: /* AES 4 */
2505 hdspm->control_register |= HDSPM_SyncRef2;
2506 break;
2507 case 5: /* AES 5 */
2508 hdspm->control_register |=
2509 HDSPM_SyncRef2+HDSPM_SyncRef0;
2510 break;
2511 case 6: /* AES 6 */
2512 hdspm->control_register |=
2513 HDSPM_SyncRef2+HDSPM_SyncRef1;
2514 break;
2515 case 7: /* AES 7 */
2516 hdspm->control_register |=
2517 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2518 break;
2519 case 8: /* AES 8 */
2520 hdspm->control_register |= HDSPM_SyncRef3;
2521 break;
2522 case 9: /* TCO */
2523 hdspm->control_register |=
2524 HDSPM_SyncRef3+HDSPM_SyncRef0;
2525 break;
2526 default:
2527 return -1;
2528 }
2529
2530 break;
2531
2532 case MADI:
2533 case MADIface:
2534 hdspm->control_register &= ~HDSPM_SyncRefMask;
2535 if (hdspm->tco) {
2536 switch (pref) {
2537 case 0: /* WC */
2538 break;
2539 case 1: /* MADI */
2540 hdspm->control_register |= HDSPM_SyncRef0;
2541 break;
2542 case 2: /* TCO */
2543 hdspm->control_register |= HDSPM_SyncRef1;
2544 break;
2545 case 3: /* SYNC_IN */
2546 hdspm->control_register |=
2547 HDSPM_SyncRef0+HDSPM_SyncRef1;
2548 break;
2549 default:
2550 return -1;
2551 }
2552 } else {
2553 switch (pref) {
2554 case 0: /* WC */
2555 break;
2556 case 1: /* MADI */
2557 hdspm->control_register |= HDSPM_SyncRef0;
2558 break;
2559 case 2: /* SYNC_IN */
2560 hdspm->control_register |=
2561 HDSPM_SyncRef0+HDSPM_SyncRef1;
2562 break;
2563 default:
2564 return -1;
2565 }
2566 }
2567
2568 break;
2569
2570 case RayDAT:
2571 if (hdspm->tco) {
2572 switch (pref) {
2573 case 0: p = 0; break; /* WC */
2574 case 1: p = 3; break; /* ADAT 1 */
2575 case 2: p = 4; break; /* ADAT 2 */
2576 case 3: p = 5; break; /* ADAT 3 */
2577 case 4: p = 6; break; /* ADAT 4 */
2578 case 5: p = 1; break; /* AES */
2579 case 6: p = 2; break; /* SPDIF */
2580 case 7: p = 9; break; /* TCO */
2581 case 8: p = 10; break; /* SYNC_IN */
2582 default: return -1;
2583 }
2584 } else {
2585 switch (pref) {
2586 case 0: p = 0; break; /* WC */
2587 case 1: p = 3; break; /* ADAT 1 */
2588 case 2: p = 4; break; /* ADAT 2 */
2589 case 3: p = 5; break; /* ADAT 3 */
2590 case 4: p = 6; break; /* ADAT 4 */
2591 case 5: p = 1; break; /* AES */
2592 case 6: p = 2; break; /* SPDIF */
2593 case 7: p = 10; break; /* SYNC_IN */
2594 default: return -1;
2595 }
2596 }
2597 break;
2598
2599 case AIO:
2600 if (hdspm->tco) {
2601 switch (pref) {
2602 case 0: p = 0; break; /* WC */
2603 case 1: p = 3; break; /* ADAT */
2604 case 2: p = 1; break; /* AES */
2605 case 3: p = 2; break; /* SPDIF */
2606 case 4: p = 9; break; /* TCO */
2607 case 5: p = 10; break; /* SYNC_IN */
2608 default: return -1;
2609 }
2610 } else {
2611 switch (pref) {
2612 case 0: p = 0; break; /* WC */
2613 case 1: p = 3; break; /* ADAT */
2614 case 2: p = 1; break; /* AES */
2615 case 3: p = 2; break; /* SPDIF */
2616 case 4: p = 10; break; /* SYNC_IN */
2617 default: return -1;
2618 }
2619 }
2620 break;
2621 }
2622
2623 switch (hdspm->io_type) {
2624 case RayDAT:
2625 case AIO:
2626 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2627 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2628 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2629 break;
2630
2631 case MADI:
2632 case MADIface:
2633 case AES32:
2634 hdspm_write(hdspm, HDSPM_controlRegister,
2635 hdspm->control_register);
2636 }
2637
2638 return 0;
2639 }
2640
2641
2642 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2643 struct snd_ctl_elem_info *uinfo)
2644 {
2645 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2646
2647 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2648 uinfo->count = 1;
2649 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2650
2651 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2652 uinfo->value.enumerated.item =
2653 uinfo->value.enumerated.items - 1;
2654
2655 strcpy(uinfo->value.enumerated.name,
2656 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2657
2658 return 0;
2659 }
2660
2661 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2662 struct snd_ctl_elem_value *ucontrol)
2663 {
2664 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2665 int psf = hdspm_pref_sync_ref(hdspm);
2666
2667 if (psf >= 0) {
2668 ucontrol->value.enumerated.item[0] = psf;
2669 return 0;
2670 }
2671
2672 return -1;
2673 }
2674
2675 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2676 struct snd_ctl_elem_value *ucontrol)
2677 {
2678 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2679 int val, change = 0;
2680
2681 if (!snd_hdspm_use_is_exclusive(hdspm))
2682 return -EBUSY;
2683
2684 val = ucontrol->value.enumerated.item[0];
2685
2686 if (val < 0)
2687 val = 0;
2688 else if (val >= hdspm->texts_autosync_items)
2689 val = hdspm->texts_autosync_items-1;
2690
2691 spin_lock_irq(&hdspm->lock);
2692 if (val != hdspm_pref_sync_ref(hdspm))
2693 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2694
2695 spin_unlock_irq(&hdspm->lock);
2696 return change;
2697 }
2698
2699
2700 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2701 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2702 .name = xname, \
2703 .index = xindex, \
2704 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2705 .info = snd_hdspm_info_autosync_ref, \
2706 .get = snd_hdspm_get_autosync_ref, \
2707 }
2708
2709 static int hdspm_autosync_ref(struct hdspm *hdspm)
2710 {
2711 if (AES32 == hdspm->io_type) {
2712 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2713 unsigned int syncref =
2714 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2715 if (syncref == 0)
2716 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2717 if (syncref <= 8)
2718 return syncref;
2719 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2720 } else if (MADI == hdspm->io_type) {
2721 /* This looks at the autosync selected sync reference */
2722 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2723
2724 switch (status2 & HDSPM_SelSyncRefMask) {
2725 case HDSPM_SelSyncRef_WORD:
2726 return HDSPM_AUTOSYNC_FROM_WORD;
2727 case HDSPM_SelSyncRef_MADI:
2728 return HDSPM_AUTOSYNC_FROM_MADI;
2729 case HDSPM_SelSyncRef_TCO:
2730 return HDSPM_AUTOSYNC_FROM_TCO;
2731 case HDSPM_SelSyncRef_SyncIn:
2732 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2733 case HDSPM_SelSyncRef_NVALID:
2734 return HDSPM_AUTOSYNC_FROM_NONE;
2735 default:
2736 return 0;
2737 }
2738
2739 }
2740 return 0;
2741 }
2742
2743
2744 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2745 struct snd_ctl_elem_info *uinfo)
2746 {
2747 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2748
2749 if (AES32 == hdspm->io_type) {
2750 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2751 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2752
2753 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2754 uinfo->count = 1;
2755 uinfo->value.enumerated.items = 10;
2756 if (uinfo->value.enumerated.item >=
2757 uinfo->value.enumerated.items)
2758 uinfo->value.enumerated.item =
2759 uinfo->value.enumerated.items - 1;
2760 strcpy(uinfo->value.enumerated.name,
2761 texts[uinfo->value.enumerated.item]);
2762 } else if (MADI == hdspm->io_type) {
2763 static char *texts[] = {"Word Clock", "MADI", "TCO",
2764 "Sync In", "None" };
2765
2766 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2767 uinfo->count = 1;
2768 uinfo->value.enumerated.items = 5;
2769 if (uinfo->value.enumerated.item >=
2770 uinfo->value.enumerated.items)
2771 uinfo->value.enumerated.item =
2772 uinfo->value.enumerated.items - 1;
2773 strcpy(uinfo->value.enumerated.name,
2774 texts[uinfo->value.enumerated.item]);
2775 }
2776 return 0;
2777 }
2778
2779 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2780 struct snd_ctl_elem_value *ucontrol)
2781 {
2782 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2783
2784 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2785 return 0;
2786 }
2787
2788
2789 #define HDSPM_LINE_OUT(xname, xindex) \
2790 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2791 .name = xname, \
2792 .index = xindex, \
2793 .info = snd_hdspm_info_line_out, \
2794 .get = snd_hdspm_get_line_out, \
2795 .put = snd_hdspm_put_line_out \
2796 }
2797
2798 static int hdspm_line_out(struct hdspm * hdspm)
2799 {
2800 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2801 }
2802
2803
2804 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2805 {
2806 if (out)
2807 hdspm->control_register |= HDSPM_LineOut;
2808 else
2809 hdspm->control_register &= ~HDSPM_LineOut;
2810 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2811
2812 return 0;
2813 }
2814
2815 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2816
2817 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2818 struct snd_ctl_elem_value *ucontrol)
2819 {
2820 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2821
2822 spin_lock_irq(&hdspm->lock);
2823 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2824 spin_unlock_irq(&hdspm->lock);
2825 return 0;
2826 }
2827
2828 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2829 struct snd_ctl_elem_value *ucontrol)
2830 {
2831 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2832 int change;
2833 unsigned int val;
2834
2835 if (!snd_hdspm_use_is_exclusive(hdspm))
2836 return -EBUSY;
2837 val = ucontrol->value.integer.value[0] & 1;
2838 spin_lock_irq(&hdspm->lock);
2839 change = (int) val != hdspm_line_out(hdspm);
2840 hdspm_set_line_output(hdspm, val);
2841 spin_unlock_irq(&hdspm->lock);
2842 return change;
2843 }
2844
2845
2846 #define HDSPM_TX_64(xname, xindex) \
2847 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2848 .name = xname, \
2849 .index = xindex, \
2850 .info = snd_hdspm_info_tx_64, \
2851 .get = snd_hdspm_get_tx_64, \
2852 .put = snd_hdspm_put_tx_64 \
2853 }
2854
2855 static int hdspm_tx_64(struct hdspm * hdspm)
2856 {
2857 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2858 }
2859
2860 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2861 {
2862 if (out)
2863 hdspm->control_register |= HDSPM_TX_64ch;
2864 else
2865 hdspm->control_register &= ~HDSPM_TX_64ch;
2866 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2867
2868 return 0;
2869 }
2870
2871 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2872
2873 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2874 struct snd_ctl_elem_value *ucontrol)
2875 {
2876 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2877
2878 spin_lock_irq(&hdspm->lock);
2879 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2880 spin_unlock_irq(&hdspm->lock);
2881 return 0;
2882 }
2883
2884 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2885 struct snd_ctl_elem_value *ucontrol)
2886 {
2887 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2888 int change;
2889 unsigned int val;
2890
2891 if (!snd_hdspm_use_is_exclusive(hdspm))
2892 return -EBUSY;
2893 val = ucontrol->value.integer.value[0] & 1;
2894 spin_lock_irq(&hdspm->lock);
2895 change = (int) val != hdspm_tx_64(hdspm);
2896 hdspm_set_tx_64(hdspm, val);
2897 spin_unlock_irq(&hdspm->lock);
2898 return change;
2899 }
2900
2901
2902 #define HDSPM_C_TMS(xname, xindex) \
2903 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2904 .name = xname, \
2905 .index = xindex, \
2906 .info = snd_hdspm_info_c_tms, \
2907 .get = snd_hdspm_get_c_tms, \
2908 .put = snd_hdspm_put_c_tms \
2909 }
2910
2911 static int hdspm_c_tms(struct hdspm * hdspm)
2912 {
2913 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2914 }
2915
2916 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2917 {
2918 if (out)
2919 hdspm->control_register |= HDSPM_clr_tms;
2920 else
2921 hdspm->control_register &= ~HDSPM_clr_tms;
2922 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2923
2924 return 0;
2925 }
2926
2927 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2928
2929 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2930 struct snd_ctl_elem_value *ucontrol)
2931 {
2932 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2933
2934 spin_lock_irq(&hdspm->lock);
2935 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2936 spin_unlock_irq(&hdspm->lock);
2937 return 0;
2938 }
2939
2940 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2941 struct snd_ctl_elem_value *ucontrol)
2942 {
2943 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2944 int change;
2945 unsigned int val;
2946
2947 if (!snd_hdspm_use_is_exclusive(hdspm))
2948 return -EBUSY;
2949 val = ucontrol->value.integer.value[0] & 1;
2950 spin_lock_irq(&hdspm->lock);
2951 change = (int) val != hdspm_c_tms(hdspm);
2952 hdspm_set_c_tms(hdspm, val);
2953 spin_unlock_irq(&hdspm->lock);
2954 return change;
2955 }
2956
2957
2958 #define HDSPM_SAFE_MODE(xname, xindex) \
2959 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2960 .name = xname, \
2961 .index = xindex, \
2962 .info = snd_hdspm_info_safe_mode, \
2963 .get = snd_hdspm_get_safe_mode, \
2964 .put = snd_hdspm_put_safe_mode \
2965 }
2966
2967 static int hdspm_safe_mode(struct hdspm * hdspm)
2968 {
2969 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2970 }
2971
2972 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2973 {
2974 if (out)
2975 hdspm->control_register |= HDSPM_AutoInp;
2976 else
2977 hdspm->control_register &= ~HDSPM_AutoInp;
2978 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2979
2980 return 0;
2981 }
2982
2983 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
2984
2985 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2986 struct snd_ctl_elem_value *ucontrol)
2987 {
2988 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2989
2990 spin_lock_irq(&hdspm->lock);
2991 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2992 spin_unlock_irq(&hdspm->lock);
2993 return 0;
2994 }
2995
2996 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
2997 struct snd_ctl_elem_value *ucontrol)
2998 {
2999 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3000 int change;
3001 unsigned int val;
3002
3003 if (!snd_hdspm_use_is_exclusive(hdspm))
3004 return -EBUSY;
3005 val = ucontrol->value.integer.value[0] & 1;
3006 spin_lock_irq(&hdspm->lock);
3007 change = (int) val != hdspm_safe_mode(hdspm);
3008 hdspm_set_safe_mode(hdspm, val);
3009 spin_unlock_irq(&hdspm->lock);
3010 return change;
3011 }
3012
3013
3014 #define HDSPM_EMPHASIS(xname, xindex) \
3015 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3016 .name = xname, \
3017 .index = xindex, \
3018 .info = snd_hdspm_info_emphasis, \
3019 .get = snd_hdspm_get_emphasis, \
3020 .put = snd_hdspm_put_emphasis \
3021 }
3022
3023 static int hdspm_emphasis(struct hdspm * hdspm)
3024 {
3025 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3026 }
3027
3028 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3029 {
3030 if (emp)
3031 hdspm->control_register |= HDSPM_Emphasis;
3032 else
3033 hdspm->control_register &= ~HDSPM_Emphasis;
3034 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3035
3036 return 0;
3037 }
3038
3039 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3040
3041 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3042 struct snd_ctl_elem_value *ucontrol)
3043 {
3044 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3045
3046 spin_lock_irq(&hdspm->lock);
3047 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3048 spin_unlock_irq(&hdspm->lock);
3049 return 0;
3050 }
3051
3052 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3053 struct snd_ctl_elem_value *ucontrol)
3054 {
3055 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3056 int change;
3057 unsigned int val;
3058
3059 if (!snd_hdspm_use_is_exclusive(hdspm))
3060 return -EBUSY;
3061 val = ucontrol->value.integer.value[0] & 1;
3062 spin_lock_irq(&hdspm->lock);
3063 change = (int) val != hdspm_emphasis(hdspm);
3064 hdspm_set_emphasis(hdspm, val);
3065 spin_unlock_irq(&hdspm->lock);
3066 return change;
3067 }
3068
3069
3070 #define HDSPM_DOLBY(xname, xindex) \
3071 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3072 .name = xname, \
3073 .index = xindex, \
3074 .info = snd_hdspm_info_dolby, \
3075 .get = snd_hdspm_get_dolby, \
3076 .put = snd_hdspm_put_dolby \
3077 }
3078
3079 static int hdspm_dolby(struct hdspm * hdspm)
3080 {
3081 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3082 }
3083
3084 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3085 {
3086 if (dol)
3087 hdspm->control_register |= HDSPM_Dolby;
3088 else
3089 hdspm->control_register &= ~HDSPM_Dolby;
3090 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3091
3092 return 0;
3093 }
3094
3095 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3096
3097 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3098 struct snd_ctl_elem_value *ucontrol)
3099 {
3100 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3101
3102 spin_lock_irq(&hdspm->lock);
3103 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3104 spin_unlock_irq(&hdspm->lock);
3105 return 0;
3106 }
3107
3108 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3109 struct snd_ctl_elem_value *ucontrol)
3110 {
3111 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3112 int change;
3113 unsigned int val;
3114
3115 if (!snd_hdspm_use_is_exclusive(hdspm))
3116 return -EBUSY;
3117 val = ucontrol->value.integer.value[0] & 1;
3118 spin_lock_irq(&hdspm->lock);
3119 change = (int) val != hdspm_dolby(hdspm);
3120 hdspm_set_dolby(hdspm, val);
3121 spin_unlock_irq(&hdspm->lock);
3122 return change;
3123 }
3124
3125
3126 #define HDSPM_PROFESSIONAL(xname, xindex) \
3127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3128 .name = xname, \
3129 .index = xindex, \
3130 .info = snd_hdspm_info_professional, \
3131 .get = snd_hdspm_get_professional, \
3132 .put = snd_hdspm_put_professional \
3133 }
3134
3135 static int hdspm_professional(struct hdspm * hdspm)
3136 {
3137 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3138 }
3139
3140 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3141 {
3142 if (dol)
3143 hdspm->control_register |= HDSPM_Professional;
3144 else
3145 hdspm->control_register &= ~HDSPM_Professional;
3146 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3147
3148 return 0;
3149 }
3150
3151 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3152
3153 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3154 struct snd_ctl_elem_value *ucontrol)
3155 {
3156 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3157
3158 spin_lock_irq(&hdspm->lock);
3159 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3160 spin_unlock_irq(&hdspm->lock);
3161 return 0;
3162 }
3163
3164 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3165 struct snd_ctl_elem_value *ucontrol)
3166 {
3167 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3168 int change;
3169 unsigned int val;
3170
3171 if (!snd_hdspm_use_is_exclusive(hdspm))
3172 return -EBUSY;
3173 val = ucontrol->value.integer.value[0] & 1;
3174 spin_lock_irq(&hdspm->lock);
3175 change = (int) val != hdspm_professional(hdspm);
3176 hdspm_set_professional(hdspm, val);
3177 spin_unlock_irq(&hdspm->lock);
3178 return change;
3179 }
3180
3181 #define HDSPM_INPUT_SELECT(xname, xindex) \
3182 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3183 .name = xname, \
3184 .index = xindex, \
3185 .info = snd_hdspm_info_input_select, \
3186 .get = snd_hdspm_get_input_select, \
3187 .put = snd_hdspm_put_input_select \
3188 }
3189
3190 static int hdspm_input_select(struct hdspm * hdspm)
3191 {
3192 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3193 }
3194
3195 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3196 {
3197 if (out)
3198 hdspm->control_register |= HDSPM_InputSelect0;
3199 else
3200 hdspm->control_register &= ~HDSPM_InputSelect0;
3201 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3202
3203 return 0;
3204 }
3205
3206 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3207 struct snd_ctl_elem_info *uinfo)
3208 {
3209 static char *texts[] = { "optical", "coaxial" };
3210
3211 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3212 uinfo->count = 1;
3213 uinfo->value.enumerated.items = 2;
3214
3215 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3216 uinfo->value.enumerated.item =
3217 uinfo->value.enumerated.items - 1;
3218 strcpy(uinfo->value.enumerated.name,
3219 texts[uinfo->value.enumerated.item]);
3220
3221 return 0;
3222 }
3223
3224 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3225 struct snd_ctl_elem_value *ucontrol)
3226 {
3227 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3228
3229 spin_lock_irq(&hdspm->lock);
3230 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3231 spin_unlock_irq(&hdspm->lock);
3232 return 0;
3233 }
3234
3235 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3236 struct snd_ctl_elem_value *ucontrol)
3237 {
3238 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3239 int change;
3240 unsigned int val;
3241
3242 if (!snd_hdspm_use_is_exclusive(hdspm))
3243 return -EBUSY;
3244 val = ucontrol->value.integer.value[0] & 1;
3245 spin_lock_irq(&hdspm->lock);
3246 change = (int) val != hdspm_input_select(hdspm);
3247 hdspm_set_input_select(hdspm, val);
3248 spin_unlock_irq(&hdspm->lock);
3249 return change;
3250 }
3251
3252
3253 #define HDSPM_DS_WIRE(xname, xindex) \
3254 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3255 .name = xname, \
3256 .index = xindex, \
3257 .info = snd_hdspm_info_ds_wire, \
3258 .get = snd_hdspm_get_ds_wire, \
3259 .put = snd_hdspm_put_ds_wire \
3260 }
3261
3262 static int hdspm_ds_wire(struct hdspm * hdspm)
3263 {
3264 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3265 }
3266
3267 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3268 {
3269 if (ds)
3270 hdspm->control_register |= HDSPM_DS_DoubleWire;
3271 else
3272 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3273 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3274
3275 return 0;
3276 }
3277
3278 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3279 struct snd_ctl_elem_info *uinfo)
3280 {
3281 static char *texts[] = { "Single", "Double" };
3282
3283 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3284 uinfo->count = 1;
3285 uinfo->value.enumerated.items = 2;
3286
3287 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3288 uinfo->value.enumerated.item =
3289 uinfo->value.enumerated.items - 1;
3290 strcpy(uinfo->value.enumerated.name,
3291 texts[uinfo->value.enumerated.item]);
3292
3293 return 0;
3294 }
3295
3296 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3297 struct snd_ctl_elem_value *ucontrol)
3298 {
3299 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3300
3301 spin_lock_irq(&hdspm->lock);
3302 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3303 spin_unlock_irq(&hdspm->lock);
3304 return 0;
3305 }
3306
3307 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3308 struct snd_ctl_elem_value *ucontrol)
3309 {
3310 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3311 int change;
3312 unsigned int val;
3313
3314 if (!snd_hdspm_use_is_exclusive(hdspm))
3315 return -EBUSY;
3316 val = ucontrol->value.integer.value[0] & 1;
3317 spin_lock_irq(&hdspm->lock);
3318 change = (int) val != hdspm_ds_wire(hdspm);
3319 hdspm_set_ds_wire(hdspm, val);
3320 spin_unlock_irq(&hdspm->lock);
3321 return change;
3322 }
3323
3324
3325 #define HDSPM_QS_WIRE(xname, xindex) \
3326 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3327 .name = xname, \
3328 .index = xindex, \
3329 .info = snd_hdspm_info_qs_wire, \
3330 .get = snd_hdspm_get_qs_wire, \
3331 .put = snd_hdspm_put_qs_wire \
3332 }
3333
3334 static int hdspm_qs_wire(struct hdspm * hdspm)
3335 {
3336 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3337 return 1;
3338 if (hdspm->control_register & HDSPM_QS_QuadWire)
3339 return 2;
3340 return 0;
3341 }
3342
3343 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3344 {
3345 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3346 switch (mode) {
3347 case 0:
3348 break;
3349 case 1:
3350 hdspm->control_register |= HDSPM_QS_DoubleWire;
3351 break;
3352 case 2:
3353 hdspm->control_register |= HDSPM_QS_QuadWire;
3354 break;
3355 }
3356 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3357
3358 return 0;
3359 }
3360
3361 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3362 struct snd_ctl_elem_info *uinfo)
3363 {
3364 static char *texts[] = { "Single", "Double", "Quad" };
3365
3366 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3367 uinfo->count = 1;
3368 uinfo->value.enumerated.items = 3;
3369
3370 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3371 uinfo->value.enumerated.item =
3372 uinfo->value.enumerated.items - 1;
3373 strcpy(uinfo->value.enumerated.name,
3374 texts[uinfo->value.enumerated.item]);
3375
3376 return 0;
3377 }
3378
3379 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3380 struct snd_ctl_elem_value *ucontrol)
3381 {
3382 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3383
3384 spin_lock_irq(&hdspm->lock);
3385 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3386 spin_unlock_irq(&hdspm->lock);
3387 return 0;
3388 }
3389
3390 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3391 struct snd_ctl_elem_value *ucontrol)
3392 {
3393 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3394 int change;
3395 int val;
3396
3397 if (!snd_hdspm_use_is_exclusive(hdspm))
3398 return -EBUSY;
3399 val = ucontrol->value.integer.value[0];
3400 if (val < 0)
3401 val = 0;
3402 if (val > 2)
3403 val = 2;
3404 spin_lock_irq(&hdspm->lock);
3405 change = val != hdspm_qs_wire(hdspm);
3406 hdspm_set_qs_wire(hdspm, val);
3407 spin_unlock_irq(&hdspm->lock);
3408 return change;
3409 }
3410
3411
3412 #define HDSPM_MIXER(xname, xindex) \
3413 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3414 .name = xname, \
3415 .index = xindex, \
3416 .device = 0, \
3417 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3418 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3419 .info = snd_hdspm_info_mixer, \
3420 .get = snd_hdspm_get_mixer, \
3421 .put = snd_hdspm_put_mixer \
3422 }
3423
3424 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3425 struct snd_ctl_elem_info *uinfo)
3426 {
3427 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3428 uinfo->count = 3;
3429 uinfo->value.integer.min = 0;
3430 uinfo->value.integer.max = 65535;
3431 uinfo->value.integer.step = 1;
3432 return 0;
3433 }
3434
3435 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3436 struct snd_ctl_elem_value *ucontrol)
3437 {
3438 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3439 int source;
3440 int destination;
3441
3442 source = ucontrol->value.integer.value[0];
3443 if (source < 0)
3444 source = 0;
3445 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3446 source = 2 * HDSPM_MAX_CHANNELS - 1;
3447
3448 destination = ucontrol->value.integer.value[1];
3449 if (destination < 0)
3450 destination = 0;
3451 else if (destination >= HDSPM_MAX_CHANNELS)
3452 destination = HDSPM_MAX_CHANNELS - 1;
3453
3454 spin_lock_irq(&hdspm->lock);
3455 if (source >= HDSPM_MAX_CHANNELS)
3456 ucontrol->value.integer.value[2] =
3457 hdspm_read_pb_gain(hdspm, destination,
3458 source - HDSPM_MAX_CHANNELS);
3459 else
3460 ucontrol->value.integer.value[2] =
3461 hdspm_read_in_gain(hdspm, destination, source);
3462
3463 spin_unlock_irq(&hdspm->lock);
3464
3465 return 0;
3466 }
3467
3468 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3469 struct snd_ctl_elem_value *ucontrol)
3470 {
3471 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3472 int change;
3473 int source;
3474 int destination;
3475 int gain;
3476
3477 if (!snd_hdspm_use_is_exclusive(hdspm))
3478 return -EBUSY;
3479
3480 source = ucontrol->value.integer.value[0];
3481 destination = ucontrol->value.integer.value[1];
3482
3483 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3484 return -1;
3485 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3486 return -1;
3487
3488 gain = ucontrol->value.integer.value[2];
3489
3490 spin_lock_irq(&hdspm->lock);
3491
3492 if (source >= HDSPM_MAX_CHANNELS)
3493 change = gain != hdspm_read_pb_gain(hdspm, destination,
3494 source -
3495 HDSPM_MAX_CHANNELS);
3496 else
3497 change = gain != hdspm_read_in_gain(hdspm, destination,
3498 source);
3499
3500 if (change) {
3501 if (source >= HDSPM_MAX_CHANNELS)
3502 hdspm_write_pb_gain(hdspm, destination,
3503 source - HDSPM_MAX_CHANNELS,
3504 gain);
3505 else
3506 hdspm_write_in_gain(hdspm, destination, source,
3507 gain);
3508 }
3509 spin_unlock_irq(&hdspm->lock);
3510
3511 return change;
3512 }
3513
3514 /* The simple mixer control(s) provide gain control for the
3515 basic 1:1 mappings of playback streams to output
3516 streams.
3517 */
3518
3519 #define HDSPM_PLAYBACK_MIXER \
3520 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3521 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3522 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3523 .info = snd_hdspm_info_playback_mixer, \
3524 .get = snd_hdspm_get_playback_mixer, \
3525 .put = snd_hdspm_put_playback_mixer \
3526 }
3527
3528 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3529 struct snd_ctl_elem_info *uinfo)
3530 {
3531 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3532 uinfo->count = 1;
3533 uinfo->value.integer.min = 0;
3534 uinfo->value.integer.max = 64;
3535 uinfo->value.integer.step = 1;
3536 return 0;
3537 }
3538
3539 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3540 struct snd_ctl_elem_value *ucontrol)
3541 {
3542 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3543 int channel;
3544
3545 channel = ucontrol->id.index - 1;
3546
3547 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3548 return -EINVAL;
3549
3550 spin_lock_irq(&hdspm->lock);
3551 ucontrol->value.integer.value[0] =
3552 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3553 spin_unlock_irq(&hdspm->lock);
3554
3555 return 0;
3556 }
3557
3558 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3559 struct snd_ctl_elem_value *ucontrol)
3560 {
3561 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3562 int change;
3563 int channel;
3564 int gain;
3565
3566 if (!snd_hdspm_use_is_exclusive(hdspm))
3567 return -EBUSY;
3568
3569 channel = ucontrol->id.index - 1;
3570
3571 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3572 return -EINVAL;
3573
3574 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3575
3576 spin_lock_irq(&hdspm->lock);
3577 change =
3578 gain != hdspm_read_pb_gain(hdspm, channel,
3579 channel);
3580 if (change)
3581 hdspm_write_pb_gain(hdspm, channel, channel,
3582 gain);
3583 spin_unlock_irq(&hdspm->lock);
3584 return change;
3585 }
3586
3587 #define HDSPM_SYNC_CHECK(xname, xindex) \
3588 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3589 .name = xname, \
3590 .private_value = xindex, \
3591 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3592 .info = snd_hdspm_info_sync_check, \
3593 .get = snd_hdspm_get_sync_check \
3594 }
3595
3596
3597 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3598 struct snd_ctl_elem_info *uinfo)
3599 {
3600 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3601 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3602 uinfo->count = 1;
3603 uinfo->value.enumerated.items = 4;
3604 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3605 uinfo->value.enumerated.item =
3606 uinfo->value.enumerated.items - 1;
3607 strcpy(uinfo->value.enumerated.name,
3608 texts[uinfo->value.enumerated.item]);
3609 return 0;
3610 }
3611
3612 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3613 {
3614 int status, status2;
3615
3616 switch (hdspm->io_type) {
3617 case AES32:
3618 status = hdspm_read(hdspm, HDSPM_statusRegister);
3619 if (status & HDSPM_wcSync)
3620 return 2;
3621 else if (status & HDSPM_wcLock)
3622 return 1;
3623 return 0;
3624 break;
3625
3626 case MADI:
3627 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3628 if (status2 & HDSPM_wcLock) {
3629 if (status2 & HDSPM_wcSync)
3630 return 2;
3631 else
3632 return 1;
3633 }
3634 return 0;
3635 break;
3636
3637 case RayDAT:
3638 case AIO:
3639 status = hdspm_read(hdspm, HDSPM_statusRegister);
3640
3641 if (status & 0x2000000)
3642 return 2;
3643 else if (status & 0x1000000)
3644 return 1;
3645 return 0;
3646
3647 break;
3648
3649 case MADIface:
3650 break;
3651 }
3652
3653
3654 return 3;
3655 }
3656
3657
3658 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3659 {
3660 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3661 if (status & HDSPM_madiLock) {
3662 if (status & HDSPM_madiSync)
3663 return 2;
3664 else
3665 return 1;
3666 }
3667 return 0;
3668 }
3669
3670
3671 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3672 {
3673 int status, lock, sync;
3674
3675 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3676
3677 lock = (status & (0x1<<idx)) ? 1 : 0;
3678 sync = (status & (0x100<<idx)) ? 1 : 0;
3679
3680 if (lock && sync)
3681 return 2;
3682 else if (lock)
3683 return 1;
3684 return 0;
3685 }
3686
3687
3688 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3689 {
3690 int status, lock = 0, sync = 0;
3691
3692 switch (hdspm->io_type) {
3693 case RayDAT:
3694 case AIO:
3695 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3696 lock = (status & 0x400) ? 1 : 0;
3697 sync = (status & 0x800) ? 1 : 0;
3698 break;
3699
3700 case MADI:
3701 case AES32:
3702 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3703 lock = (status & 0x400000) ? 1 : 0;
3704 sync = (status & 0x800000) ? 1 : 0;
3705 break;
3706
3707 case MADIface:
3708 break;
3709 }
3710
3711 if (lock && sync)
3712 return 2;
3713 else if (lock)
3714 return 1;
3715
3716 return 0;
3717 }
3718
3719 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3720 {
3721 int status2, lock, sync;
3722 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3723
3724 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3725 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3726
3727 if (sync)
3728 return 2;
3729 else if (lock)
3730 return 1;
3731 return 0;
3732 }
3733
3734
3735 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3736 {
3737 int status;
3738
3739 if (hdspm->tco) {
3740 switch (hdspm->io_type) {
3741 case MADI:
3742 case AES32:
3743 status = hdspm_read(hdspm, HDSPM_statusRegister);
3744 if (status & HDSPM_tcoLock) {
3745 if (status & HDSPM_tcoSync)
3746 return 2;
3747 else
3748 return 1;
3749 }
3750 return 0;
3751
3752 break;
3753
3754 case RayDAT:
3755 case AIO:
3756 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3757
3758 if (status & 0x8000000)
3759 return 2; /* Sync */
3760 if (status & 0x4000000)
3761 return 1; /* Lock */
3762 return 0; /* No signal */
3763 break;
3764
3765 default:
3766 break;
3767 }
3768 }
3769
3770 return 3; /* N/A */
3771 }
3772
3773
3774 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3775 struct snd_ctl_elem_value *ucontrol)
3776 {
3777 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3778 int val = -1;
3779
3780 switch (hdspm->io_type) {
3781 case RayDAT:
3782 switch (kcontrol->private_value) {
3783 case 0: /* WC */
3784 val = hdspm_wc_sync_check(hdspm); break;
3785 case 7: /* TCO */
3786 val = hdspm_tco_sync_check(hdspm); break;
3787 case 8: /* SYNC IN */
3788 val = hdspm_sync_in_sync_check(hdspm); break;
3789 default:
3790 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3791 }
3792
3793 case AIO:
3794 switch (kcontrol->private_value) {
3795 case 0: /* WC */
3796 val = hdspm_wc_sync_check(hdspm); break;
3797 case 4: /* TCO */
3798 val = hdspm_tco_sync_check(hdspm); break;
3799 case 5: /* SYNC IN */
3800 val = hdspm_sync_in_sync_check(hdspm); break;
3801 default:
3802 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3803 }
3804
3805 case MADI:
3806 switch (kcontrol->private_value) {
3807 case 0: /* WC */
3808 val = hdspm_wc_sync_check(hdspm); break;
3809 case 1: /* MADI */
3810 val = hdspm_madi_sync_check(hdspm); break;
3811 case 2: /* TCO */
3812 val = hdspm_tco_sync_check(hdspm); break;
3813 case 3: /* SYNC_IN */
3814 val = hdspm_sync_in_sync_check(hdspm); break;
3815 }
3816
3817 case MADIface:
3818 val = hdspm_madi_sync_check(hdspm); /* MADI */
3819 break;
3820
3821 case AES32:
3822 switch (kcontrol->private_value) {
3823 case 0: /* WC */
3824 val = hdspm_wc_sync_check(hdspm); break;
3825 case 9: /* TCO */
3826 val = hdspm_tco_sync_check(hdspm); break;
3827 case 10 /* SYNC IN */:
3828 val = hdspm_sync_in_sync_check(hdspm); break;
3829 default: /* AES1 to AES8 */
3830 val = hdspm_aes_sync_check(hdspm,
3831 kcontrol->private_value-1);
3832 }
3833
3834 }
3835
3836 if (-1 == val)
3837 val = 3;
3838
3839 ucontrol->value.enumerated.item[0] = val;
3840 return 0;
3841 }
3842
3843
3844
3845 /**
3846 * TCO controls
3847 **/
3848 static void hdspm_tco_write(struct hdspm *hdspm)
3849 {
3850 unsigned int tc[4] = { 0, 0, 0, 0};
3851
3852 switch (hdspm->tco->input) {
3853 case 0:
3854 tc[2] |= HDSPM_TCO2_set_input_MSB;
3855 break;
3856 case 1:
3857 tc[2] |= HDSPM_TCO2_set_input_LSB;
3858 break;
3859 default:
3860 break;
3861 }
3862
3863 switch (hdspm->tco->framerate) {
3864 case 1:
3865 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3866 break;
3867 case 2:
3868 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3869 break;
3870 case 3:
3871 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3872 HDSPM_TCO1_set_drop_frame_flag;
3873 break;
3874 case 4:
3875 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3876 HDSPM_TCO1_LTC_Format_MSB;
3877 break;
3878 case 5:
3879 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3880 HDSPM_TCO1_LTC_Format_MSB +
3881 HDSPM_TCO1_set_drop_frame_flag;
3882 break;
3883 default:
3884 break;
3885 }
3886
3887 switch (hdspm->tco->wordclock) {
3888 case 1:
3889 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3890 break;
3891 case 2:
3892 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3893 break;
3894 default:
3895 break;
3896 }
3897
3898 switch (hdspm->tco->samplerate) {
3899 case 1:
3900 tc[2] |= HDSPM_TCO2_set_freq;
3901 break;
3902 case 2:
3903 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3904 break;
3905 default:
3906 break;
3907 }
3908
3909 switch (hdspm->tco->pull) {
3910 case 1:
3911 tc[2] |= HDSPM_TCO2_set_pull_up;
3912 break;
3913 case 2:
3914 tc[2] |= HDSPM_TCO2_set_pull_down;
3915 break;
3916 case 3:
3917 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3918 break;
3919 case 4:
3920 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3921 break;
3922 default:
3923 break;
3924 }
3925
3926 if (1 == hdspm->tco->term) {
3927 tc[2] |= HDSPM_TCO2_set_term_75R;
3928 }
3929
3930 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3931 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3932 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3933 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3934 }
3935
3936
3937 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3938 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3939 .name = xname, \
3940 .index = xindex, \
3941 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3942 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3943 .info = snd_hdspm_info_tco_sample_rate, \
3944 .get = snd_hdspm_get_tco_sample_rate, \
3945 .put = snd_hdspm_put_tco_sample_rate \
3946 }
3947
3948 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3949 struct snd_ctl_elem_info *uinfo)
3950 {
3951 static char *texts[] = { "44.1 kHz", "48 kHz" };
3952 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3953 uinfo->count = 1;
3954 uinfo->value.enumerated.items = 2;
3955
3956 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3957 uinfo->value.enumerated.item =
3958 uinfo->value.enumerated.items - 1;
3959
3960 strcpy(uinfo->value.enumerated.name,
3961 texts[uinfo->value.enumerated.item]);
3962
3963 return 0;
3964 }
3965
3966 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3967 struct snd_ctl_elem_value *ucontrol)
3968 {
3969 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3970
3971 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3972
3973 return 0;
3974 }
3975
3976 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3977 struct snd_ctl_elem_value *ucontrol)
3978 {
3979 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3980
3981 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3982 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
3983
3984 hdspm_tco_write(hdspm);
3985
3986 return 1;
3987 }
3988
3989 return 0;
3990 }
3991
3992
3993 #define HDSPM_TCO_PULL(xname, xindex) \
3994 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3995 .name = xname, \
3996 .index = xindex, \
3997 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3998 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3999 .info = snd_hdspm_info_tco_pull, \
4000 .get = snd_hdspm_get_tco_pull, \
4001 .put = snd_hdspm_put_tco_pull \
4002 }
4003
4004 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4005 struct snd_ctl_elem_info *uinfo)
4006 {
4007 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4008 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4009 uinfo->count = 1;
4010 uinfo->value.enumerated.items = 5;
4011
4012 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4013 uinfo->value.enumerated.item =
4014 uinfo->value.enumerated.items - 1;
4015
4016 strcpy(uinfo->value.enumerated.name,
4017 texts[uinfo->value.enumerated.item]);
4018
4019 return 0;
4020 }
4021
4022 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4023 struct snd_ctl_elem_value *ucontrol)
4024 {
4025 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4026
4027 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4028
4029 return 0;
4030 }
4031
4032 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4033 struct snd_ctl_elem_value *ucontrol)
4034 {
4035 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4036
4037 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4038 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4039
4040 hdspm_tco_write(hdspm);
4041
4042 return 1;
4043 }
4044
4045 return 0;
4046 }
4047
4048 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4049 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4050 .name = xname, \
4051 .index = xindex, \
4052 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4053 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4054 .info = snd_hdspm_info_tco_wck_conversion, \
4055 .get = snd_hdspm_get_tco_wck_conversion, \
4056 .put = snd_hdspm_put_tco_wck_conversion \
4057 }
4058
4059 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4060 struct snd_ctl_elem_info *uinfo)
4061 {
4062 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4063 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4064 uinfo->count = 1;
4065 uinfo->value.enumerated.items = 3;
4066
4067 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4068 uinfo->value.enumerated.item =
4069 uinfo->value.enumerated.items - 1;
4070
4071 strcpy(uinfo->value.enumerated.name,
4072 texts[uinfo->value.enumerated.item]);
4073
4074 return 0;
4075 }
4076
4077 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4078 struct snd_ctl_elem_value *ucontrol)
4079 {
4080 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4081
4082 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4083
4084 return 0;
4085 }
4086
4087 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4088 struct snd_ctl_elem_value *ucontrol)
4089 {
4090 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4091
4092 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4093 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4094
4095 hdspm_tco_write(hdspm);
4096
4097 return 1;
4098 }
4099
4100 return 0;
4101 }
4102
4103
4104 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4105 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4106 .name = xname, \
4107 .index = xindex, \
4108 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4109 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4110 .info = snd_hdspm_info_tco_frame_rate, \
4111 .get = snd_hdspm_get_tco_frame_rate, \
4112 .put = snd_hdspm_put_tco_frame_rate \
4113 }
4114
4115 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4116 struct snd_ctl_elem_info *uinfo)
4117 {
4118 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4119 "29.97 dfps", "30 fps", "30 dfps" };
4120 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4121 uinfo->count = 1;
4122 uinfo->value.enumerated.items = 6;
4123
4124 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4125 uinfo->value.enumerated.item =
4126 uinfo->value.enumerated.items - 1;
4127
4128 strcpy(uinfo->value.enumerated.name,
4129 texts[uinfo->value.enumerated.item]);
4130
4131 return 0;
4132 }
4133
4134 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4135 struct snd_ctl_elem_value *ucontrol)
4136 {
4137 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4138
4139 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4140
4141 return 0;
4142 }
4143
4144 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4145 struct snd_ctl_elem_value *ucontrol)
4146 {
4147 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4148
4149 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4150 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4151
4152 hdspm_tco_write(hdspm);
4153
4154 return 1;
4155 }
4156
4157 return 0;
4158 }
4159
4160
4161 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4162 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4163 .name = xname, \
4164 .index = xindex, \
4165 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4166 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4167 .info = snd_hdspm_info_tco_sync_source, \
4168 .get = snd_hdspm_get_tco_sync_source, \
4169 .put = snd_hdspm_put_tco_sync_source \
4170 }
4171
4172 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4173 struct snd_ctl_elem_info *uinfo)
4174 {
4175 static char *texts[] = { "LTC", "Video", "WCK" };
4176 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4177 uinfo->count = 1;
4178 uinfo->value.enumerated.items = 3;
4179
4180 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4181 uinfo->value.enumerated.item =
4182 uinfo->value.enumerated.items - 1;
4183
4184 strcpy(uinfo->value.enumerated.name,
4185 texts[uinfo->value.enumerated.item]);
4186
4187 return 0;
4188 }
4189
4190 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4191 struct snd_ctl_elem_value *ucontrol)
4192 {
4193 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4194
4195 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4196
4197 return 0;
4198 }
4199
4200 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4201 struct snd_ctl_elem_value *ucontrol)
4202 {
4203 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4204
4205 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4206 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4207
4208 hdspm_tco_write(hdspm);
4209
4210 return 1;
4211 }
4212
4213 return 0;
4214 }
4215
4216
4217 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4218 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4219 .name = xname, \
4220 .index = xindex, \
4221 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4222 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4223 .info = snd_hdspm_info_tco_word_term, \
4224 .get = snd_hdspm_get_tco_word_term, \
4225 .put = snd_hdspm_put_tco_word_term \
4226 }
4227
4228 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4229 struct snd_ctl_elem_info *uinfo)
4230 {
4231 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4232 uinfo->count = 1;
4233 uinfo->value.integer.min = 0;
4234 uinfo->value.integer.max = 1;
4235
4236 return 0;
4237 }
4238
4239
4240 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4241 struct snd_ctl_elem_value *ucontrol)
4242 {
4243 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4244
4245 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4246
4247 return 0;
4248 }
4249
4250
4251 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4252 struct snd_ctl_elem_value *ucontrol)
4253 {
4254 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4255
4256 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4257 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4258
4259 hdspm_tco_write(hdspm);
4260
4261 return 1;
4262 }
4263
4264 return 0;
4265 }
4266
4267
4268
4269
4270 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4271 HDSPM_MIXER("Mixer", 0),
4272 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4273 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4274 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4275 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4276 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4277 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4278 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4279 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4280 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4281 HDSPM_LINE_OUT("Line Out", 0),
4282 HDSPM_TX_64("TX 64 channels mode", 0),
4283 HDSPM_C_TMS("Clear Track Marker", 0),
4284 HDSPM_SAFE_MODE("Safe Mode", 0),
4285 HDSPM_INPUT_SELECT("Input Select", 0)
4286 };
4287
4288
4289 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4290 HDSPM_MIXER("Mixer", 0),
4291 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4292 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4293 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4294 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4295 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4296 HDSPM_TX_64("TX 64 channels mode", 0),
4297 HDSPM_C_TMS("Clear Track Marker", 0),
4298 HDSPM_SAFE_MODE("Safe Mode", 0)
4299 };
4300
4301 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4302 HDSPM_MIXER("Mixer", 0),
4303 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4304 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4305 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4306 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4307 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4308 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4309 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4310 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4311 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4312 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4313 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4314 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4315 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4316 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4317 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4318 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4319 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4320 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4321
4322 /*
4323 HDSPM_INPUT_SELECT("Input Select", 0),
4324 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4325 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4326 HDSPM_SPDIF_IN("SPDIF In", 0);
4327 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4328 HDSPM_INPUT_LEVEL("Input Level", 0);
4329 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4330 HDSPM_PHONES("Phones", 0);
4331 */
4332 };
4333
4334 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4335 HDSPM_MIXER("Mixer", 0),
4336 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4337 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4338 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4339 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4340 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4341 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4342 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4343 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4344 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4345 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4346 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4347 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4348 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4349 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4350 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4351 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4352 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4353 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4354 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4355 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4356 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4357 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4358 };
4359
4360 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4361 HDSPM_MIXER("Mixer", 0),
4362 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4363 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4364 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4365 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4366 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4367 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4368 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4369 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4370 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4371 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4372 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4373 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4374 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4375 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4376 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4377 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4378 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4379 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4380 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4381 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4382 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4383 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4384 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4385 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4386 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4387 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4388 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4389 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4390 HDSPM_LINE_OUT("Line Out", 0),
4391 HDSPM_EMPHASIS("Emphasis", 0),
4392 HDSPM_DOLBY("Non Audio", 0),
4393 HDSPM_PROFESSIONAL("Professional", 0),
4394 HDSPM_C_TMS("Clear Track Marker", 0),
4395 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4396 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4397 };
4398
4399
4400
4401 /* Control elements for the optional TCO module */
4402 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4403 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4404 HDSPM_TCO_PULL("TCO Pull", 0),
4405 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4406 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4407 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4408 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4409 };
4410
4411
4412 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4413
4414
4415 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4416 {
4417 int i;
4418
4419 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4420 if (hdspm->system_sample_rate > 48000) {
4421 hdspm->playback_mixer_ctls[i]->vd[0].access =
4422 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4423 SNDRV_CTL_ELEM_ACCESS_READ |
4424 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4425 } else {
4426 hdspm->playback_mixer_ctls[i]->vd[0].access =
4427 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4428 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4429 }
4430 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4431 SNDRV_CTL_EVENT_MASK_INFO,
4432 &hdspm->playback_mixer_ctls[i]->id);
4433 }
4434
4435 return 0;
4436 }
4437
4438
4439 static int snd_hdspm_create_controls(struct snd_card *card,
4440 struct hdspm *hdspm)
4441 {
4442 unsigned int idx, limit;
4443 int err;
4444 struct snd_kcontrol *kctl;
4445 struct snd_kcontrol_new *list = NULL;
4446
4447 switch (hdspm->io_type) {
4448 case MADI:
4449 list = snd_hdspm_controls_madi;
4450 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4451 break;
4452 case MADIface:
4453 list = snd_hdspm_controls_madiface;
4454 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4455 break;
4456 case AIO:
4457 list = snd_hdspm_controls_aio;
4458 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4459 break;
4460 case RayDAT:
4461 list = snd_hdspm_controls_raydat;
4462 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4463 break;
4464 case AES32:
4465 list = snd_hdspm_controls_aes32;
4466 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4467 break;
4468 }
4469
4470 if (NULL != list) {
4471 for (idx = 0; idx < limit; idx++) {
4472 err = snd_ctl_add(card,
4473 snd_ctl_new1(&list[idx], hdspm));
4474 if (err < 0)
4475 return err;
4476 }
4477 }
4478
4479
4480 /* create simple 1:1 playback mixer controls */
4481 snd_hdspm_playback_mixer.name = "Chn";
4482 if (hdspm->system_sample_rate >= 128000) {
4483 limit = hdspm->qs_out_channels;
4484 } else if (hdspm->system_sample_rate >= 64000) {
4485 limit = hdspm->ds_out_channels;
4486 } else {
4487 limit = hdspm->ss_out_channels;
4488 }
4489 for (idx = 0; idx < limit; ++idx) {
4490 snd_hdspm_playback_mixer.index = idx + 1;
4491 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4492 err = snd_ctl_add(card, kctl);
4493 if (err < 0)
4494 return err;
4495 hdspm->playback_mixer_ctls[idx] = kctl;
4496 }
4497
4498
4499 if (hdspm->tco) {
4500 /* add tco control elements */
4501 list = snd_hdspm_controls_tco;
4502 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4503 for (idx = 0; idx < limit; idx++) {
4504 err = snd_ctl_add(card,
4505 snd_ctl_new1(&list[idx], hdspm));
4506 if (err < 0)
4507 return err;
4508 }
4509 }
4510
4511 return 0;
4512 }
4513
4514 /*------------------------------------------------------------
4515 /proc interface
4516 ------------------------------------------------------------*/
4517
4518 static void
4519 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4520 struct snd_info_buffer *buffer)
4521 {
4522 struct hdspm *hdspm = entry->private_data;
4523 unsigned int status, status2, control, freq;
4524
4525 char *pref_sync_ref;
4526 char *autosync_ref;
4527 char *system_clock_mode;
4528 char *insel;
4529 int x, x2;
4530
4531 /* TCO stuff */
4532 int a, ltc, frames, seconds, minutes, hours;
4533 unsigned int period;
4534 u64 freq_const = 0;
4535 u32 rate;
4536
4537 status = hdspm_read(hdspm, HDSPM_statusRegister);
4538 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4539 control = hdspm->control_register;
4540 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4541
4542 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4543 hdspm->card_name, hdspm->card->number + 1,
4544 hdspm->firmware_rev,
4545 (status2 & HDSPM_version0) |
4546 (status2 & HDSPM_version1) | (status2 &
4547 HDSPM_version2));
4548
4549 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4550 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4551 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4552
4553 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4554 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4555
4556 snd_iprintf(buffer, "--- System ---\n");
4557
4558 snd_iprintf(buffer,
4559 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4560 status & HDSPM_audioIRQPending,
4561 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4562 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4563 hdspm->irq_count);
4564 snd_iprintf(buffer,
4565 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4566 "estimated= %ld (bytes)\n",
4567 ((status & HDSPM_BufferID) ? 1 : 0),
4568 (status & HDSPM_BufferPositionMask),
4569 (status & HDSPM_BufferPositionMask) %
4570 (2 * (int)hdspm->period_bytes),
4571 ((status & HDSPM_BufferPositionMask) - 64) %
4572 (2 * (int)hdspm->period_bytes),
4573 (long) hdspm_hw_pointer(hdspm) * 4);
4574
4575 snd_iprintf(buffer,
4576 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4577 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4578 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4579 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4580 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4581 snd_iprintf(buffer,
4582 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4583 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4584 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4585 snd_iprintf(buffer,
4586 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4587 "status2=0x%x\n",
4588 hdspm->control_register, hdspm->control2_register,
4589 status, status2);
4590 if (status & HDSPM_tco_detect) {
4591 snd_iprintf(buffer, "TCO module detected.\n");
4592 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4593 if (a & HDSPM_TCO1_LTC_Input_valid) {
4594 snd_iprintf(buffer, " LTC valid, ");
4595 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4596 HDSPM_TCO1_LTC_Format_MSB)) {
4597 case 0:
4598 snd_iprintf(buffer, "24 fps, ");
4599 break;
4600 case HDSPM_TCO1_LTC_Format_LSB:
4601 snd_iprintf(buffer, "25 fps, ");
4602 break;
4603 case HDSPM_TCO1_LTC_Format_MSB:
4604 snd_iprintf(buffer, "29.97 fps, ");
4605 break;
4606 default:
4607 snd_iprintf(buffer, "30 fps, ");
4608 break;
4609 }
4610 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4611 snd_iprintf(buffer, "drop frame\n");
4612 } else {
4613 snd_iprintf(buffer, "full frame\n");
4614 }
4615 } else {
4616 snd_iprintf(buffer, " no LTC\n");
4617 }
4618 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4619 snd_iprintf(buffer, " Video: NTSC\n");
4620 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4621 snd_iprintf(buffer, " Video: PAL\n");
4622 } else {
4623 snd_iprintf(buffer, " No video\n");
4624 }
4625 if (a & HDSPM_TCO1_TCO_lock) {
4626 snd_iprintf(buffer, " Sync: lock\n");
4627 } else {
4628 snd_iprintf(buffer, " Sync: no lock\n");
4629 }
4630
4631 switch (hdspm->io_type) {
4632 case MADI:
4633 case AES32:
4634 freq_const = 110069313433624ULL;
4635 break;
4636 case RayDAT:
4637 case AIO:
4638 freq_const = 104857600000000ULL;
4639 break;
4640 case MADIface:
4641 break; /* no TCO possible */
4642 }
4643
4644 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4645 snd_iprintf(buffer, " period: %u\n", period);
4646
4647
4648 /* rate = freq_const/period; */
4649 rate = div_u64(freq_const, period);
4650
4651 if (control & HDSPM_QuadSpeed) {
4652 rate *= 4;
4653 } else if (control & HDSPM_DoubleSpeed) {
4654 rate *= 2;
4655 }
4656
4657 snd_iprintf(buffer, " Frequency: %u Hz\n",
4658 (unsigned int) rate);
4659
4660 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4661 frames = ltc & 0xF;
4662 ltc >>= 4;
4663 frames += (ltc & 0x3) * 10;
4664 ltc >>= 4;
4665 seconds = ltc & 0xF;
4666 ltc >>= 4;
4667 seconds += (ltc & 0x7) * 10;
4668 ltc >>= 4;
4669 minutes = ltc & 0xF;
4670 ltc >>= 4;
4671 minutes += (ltc & 0x7) * 10;
4672 ltc >>= 4;
4673 hours = ltc & 0xF;
4674 ltc >>= 4;
4675 hours += (ltc & 0x3) * 10;
4676 snd_iprintf(buffer,
4677 " LTC In: %02d:%02d:%02d:%02d\n",
4678 hours, minutes, seconds, frames);
4679
4680 } else {
4681 snd_iprintf(buffer, "No TCO module detected.\n");
4682 }
4683
4684 snd_iprintf(buffer, "--- Settings ---\n");
4685
4686 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4687 HDSPM_LatencyMask));
4688
4689 snd_iprintf(buffer,
4690 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4691 x, (unsigned long) hdspm->period_bytes);
4692
4693 snd_iprintf(buffer, "Line out: %s\n",
4694 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4695
4696 switch (hdspm->control_register & HDSPM_InputMask) {
4697 case HDSPM_InputOptical:
4698 insel = "Optical";
4699 break;
4700 case HDSPM_InputCoaxial:
4701 insel = "Coaxial";
4702 break;
4703 default:
4704 insel = "Unkown";
4705 }
4706
4707 snd_iprintf(buffer,
4708 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4709 "Auto Input %s\n",
4710 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4711 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4712 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4713
4714
4715 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4716 system_clock_mode = "AutoSync";
4717 else
4718 system_clock_mode = "Master";
4719 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4720
4721 switch (hdspm_pref_sync_ref(hdspm)) {
4722 case HDSPM_SYNC_FROM_WORD:
4723 pref_sync_ref = "Word Clock";
4724 break;
4725 case HDSPM_SYNC_FROM_MADI:
4726 pref_sync_ref = "MADI Sync";
4727 break;
4728 case HDSPM_SYNC_FROM_TCO:
4729 pref_sync_ref = "TCO";
4730 break;
4731 case HDSPM_SYNC_FROM_SYNC_IN:
4732 pref_sync_ref = "Sync In";
4733 break;
4734 default:
4735 pref_sync_ref = "XXXX Clock";
4736 break;
4737 }
4738 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4739 pref_sync_ref);
4740
4741 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4742 hdspm->system_sample_rate);
4743
4744
4745 snd_iprintf(buffer, "--- Status:\n");
4746
4747 x = status & HDSPM_madiSync;
4748 x2 = status2 & HDSPM_wcSync;
4749
4750 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4751 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4752 "NoLock",
4753 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4754 "NoLock");
4755
4756 switch (hdspm_autosync_ref(hdspm)) {
4757 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4758 autosync_ref = "Sync In";
4759 break;
4760 case HDSPM_AUTOSYNC_FROM_TCO:
4761 autosync_ref = "TCO";
4762 break;
4763 case HDSPM_AUTOSYNC_FROM_WORD:
4764 autosync_ref = "Word Clock";
4765 break;
4766 case HDSPM_AUTOSYNC_FROM_MADI:
4767 autosync_ref = "MADI Sync";
4768 break;
4769 case HDSPM_AUTOSYNC_FROM_NONE:
4770 autosync_ref = "Input not valid";
4771 break;
4772 default:
4773 autosync_ref = "---";
4774 break;
4775 }
4776 snd_iprintf(buffer,
4777 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4778 autosync_ref, hdspm_external_sample_rate(hdspm),
4779 (status & HDSPM_madiFreqMask) >> 22,
4780 (status2 & HDSPM_wcFreqMask) >> 5);
4781
4782 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4783 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4784 (status & HDSPM_RX_64ch) ? "64 channels" :
4785 "56 channels");
4786
4787 snd_iprintf(buffer, "\n");
4788 }
4789
4790 static void
4791 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4792 struct snd_info_buffer *buffer)
4793 {
4794 struct hdspm *hdspm = entry->private_data;
4795 unsigned int status;
4796 unsigned int status2;
4797 unsigned int timecode;
4798 int pref_syncref;
4799 char *autosync_ref;
4800 int x;
4801
4802 status = hdspm_read(hdspm, HDSPM_statusRegister);
4803 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4804 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4805
4806 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4807 hdspm->card_name, hdspm->card->number + 1,
4808 hdspm->firmware_rev);
4809
4810 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4811 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4812
4813 snd_iprintf(buffer, "--- System ---\n");
4814
4815 snd_iprintf(buffer,
4816 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4817 status & HDSPM_audioIRQPending,
4818 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4819 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4820 hdspm->irq_count);
4821 snd_iprintf(buffer,
4822 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4823 "estimated= %ld (bytes)\n",
4824 ((status & HDSPM_BufferID) ? 1 : 0),
4825 (status & HDSPM_BufferPositionMask),
4826 (status & HDSPM_BufferPositionMask) %
4827 (2 * (int)hdspm->period_bytes),
4828 ((status & HDSPM_BufferPositionMask) - 64) %
4829 (2 * (int)hdspm->period_bytes),
4830 (long) hdspm_hw_pointer(hdspm) * 4);
4831
4832 snd_iprintf(buffer,
4833 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4834 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4835 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4836 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4837 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4838 snd_iprintf(buffer,
4839 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4840 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4841 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4842 snd_iprintf(buffer,
4843 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4844 "status2=0x%x\n",
4845 hdspm->control_register, hdspm->control2_register,
4846 status, status2);
4847
4848 snd_iprintf(buffer, "--- Settings ---\n");
4849
4850 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4851 HDSPM_LatencyMask));
4852
4853 snd_iprintf(buffer,
4854 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4855 x, (unsigned long) hdspm->period_bytes);
4856
4857 snd_iprintf(buffer, "Line out: %s\n",
4858 (hdspm->
4859 control_register & HDSPM_LineOut) ? "on " : "off");
4860
4861 snd_iprintf(buffer,
4862 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4863 (hdspm->
4864 control_register & HDSPM_clr_tms) ? "on" : "off",
4865 (hdspm->
4866 control_register & HDSPM_Emphasis) ? "on" : "off",
4867 (hdspm->
4868 control_register & HDSPM_Dolby) ? "on" : "off");
4869
4870
4871 pref_syncref = hdspm_pref_sync_ref(hdspm);
4872 if (pref_syncref == 0)
4873 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4874 else
4875 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4876 pref_syncref);
4877
4878 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4879 hdspm->system_sample_rate);
4880
4881 snd_iprintf(buffer, "Double speed: %s\n",
4882 hdspm->control_register & HDSPM_DS_DoubleWire?
4883 "Double wire" : "Single wire");
4884 snd_iprintf(buffer, "Quad speed: %s\n",
4885 hdspm->control_register & HDSPM_QS_DoubleWire?
4886 "Double wire" :
4887 hdspm->control_register & HDSPM_QS_QuadWire?
4888 "Quad wire" : "Single wire");
4889
4890 snd_iprintf(buffer, "--- Status:\n");
4891
4892 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
4893 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
4894 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4895
4896 for (x = 0; x < 8; x++) {
4897 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
4898 x+1,
4899 (status2 & (HDSPM_LockAES >> x)) ?
4900 "Sync " : "No Lock",
4901 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4902 }
4903
4904 switch (hdspm_autosync_ref(hdspm)) {
4905 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4906 autosync_ref = "None"; break;
4907 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4908 autosync_ref = "Word Clock"; break;
4909 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4910 autosync_ref = "AES1"; break;
4911 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4912 autosync_ref = "AES2"; break;
4913 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4914 autosync_ref = "AES3"; break;
4915 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4916 autosync_ref = "AES4"; break;
4917 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4918 autosync_ref = "AES5"; break;
4919 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4920 autosync_ref = "AES6"; break;
4921 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4922 autosync_ref = "AES7"; break;
4923 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4924 autosync_ref = "AES8"; break;
4925 default:
4926 autosync_ref = "---"; break;
4927 }
4928 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4929
4930 snd_iprintf(buffer, "\n");
4931 }
4932
4933 static void
4934 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4935 struct snd_info_buffer *buffer)
4936 {
4937 struct hdspm *hdspm = entry->private_data;
4938 unsigned int status1, status2, status3, control, i;
4939 unsigned int lock, sync;
4940
4941 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4942 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4943 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4944
4945 control = hdspm->control_register;
4946
4947 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4948 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4949 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4950
4951
4952 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4953
4954 snd_iprintf(buffer, "Clock mode : %s\n",
4955 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4956 snd_iprintf(buffer, "System frequency: %d Hz\n",
4957 hdspm_get_system_sample_rate(hdspm));
4958
4959 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4960
4961 lock = 0x1;
4962 sync = 0x100;
4963
4964 for (i = 0; i < 8; i++) {
4965 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4966 i,
4967 (status1 & lock) ? 1 : 0,
4968 (status1 & sync) ? 1 : 0,
4969 texts_freq[(status2 >> (i * 4)) & 0xF]);
4970
4971 lock = lock<<1;
4972 sync = sync<<1;
4973 }
4974
4975 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4976 (status1 & 0x1000000) ? 1 : 0,
4977 (status1 & 0x2000000) ? 1 : 0,
4978 texts_freq[(status1 >> 16) & 0xF]);
4979
4980 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4981 (status1 & 0x4000000) ? 1 : 0,
4982 (status1 & 0x8000000) ? 1 : 0,
4983 texts_freq[(status1 >> 20) & 0xF]);
4984
4985 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4986 (status3 & 0x400) ? 1 : 0,
4987 (status3 & 0x800) ? 1 : 0,
4988 texts_freq[(status2 >> 12) & 0xF]);
4989
4990 }
4991
4992 #ifdef CONFIG_SND_DEBUG
4993 static void
4994 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
4995 struct snd_info_buffer *buffer)
4996 {
4997 struct hdspm *hdspm = entry->private_data;
4998
4999 int j,i;
5000
5001 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5002 snd_iprintf(buffer, "0x%08X: ", i);
5003 for (j = 0; j < 16; j += 4)
5004 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5005 snd_iprintf(buffer, "\n");
5006 }
5007 }
5008 #endif
5009
5010
5011 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5012 struct snd_info_buffer *buffer)
5013 {
5014 struct hdspm *hdspm = entry->private_data;
5015 int i;
5016
5017 snd_iprintf(buffer, "# generated by hdspm\n");
5018
5019 for (i = 0; i < hdspm->max_channels_in; i++) {
5020 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5021 }
5022 }
5023
5024 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5025 struct snd_info_buffer *buffer)
5026 {
5027 struct hdspm *hdspm = entry->private_data;
5028 int i;
5029
5030 snd_iprintf(buffer, "# generated by hdspm\n");
5031
5032 for (i = 0; i < hdspm->max_channels_out; i++) {
5033 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5034 }
5035 }
5036
5037
5038 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5039 {
5040 struct snd_info_entry *entry;
5041
5042 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5043 switch (hdspm->io_type) {
5044 case AES32:
5045 snd_info_set_text_ops(entry, hdspm,
5046 snd_hdspm_proc_read_aes32);
5047 break;
5048 case MADI:
5049 snd_info_set_text_ops(entry, hdspm,
5050 snd_hdspm_proc_read_madi);
5051 break;
5052 case MADIface:
5053 /* snd_info_set_text_ops(entry, hdspm,
5054 snd_hdspm_proc_read_madiface); */
5055 break;
5056 case RayDAT:
5057 snd_info_set_text_ops(entry, hdspm,
5058 snd_hdspm_proc_read_raydat);
5059 break;
5060 case AIO:
5061 break;
5062 }
5063 }
5064
5065 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5066 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5067 }
5068
5069 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5070 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5071 }
5072
5073 #ifdef CONFIG_SND_DEBUG
5074 /* debug file to read all hdspm registers */
5075 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5076 snd_info_set_text_ops(entry, hdspm,
5077 snd_hdspm_proc_read_debug);
5078 #endif
5079 }
5080
5081 /*------------------------------------------------------------
5082 hdspm intitialize
5083 ------------------------------------------------------------*/
5084
5085 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5086 {
5087 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5088 hold it (e.g. during module initialization).
5089 */
5090
5091 /* set defaults: */
5092
5093 hdspm->settings_register = 0;
5094
5095 switch (hdspm->io_type) {
5096 case MADI:
5097 case MADIface:
5098 hdspm->control_register =
5099 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5100 break;
5101
5102 case RayDAT:
5103 case AIO:
5104 hdspm->settings_register = 0x1 + 0x1000;
5105 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5106 * line_out */
5107 hdspm->control_register =
5108 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5109 break;
5110
5111 case AES32:
5112 hdspm->control_register =
5113 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5114 hdspm_encode_latency(7) | /* latency max=8192samples */
5115 HDSPM_SyncRef0 | /* AES1 is syncclock */
5116 HDSPM_LineOut | /* Analog output in */
5117 HDSPM_Professional; /* Professional mode */
5118 break;
5119 }
5120
5121 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5122
5123 if (AES32 == hdspm->io_type) {
5124 /* No control2 register for AES32 */
5125 #ifdef SNDRV_BIG_ENDIAN
5126 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5127 #else
5128 hdspm->control2_register = 0;
5129 #endif
5130
5131 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5132 }
5133 hdspm_compute_period_size(hdspm);
5134
5135 /* silence everything */
5136
5137 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5138
5139 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5140 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5141 }
5142
5143 /* set a default rate so that the channel map is set up. */
5144 hdspm_set_rate(hdspm, 48000, 1);
5145
5146 return 0;
5147 }
5148
5149
5150 /*------------------------------------------------------------
5151 interrupt
5152 ------------------------------------------------------------*/
5153
5154 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5155 {
5156 struct hdspm *hdspm = (struct hdspm *) dev_id;
5157 unsigned int status;
5158 int i, audio, midi, schedule = 0;
5159 /* cycles_t now; */
5160
5161 status = hdspm_read(hdspm, HDSPM_statusRegister);
5162
5163 audio = status & HDSPM_audioIRQPending;
5164 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5165 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5166
5167 /* now = get_cycles(); */
5168 /**
5169 * LAT_2..LAT_0 period counter (win) counter (mac)
5170 * 6 4096 ~256053425 ~514672358
5171 * 5 2048 ~128024983 ~257373821
5172 * 4 1024 ~64023706 ~128718089
5173 * 3 512 ~32005945 ~64385999
5174 * 2 256 ~16003039 ~32260176
5175 * 1 128 ~7998738 ~16194507
5176 * 0 64 ~3998231 ~8191558
5177 **/
5178 /*
5179 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5180 now-hdspm->last_interrupt, status & 0xFFC0);
5181 hdspm->last_interrupt = now;
5182 */
5183
5184 if (!audio && !midi)
5185 return IRQ_NONE;
5186
5187 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5188 hdspm->irq_count++;
5189
5190
5191 if (audio) {
5192 if (hdspm->capture_substream)
5193 snd_pcm_period_elapsed(hdspm->capture_substream);
5194
5195 if (hdspm->playback_substream)
5196 snd_pcm_period_elapsed(hdspm->playback_substream);
5197 }
5198
5199 if (midi) {
5200 i = 0;
5201 while (i < hdspm->midiPorts) {
5202 if ((hdspm_read(hdspm,
5203 hdspm->midi[i].statusIn) & 0xff) &&
5204 (status & hdspm->midi[i].irq)) {
5205 /* we disable interrupts for this input until
5206 * processing is done
5207 */
5208 hdspm->control_register &= ~hdspm->midi[i].ie;
5209 hdspm_write(hdspm, HDSPM_controlRegister,
5210 hdspm->control_register);
5211 hdspm->midi[i].pending = 1;
5212 schedule = 1;
5213 }
5214
5215 i++;
5216 }
5217
5218 if (schedule)
5219 tasklet_hi_schedule(&hdspm->midi_tasklet);
5220 }
5221
5222 return IRQ_HANDLED;
5223 }
5224
5225 /*------------------------------------------------------------
5226 pcm interface
5227 ------------------------------------------------------------*/
5228
5229
5230 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5231 *substream)
5232 {
5233 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5234 return hdspm_hw_pointer(hdspm);
5235 }
5236
5237
5238 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5239 {
5240 struct snd_pcm_runtime *runtime = substream->runtime;
5241 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5242 struct snd_pcm_substream *other;
5243
5244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5245 other = hdspm->capture_substream;
5246 else
5247 other = hdspm->playback_substream;
5248
5249 if (hdspm->running)
5250 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5251 else
5252 runtime->status->hw_ptr = 0;
5253 if (other) {
5254 struct snd_pcm_substream *s;
5255 struct snd_pcm_runtime *oruntime = other->runtime;
5256 snd_pcm_group_for_each_entry(s, substream) {
5257 if (s == other) {
5258 oruntime->status->hw_ptr =
5259 runtime->status->hw_ptr;
5260 break;
5261 }
5262 }
5263 }
5264 return 0;
5265 }
5266
5267 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5268 struct snd_pcm_hw_params *params)
5269 {
5270 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5271 int err;
5272 int i;
5273 pid_t this_pid;
5274 pid_t other_pid;
5275
5276 spin_lock_irq(&hdspm->lock);
5277
5278 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5279 this_pid = hdspm->playback_pid;
5280 other_pid = hdspm->capture_pid;
5281 } else {
5282 this_pid = hdspm->capture_pid;
5283 other_pid = hdspm->playback_pid;
5284 }
5285
5286 if (other_pid > 0 && this_pid != other_pid) {
5287
5288 /* The other stream is open, and not by the same
5289 task as this one. Make sure that the parameters
5290 that matter are the same.
5291 */
5292
5293 if (params_rate(params) != hdspm->system_sample_rate) {
5294 spin_unlock_irq(&hdspm->lock);
5295 _snd_pcm_hw_param_setempty(params,
5296 SNDRV_PCM_HW_PARAM_RATE);
5297 return -EBUSY;
5298 }
5299
5300 if (params_period_size(params) != hdspm->period_bytes / 4) {
5301 spin_unlock_irq(&hdspm->lock);
5302 _snd_pcm_hw_param_setempty(params,
5303 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5304 return -EBUSY;
5305 }
5306
5307 }
5308 /* We're fine. */
5309 spin_unlock_irq(&hdspm->lock);
5310
5311 /* how to make sure that the rate matches an externally-set one ? */
5312
5313 spin_lock_irq(&hdspm->lock);
5314 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5315 if (err < 0) {
5316 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5317 spin_unlock_irq(&hdspm->lock);
5318 _snd_pcm_hw_param_setempty(params,
5319 SNDRV_PCM_HW_PARAM_RATE);
5320 return err;
5321 }
5322 spin_unlock_irq(&hdspm->lock);
5323
5324 err = hdspm_set_interrupt_interval(hdspm,
5325 params_period_size(params));
5326 if (err < 0) {
5327 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5328 _snd_pcm_hw_param_setempty(params,
5329 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5330 return err;
5331 }
5332
5333 /* Memory allocation, takashi's method, dont know if we should
5334 * spinlock
5335 */
5336 /* malloc all buffer even if not enabled to get sure */
5337 /* Update for MADI rev 204: we need to allocate for all channels,
5338 * otherwise it doesn't work at 96kHz */
5339
5340 err =
5341 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5342 if (err < 0) {
5343 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5344 return err;
5345 }
5346
5347 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5348
5349 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5350 params_channels(params));
5351
5352 for (i = 0; i < params_channels(params); ++i)
5353 snd_hdspm_enable_out(hdspm, i, 1);
5354
5355 hdspm->playback_buffer =
5356 (unsigned char *) substream->runtime->dma_area;
5357 snd_printdd("Allocated sample buffer for playback at %p\n",
5358 hdspm->playback_buffer);
5359 } else {
5360 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5361 params_channels(params));
5362
5363 for (i = 0; i < params_channels(params); ++i)
5364 snd_hdspm_enable_in(hdspm, i, 1);
5365
5366 hdspm->capture_buffer =
5367 (unsigned char *) substream->runtime->dma_area;
5368 snd_printdd("Allocated sample buffer for capture at %p\n",
5369 hdspm->capture_buffer);
5370 }
5371
5372 /*
5373 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5374 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5375 "playback" : "capture",
5376 snd_pcm_sgbuf_get_addr(substream, 0));
5377 */
5378 /*
5379 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5380 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5381 "playback" : "capture",
5382 params_rate(params), params_channels(params),
5383 params_buffer_size(params));
5384 */
5385
5386
5387 /* Switch to native float format if requested */
5388 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5389 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5390 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5391
5392 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5393 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5394 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5395 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5396
5397 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5398 }
5399 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5400
5401 return 0;
5402 }
5403
5404 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5405 {
5406 int i;
5407 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5408
5409 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5410
5411 /* params_channels(params) should be enough,
5412 but to get sure in case of error */
5413 for (i = 0; i < hdspm->max_channels_out; ++i)
5414 snd_hdspm_enable_out(hdspm, i, 0);
5415
5416 hdspm->playback_buffer = NULL;
5417 } else {
5418 for (i = 0; i < hdspm->max_channels_in; ++i)
5419 snd_hdspm_enable_in(hdspm, i, 0);
5420
5421 hdspm->capture_buffer = NULL;
5422
5423 }
5424
5425 snd_pcm_lib_free_pages(substream);
5426
5427 return 0;
5428 }
5429
5430
5431 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5432 struct snd_pcm_channel_info *info)
5433 {
5434 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5435
5436 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5437 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5438 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5439 return -EINVAL;
5440 }
5441
5442 if (hdspm->channel_map_out[info->channel] < 0) {
5443 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5444 return -EINVAL;
5445 }
5446
5447 info->offset = hdspm->channel_map_out[info->channel] *
5448 HDSPM_CHANNEL_BUFFER_BYTES;
5449 } else {
5450 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5451 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5452 return -EINVAL;
5453 }
5454
5455 if (hdspm->channel_map_in[info->channel] < 0) {
5456 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5457 return -EINVAL;
5458 }
5459
5460 info->offset = hdspm->channel_map_in[info->channel] *
5461 HDSPM_CHANNEL_BUFFER_BYTES;
5462 }
5463
5464 info->first = 0;
5465 info->step = 32;
5466 return 0;
5467 }
5468
5469
5470 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5471 unsigned int cmd, void *arg)
5472 {
5473 switch (cmd) {
5474 case SNDRV_PCM_IOCTL1_RESET:
5475 return snd_hdspm_reset(substream);
5476
5477 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5478 {
5479 struct snd_pcm_channel_info *info = arg;
5480 return snd_hdspm_channel_info(substream, info);
5481 }
5482 default:
5483 break;
5484 }
5485
5486 return snd_pcm_lib_ioctl(substream, cmd, arg);
5487 }
5488
5489 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5490 {
5491 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5492 struct snd_pcm_substream *other;
5493 int running;
5494
5495 spin_lock(&hdspm->lock);
5496 running = hdspm->running;
5497 switch (cmd) {
5498 case SNDRV_PCM_TRIGGER_START:
5499 running |= 1 << substream->stream;
5500 break;
5501 case SNDRV_PCM_TRIGGER_STOP:
5502 running &= ~(1 << substream->stream);
5503 break;
5504 default:
5505 snd_BUG();
5506 spin_unlock(&hdspm->lock);
5507 return -EINVAL;
5508 }
5509 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5510 other = hdspm->capture_substream;
5511 else
5512 other = hdspm->playback_substream;
5513
5514 if (other) {
5515 struct snd_pcm_substream *s;
5516 snd_pcm_group_for_each_entry(s, substream) {
5517 if (s == other) {
5518 snd_pcm_trigger_done(s, substream);
5519 if (cmd == SNDRV_PCM_TRIGGER_START)
5520 running |= 1 << s->stream;
5521 else
5522 running &= ~(1 << s->stream);
5523 goto _ok;
5524 }
5525 }
5526 if (cmd == SNDRV_PCM_TRIGGER_START) {
5527 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5528 && substream->stream ==
5529 SNDRV_PCM_STREAM_CAPTURE)
5530 hdspm_silence_playback(hdspm);
5531 } else {
5532 if (running &&
5533 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5534 hdspm_silence_playback(hdspm);
5535 }
5536 } else {
5537 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5538 hdspm_silence_playback(hdspm);
5539 }
5540 _ok:
5541 snd_pcm_trigger_done(substream, substream);
5542 if (!hdspm->running && running)
5543 hdspm_start_audio(hdspm);
5544 else if (hdspm->running && !running)
5545 hdspm_stop_audio(hdspm);
5546 hdspm->running = running;
5547 spin_unlock(&hdspm->lock);
5548
5549 return 0;
5550 }
5551
5552 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5553 {
5554 return 0;
5555 }
5556
5557 static unsigned int period_sizes_old[] = {
5558 64, 128, 256, 512, 1024, 2048, 4096
5559 };
5560
5561 static unsigned int period_sizes_new[] = {
5562 32, 64, 128, 256, 512, 1024, 2048, 4096
5563 };
5564
5565 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5566 static unsigned int raydat_aio_buffer_sizes[] = {
5567 16384
5568 };
5569
5570 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5571 .info = (SNDRV_PCM_INFO_MMAP |
5572 SNDRV_PCM_INFO_MMAP_VALID |
5573 SNDRV_PCM_INFO_NONINTERLEAVED |
5574 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5575 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5576 .rates = (SNDRV_PCM_RATE_32000 |
5577 SNDRV_PCM_RATE_44100 |
5578 SNDRV_PCM_RATE_48000 |
5579 SNDRV_PCM_RATE_64000 |
5580 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5581 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5582 .rate_min = 32000,
5583 .rate_max = 192000,
5584 .channels_min = 1,
5585 .channels_max = HDSPM_MAX_CHANNELS,
5586 .buffer_bytes_max =
5587 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5588 .period_bytes_min = (64 * 4),
5589 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5590 .periods_min = 2,
5591 .periods_max = 512,
5592 .fifo_size = 0
5593 };
5594
5595 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5596 .info = (SNDRV_PCM_INFO_MMAP |
5597 SNDRV_PCM_INFO_MMAP_VALID |
5598 SNDRV_PCM_INFO_NONINTERLEAVED |
5599 SNDRV_PCM_INFO_SYNC_START),
5600 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5601 .rates = (SNDRV_PCM_RATE_32000 |
5602 SNDRV_PCM_RATE_44100 |
5603 SNDRV_PCM_RATE_48000 |
5604 SNDRV_PCM_RATE_64000 |
5605 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5606 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5607 .rate_min = 32000,
5608 .rate_max = 192000,
5609 .channels_min = 1,
5610 .channels_max = HDSPM_MAX_CHANNELS,
5611 .buffer_bytes_max =
5612 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5613 .period_bytes_min = (64 * 4),
5614 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5615 .periods_min = 2,
5616 .periods_max = 512,
5617 .fifo_size = 0
5618 };
5619
5620 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5621 .count = ARRAY_SIZE(period_sizes_old),
5622 .list = period_sizes_old,
5623 .mask = 0
5624 };
5625
5626 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5627 .count = ARRAY_SIZE(period_sizes_new),
5628 .list = period_sizes_new,
5629 .mask = 0
5630 };
5631
5632 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5633 .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5634 .list = raydat_aio_buffer_sizes,
5635 .mask = 0
5636 };
5637
5638 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5639 struct snd_pcm_hw_rule *rule)
5640 {
5641 struct hdspm *hdspm = rule->private;
5642 struct snd_interval *c =
5643 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5644 struct snd_interval *r =
5645 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5646
5647 if (r->min > 96000 && r->max <= 192000) {
5648 struct snd_interval t = {
5649 .min = hdspm->qs_in_channels,
5650 .max = hdspm->qs_in_channels,
5651 .integer = 1,
5652 };
5653 return snd_interval_refine(c, &t);
5654 } else if (r->min > 48000 && r->max <= 96000) {
5655 struct snd_interval t = {
5656 .min = hdspm->ds_in_channels,
5657 .max = hdspm->ds_in_channels,
5658 .integer = 1,
5659 };
5660 return snd_interval_refine(c, &t);
5661 } else if (r->max < 64000) {
5662 struct snd_interval t = {
5663 .min = hdspm->ss_in_channels,
5664 .max = hdspm->ss_in_channels,
5665 .integer = 1,
5666 };
5667 return snd_interval_refine(c, &t);
5668 }
5669
5670 return 0;
5671 }
5672
5673 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5674 struct snd_pcm_hw_rule * rule)
5675 {
5676 struct hdspm *hdspm = rule->private;
5677 struct snd_interval *c =
5678 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5679 struct snd_interval *r =
5680 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5681
5682 if (r->min > 96000 && r->max <= 192000) {
5683 struct snd_interval t = {
5684 .min = hdspm->qs_out_channels,
5685 .max = hdspm->qs_out_channels,
5686 .integer = 1,
5687 };
5688 return snd_interval_refine(c, &t);
5689 } else if (r->min > 48000 && r->max <= 96000) {
5690 struct snd_interval t = {
5691 .min = hdspm->ds_out_channels,
5692 .max = hdspm->ds_out_channels,
5693 .integer = 1,
5694 };
5695 return snd_interval_refine(c, &t);
5696 } else if (r->max < 64000) {
5697 struct snd_interval t = {
5698 .min = hdspm->ss_out_channels,
5699 .max = hdspm->ss_out_channels,
5700 .integer = 1,
5701 };
5702 return snd_interval_refine(c, &t);
5703 } else {
5704 }
5705 return 0;
5706 }
5707
5708 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5709 struct snd_pcm_hw_rule * rule)
5710 {
5711 struct hdspm *hdspm = rule->private;
5712 struct snd_interval *c =
5713 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5714 struct snd_interval *r =
5715 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5716
5717 if (c->min >= hdspm->ss_in_channels) {
5718 struct snd_interval t = {
5719 .min = 32000,
5720 .max = 48000,
5721 .integer = 1,
5722 };
5723 return snd_interval_refine(r, &t);
5724 } else if (c->max <= hdspm->qs_in_channels) {
5725 struct snd_interval t = {
5726 .min = 128000,
5727 .max = 192000,
5728 .integer = 1,
5729 };
5730 return snd_interval_refine(r, &t);
5731 } else if (c->max <= hdspm->ds_in_channels) {
5732 struct snd_interval t = {
5733 .min = 64000,
5734 .max = 96000,
5735 .integer = 1,
5736 };
5737 return snd_interval_refine(r, &t);
5738 }
5739
5740 return 0;
5741 }
5742 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5743 struct snd_pcm_hw_rule *rule)
5744 {
5745 struct hdspm *hdspm = rule->private;
5746 struct snd_interval *c =
5747 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5748 struct snd_interval *r =
5749 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5750
5751 if (c->min >= hdspm->ss_out_channels) {
5752 struct snd_interval t = {
5753 .min = 32000,
5754 .max = 48000,
5755 .integer = 1,
5756 };
5757 return snd_interval_refine(r, &t);
5758 } else if (c->max <= hdspm->qs_out_channels) {
5759 struct snd_interval t = {
5760 .min = 128000,
5761 .max = 192000,
5762 .integer = 1,
5763 };
5764 return snd_interval_refine(r, &t);
5765 } else if (c->max <= hdspm->ds_out_channels) {
5766 struct snd_interval t = {
5767 .min = 64000,
5768 .max = 96000,
5769 .integer = 1,
5770 };
5771 return snd_interval_refine(r, &t);
5772 }
5773
5774 return 0;
5775 }
5776
5777 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5778 struct snd_pcm_hw_rule *rule)
5779 {
5780 unsigned int list[3];
5781 struct hdspm *hdspm = rule->private;
5782 struct snd_interval *c = hw_param_interval(params,
5783 SNDRV_PCM_HW_PARAM_CHANNELS);
5784
5785 list[0] = hdspm->qs_in_channels;
5786 list[1] = hdspm->ds_in_channels;
5787 list[2] = hdspm->ss_in_channels;
5788 return snd_interval_list(c, 3, list, 0);
5789 }
5790
5791 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5792 struct snd_pcm_hw_rule *rule)
5793 {
5794 unsigned int list[3];
5795 struct hdspm *hdspm = rule->private;
5796 struct snd_interval *c = hw_param_interval(params,
5797 SNDRV_PCM_HW_PARAM_CHANNELS);
5798
5799 list[0] = hdspm->qs_out_channels;
5800 list[1] = hdspm->ds_out_channels;
5801 list[2] = hdspm->ss_out_channels;
5802 return snd_interval_list(c, 3, list, 0);
5803 }
5804
5805
5806 static unsigned int hdspm_aes32_sample_rates[] = {
5807 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5808 };
5809
5810 static struct snd_pcm_hw_constraint_list
5811 hdspm_hw_constraints_aes32_sample_rates = {
5812 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5813 .list = hdspm_aes32_sample_rates,
5814 .mask = 0
5815 };
5816
5817 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5818 {
5819 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5820 struct snd_pcm_runtime *runtime = substream->runtime;
5821
5822 spin_lock_irq(&hdspm->lock);
5823
5824 snd_pcm_set_sync(substream);
5825
5826
5827 runtime->hw = snd_hdspm_playback_subinfo;
5828
5829 if (hdspm->capture_substream == NULL)
5830 hdspm_stop_audio(hdspm);
5831
5832 hdspm->playback_pid = current->pid;
5833 hdspm->playback_substream = substream;
5834
5835 spin_unlock_irq(&hdspm->lock);
5836
5837 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5838
5839 switch (hdspm->io_type) {
5840 case AIO:
5841 case RayDAT:
5842 snd_pcm_hw_constraint_list(runtime, 0,
5843 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5844 &hw_constraints_period_sizes_new);
5845 snd_pcm_hw_constraint_list(runtime, 0,
5846 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5847 &hw_constraints_raydat_io_buffer);
5848
5849 break;
5850
5851 default:
5852 snd_pcm_hw_constraint_list(runtime, 0,
5853 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5854 &hw_constraints_period_sizes_old);
5855 }
5856
5857 if (AES32 == hdspm->io_type) {
5858 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5859 &hdspm_hw_constraints_aes32_sample_rates);
5860 } else {
5861 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5862 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5863 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5864 }
5865
5866 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5867 snd_hdspm_hw_rule_out_channels, hdspm,
5868 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5869
5870 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5871 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5872 SNDRV_PCM_HW_PARAM_RATE, -1);
5873
5874 return 0;
5875 }
5876
5877 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5878 {
5879 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5880
5881 spin_lock_irq(&hdspm->lock);
5882
5883 hdspm->playback_pid = -1;
5884 hdspm->playback_substream = NULL;
5885
5886 spin_unlock_irq(&hdspm->lock);
5887
5888 return 0;
5889 }
5890
5891
5892 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5893 {
5894 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5895 struct snd_pcm_runtime *runtime = substream->runtime;
5896
5897 spin_lock_irq(&hdspm->lock);
5898 snd_pcm_set_sync(substream);
5899 runtime->hw = snd_hdspm_capture_subinfo;
5900
5901 if (hdspm->playback_substream == NULL)
5902 hdspm_stop_audio(hdspm);
5903
5904 hdspm->capture_pid = current->pid;
5905 hdspm->capture_substream = substream;
5906
5907 spin_unlock_irq(&hdspm->lock);
5908
5909 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5910 switch (hdspm->io_type) {
5911 case AIO:
5912 case RayDAT:
5913 snd_pcm_hw_constraint_list(runtime, 0,
5914 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5915 &hw_constraints_period_sizes_new);
5916 snd_pcm_hw_constraint_list(runtime, 0,
5917 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5918 &hw_constraints_raydat_io_buffer);
5919 break;
5920
5921 default:
5922 snd_pcm_hw_constraint_list(runtime, 0,
5923 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5924 &hw_constraints_period_sizes_old);
5925 }
5926
5927 if (AES32 == hdspm->io_type) {
5928 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5929 &hdspm_hw_constraints_aes32_sample_rates);
5930 } else {
5931 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5932 snd_hdspm_hw_rule_rate_in_channels, hdspm,
5933 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5934 }
5935
5936 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5937 snd_hdspm_hw_rule_in_channels, hdspm,
5938 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5939
5940 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5941 snd_hdspm_hw_rule_in_channels_rate, hdspm,
5942 SNDRV_PCM_HW_PARAM_RATE, -1);
5943
5944 return 0;
5945 }
5946
5947 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
5948 {
5949 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5950
5951 spin_lock_irq(&hdspm->lock);
5952
5953 hdspm->capture_pid = -1;
5954 hdspm->capture_substream = NULL;
5955
5956 spin_unlock_irq(&hdspm->lock);
5957 return 0;
5958 }
5959
5960 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
5961 {
5962 /* we have nothing to initialize but the call is required */
5963 return 0;
5964 }
5965
5966 static inline int copy_u32_le(void __user *dest, void __iomem *src)
5967 {
5968 u32 val = readl(src);
5969 return copy_to_user(dest, &val, 4);
5970 }
5971
5972 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
5973 unsigned int cmd, unsigned long __user arg)
5974 {
5975 void __user *argp = (void __user *)arg;
5976 struct hdspm *hdspm = hw->private_data;
5977 struct hdspm_mixer_ioctl mixer;
5978 struct hdspm_config info;
5979 struct hdspm_status status;
5980 struct hdspm_version hdspm_version;
5981 struct hdspm_peak_rms *levels;
5982 struct hdspm_ltc ltc;
5983 unsigned int statusregister;
5984 long unsigned int s;
5985 int i = 0;
5986
5987 switch (cmd) {
5988
5989 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
5990 levels = &hdspm->peak_rms;
5991 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
5992 levels->input_peaks[i] =
5993 readl(hdspm->iobase +
5994 HDSPM_MADI_INPUT_PEAK + i*4);
5995 levels->playback_peaks[i] =
5996 readl(hdspm->iobase +
5997 HDSPM_MADI_PLAYBACK_PEAK + i*4);
5998 levels->output_peaks[i] =
5999 readl(hdspm->iobase +
6000 HDSPM_MADI_OUTPUT_PEAK + i*4);
6001
6002 levels->input_rms[i] =
6003 ((uint64_t) readl(hdspm->iobase +
6004 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6005 (uint64_t) readl(hdspm->iobase +
6006 HDSPM_MADI_INPUT_RMS_L + i*4);
6007 levels->playback_rms[i] =
6008 ((uint64_t)readl(hdspm->iobase +
6009 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6010 (uint64_t)readl(hdspm->iobase +
6011 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6012 levels->output_rms[i] =
6013 ((uint64_t)readl(hdspm->iobase +
6014 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6015 (uint64_t)readl(hdspm->iobase +
6016 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6017 }
6018
6019 if (hdspm->system_sample_rate > 96000) {
6020 levels->speed = qs;
6021 } else if (hdspm->system_sample_rate > 48000) {
6022 levels->speed = ds;
6023 } else {
6024 levels->speed = ss;
6025 }
6026 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6027
6028 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6029 if (0 != s) {
6030 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6031 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6032 */
6033 return -EFAULT;
6034 }
6035 break;
6036
6037 case SNDRV_HDSPM_IOCTL_GET_LTC:
6038 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6039 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6040 if (i & HDSPM_TCO1_LTC_Input_valid) {
6041 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6042 HDSPM_TCO1_LTC_Format_MSB)) {
6043 case 0:
6044 ltc.format = fps_24;
6045 break;
6046 case HDSPM_TCO1_LTC_Format_LSB:
6047 ltc.format = fps_25;
6048 break;
6049 case HDSPM_TCO1_LTC_Format_MSB:
6050 ltc.format = fps_2997;
6051 break;
6052 default:
6053 ltc.format = 30;
6054 break;
6055 }
6056 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6057 ltc.frame = drop_frame;
6058 } else {
6059 ltc.frame = full_frame;
6060 }
6061 } else {
6062 ltc.format = format_invalid;
6063 ltc.frame = frame_invalid;
6064 }
6065 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6066 ltc.input_format = ntsc;
6067 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6068 ltc.input_format = pal;
6069 } else {
6070 ltc.input_format = no_video;
6071 }
6072
6073 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6074 if (0 != s) {
6075 /*
6076 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6077 return -EFAULT;
6078 }
6079
6080 break;
6081
6082 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6083
6084 memset(&info, 0, sizeof(info));
6085 spin_lock_irq(&hdspm->lock);
6086 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6087 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6088
6089 info.system_sample_rate = hdspm->system_sample_rate;
6090 info.autosync_sample_rate =
6091 hdspm_external_sample_rate(hdspm);
6092 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6093 info.clock_source = hdspm_clock_source(hdspm);
6094 info.autosync_ref = hdspm_autosync_ref(hdspm);
6095 info.line_out = hdspm_line_out(hdspm);
6096 info.passthru = 0;
6097 spin_unlock_irq(&hdspm->lock);
6098 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6099 return -EFAULT;
6100 break;
6101
6102 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6103 status.card_type = hdspm->io_type;
6104
6105 status.autosync_source = hdspm_autosync_ref(hdspm);
6106
6107 status.card_clock = 110069313433624ULL;
6108 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6109
6110 switch (hdspm->io_type) {
6111 case MADI:
6112 case MADIface:
6113 status.card_specific.madi.sync_wc =
6114 hdspm_wc_sync_check(hdspm);
6115 status.card_specific.madi.sync_madi =
6116 hdspm_madi_sync_check(hdspm);
6117 status.card_specific.madi.sync_tco =
6118 hdspm_tco_sync_check(hdspm);
6119 status.card_specific.madi.sync_in =
6120 hdspm_sync_in_sync_check(hdspm);
6121
6122 statusregister =
6123 hdspm_read(hdspm, HDSPM_statusRegister);
6124 status.card_specific.madi.madi_input =
6125 (statusregister & HDSPM_AB_int) ? 1 : 0;
6126 status.card_specific.madi.channel_format =
6127 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6128 /* TODO: Mac driver sets it when f_s>48kHz */
6129 status.card_specific.madi.frame_format = 0;
6130
6131 default:
6132 break;
6133 }
6134
6135 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6136 return -EFAULT;
6137
6138
6139 break;
6140
6141 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6142 hdspm_version.card_type = hdspm->io_type;
6143 strncpy(hdspm_version.cardname, hdspm->card_name,
6144 sizeof(hdspm_version.cardname));
6145 hdspm_version.serial = (hdspm_read(hdspm,
6146 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6147 hdspm_version.firmware_rev = hdspm->firmware_rev;
6148 hdspm_version.addons = 0;
6149 if (hdspm->tco)
6150 hdspm_version.addons |= HDSPM_ADDON_TCO;
6151
6152 if (copy_to_user((void __user *) arg, &hdspm_version,
6153 sizeof(hdspm_version)))
6154 return -EFAULT;
6155 break;
6156
6157 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6158 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6159 return -EFAULT;
6160 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6161 sizeof(struct hdspm_mixer)))
6162 return -EFAULT;
6163 break;
6164
6165 default:
6166 return -EINVAL;
6167 }
6168 return 0;
6169 }
6170
6171 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6172 .open = snd_hdspm_playback_open,
6173 .close = snd_hdspm_playback_release,
6174 .ioctl = snd_hdspm_ioctl,
6175 .hw_params = snd_hdspm_hw_params,
6176 .hw_free = snd_hdspm_hw_free,
6177 .prepare = snd_hdspm_prepare,
6178 .trigger = snd_hdspm_trigger,
6179 .pointer = snd_hdspm_hw_pointer,
6180 .page = snd_pcm_sgbuf_ops_page,
6181 };
6182
6183 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6184 .open = snd_hdspm_capture_open,
6185 .close = snd_hdspm_capture_release,
6186 .ioctl = snd_hdspm_ioctl,
6187 .hw_params = snd_hdspm_hw_params,
6188 .hw_free = snd_hdspm_hw_free,
6189 .prepare = snd_hdspm_prepare,
6190 .trigger = snd_hdspm_trigger,
6191 .pointer = snd_hdspm_hw_pointer,
6192 .page = snd_pcm_sgbuf_ops_page,
6193 };
6194
6195 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6196 struct hdspm * hdspm)
6197 {
6198 struct snd_hwdep *hw;
6199 int err;
6200
6201 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6202 if (err < 0)
6203 return err;
6204
6205 hdspm->hwdep = hw;
6206 hw->private_data = hdspm;
6207 strcpy(hw->name, "HDSPM hwdep interface");
6208
6209 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6210 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6211 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6212
6213 return 0;
6214 }
6215
6216
6217 /*------------------------------------------------------------
6218 memory interface
6219 ------------------------------------------------------------*/
6220 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6221 {
6222 int err;
6223 struct snd_pcm *pcm;
6224 size_t wanted;
6225
6226 pcm = hdspm->pcm;
6227
6228 wanted = HDSPM_DMA_AREA_BYTES;
6229
6230 err =
6231 snd_pcm_lib_preallocate_pages_for_all(pcm,
6232 SNDRV_DMA_TYPE_DEV_SG,
6233 snd_dma_pci_data(hdspm->pci),
6234 wanted,
6235 wanted);
6236 if (err < 0) {
6237 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6238
6239 return err;
6240 } else
6241 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6242
6243 return 0;
6244 }
6245
6246
6247 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6248 struct snd_pcm_substream *substream,
6249 unsigned int reg, int channels)
6250 {
6251 int i;
6252
6253 /* continuous memory segment */
6254 for (i = 0; i < (channels * 16); i++)
6255 hdspm_write(hdspm, reg + 4 * i,
6256 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6257 }
6258
6259
6260 /* ------------- ALSA Devices ---------------------------- */
6261 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6262 struct hdspm *hdspm)
6263 {
6264 struct snd_pcm *pcm;
6265 int err;
6266
6267 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6268 if (err < 0)
6269 return err;
6270
6271 hdspm->pcm = pcm;
6272 pcm->private_data = hdspm;
6273 strcpy(pcm->name, hdspm->card_name);
6274
6275 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6276 &snd_hdspm_playback_ops);
6277 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6278 &snd_hdspm_capture_ops);
6279
6280 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6281
6282 err = snd_hdspm_preallocate_memory(hdspm);
6283 if (err < 0)
6284 return err;
6285
6286 return 0;
6287 }
6288
6289 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6290 {
6291 snd_hdspm_flush_midi_input(hdspm, 0);
6292 snd_hdspm_flush_midi_input(hdspm, 1);
6293 }
6294
6295 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6296 struct hdspm * hdspm)
6297 {
6298 int err, i;
6299
6300 snd_printdd("Create card...\n");
6301 err = snd_hdspm_create_pcm(card, hdspm);
6302 if (err < 0)
6303 return err;
6304
6305 i = 0;
6306 while (i < hdspm->midiPorts) {
6307 err = snd_hdspm_create_midi(card, hdspm, i);
6308 if (err < 0) {
6309 return err;
6310 }
6311 i++;
6312 }
6313
6314 err = snd_hdspm_create_controls(card, hdspm);
6315 if (err < 0)
6316 return err;
6317
6318 err = snd_hdspm_create_hwdep(card, hdspm);
6319 if (err < 0)
6320 return err;
6321
6322 snd_printdd("proc init...\n");
6323 snd_hdspm_proc_init(hdspm);
6324
6325 hdspm->system_sample_rate = -1;
6326 hdspm->last_external_sample_rate = -1;
6327 hdspm->last_internal_sample_rate = -1;
6328 hdspm->playback_pid = -1;
6329 hdspm->capture_pid = -1;
6330 hdspm->capture_substream = NULL;
6331 hdspm->playback_substream = NULL;
6332
6333 snd_printdd("Set defaults...\n");
6334 err = snd_hdspm_set_defaults(hdspm);
6335 if (err < 0)
6336 return err;
6337
6338 snd_printdd("Update mixer controls...\n");
6339 hdspm_update_simple_mixer_controls(hdspm);
6340
6341 snd_printdd("Initializeing complete ???\n");
6342
6343 err = snd_card_register(card);
6344 if (err < 0) {
6345 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6346 return err;
6347 }
6348
6349 snd_printdd("... yes now\n");
6350
6351 return 0;
6352 }
6353
6354 static int __devinit snd_hdspm_create(struct snd_card *card,
6355 struct hdspm *hdspm) {
6356
6357 struct pci_dev *pci = hdspm->pci;
6358 int err;
6359 unsigned long io_extent;
6360
6361 hdspm->irq = -1;
6362 hdspm->card = card;
6363
6364 spin_lock_init(&hdspm->lock);
6365
6366 pci_read_config_word(hdspm->pci,
6367 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6368
6369 strcpy(card->mixername, "Xilinx FPGA");
6370 strcpy(card->driver, "HDSPM");
6371
6372 switch (hdspm->firmware_rev) {
6373 case HDSPM_MADI_REV:
6374 hdspm->io_type = MADI;
6375 hdspm->card_name = "RME MADI";
6376 hdspm->midiPorts = 3;
6377 break;
6378 case HDSPM_RAYDAT_REV:
6379 hdspm->io_type = RayDAT;
6380 hdspm->card_name = "RME RayDAT";
6381 hdspm->midiPorts = 2;
6382 break;
6383 case HDSPM_AIO_REV:
6384 hdspm->io_type = AIO;
6385 hdspm->card_name = "RME AIO";
6386 hdspm->midiPorts = 1;
6387 break;
6388 case HDSPM_MADIFACE_REV:
6389 hdspm->io_type = MADIface;
6390 hdspm->card_name = "RME MADIface";
6391 hdspm->midiPorts = 1;
6392 break;
6393 case HDSPM_AES_REV:
6394 hdspm->io_type = AES32;
6395 hdspm->card_name = "RME AES32";
6396 hdspm->midiPorts = 2;
6397 break;
6398 }
6399
6400 err = pci_enable_device(pci);
6401 if (err < 0)
6402 return err;
6403
6404 pci_set_master(hdspm->pci);
6405
6406 err = pci_request_regions(pci, "hdspm");
6407 if (err < 0)
6408 return err;
6409
6410 hdspm->port = pci_resource_start(pci, 0);
6411 io_extent = pci_resource_len(pci, 0);
6412
6413 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6414 hdspm->port, hdspm->port + io_extent - 1);
6415
6416 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6417 if (!hdspm->iobase) {
6418 snd_printk(KERN_ERR "HDSPM: "
6419 "unable to remap region 0x%lx-0x%lx\n",
6420 hdspm->port, hdspm->port + io_extent - 1);
6421 return -EBUSY;
6422 }
6423 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6424 (unsigned long)hdspm->iobase, hdspm->port,
6425 hdspm->port + io_extent - 1);
6426
6427 if (request_irq(pci->irq, snd_hdspm_interrupt,
6428 IRQF_SHARED, "hdspm", hdspm)) {
6429 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6430 return -EBUSY;
6431 }
6432
6433 snd_printdd("use IRQ %d\n", pci->irq);
6434
6435 hdspm->irq = pci->irq;
6436
6437 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6438 sizeof(struct hdspm_mixer));
6439 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6440 if (!hdspm->mixer) {
6441 snd_printk(KERN_ERR "HDSPM: "
6442 "unable to kmalloc Mixer memory of %d Bytes\n",
6443 (int)sizeof(struct hdspm_mixer));
6444 return err;
6445 }
6446
6447 hdspm->port_names_in = NULL;
6448 hdspm->port_names_out = NULL;
6449
6450 switch (hdspm->io_type) {
6451 case AES32:
6452 hdspm->ss_in_channels = hdspm->ss_out_channels = 16;
6453 hdspm->ds_in_channels = hdspm->ds_out_channels = 16;
6454 hdspm->qs_in_channels = hdspm->qs_out_channels = 16;
6455
6456 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6457 channel_map_aes32;
6458 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6459 channel_map_aes32;
6460 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6461 channel_map_aes32;
6462 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6463 texts_ports_aes32;
6464 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6465 texts_ports_aes32;
6466 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6467 texts_ports_aes32;
6468
6469 hdspm->max_channels_out = hdspm->max_channels_in = 16;
6470 hdspm->port_names_in = hdspm->port_names_out =
6471 texts_ports_aes32;
6472 hdspm->channel_map_in = hdspm->channel_map_out =
6473 channel_map_aes32;
6474
6475 break;
6476
6477 case MADI:
6478 case MADIface:
6479 hdspm->ss_in_channels = hdspm->ss_out_channels =
6480 MADI_SS_CHANNELS;
6481 hdspm->ds_in_channels = hdspm->ds_out_channels =
6482 MADI_DS_CHANNELS;
6483 hdspm->qs_in_channels = hdspm->qs_out_channels =
6484 MADI_QS_CHANNELS;
6485
6486 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6487 channel_map_unity_ss;
6488 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6489 channel_map_unity_ss;
6490 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6491 channel_map_unity_ss;
6492
6493 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6494 texts_ports_madi;
6495 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6496 texts_ports_madi;
6497 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6498 texts_ports_madi;
6499 break;
6500
6501 case AIO:
6502 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6503 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6504 }
6505
6506 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6507 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6508 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6509 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6510 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6511 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6512
6513 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6514 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6515 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6516
6517 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6518 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6519 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6520
6521 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6522 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6523 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6524 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6525 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6526 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6527
6528 break;
6529
6530 case RayDAT:
6531 hdspm->ss_in_channels = hdspm->ss_out_channels =
6532 RAYDAT_SS_CHANNELS;
6533 hdspm->ds_in_channels = hdspm->ds_out_channels =
6534 RAYDAT_DS_CHANNELS;
6535 hdspm->qs_in_channels = hdspm->qs_out_channels =
6536 RAYDAT_QS_CHANNELS;
6537
6538 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6539 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6540
6541 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6542 channel_map_raydat_ss;
6543 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6544 channel_map_raydat_ds;
6545 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6546 channel_map_raydat_qs;
6547 hdspm->channel_map_in = hdspm->channel_map_out =
6548 channel_map_raydat_ss;
6549
6550 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6551 texts_ports_raydat_ss;
6552 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6553 texts_ports_raydat_ds;
6554 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6555 texts_ports_raydat_qs;
6556
6557
6558 break;
6559
6560 }
6561
6562 /* TCO detection */
6563 switch (hdspm->io_type) {
6564 case AIO:
6565 case RayDAT:
6566 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6567 HDSPM_s2_tco_detect) {
6568 hdspm->midiPorts++;
6569 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6570 GFP_KERNEL);
6571 if (NULL != hdspm->tco) {
6572 hdspm_tco_write(hdspm);
6573 }
6574 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6575 } else {
6576 hdspm->tco = NULL;
6577 }
6578 break;
6579
6580 case MADI:
6581 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6582 hdspm->midiPorts++;
6583 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6584 GFP_KERNEL);
6585 if (NULL != hdspm->tco) {
6586 hdspm_tco_write(hdspm);
6587 }
6588 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6589 } else {
6590 hdspm->tco = NULL;
6591 }
6592 break;
6593
6594 default:
6595 hdspm->tco = NULL;
6596 }
6597
6598 /* texts */
6599 switch (hdspm->io_type) {
6600 case AES32:
6601 if (hdspm->tco) {
6602 hdspm->texts_autosync = texts_autosync_aes_tco;
6603 hdspm->texts_autosync_items = 10;
6604 } else {
6605 hdspm->texts_autosync = texts_autosync_aes;
6606 hdspm->texts_autosync_items = 9;
6607 }
6608 break;
6609
6610 case MADI:
6611 if (hdspm->tco) {
6612 hdspm->texts_autosync = texts_autosync_madi_tco;
6613 hdspm->texts_autosync_items = 4;
6614 } else {
6615 hdspm->texts_autosync = texts_autosync_madi;
6616 hdspm->texts_autosync_items = 3;
6617 }
6618 break;
6619
6620 case MADIface:
6621
6622 break;
6623
6624 case RayDAT:
6625 if (hdspm->tco) {
6626 hdspm->texts_autosync = texts_autosync_raydat_tco;
6627 hdspm->texts_autosync_items = 9;
6628 } else {
6629 hdspm->texts_autosync = texts_autosync_raydat;
6630 hdspm->texts_autosync_items = 8;
6631 }
6632 break;
6633
6634 case AIO:
6635 if (hdspm->tco) {
6636 hdspm->texts_autosync = texts_autosync_aio_tco;
6637 hdspm->texts_autosync_items = 6;
6638 } else {
6639 hdspm->texts_autosync = texts_autosync_aio;
6640 hdspm->texts_autosync_items = 5;
6641 }
6642 break;
6643
6644 }
6645
6646 tasklet_init(&hdspm->midi_tasklet,
6647 hdspm_midi_tasklet, (unsigned long) hdspm);
6648
6649 snd_printdd("create alsa devices.\n");
6650 err = snd_hdspm_create_alsa_devices(card, hdspm);
6651 if (err < 0)
6652 return err;
6653
6654 snd_hdspm_initialize_midi_flush(hdspm);
6655
6656 return 0;
6657 }
6658
6659
6660 static int snd_hdspm_free(struct hdspm * hdspm)
6661 {
6662
6663 if (hdspm->port) {
6664
6665 /* stop th audio, and cancel all interrupts */
6666 hdspm->control_register &=
6667 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6668 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6669 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6670 hdspm_write(hdspm, HDSPM_controlRegister,
6671 hdspm->control_register);
6672 }
6673
6674 if (hdspm->irq >= 0)
6675 free_irq(hdspm->irq, (void *) hdspm);
6676
6677 kfree(hdspm->mixer);
6678
6679 if (hdspm->iobase)
6680 iounmap(hdspm->iobase);
6681
6682 if (hdspm->port)
6683 pci_release_regions(hdspm->pci);
6684
6685 pci_disable_device(hdspm->pci);
6686 return 0;
6687 }
6688
6689
6690 static void snd_hdspm_card_free(struct snd_card *card)
6691 {
6692 struct hdspm *hdspm = card->private_data;
6693
6694 if (hdspm)
6695 snd_hdspm_free(hdspm);
6696 }
6697
6698
6699 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6700 const struct pci_device_id *pci_id)
6701 {
6702 static int dev;
6703 struct hdspm *hdspm;
6704 struct snd_card *card;
6705 int err;
6706
6707 if (dev >= SNDRV_CARDS)
6708 return -ENODEV;
6709 if (!enable[dev]) {
6710 dev++;
6711 return -ENOENT;
6712 }
6713
6714 err = snd_card_create(index[dev], id[dev],
6715 THIS_MODULE, sizeof(struct hdspm), &card);
6716 if (err < 0)
6717 return err;
6718
6719 hdspm = card->private_data;
6720 card->private_free = snd_hdspm_card_free;
6721 hdspm->dev = dev;
6722 hdspm->pci = pci;
6723
6724 snd_card_set_dev(card, &pci->dev);
6725
6726 err = snd_hdspm_create(card, hdspm);
6727 if (err < 0) {
6728 snd_card_free(card);
6729 return err;
6730 }
6731
6732 if (hdspm->io_type != MADIface) {
6733 sprintf(card->shortname, "%s_%x",
6734 hdspm->card_name,
6735 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6736 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6737 hdspm->card_name,
6738 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6739 hdspm->port, hdspm->irq);
6740 } else {
6741 sprintf(card->shortname, "%s", hdspm->card_name);
6742 sprintf(card->longname, "%s at 0x%lx, irq %d",
6743 hdspm->card_name, hdspm->port, hdspm->irq);
6744 }
6745
6746 err = snd_card_register(card);
6747 if (err < 0) {
6748 snd_card_free(card);
6749 return err;
6750 }
6751
6752 pci_set_drvdata(pci, card);
6753
6754 dev++;
6755 return 0;
6756 }
6757
6758 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6759 {
6760 snd_card_free(pci_get_drvdata(pci));
6761 pci_set_drvdata(pci, NULL);
6762 }
6763
6764 static struct pci_driver driver = {
6765 .name = "RME Hammerfall DSP MADI",
6766 .id_table = snd_hdspm_ids,
6767 .probe = snd_hdspm_probe,
6768 .remove = __devexit_p(snd_hdspm_remove),
6769 };
6770
6771
6772 static int __init alsa_card_hdspm_init(void)
6773 {
6774 return pci_register_driver(&driver);
6775 }
6776
6777 static void __exit alsa_card_hdspm_exit(void)
6778 {
6779 pci_unregister_driver(&driver);
6780 }
6781
6782 module_init(alsa_card_hdspm_init)
6783 module_exit(alsa_card_hdspm_exit)
Linux kernel - Deliverables
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