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Merge tag 'for-v3.12' of git://git.infradead.org/battery-2.6
[deliverable/linux.git] / sound / pci / rme9652 / hdspm.c
1 /*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
41
42 /* ************* Register Documentation *******************************************************
43 *
44 * Work in progress! Documentation is based on the code in this file.
45 *
46 * --------- HDSPM_controlRegister ---------
47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
48 * :||||.||||:||||.||||:||||.||||:||||.||||:
49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
51 * :||||.||||:||||.||||:||||.||||:||||.||||:
52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits
54 * : . : . : . : . x: HDSPM_Start / enables audio IO
55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave
56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency
57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512,
58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192
59 * :x . : . : . x:xx . : HDSPM_FrequencyMask
60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed
62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed
63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask :
64 * : . : . x: . : . : HDSPM_SyncRef0
65 * : . : . x : . : . : HDSPM_SyncRef1
66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2
67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3
68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT
71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1
73 * : . : .x : . : . : <MADI> HDSPM_clr_tms
74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch
75 * : . : . : . x : . : <AES32> HDSPM_Emphasis
76 * : . : . : .x : . : <MADI> HDSPM_AutoInp
77 * : . : . x : . : . : <MADI> HDSPM_SMUX
78 * : . : .x : . : . : <MADI> HDSPM_clr_tms
79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset
80 * : . x: . : . : . : <MADI> HDSPM_LineOut
81 * : . x: . : . : . : <AES32> ??????????????????
82 * : . : x. : . : . : <AES32> HDSPM_WCK48
83 * : . : . : .x : . : <AES32> HDSPM_Dolby
84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable
85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable
86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable
87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable
88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire
89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire
90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire
91 * : . : . : . x : . : <AES32> HDSPM_Professional
92 * : x . : . : . : . : HDSPM_wclk_sel
93 * : . : . : . : . :
94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
95 * :||||.||||:||||.||||:||||.||||:||||.||||:
96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
98 * :||||.||||:||||.||||:||||.||||:||||.||||:
99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
100 *
101 *
102 *
103 * AIO / RayDAT only
104 *
105 * ------------ HDSPM_WR_SETTINGS ----------
106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107 * :1098.7654:3210.9876:5432.1098:7654.3210:
108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110 * :||||.||||:||||.||||:||||.||||:||||.||||:
111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave
113 * : . : . : . : . x : HDSPM_c0_SyncRef0
114 * : . : . : . : . x : HDSPM_c0_SyncRef1
115 * : . : . : . : .x : HDSPM_c0_SyncRef2
116 * : . : . : . : x. : HDSPM_c0_SyncRef3
117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask:
118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119 * : . : . : . : . : 9:TCO, 10:SyncIn
120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121 * : . : . : . : . : 9:TCO, 10:SyncIn
122 * : . : . : . : . :
123 * : . : . : . : . :
124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125 * :1098.7654:3210.9876:5432.1098:7654.3210:
126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128 * :||||.||||:||||.||||:||||.||||:||||.||||:
129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
130 *
131 */
132 #include <linux/init.h>
133 #include <linux/delay.h>
134 #include <linux/interrupt.h>
135 #include <linux/module.h>
136 #include <linux/slab.h>
137 #include <linux/pci.h>
138 #include <linux/math64.h>
139 #include <asm/io.h>
140
141 #include <sound/core.h>
142 #include <sound/control.h>
143 #include <sound/pcm.h>
144 #include <sound/pcm_params.h>
145 #include <sound/info.h>
146 #include <sound/asoundef.h>
147 #include <sound/rawmidi.h>
148 #include <sound/hwdep.h>
149 #include <sound/initval.h>
150
151 #include <sound/hdspm.h>
152
153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
156
157 module_param_array(index, int, NULL, 0444);
158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
159
160 module_param_array(id, charp, NULL, 0444);
161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
162
163 module_param_array(enable, bool, NULL, 0444);
164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
165
166
167 MODULE_AUTHOR
168 (
169 "Winfried Ritsch <ritsch_AT_iem.at>, "
170 "Paul Davis <paul@linuxaudiosystems.com>, "
171 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
172 "Remy Bruno <remy.bruno@trinnov.com>, "
173 "Florian Faber <faberman@linuxproaudio.org>, "
174 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
175 );
176 MODULE_DESCRIPTION("RME HDSPM");
177 MODULE_LICENSE("GPL");
178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
179
180 /* --- Write registers. ---
181 These are defined as byte-offsets from the iobase value. */
182
183 #define HDSPM_WR_SETTINGS 0
184 #define HDSPM_outputBufferAddress 32
185 #define HDSPM_inputBufferAddress 36
186 #define HDSPM_controlRegister 64
187 #define HDSPM_interruptConfirmation 96
188 #define HDSPM_control2Reg 256 /* not in specs ???????? */
189 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */
190 #define HDSPM_midiDataOut0 352 /* just believe in old code */
191 #define HDSPM_midiDataOut1 356
192 #define HDSPM_eeprom_wr 384 /* for AES32 */
193
194 /* DMA enable for 64 channels, only Bit 0 is relevant */
195 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
196 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
197
198 /* 16 page addresses for each of the 64 channels DMA buffer in and out
199 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
200 #define HDSPM_pageAddressBufferOut 8192
201 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
202
203 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
204
205 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
206
207 /* --- Read registers. ---
208 These are defined as byte-offsets from the iobase value */
209 #define HDSPM_statusRegister 0
210 /*#define HDSPM_statusRegister2 96 */
211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
212 * offset 192, for AES32 *and* MADI
213 * => need to check that offset 192 is working on MADI */
214 #define HDSPM_statusRegister2 192
215 #define HDSPM_timecodeRegister 128
216
217 /* AIO, RayDAT */
218 #define HDSPM_RD_STATUS_0 0
219 #define HDSPM_RD_STATUS_1 64
220 #define HDSPM_RD_STATUS_2 128
221 #define HDSPM_RD_STATUS_3 192
222
223 #define HDSPM_RD_TCO 256
224 #define HDSPM_RD_PLL_FREQ 512
225 #define HDSPM_WR_TCO 128
226
227 #define HDSPM_TCO1_TCO_lock 0x00000001
228 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
229 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
230 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
231 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
232 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
233 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
234
235 #define HDSPM_TCO1_set_TC 0x00000100
236 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
237 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
238 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
239
240 #define HDSPM_TCO2_TC_run 0x00010000
241 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
242 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
243 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
244 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
245 #define HDSPM_TCO2_set_jam_sync 0x00200000
246 #define HDSPM_TCO2_set_flywheel 0x00400000
247
248 #define HDSPM_TCO2_set_01_4 0x01000000
249 #define HDSPM_TCO2_set_pull_down 0x02000000
250 #define HDSPM_TCO2_set_pull_up 0x04000000
251 #define HDSPM_TCO2_set_freq 0x08000000
252 #define HDSPM_TCO2_set_term_75R 0x10000000
253 #define HDSPM_TCO2_set_input_LSB 0x20000000
254 #define HDSPM_TCO2_set_input_MSB 0x40000000
255 #define HDSPM_TCO2_set_freq_from_app 0x80000000
256
257
258 #define HDSPM_midiDataOut0 352
259 #define HDSPM_midiDataOut1 356
260 #define HDSPM_midiDataOut2 368
261
262 #define HDSPM_midiDataIn0 360
263 #define HDSPM_midiDataIn1 364
264 #define HDSPM_midiDataIn2 372
265 #define HDSPM_midiDataIn3 376
266
267 /* status is data bytes in MIDI-FIFO (0-128) */
268 #define HDSPM_midiStatusOut0 384
269 #define HDSPM_midiStatusOut1 388
270 #define HDSPM_midiStatusOut2 400
271
272 #define HDSPM_midiStatusIn0 392
273 #define HDSPM_midiStatusIn1 396
274 #define HDSPM_midiStatusIn2 404
275 #define HDSPM_midiStatusIn3 408
276
277
278 /* the meters are regular i/o-mapped registers, but offset
279 considerably from the rest. the peak registers are reset
280 when read; the least-significant 4 bits are full-scale counters;
281 the actual peak value is in the most-significant 24 bits.
282 */
283
284 #define HDSPM_MADI_INPUT_PEAK 4096
285 #define HDSPM_MADI_PLAYBACK_PEAK 4352
286 #define HDSPM_MADI_OUTPUT_PEAK 4608
287
288 #define HDSPM_MADI_INPUT_RMS_L 6144
289 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
290 #define HDSPM_MADI_OUTPUT_RMS_L 6656
291
292 #define HDSPM_MADI_INPUT_RMS_H 7168
293 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
294 #define HDSPM_MADI_OUTPUT_RMS_H 7680
295
296 /* --- Control Register bits --------- */
297 #define HDSPM_Start (1<<0) /* start engine */
298
299 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
300 #define HDSPM_Latency1 (1<<2) /* where n is defined */
301 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
302
303 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
304 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
305 register [RayDAT, AIO] */
306
307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
308
309 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
310 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
311 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
312 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
313
314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
315 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
316 56channelMODE=0 */ /* MADI ONLY*/
317 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
318
319 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
320 0=off, 1=on */ /* MADI ONLY */
321 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
322
323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
324 * -- MADI ONLY
325 */
326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
327
328 #define HDSPM_SyncRef2 (1<<13)
329 #define HDSPM_SyncRef3 (1<<25)
330
331 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
332 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
333 AES additional bits in
334 lower 5 Audiodatabits ??? */
335 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
336 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
337
338 #define HDSPM_Midi0InterruptEnable 0x0400000
339 #define HDSPM_Midi1InterruptEnable 0x0800000
340 #define HDSPM_Midi2InterruptEnable 0x0200000
341 #define HDSPM_Midi3InterruptEnable 0x4000000
342
343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
344 #define HDSPe_FLOAT_FORMAT 0x2000000
345
346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
348 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
349
350 #define HDSPM_wclk_sel (1<<30)
351
352 /* additional control register bits for AIO*/
353 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */
354 #define HDSPM_c0_Input0 0x1000
355 #define HDSPM_c0_Input1 0x2000
356 #define HDSPM_c0_Spdif_Opt 0x4000
357 #define HDSPM_c0_Pro 0x8000
358 #define HDSPM_c0_clr_tms 0x10000
359 #define HDSPM_c0_AEB1 0x20000
360 #define HDSPM_c0_AEB2 0x40000
361 #define HDSPM_c0_LineOut 0x80000
362 #define HDSPM_c0_AD_GAIN0 0x100000
363 #define HDSPM_c0_AD_GAIN1 0x200000
364 #define HDSPM_c0_DA_GAIN0 0x400000
365 #define HDSPM_c0_DA_GAIN1 0x800000
366 #define HDSPM_c0_PH_GAIN0 0x1000000
367 #define HDSPM_c0_PH_GAIN1 0x2000000
368 #define HDSPM_c0_Sym6db 0x4000000
369
370
371 /* --- bit helper defines */
372 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
373 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
374 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
375 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
376 #define HDSPM_InputOptical 0
377 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
378 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
379 HDSPM_SyncRef2|HDSPM_SyncRef3)
380
381 #define HDSPM_c0_SyncRef0 0x2
382 #define HDSPM_c0_SyncRef1 0x4
383 #define HDSPM_c0_SyncRef2 0x8
384 #define HDSPM_c0_SyncRef3 0x10
385 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
386 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
387
388 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
389 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
390 #define HDSPM_SYNC_FROM_TCO 2
391 #define HDSPM_SYNC_FROM_SYNC_IN 3
392
393 #define HDSPM_Frequency32KHz HDSPM_Frequency0
394 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
395 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
396 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
398 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
399 HDSPM_Frequency0)
400 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
401 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
402 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
403 HDSPM_Frequency0)
404
405
406 /* Synccheck Status */
407 #define HDSPM_SYNC_CHECK_NO_LOCK 0
408 #define HDSPM_SYNC_CHECK_LOCK 1
409 #define HDSPM_SYNC_CHECK_SYNC 2
410
411 /* AutoSync References - used by "autosync_ref" control switch */
412 #define HDSPM_AUTOSYNC_FROM_WORD 0
413 #define HDSPM_AUTOSYNC_FROM_MADI 1
414 #define HDSPM_AUTOSYNC_FROM_TCO 2
415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
416 #define HDSPM_AUTOSYNC_FROM_NONE 4
417
418 /* Possible sources of MADI input */
419 #define HDSPM_OPTICAL 0 /* optical */
420 #define HDSPM_COAXIAL 1 /* BNC */
421
422 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
423 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
424
425 #define hdspm_encode_in(x) (((x)&0x3)<<14)
426 #define hdspm_decode_in(x) (((x)>>14)&0x3)
427
428 /* --- control2 register bits --- */
429 #define HDSPM_TMS (1<<0)
430 #define HDSPM_TCK (1<<1)
431 #define HDSPM_TDI (1<<2)
432 #define HDSPM_JTAG (1<<3)
433 #define HDSPM_PWDN (1<<4)
434 #define HDSPM_PROGRAM (1<<5)
435 #define HDSPM_CONFIG_MODE_0 (1<<6)
436 #define HDSPM_CONFIG_MODE_1 (1<<7)
437 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
438 #define HDSPM_BIGENDIAN_MODE (1<<9)
439 #define HDSPM_RD_MULTIPLE (1<<10)
440
441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
442 that do not conflict with specific bits for AES32 seem to be valid also
443 for the AES32
444 */
445 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
446 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
447 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
448 * (like inp0)
449 */
450
451 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
452 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
453
454 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/
455 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
456
457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
459
460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
461 /* since 64byte accurate, last 6 bits are not used */
462
463
464
465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
466
467 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
468 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
469 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
470 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
471
472 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
473 * Interrupt
474 */
475 #define HDSPM_tco_detect 0x08000000
476 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */
477
478 #define HDSPM_s2_tco_detect 0x00000040
479 #define HDSPM_s2_AEBO_D 0x00000080
480 #define HDSPM_s2_AEBI_D 0x00000100
481
482
483 #define HDSPM_midi0IRQPending 0x40000000
484 #define HDSPM_midi1IRQPending 0x80000000
485 #define HDSPM_midi2IRQPending 0x20000000
486 #define HDSPM_midi2IRQPendingAES 0x00000020
487 #define HDSPM_midi3IRQPending 0x00200000
488
489 /* --- status bit helpers */
490 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
491 HDSPM_madiFreq2|HDSPM_madiFreq3)
492 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
493 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
494 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
495 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
496 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
497 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
498 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
500 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
501
502 /* Status2 Register bits */ /* MADI ONLY */
503
504 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
505 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
506 #define HDSPM_version2 (1<<2)
507
508 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
509 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
510
511 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
512 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
513 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */
514 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */
515
516 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
517 #define HDSPM_SyncRef1 0x20000
518
519 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
520 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
521 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
522
523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
524
525 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
526 HDSPM_wc_freq3)
527 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
528 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
529 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
530 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
531 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
532 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
533 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
535 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3)
536
537 #define HDSPM_status1_F_0 0x0400000
538 #define HDSPM_status1_F_1 0x0800000
539 #define HDSPM_status1_F_2 0x1000000
540 #define HDSPM_status1_F_3 0x2000000
541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
542
543
544 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
545 HDSPM_SelSyncRef2)
546 #define HDSPM_SelSyncRef_WORD 0
547 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
548 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
549 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
550 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
551 HDSPM_SelSyncRef2)
552
553 /*
554 For AES32, bits for status, status2 and timecode are different
555 */
556 /* status */
557 #define HDSPM_AES32_wcLock 0x0200000
558 #define HDSPM_AES32_wcSync 0x0100000
559 #define HDSPM_AES32_wcFreq_bit 22
560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
561 HDSPM_bit2freq */
562 #define HDSPM_AES32_syncref_bit 16
563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
564
565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
577
578 /* status2 */
579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
580 #define HDSPM_LockAES 0x80
581 #define HDSPM_LockAES1 0x80
582 #define HDSPM_LockAES2 0x40
583 #define HDSPM_LockAES3 0x20
584 #define HDSPM_LockAES4 0x10
585 #define HDSPM_LockAES5 0x8
586 #define HDSPM_LockAES6 0x4
587 #define HDSPM_LockAES7 0x2
588 #define HDSPM_LockAES8 0x1
589 /*
590 Timecode
591 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
592 AES i+1
593 bits 3210
594 0001 32kHz
595 0010 44.1kHz
596 0011 48kHz
597 0100 64kHz
598 0101 88.2kHz
599 0110 96kHz
600 0111 128kHz
601 1000 176.4kHz
602 1001 192kHz
603 NB: Timecode register doesn't seem to work on AES32 card revision 230
604 */
605
606 /* Mixer Values */
607 #define UNITY_GAIN 32768 /* = 65536/2 */
608 #define MINUS_INFINITY_GAIN 0
609
610 /* Number of channels for different Speed Modes */
611 #define MADI_SS_CHANNELS 64
612 #define MADI_DS_CHANNELS 32
613 #define MADI_QS_CHANNELS 16
614
615 #define RAYDAT_SS_CHANNELS 36
616 #define RAYDAT_DS_CHANNELS 20
617 #define RAYDAT_QS_CHANNELS 12
618
619 #define AIO_IN_SS_CHANNELS 14
620 #define AIO_IN_DS_CHANNELS 10
621 #define AIO_IN_QS_CHANNELS 8
622 #define AIO_OUT_SS_CHANNELS 16
623 #define AIO_OUT_DS_CHANNELS 12
624 #define AIO_OUT_QS_CHANNELS 10
625
626 #define AES32_CHANNELS 16
627
628 /* the size of a substream (1 mono data stream) */
629 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
630 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
631
632 /* the size of the area we need to allocate for DMA transfers. the
633 size is the same regardless of the number of channels, and
634 also the latency to use.
635 for one direction !!!
636 */
637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
639
640 #define HDSPM_RAYDAT_REV 211
641 #define HDSPM_AIO_REV 212
642 #define HDSPM_MADIFACE_REV 213
643
644 /* speed factor modes */
645 #define HDSPM_SPEED_SINGLE 0
646 #define HDSPM_SPEED_DOUBLE 1
647 #define HDSPM_SPEED_QUAD 2
648
649 /* names for speed modes */
650 static char *hdspm_speed_names[] = { "single", "double", "quad" };
651
652 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
653 "AES1", "AES2", "AES3", "AES4",
654 "AES5", "AES6", "AES7", "AES8",
655 "TCO", "Sync In"
656 };
657 static const char *const texts_autosync_aes[] = { "Word Clock",
658 "AES1", "AES2", "AES3", "AES4",
659 "AES5", "AES6", "AES7", "AES8",
660 "Sync In"
661 };
662 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
663 "MADI", "TCO", "Sync In" };
664 static const char *const texts_autosync_madi[] = { "Word Clock",
665 "MADI", "Sync In" };
666
667 static const char *const texts_autosync_raydat_tco[] = {
668 "Word Clock",
669 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
670 "AES", "SPDIF", "TCO", "Sync In"
671 };
672 static const char *const texts_autosync_raydat[] = {
673 "Word Clock",
674 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
675 "AES", "SPDIF", "Sync In"
676 };
677 static const char *const texts_autosync_aio_tco[] = {
678 "Word Clock",
679 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
680 };
681 static const char *const texts_autosync_aio[] = { "Word Clock",
682 "ADAT", "AES", "SPDIF", "Sync In" };
683
684 static const char *const texts_freq[] = {
685 "No Lock",
686 "32 kHz",
687 "44.1 kHz",
688 "48 kHz",
689 "64 kHz",
690 "88.2 kHz",
691 "96 kHz",
692 "128 kHz",
693 "176.4 kHz",
694 "192 kHz"
695 };
696
697 static char *texts_ports_madi[] = {
698 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
699 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
700 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
701 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
702 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
703 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
704 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
705 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
706 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
707 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
708 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
709 };
710
711
712 static char *texts_ports_raydat_ss[] = {
713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
714 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
716 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
718 "ADAT4.7", "ADAT4.8",
719 "AES.L", "AES.R",
720 "SPDIF.L", "SPDIF.R"
721 };
722
723 static char *texts_ports_raydat_ds[] = {
724 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
725 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
726 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
727 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
728 "AES.L", "AES.R",
729 "SPDIF.L", "SPDIF.R"
730 };
731
732 static char *texts_ports_raydat_qs[] = {
733 "ADAT1.1", "ADAT1.2",
734 "ADAT2.1", "ADAT2.2",
735 "ADAT3.1", "ADAT3.2",
736 "ADAT4.1", "ADAT4.2",
737 "AES.L", "AES.R",
738 "SPDIF.L", "SPDIF.R"
739 };
740
741
742 static char *texts_ports_aio_in_ss[] = {
743 "Analogue.L", "Analogue.R",
744 "AES.L", "AES.R",
745 "SPDIF.L", "SPDIF.R",
746 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
747 "ADAT.7", "ADAT.8",
748 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
749 };
750
751 static char *texts_ports_aio_out_ss[] = {
752 "Analogue.L", "Analogue.R",
753 "AES.L", "AES.R",
754 "SPDIF.L", "SPDIF.R",
755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
756 "ADAT.7", "ADAT.8",
757 "Phone.L", "Phone.R",
758 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
759 };
760
761 static char *texts_ports_aio_in_ds[] = {
762 "Analogue.L", "Analogue.R",
763 "AES.L", "AES.R",
764 "SPDIF.L", "SPDIF.R",
765 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
766 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
767 };
768
769 static char *texts_ports_aio_out_ds[] = {
770 "Analogue.L", "Analogue.R",
771 "AES.L", "AES.R",
772 "SPDIF.L", "SPDIF.R",
773 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
774 "Phone.L", "Phone.R",
775 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
776 };
777
778 static char *texts_ports_aio_in_qs[] = {
779 "Analogue.L", "Analogue.R",
780 "AES.L", "AES.R",
781 "SPDIF.L", "SPDIF.R",
782 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
783 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
784 };
785
786 static char *texts_ports_aio_out_qs[] = {
787 "Analogue.L", "Analogue.R",
788 "AES.L", "AES.R",
789 "SPDIF.L", "SPDIF.R",
790 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
791 "Phone.L", "Phone.R",
792 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
793 };
794
795 static char *texts_ports_aes32[] = {
796 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
797 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
798 "AES.15", "AES.16"
799 };
800
801 /* These tables map the ALSA channels 1..N to the channels that we
802 need to use in order to find the relevant channel buffer. RME
803 refers to this kind of mapping as between "the ADAT channel and
804 the DMA channel." We index it using the logical audio channel,
805 and the value is the DMA channel (i.e. channel buffer number)
806 where the data for that channel can be read/written from/to.
807 */
808
809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
810 0, 1, 2, 3, 4, 5, 6, 7,
811 8, 9, 10, 11, 12, 13, 14, 15,
812 16, 17, 18, 19, 20, 21, 22, 23,
813 24, 25, 26, 27, 28, 29, 30, 31,
814 32, 33, 34, 35, 36, 37, 38, 39,
815 40, 41, 42, 43, 44, 45, 46, 47,
816 48, 49, 50, 51, 52, 53, 54, 55,
817 56, 57, 58, 59, 60, 61, 62, 63
818 };
819
820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
821 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
822 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
823 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
824 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
825 0, 1, /* AES */
826 2, 3, /* SPDIF */
827 -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 };
832
833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
834 4, 5, 6, 7, /* ADAT 1 */
835 8, 9, 10, 11, /* ADAT 2 */
836 12, 13, 14, 15, /* ADAT 3 */
837 16, 17, 18, 19, /* ADAT 4 */
838 0, 1, /* AES */
839 2, 3, /* SPDIF */
840 -1, -1, -1, -1,
841 -1, -1, -1, -1, -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1, -1, -1, -1, -1,
845 -1, -1, -1, -1, -1, -1, -1, -1,
846 };
847
848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
849 4, 5, /* ADAT 1 */
850 6, 7, /* ADAT 2 */
851 8, 9, /* ADAT 3 */
852 10, 11, /* ADAT 4 */
853 0, 1, /* AES */
854 2, 3, /* SPDIF */
855 -1, -1, -1, -1,
856 -1, -1, -1, -1, -1, -1, -1, -1,
857 -1, -1, -1, -1, -1, -1, -1, -1,
858 -1, -1, -1, -1, -1, -1, -1, -1,
859 -1, -1, -1, -1, -1, -1, -1, -1,
860 -1, -1, -1, -1, -1, -1, -1, -1,
861 -1, -1, -1, -1, -1, -1, -1, -1,
862 };
863
864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
865 0, 1, /* line in */
866 8, 9, /* aes in, */
867 10, 11, /* spdif in */
868 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
869 2, 3, 4, 5, /* AEB */
870 -1, -1, -1, -1, -1, -1,
871 -1, -1, -1, -1, -1, -1, -1, -1,
872 -1, -1, -1, -1, -1, -1, -1, -1,
873 -1, -1, -1, -1, -1, -1, -1, -1,
874 -1, -1, -1, -1, -1, -1, -1, -1,
875 -1, -1, -1, -1, -1, -1, -1, -1,
876 };
877
878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
879 0, 1, /* line out */
880 8, 9, /* aes out */
881 10, 11, /* spdif out */
882 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
883 6, 7, /* phone out */
884 2, 3, 4, 5, /* AEB */
885 -1, -1, -1, -1,
886 -1, -1, -1, -1, -1, -1, -1, -1,
887 -1, -1, -1, -1, -1, -1, -1, -1,
888 -1, -1, -1, -1, -1, -1, -1, -1,
889 -1, -1, -1, -1, -1, -1, -1, -1,
890 -1, -1, -1, -1, -1, -1, -1, -1,
891 };
892
893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
894 0, 1, /* line in */
895 8, 9, /* aes in */
896 10, 11, /* spdif in */
897 12, 14, 16, 18, /* adat in */
898 2, 3, 4, 5, /* AEB */
899 -1, -1,
900 -1, -1, -1, -1, -1, -1, -1, -1,
901 -1, -1, -1, -1, -1, -1, -1, -1,
902 -1, -1, -1, -1, -1, -1, -1, -1,
903 -1, -1, -1, -1, -1, -1, -1, -1,
904 -1, -1, -1, -1, -1, -1, -1, -1,
905 -1, -1, -1, -1, -1, -1, -1, -1
906 };
907
908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
909 0, 1, /* line out */
910 8, 9, /* aes out */
911 10, 11, /* spdif out */
912 12, 14, 16, 18, /* adat out */
913 6, 7, /* phone out */
914 2, 3, 4, 5, /* AEB */
915 -1, -1, -1, -1, -1, -1, -1, -1,
916 -1, -1, -1, -1, -1, -1, -1, -1,
917 -1, -1, -1, -1, -1, -1, -1, -1,
918 -1, -1, -1, -1, -1, -1, -1, -1,
919 -1, -1, -1, -1, -1, -1, -1, -1,
920 -1, -1, -1, -1, -1, -1, -1, -1
921 };
922
923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
924 0, 1, /* line in */
925 8, 9, /* aes in */
926 10, 11, /* spdif in */
927 12, 16, /* adat in */
928 2, 3, 4, 5, /* AEB */
929 -1, -1, -1, -1,
930 -1, -1, -1, -1, -1, -1, -1, -1,
931 -1, -1, -1, -1, -1, -1, -1, -1,
932 -1, -1, -1, -1, -1, -1, -1, -1,
933 -1, -1, -1, -1, -1, -1, -1, -1,
934 -1, -1, -1, -1, -1, -1, -1, -1,
935 -1, -1, -1, -1, -1, -1, -1, -1
936 };
937
938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
939 0, 1, /* line out */
940 8, 9, /* aes out */
941 10, 11, /* spdif out */
942 12, 16, /* adat out */
943 6, 7, /* phone out */
944 2, 3, 4, 5, /* AEB */
945 -1, -1,
946 -1, -1, -1, -1, -1, -1, -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, -1, -1, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1
952 };
953
954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
955 0, 1, 2, 3, 4, 5, 6, 7,
956 8, 9, 10, 11, 12, 13, 14, 15,
957 -1, -1, -1, -1, -1, -1, -1, -1,
958 -1, -1, -1, -1, -1, -1, -1, -1,
959 -1, -1, -1, -1, -1, -1, -1, -1,
960 -1, -1, -1, -1, -1, -1, -1, -1,
961 -1, -1, -1, -1, -1, -1, -1, -1,
962 -1, -1, -1, -1, -1, -1, -1, -1
963 };
964
965 struct hdspm_midi {
966 struct hdspm *hdspm;
967 int id;
968 struct snd_rawmidi *rmidi;
969 struct snd_rawmidi_substream *input;
970 struct snd_rawmidi_substream *output;
971 char istimer; /* timer in use */
972 struct timer_list timer;
973 spinlock_t lock;
974 int pending;
975 int dataIn;
976 int statusIn;
977 int dataOut;
978 int statusOut;
979 int ie;
980 int irq;
981 };
982
983 struct hdspm_tco {
984 int input; /* 0: LTC, 1:Video, 2: WC*/
985 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
986 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
987 int samplerate; /* 0=44.1, 1=48, 2= freq from app */
988 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
989 int term; /* 0 = off, 1 = on */
990 };
991
992 struct hdspm {
993 spinlock_t lock;
994 /* only one playback and/or capture stream */
995 struct snd_pcm_substream *capture_substream;
996 struct snd_pcm_substream *playback_substream;
997
998 char *card_name; /* for procinfo */
999 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1000
1001 uint8_t io_type;
1002
1003 int monitor_outs; /* set up monitoring outs init flag */
1004
1005 u32 control_register; /* cached value */
1006 u32 control2_register; /* cached value */
1007 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */
1008
1009 struct hdspm_midi midi[4];
1010 struct tasklet_struct midi_tasklet;
1011
1012 size_t period_bytes;
1013 unsigned char ss_in_channels;
1014 unsigned char ds_in_channels;
1015 unsigned char qs_in_channels;
1016 unsigned char ss_out_channels;
1017 unsigned char ds_out_channels;
1018 unsigned char qs_out_channels;
1019
1020 unsigned char max_channels_in;
1021 unsigned char max_channels_out;
1022
1023 signed char *channel_map_in;
1024 signed char *channel_map_out;
1025
1026 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1028
1029 char **port_names_in;
1030 char **port_names_out;
1031
1032 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1034
1035 unsigned char *playback_buffer; /* suitably aligned address */
1036 unsigned char *capture_buffer; /* suitably aligned address */
1037
1038 pid_t capture_pid; /* process id which uses capture */
1039 pid_t playback_pid; /* process id which uses capture */
1040 int running; /* running status */
1041
1042 int last_external_sample_rate; /* samplerate mystic ... */
1043 int last_internal_sample_rate;
1044 int system_sample_rate;
1045
1046 int dev; /* Hardware vars... */
1047 int irq;
1048 unsigned long port;
1049 void __iomem *iobase;
1050
1051 int irq_count; /* for debug */
1052 int midiPorts;
1053
1054 struct snd_card *card; /* one card */
1055 struct snd_pcm *pcm; /* has one pcm */
1056 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
1057 struct pci_dev *pci; /* and an pci info */
1058
1059 /* Mixer vars */
1060 /* fast alsa mixer */
1061 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062 /* but input to much, so not used */
1063 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1064 /* full mixer accessible over mixer ioctl or hwdep-device */
1065 struct hdspm_mixer *mixer;
1066
1067 struct hdspm_tco *tco; /* NULL if no TCO detected */
1068
1069 const char *const *texts_autosync;
1070 int texts_autosync_items;
1071
1072 cycles_t last_interrupt;
1073
1074 unsigned int serial;
1075
1076 struct hdspm_peak_rms peak_rms;
1077 };
1078
1079
1080 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
1081 {
1082 .vendor = PCI_VENDOR_ID_XILINX,
1083 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084 .subvendor = PCI_ANY_ID,
1085 .subdevice = PCI_ANY_ID,
1086 .class = 0,
1087 .class_mask = 0,
1088 .driver_data = 0},
1089 {0,}
1090 };
1091
1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1093
1094 /* prototypes */
1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096 struct hdspm *hdspm);
1097 static int snd_hdspm_create_pcm(struct snd_card *card,
1098 struct hdspm *hdspm);
1099
1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103 static int hdspm_autosync_ref(struct hdspm *hdspm);
1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1106 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1107 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1108 struct snd_pcm_substream *substream,
1109 unsigned int reg, int channels);
1110
1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1115
1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1119
1120
1121
1122 static inline int HDSPM_bit2freq(int n)
1123 {
1124 static const int bit2freq_tab[] = {
1125 0, 32000, 44100, 48000, 64000, 88200,
1126 96000, 128000, 176400, 192000 };
1127 if (n < 1 || n > 9)
1128 return 0;
1129 return bit2freq_tab[n];
1130 }
1131
1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1133 {
1134 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1135 }
1136
1137
1138 /* Write/read to/from HDSPM with Adresses in Bytes
1139 not words but only 32Bit writes are allowed */
1140
1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1142 unsigned int val)
1143 {
1144 writel(val, hdspm->iobase + reg);
1145 }
1146
1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1148 {
1149 return readl(hdspm->iobase + reg);
1150 }
1151
1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153 mixer is write only on hardware so we have to cache him for read
1154 each fader is a u32, but uses only the first 16 bit */
1155
1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1157 unsigned int in)
1158 {
1159 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1160 return 0;
1161
1162 return hdspm->mixer->ch[chan].in[in];
1163 }
1164
1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1166 unsigned int pb)
1167 {
1168 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1169 return 0;
1170 return hdspm->mixer->ch[chan].pb[pb];
1171 }
1172
1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1174 unsigned int in, unsigned short data)
1175 {
1176 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1177 return -1;
1178
1179 hdspm_write(hdspm,
1180 HDSPM_MADI_mixerBase +
1181 ((in + 128 * chan) * sizeof(u32)),
1182 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183 return 0;
1184 }
1185
1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1187 unsigned int pb, unsigned short data)
1188 {
1189 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1190 return -1;
1191
1192 hdspm_write(hdspm,
1193 HDSPM_MADI_mixerBase +
1194 ((64 + pb + 128 * chan) * sizeof(u32)),
1195 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1196 return 0;
1197 }
1198
1199
1200 /* enable DMA for specific channels, now available for DSP-MADI */
1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1202 {
1203 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1204 }
1205
1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1207 {
1208 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1209 }
1210
1211 /* check if same process is writing and reading */
1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1213 {
1214 unsigned long flags;
1215 int ret = 1;
1216
1217 spin_lock_irqsave(&hdspm->lock, flags);
1218 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1220 ret = 0;
1221 }
1222 spin_unlock_irqrestore(&hdspm->lock, flags);
1223 return ret;
1224 }
1225
1226 /* round arbitary sample rates to commonly known rates */
1227 static int hdspm_round_frequency(int rate)
1228 {
1229 if (rate < 38050)
1230 return 32000;
1231 if (rate < 46008)
1232 return 44100;
1233 else
1234 return 48000;
1235 }
1236
1237 /* QS and DS rates normally can not be detected
1238 * automatically by the card. Only exception is MADI
1239 * in 96k frame mode.
1240 *
1241 * So if we read SS values (32 .. 48k), check for
1242 * user-provided DS/QS bits in the control register
1243 * and multiply the base frequency accordingly.
1244 */
1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1246 {
1247 if (rate <= 48000) {
1248 if (hdspm->control_register & HDSPM_QuadSpeed)
1249 return rate * 4;
1250 else if (hdspm->control_register &
1251 HDSPM_DoubleSpeed)
1252 return rate * 2;
1253 }
1254 return rate;
1255 }
1256
1257 /* check for external sample rate, returns the sample rate in Hz*/
1258 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1259 {
1260 unsigned int status, status2, timecode;
1261 int syncref, rate = 0, rate_bits;
1262
1263 switch (hdspm->io_type) {
1264 case AES32:
1265 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266 status = hdspm_read(hdspm, HDSPM_statusRegister);
1267 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1268
1269 syncref = hdspm_autosync_ref(hdspm);
1270 switch (syncref) {
1271 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1272 /* Check WC sync and get sample rate */
1273 if (hdspm_wc_sync_check(hdspm))
1274 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1275 break;
1276
1277 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1278 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1279 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1280 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1281 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1282 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1283 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1284 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1285 /* Check AES sync and get sample rate */
1286 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1287 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1288 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1289 break;
1290
1291
1292 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1293 /* Check TCO sync and get sample rate */
1294 if (hdspm_tco_sync_check(hdspm))
1295 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1296 break;
1297 default:
1298 return 0;
1299 } /* end switch(syncref) */
1300 break;
1301
1302 case MADIface:
1303 status = hdspm_read(hdspm, HDSPM_statusRegister);
1304
1305 if (!(status & HDSPM_madiLock)) {
1306 rate = 0; /* no lock */
1307 } else {
1308 switch (status & (HDSPM_status1_freqMask)) {
1309 case HDSPM_status1_F_0*1:
1310 rate = 32000; break;
1311 case HDSPM_status1_F_0*2:
1312 rate = 44100; break;
1313 case HDSPM_status1_F_0*3:
1314 rate = 48000; break;
1315 case HDSPM_status1_F_0*4:
1316 rate = 64000; break;
1317 case HDSPM_status1_F_0*5:
1318 rate = 88200; break;
1319 case HDSPM_status1_F_0*6:
1320 rate = 96000; break;
1321 case HDSPM_status1_F_0*7:
1322 rate = 128000; break;
1323 case HDSPM_status1_F_0*8:
1324 rate = 176400; break;
1325 case HDSPM_status1_F_0*9:
1326 rate = 192000; break;
1327 default:
1328 rate = 0; break;
1329 }
1330 }
1331
1332 break;
1333
1334 case MADI:
1335 case AIO:
1336 case RayDAT:
1337 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1338 status = hdspm_read(hdspm, HDSPM_statusRegister);
1339 rate = 0;
1340
1341 /* if wordclock has synced freq and wordclock is valid */
1342 if ((status2 & HDSPM_wcLock) != 0 &&
1343 (status2 & HDSPM_SelSyncRef0) == 0) {
1344
1345 rate_bits = status2 & HDSPM_wcFreqMask;
1346
1347
1348 switch (rate_bits) {
1349 case HDSPM_wcFreq32:
1350 rate = 32000;
1351 break;
1352 case HDSPM_wcFreq44_1:
1353 rate = 44100;
1354 break;
1355 case HDSPM_wcFreq48:
1356 rate = 48000;
1357 break;
1358 case HDSPM_wcFreq64:
1359 rate = 64000;
1360 break;
1361 case HDSPM_wcFreq88_2:
1362 rate = 88200;
1363 break;
1364 case HDSPM_wcFreq96:
1365 rate = 96000;
1366 break;
1367 case HDSPM_wcFreq128:
1368 rate = 128000;
1369 break;
1370 case HDSPM_wcFreq176_4:
1371 rate = 176400;
1372 break;
1373 case HDSPM_wcFreq192:
1374 rate = 192000;
1375 break;
1376 default:
1377 rate = 0;
1378 break;
1379 }
1380 }
1381
1382 /* if rate detected and Syncref is Word than have it,
1383 * word has priority to MADI
1384 */
1385 if (rate != 0 &&
1386 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1387 return hdspm_rate_multiplier(hdspm, rate);
1388
1389 /* maybe a madi input (which is taken if sel sync is madi) */
1390 if (status & HDSPM_madiLock) {
1391 rate_bits = status & HDSPM_madiFreqMask;
1392
1393 switch (rate_bits) {
1394 case HDSPM_madiFreq32:
1395 rate = 32000;
1396 break;
1397 case HDSPM_madiFreq44_1:
1398 rate = 44100;
1399 break;
1400 case HDSPM_madiFreq48:
1401 rate = 48000;
1402 break;
1403 case HDSPM_madiFreq64:
1404 rate = 64000;
1405 break;
1406 case HDSPM_madiFreq88_2:
1407 rate = 88200;
1408 break;
1409 case HDSPM_madiFreq96:
1410 rate = 96000;
1411 break;
1412 case HDSPM_madiFreq128:
1413 rate = 128000;
1414 break;
1415 case HDSPM_madiFreq176_4:
1416 rate = 176400;
1417 break;
1418 case HDSPM_madiFreq192:
1419 rate = 192000;
1420 break;
1421 default:
1422 rate = 0;
1423 break;
1424 }
1425
1426 } /* endif HDSPM_madiLock */
1427
1428 /* check sample rate from TCO or SYNC_IN */
1429 {
1430 bool is_valid_input = 0;
1431 bool has_sync = 0;
1432
1433 syncref = hdspm_autosync_ref(hdspm);
1434 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1435 is_valid_input = 1;
1436 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1437 hdspm_tco_sync_check(hdspm));
1438 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1439 is_valid_input = 1;
1440 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1441 hdspm_sync_in_sync_check(hdspm));
1442 }
1443
1444 if (is_valid_input && has_sync) {
1445 rate = hdspm_round_frequency(
1446 hdspm_get_pll_freq(hdspm));
1447 }
1448 }
1449
1450 rate = hdspm_rate_multiplier(hdspm, rate);
1451
1452 break;
1453 }
1454
1455 return rate;
1456 }
1457
1458 /* return latency in samples per period */
1459 static int hdspm_get_latency(struct hdspm *hdspm)
1460 {
1461 int n;
1462
1463 n = hdspm_decode_latency(hdspm->control_register);
1464
1465 /* Special case for new RME cards with 32 samples period size.
1466 * The three latency bits in the control register
1467 * (HDSP_LatencyMask) encode latency values of 64 samples as
1468 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1469 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1470 * it corresponds to 32 samples.
1471 */
1472 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1473 n = -1;
1474
1475 return 1 << (n + 6);
1476 }
1477
1478 /* Latency function */
1479 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1480 {
1481 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1482 }
1483
1484
1485 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1486 {
1487 int position;
1488
1489 position = hdspm_read(hdspm, HDSPM_statusRegister);
1490
1491 switch (hdspm->io_type) {
1492 case RayDAT:
1493 case AIO:
1494 position &= HDSPM_BufferPositionMask;
1495 position /= 4; /* Bytes per sample */
1496 break;
1497 default:
1498 position = (position & HDSPM_BufferID) ?
1499 (hdspm->period_bytes / 4) : 0;
1500 }
1501
1502 return position;
1503 }
1504
1505
1506 static inline void hdspm_start_audio(struct hdspm * s)
1507 {
1508 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1509 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1510 }
1511
1512 static inline void hdspm_stop_audio(struct hdspm * s)
1513 {
1514 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1515 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1516 }
1517
1518 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1519 static void hdspm_silence_playback(struct hdspm *hdspm)
1520 {
1521 int i;
1522 int n = hdspm->period_bytes;
1523 void *buf = hdspm->playback_buffer;
1524
1525 if (buf == NULL)
1526 return;
1527
1528 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1529 memset(buf, 0, n);
1530 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1531 }
1532 }
1533
1534 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1535 {
1536 int n;
1537
1538 spin_lock_irq(&s->lock);
1539
1540 if (32 == frames) {
1541 /* Special case for new RME cards like RayDAT/AIO which
1542 * support period sizes of 32 samples. Since latency is
1543 * encoded in the three bits of HDSP_LatencyMask, we can only
1544 * have values from 0 .. 7. While 0 still means 64 samples and
1545 * 6 represents 4096 samples on all cards, 7 represents 8192
1546 * on older cards and 32 samples on new cards.
1547 *
1548 * In other words, period size in samples is calculated by
1549 * 2^(n+6) with n ranging from 0 .. 7.
1550 */
1551 n = 7;
1552 } else {
1553 frames >>= 7;
1554 n = 0;
1555 while (frames) {
1556 n++;
1557 frames >>= 1;
1558 }
1559 }
1560
1561 s->control_register &= ~HDSPM_LatencyMask;
1562 s->control_register |= hdspm_encode_latency(n);
1563
1564 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1565
1566 hdspm_compute_period_size(s);
1567
1568 spin_unlock_irq(&s->lock);
1569
1570 return 0;
1571 }
1572
1573 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1574 {
1575 u64 freq_const;
1576
1577 if (period == 0)
1578 return 0;
1579
1580 switch (hdspm->io_type) {
1581 case MADI:
1582 case AES32:
1583 freq_const = 110069313433624ULL;
1584 break;
1585 case RayDAT:
1586 case AIO:
1587 freq_const = 104857600000000ULL;
1588 break;
1589 case MADIface:
1590 freq_const = 131072000000000ULL;
1591 break;
1592 default:
1593 snd_BUG();
1594 return 0;
1595 }
1596
1597 return div_u64(freq_const, period);
1598 }
1599
1600
1601 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1602 {
1603 u64 n;
1604
1605 if (rate >= 112000)
1606 rate /= 4;
1607 else if (rate >= 56000)
1608 rate /= 2;
1609
1610 switch (hdspm->io_type) {
1611 case MADIface:
1612 n = 131072000000000ULL; /* 125 MHz */
1613 break;
1614 case MADI:
1615 case AES32:
1616 n = 110069313433624ULL; /* 105 MHz */
1617 break;
1618 case RayDAT:
1619 case AIO:
1620 n = 104857600000000ULL; /* 100 MHz */
1621 break;
1622 default:
1623 snd_BUG();
1624 return;
1625 }
1626
1627 n = div_u64(n, rate);
1628 /* n should be less than 2^32 for being written to FREQ register */
1629 snd_BUG_ON(n >> 32);
1630 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1631 }
1632
1633 /* dummy set rate lets see what happens */
1634 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1635 {
1636 int current_rate;
1637 int rate_bits;
1638 int not_set = 0;
1639 int current_speed, target_speed;
1640
1641 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1642 it (e.g. during module initialization).
1643 */
1644
1645 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1646
1647 /* SLAVE --- */
1648 if (called_internally) {
1649
1650 /* request from ctl or card initialization
1651 just make a warning an remember setting
1652 for future master mode switching */
1653
1654 snd_printk(KERN_WARNING "HDSPM: "
1655 "Warning: device is not running "
1656 "as a clock master.\n");
1657 not_set = 1;
1658 } else {
1659
1660 /* hw_param request while in AutoSync mode */
1661 int external_freq =
1662 hdspm_external_sample_rate(hdspm);
1663
1664 if (hdspm_autosync_ref(hdspm) ==
1665 HDSPM_AUTOSYNC_FROM_NONE) {
1666
1667 snd_printk(KERN_WARNING "HDSPM: "
1668 "Detected no Externel Sync \n");
1669 not_set = 1;
1670
1671 } else if (rate != external_freq) {
1672
1673 snd_printk(KERN_WARNING "HDSPM: "
1674 "Warning: No AutoSync source for "
1675 "requested rate\n");
1676 not_set = 1;
1677 }
1678 }
1679 }
1680
1681 current_rate = hdspm->system_sample_rate;
1682
1683 /* Changing between Singe, Double and Quad speed is not
1684 allowed if any substreams are open. This is because such a change
1685 causes a shift in the location of the DMA buffers and a reduction
1686 in the number of available buffers.
1687
1688 Note that a similar but essentially insoluble problem exists for
1689 externally-driven rate changes. All we can do is to flag rate
1690 changes in the read/write routines.
1691 */
1692
1693 if (current_rate <= 48000)
1694 current_speed = HDSPM_SPEED_SINGLE;
1695 else if (current_rate <= 96000)
1696 current_speed = HDSPM_SPEED_DOUBLE;
1697 else
1698 current_speed = HDSPM_SPEED_QUAD;
1699
1700 if (rate <= 48000)
1701 target_speed = HDSPM_SPEED_SINGLE;
1702 else if (rate <= 96000)
1703 target_speed = HDSPM_SPEED_DOUBLE;
1704 else
1705 target_speed = HDSPM_SPEED_QUAD;
1706
1707 switch (rate) {
1708 case 32000:
1709 rate_bits = HDSPM_Frequency32KHz;
1710 break;
1711 case 44100:
1712 rate_bits = HDSPM_Frequency44_1KHz;
1713 break;
1714 case 48000:
1715 rate_bits = HDSPM_Frequency48KHz;
1716 break;
1717 case 64000:
1718 rate_bits = HDSPM_Frequency64KHz;
1719 break;
1720 case 88200:
1721 rate_bits = HDSPM_Frequency88_2KHz;
1722 break;
1723 case 96000:
1724 rate_bits = HDSPM_Frequency96KHz;
1725 break;
1726 case 128000:
1727 rate_bits = HDSPM_Frequency128KHz;
1728 break;
1729 case 176400:
1730 rate_bits = HDSPM_Frequency176_4KHz;
1731 break;
1732 case 192000:
1733 rate_bits = HDSPM_Frequency192KHz;
1734 break;
1735 default:
1736 return -EINVAL;
1737 }
1738
1739 if (current_speed != target_speed
1740 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1741 snd_printk
1742 (KERN_ERR "HDSPM: "
1743 "cannot change from %s speed to %s speed mode "
1744 "(capture PID = %d, playback PID = %d)\n",
1745 hdspm_speed_names[current_speed],
1746 hdspm_speed_names[target_speed],
1747 hdspm->capture_pid, hdspm->playback_pid);
1748 return -EBUSY;
1749 }
1750
1751 hdspm->control_register &= ~HDSPM_FrequencyMask;
1752 hdspm->control_register |= rate_bits;
1753 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1754
1755 /* For AES32, need to set DDS value in FREQ register
1756 For MADI, also apparently */
1757 hdspm_set_dds_value(hdspm, rate);
1758
1759 if (AES32 == hdspm->io_type && rate != current_rate)
1760 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1761
1762 hdspm->system_sample_rate = rate;
1763
1764 if (rate <= 48000) {
1765 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1766 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1767 hdspm->max_channels_in = hdspm->ss_in_channels;
1768 hdspm->max_channels_out = hdspm->ss_out_channels;
1769 hdspm->port_names_in = hdspm->port_names_in_ss;
1770 hdspm->port_names_out = hdspm->port_names_out_ss;
1771 } else if (rate <= 96000) {
1772 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1773 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1774 hdspm->max_channels_in = hdspm->ds_in_channels;
1775 hdspm->max_channels_out = hdspm->ds_out_channels;
1776 hdspm->port_names_in = hdspm->port_names_in_ds;
1777 hdspm->port_names_out = hdspm->port_names_out_ds;
1778 } else {
1779 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1780 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1781 hdspm->max_channels_in = hdspm->qs_in_channels;
1782 hdspm->max_channels_out = hdspm->qs_out_channels;
1783 hdspm->port_names_in = hdspm->port_names_in_qs;
1784 hdspm->port_names_out = hdspm->port_names_out_qs;
1785 }
1786
1787 if (not_set != 0)
1788 return -1;
1789
1790 return 0;
1791 }
1792
1793 /* mainly for init to 0 on load */
1794 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1795 {
1796 int i, j;
1797 unsigned int gain;
1798
1799 if (sgain > UNITY_GAIN)
1800 gain = UNITY_GAIN;
1801 else if (sgain < 0)
1802 gain = 0;
1803 else
1804 gain = sgain;
1805
1806 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1807 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1808 hdspm_write_in_gain(hdspm, i, j, gain);
1809 hdspm_write_pb_gain(hdspm, i, j, gain);
1810 }
1811 }
1812
1813 /*----------------------------------------------------------------------------
1814 MIDI
1815 ----------------------------------------------------------------------------*/
1816
1817 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1818 int id)
1819 {
1820 /* the hardware already does the relevant bit-mask with 0xff */
1821 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1822 }
1823
1824 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1825 int val)
1826 {
1827 /* the hardware already does the relevant bit-mask with 0xff */
1828 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1829 }
1830
1831 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1832 {
1833 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1834 }
1835
1836 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1837 {
1838 int fifo_bytes_used;
1839
1840 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1841
1842 if (fifo_bytes_used < 128)
1843 return 128 - fifo_bytes_used;
1844 else
1845 return 0;
1846 }
1847
1848 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1849 {
1850 while (snd_hdspm_midi_input_available (hdspm, id))
1851 snd_hdspm_midi_read_byte (hdspm, id);
1852 }
1853
1854 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1855 {
1856 unsigned long flags;
1857 int n_pending;
1858 int to_write;
1859 int i;
1860 unsigned char buf[128];
1861
1862 /* Output is not interrupt driven */
1863
1864 spin_lock_irqsave (&hmidi->lock, flags);
1865 if (hmidi->output &&
1866 !snd_rawmidi_transmit_empty (hmidi->output)) {
1867 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1868 hmidi->id);
1869 if (n_pending > 0) {
1870 if (n_pending > (int)sizeof (buf))
1871 n_pending = sizeof (buf);
1872
1873 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1874 n_pending);
1875 if (to_write > 0) {
1876 for (i = 0; i < to_write; ++i)
1877 snd_hdspm_midi_write_byte (hmidi->hdspm,
1878 hmidi->id,
1879 buf[i]);
1880 }
1881 }
1882 }
1883 spin_unlock_irqrestore (&hmidi->lock, flags);
1884 return 0;
1885 }
1886
1887 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1888 {
1889 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1890 * input FIFO size
1891 */
1892 unsigned long flags;
1893 int n_pending;
1894 int i;
1895
1896 spin_lock_irqsave (&hmidi->lock, flags);
1897 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1898 if (n_pending > 0) {
1899 if (hmidi->input) {
1900 if (n_pending > (int)sizeof (buf))
1901 n_pending = sizeof (buf);
1902 for (i = 0; i < n_pending; ++i)
1903 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1904 hmidi->id);
1905 if (n_pending)
1906 snd_rawmidi_receive (hmidi->input, buf,
1907 n_pending);
1908 } else {
1909 /* flush the MIDI input FIFO */
1910 while (n_pending--)
1911 snd_hdspm_midi_read_byte (hmidi->hdspm,
1912 hmidi->id);
1913 }
1914 }
1915 hmidi->pending = 0;
1916 spin_unlock_irqrestore(&hmidi->lock, flags);
1917
1918 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1919 hmidi->hdspm->control_register |= hmidi->ie;
1920 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1921 hmidi->hdspm->control_register);
1922 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1923
1924 return snd_hdspm_midi_output_write (hmidi);
1925 }
1926
1927 static void
1928 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1929 {
1930 struct hdspm *hdspm;
1931 struct hdspm_midi *hmidi;
1932 unsigned long flags;
1933
1934 hmidi = substream->rmidi->private_data;
1935 hdspm = hmidi->hdspm;
1936
1937 spin_lock_irqsave (&hdspm->lock, flags);
1938 if (up) {
1939 if (!(hdspm->control_register & hmidi->ie)) {
1940 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1941 hdspm->control_register |= hmidi->ie;
1942 }
1943 } else {
1944 hdspm->control_register &= ~hmidi->ie;
1945 }
1946
1947 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1948 spin_unlock_irqrestore (&hdspm->lock, flags);
1949 }
1950
1951 static void snd_hdspm_midi_output_timer(unsigned long data)
1952 {
1953 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1954 unsigned long flags;
1955
1956 snd_hdspm_midi_output_write(hmidi);
1957 spin_lock_irqsave (&hmidi->lock, flags);
1958
1959 /* this does not bump hmidi->istimer, because the
1960 kernel automatically removed the timer when it
1961 expired, and we are now adding it back, thus
1962 leaving istimer wherever it was set before.
1963 */
1964
1965 if (hmidi->istimer) {
1966 hmidi->timer.expires = 1 + jiffies;
1967 add_timer(&hmidi->timer);
1968 }
1969
1970 spin_unlock_irqrestore (&hmidi->lock, flags);
1971 }
1972
1973 static void
1974 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1975 {
1976 struct hdspm_midi *hmidi;
1977 unsigned long flags;
1978
1979 hmidi = substream->rmidi->private_data;
1980 spin_lock_irqsave (&hmidi->lock, flags);
1981 if (up) {
1982 if (!hmidi->istimer) {
1983 init_timer(&hmidi->timer);
1984 hmidi->timer.function = snd_hdspm_midi_output_timer;
1985 hmidi->timer.data = (unsigned long) hmidi;
1986 hmidi->timer.expires = 1 + jiffies;
1987 add_timer(&hmidi->timer);
1988 hmidi->istimer++;
1989 }
1990 } else {
1991 if (hmidi->istimer && --hmidi->istimer <= 0)
1992 del_timer (&hmidi->timer);
1993 }
1994 spin_unlock_irqrestore (&hmidi->lock, flags);
1995 if (up)
1996 snd_hdspm_midi_output_write(hmidi);
1997 }
1998
1999 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
2000 {
2001 struct hdspm_midi *hmidi;
2002
2003 hmidi = substream->rmidi->private_data;
2004 spin_lock_irq (&hmidi->lock);
2005 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2006 hmidi->input = substream;
2007 spin_unlock_irq (&hmidi->lock);
2008
2009 return 0;
2010 }
2011
2012 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2013 {
2014 struct hdspm_midi *hmidi;
2015
2016 hmidi = substream->rmidi->private_data;
2017 spin_lock_irq (&hmidi->lock);
2018 hmidi->output = substream;
2019 spin_unlock_irq (&hmidi->lock);
2020
2021 return 0;
2022 }
2023
2024 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2025 {
2026 struct hdspm_midi *hmidi;
2027
2028 snd_hdspm_midi_input_trigger (substream, 0);
2029
2030 hmidi = substream->rmidi->private_data;
2031 spin_lock_irq (&hmidi->lock);
2032 hmidi->input = NULL;
2033 spin_unlock_irq (&hmidi->lock);
2034
2035 return 0;
2036 }
2037
2038 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2039 {
2040 struct hdspm_midi *hmidi;
2041
2042 snd_hdspm_midi_output_trigger (substream, 0);
2043
2044 hmidi = substream->rmidi->private_data;
2045 spin_lock_irq (&hmidi->lock);
2046 hmidi->output = NULL;
2047 spin_unlock_irq (&hmidi->lock);
2048
2049 return 0;
2050 }
2051
2052 static struct snd_rawmidi_ops snd_hdspm_midi_output =
2053 {
2054 .open = snd_hdspm_midi_output_open,
2055 .close = snd_hdspm_midi_output_close,
2056 .trigger = snd_hdspm_midi_output_trigger,
2057 };
2058
2059 static struct snd_rawmidi_ops snd_hdspm_midi_input =
2060 {
2061 .open = snd_hdspm_midi_input_open,
2062 .close = snd_hdspm_midi_input_close,
2063 .trigger = snd_hdspm_midi_input_trigger,
2064 };
2065
2066 static int snd_hdspm_create_midi(struct snd_card *card,
2067 struct hdspm *hdspm, int id)
2068 {
2069 int err;
2070 char buf[32];
2071
2072 hdspm->midi[id].id = id;
2073 hdspm->midi[id].hdspm = hdspm;
2074 spin_lock_init (&hdspm->midi[id].lock);
2075
2076 if (0 == id) {
2077 if (MADIface == hdspm->io_type) {
2078 /* MIDI-over-MADI on HDSPe MADIface */
2079 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2080 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2081 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2082 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2083 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2084 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2085 } else {
2086 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2087 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2088 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2089 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2090 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2091 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2092 }
2093 } else if (1 == id) {
2094 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2095 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2096 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2097 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2098 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2099 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2100 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2101 /* MIDI-over-MADI on HDSPe MADI */
2102 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2103 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2104 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2105 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2106 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2107 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2108 } else if (2 == id) {
2109 /* TCO MTC, read only */
2110 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2111 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2112 hdspm->midi[2].dataOut = -1;
2113 hdspm->midi[2].statusOut = -1;
2114 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2115 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2116 } else if (3 == id) {
2117 /* TCO MTC on HDSPe MADI */
2118 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2119 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2120 hdspm->midi[3].dataOut = -1;
2121 hdspm->midi[3].statusOut = -1;
2122 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2123 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2124 }
2125
2126 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2127 (MADIface == hdspm->io_type)))) {
2128 if ((id == 0) && (MADIface == hdspm->io_type)) {
2129 sprintf(buf, "%s MIDIoverMADI", card->shortname);
2130 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2131 sprintf(buf, "%s MIDIoverMADI", card->shortname);
2132 } else {
2133 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2134 }
2135 err = snd_rawmidi_new(card, buf, id, 1, 1,
2136 &hdspm->midi[id].rmidi);
2137 if (err < 0)
2138 return err;
2139
2140 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2141 card->id, id+1);
2142 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2143
2144 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2145 SNDRV_RAWMIDI_STREAM_OUTPUT,
2146 &snd_hdspm_midi_output);
2147 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2148 SNDRV_RAWMIDI_STREAM_INPUT,
2149 &snd_hdspm_midi_input);
2150
2151 hdspm->midi[id].rmidi->info_flags |=
2152 SNDRV_RAWMIDI_INFO_OUTPUT |
2153 SNDRV_RAWMIDI_INFO_INPUT |
2154 SNDRV_RAWMIDI_INFO_DUPLEX;
2155 } else {
2156 /* TCO MTC, read only */
2157 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2158 err = snd_rawmidi_new(card, buf, id, 1, 1,
2159 &hdspm->midi[id].rmidi);
2160 if (err < 0)
2161 return err;
2162
2163 sprintf(hdspm->midi[id].rmidi->name,
2164 "%s MTC %d", card->id, id+1);
2165 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2166
2167 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2168 SNDRV_RAWMIDI_STREAM_INPUT,
2169 &snd_hdspm_midi_input);
2170
2171 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2172 }
2173
2174 return 0;
2175 }
2176
2177
2178 static void hdspm_midi_tasklet(unsigned long arg)
2179 {
2180 struct hdspm *hdspm = (struct hdspm *)arg;
2181 int i = 0;
2182
2183 while (i < hdspm->midiPorts) {
2184 if (hdspm->midi[i].pending)
2185 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2186
2187 i++;
2188 }
2189 }
2190
2191
2192 /*-----------------------------------------------------------------------------
2193 Status Interface
2194 ----------------------------------------------------------------------------*/
2195
2196 /* get the system sample rate which is set */
2197
2198
2199 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2200 {
2201 unsigned int period, rate;
2202
2203 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2204 rate = hdspm_calc_dds_value(hdspm, period);
2205
2206 return rate;
2207 }
2208
2209 /**
2210 * Calculate the real sample rate from the
2211 * current DDS value.
2212 **/
2213 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2214 {
2215 unsigned int rate;
2216
2217 rate = hdspm_get_pll_freq(hdspm);
2218
2219 if (rate > 207000) {
2220 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2221 if (0 == hdspm_system_clock_mode(hdspm)) {
2222 /* master mode, return internal sample rate */
2223 rate = hdspm->system_sample_rate;
2224 } else {
2225 /* slave mode, return external sample rate */
2226 rate = hdspm_external_sample_rate(hdspm);
2227 }
2228 }
2229
2230 return rate;
2231 }
2232
2233
2234 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2235 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2236 .name = xname, \
2237 .index = xindex, \
2238 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2239 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2240 .info = snd_hdspm_info_system_sample_rate, \
2241 .put = snd_hdspm_put_system_sample_rate, \
2242 .get = snd_hdspm_get_system_sample_rate \
2243 }
2244
2245 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2246 struct snd_ctl_elem_info *uinfo)
2247 {
2248 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2249 uinfo->count = 1;
2250 uinfo->value.integer.min = 27000;
2251 uinfo->value.integer.max = 207000;
2252 uinfo->value.integer.step = 1;
2253 return 0;
2254 }
2255
2256
2257 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2258 struct snd_ctl_elem_value *
2259 ucontrol)
2260 {
2261 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2262
2263 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2264 return 0;
2265 }
2266
2267 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2268 struct snd_ctl_elem_value *
2269 ucontrol)
2270 {
2271 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2272
2273 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2274 return 0;
2275 }
2276
2277
2278 /**
2279 * Returns the WordClock sample rate class for the given card.
2280 **/
2281 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2282 {
2283 int status;
2284
2285 switch (hdspm->io_type) {
2286 case RayDAT:
2287 case AIO:
2288 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2289 return (status >> 16) & 0xF;
2290 break;
2291 case AES32:
2292 status = hdspm_read(hdspm, HDSPM_statusRegister);
2293 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2294 default:
2295 break;
2296 }
2297
2298
2299 return 0;
2300 }
2301
2302
2303 /**
2304 * Returns the TCO sample rate class for the given card.
2305 **/
2306 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2307 {
2308 int status;
2309
2310 if (hdspm->tco) {
2311 switch (hdspm->io_type) {
2312 case RayDAT:
2313 case AIO:
2314 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2315 return (status >> 20) & 0xF;
2316 break;
2317 case AES32:
2318 status = hdspm_read(hdspm, HDSPM_statusRegister);
2319 return (status >> 1) & 0xF;
2320 default:
2321 break;
2322 }
2323 }
2324
2325 return 0;
2326 }
2327
2328
2329 /**
2330 * Returns the SYNC_IN sample rate class for the given card.
2331 **/
2332 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2333 {
2334 int status;
2335
2336 if (hdspm->tco) {
2337 switch (hdspm->io_type) {
2338 case RayDAT:
2339 case AIO:
2340 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2341 return (status >> 12) & 0xF;
2342 break;
2343 default:
2344 break;
2345 }
2346 }
2347
2348 return 0;
2349 }
2350
2351 /**
2352 * Returns the AES sample rate class for the given card.
2353 **/
2354 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2355 {
2356 int timecode;
2357
2358 switch (hdspm->io_type) {
2359 case AES32:
2360 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2361 return (timecode >> (4*index)) & 0xF;
2362 break;
2363 default:
2364 break;
2365 }
2366 return 0;
2367 }
2368
2369 /**
2370 * Returns the sample rate class for input source <idx> for
2371 * 'new style' cards like the AIO and RayDAT.
2372 **/
2373 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2374 {
2375 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2376
2377 return (status >> (idx*4)) & 0xF;
2378 }
2379
2380 #define ENUMERATED_CTL_INFO(info, texts) \
2381 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2382
2383
2384 /* Helper function to query the external sample rate and return the
2385 * corresponding enum to be returned to userspace.
2386 */
2387 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2388 {
2389 int rate = hdspm_external_sample_rate(hdspm);
2390 int i, selected_rate = 0;
2391 for (i = 1; i < 10; i++)
2392 if (HDSPM_bit2freq(i) == rate) {
2393 selected_rate = i;
2394 break;
2395 }
2396 return selected_rate;
2397 }
2398
2399
2400 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2401 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2402 .name = xname, \
2403 .private_value = xindex, \
2404 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2405 .info = snd_hdspm_info_autosync_sample_rate, \
2406 .get = snd_hdspm_get_autosync_sample_rate \
2407 }
2408
2409
2410 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2411 struct snd_ctl_elem_info *uinfo)
2412 {
2413 ENUMERATED_CTL_INFO(uinfo, texts_freq);
2414 return 0;
2415 }
2416
2417
2418 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2419 struct snd_ctl_elem_value *
2420 ucontrol)
2421 {
2422 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2423
2424 switch (hdspm->io_type) {
2425 case RayDAT:
2426 switch (kcontrol->private_value) {
2427 case 0:
2428 ucontrol->value.enumerated.item[0] =
2429 hdspm_get_wc_sample_rate(hdspm);
2430 break;
2431 case 7:
2432 ucontrol->value.enumerated.item[0] =
2433 hdspm_get_tco_sample_rate(hdspm);
2434 break;
2435 case 8:
2436 ucontrol->value.enumerated.item[0] =
2437 hdspm_get_sync_in_sample_rate(hdspm);
2438 break;
2439 default:
2440 ucontrol->value.enumerated.item[0] =
2441 hdspm_get_s1_sample_rate(hdspm,
2442 kcontrol->private_value-1);
2443 }
2444 break;
2445
2446 case AIO:
2447 switch (kcontrol->private_value) {
2448 case 0: /* WC */
2449 ucontrol->value.enumerated.item[0] =
2450 hdspm_get_wc_sample_rate(hdspm);
2451 break;
2452 case 4: /* TCO */
2453 ucontrol->value.enumerated.item[0] =
2454 hdspm_get_tco_sample_rate(hdspm);
2455 break;
2456 case 5: /* SYNC_IN */
2457 ucontrol->value.enumerated.item[0] =
2458 hdspm_get_sync_in_sample_rate(hdspm);
2459 break;
2460 default:
2461 ucontrol->value.enumerated.item[0] =
2462 hdspm_get_s1_sample_rate(hdspm,
2463 kcontrol->private_value-1);
2464 }
2465 break;
2466
2467 case AES32:
2468
2469 switch (kcontrol->private_value) {
2470 case 0: /* WC */
2471 ucontrol->value.enumerated.item[0] =
2472 hdspm_get_wc_sample_rate(hdspm);
2473 break;
2474 case 9: /* TCO */
2475 ucontrol->value.enumerated.item[0] =
2476 hdspm_get_tco_sample_rate(hdspm);
2477 break;
2478 case 10: /* SYNC_IN */
2479 ucontrol->value.enumerated.item[0] =
2480 hdspm_get_sync_in_sample_rate(hdspm);
2481 break;
2482 case 11: /* External Rate */
2483 ucontrol->value.enumerated.item[0] =
2484 hdspm_external_rate_to_enum(hdspm);
2485 break;
2486 default: /* AES1 to AES8 */
2487 ucontrol->value.enumerated.item[0] =
2488 hdspm_get_aes_sample_rate(hdspm,
2489 kcontrol->private_value -
2490 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2491 break;
2492 }
2493 break;
2494
2495 case MADI:
2496 case MADIface:
2497 ucontrol->value.enumerated.item[0] =
2498 hdspm_external_rate_to_enum(hdspm);
2499 break;
2500 default:
2501 break;
2502 }
2503
2504 return 0;
2505 }
2506
2507
2508 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2509 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2510 .name = xname, \
2511 .index = xindex, \
2512 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2513 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2514 .info = snd_hdspm_info_system_clock_mode, \
2515 .get = snd_hdspm_get_system_clock_mode, \
2516 .put = snd_hdspm_put_system_clock_mode, \
2517 }
2518
2519
2520 /**
2521 * Returns the system clock mode for the given card.
2522 * @returns 0 - master, 1 - slave
2523 **/
2524 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2525 {
2526 switch (hdspm->io_type) {
2527 case AIO:
2528 case RayDAT:
2529 if (hdspm->settings_register & HDSPM_c0Master)
2530 return 0;
2531 break;
2532
2533 default:
2534 if (hdspm->control_register & HDSPM_ClockModeMaster)
2535 return 0;
2536 }
2537
2538 return 1;
2539 }
2540
2541
2542 /**
2543 * Sets the system clock mode.
2544 * @param mode 0 - master, 1 - slave
2545 **/
2546 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2547 {
2548 hdspm_set_toggle_setting(hdspm,
2549 (hdspm_is_raydat_or_aio(hdspm)) ?
2550 HDSPM_c0Master : HDSPM_ClockModeMaster,
2551 (0 == mode));
2552 }
2553
2554
2555 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2556 struct snd_ctl_elem_info *uinfo)
2557 {
2558 static const char *const texts[] = { "Master", "AutoSync" };
2559 ENUMERATED_CTL_INFO(uinfo, texts);
2560 return 0;
2561 }
2562
2563 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2564 struct snd_ctl_elem_value *ucontrol)
2565 {
2566 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2567
2568 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2569 return 0;
2570 }
2571
2572 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2573 struct snd_ctl_elem_value *ucontrol)
2574 {
2575 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2576 int val;
2577
2578 if (!snd_hdspm_use_is_exclusive(hdspm))
2579 return -EBUSY;
2580
2581 val = ucontrol->value.enumerated.item[0];
2582 if (val < 0)
2583 val = 0;
2584 else if (val > 1)
2585 val = 1;
2586
2587 hdspm_set_system_clock_mode(hdspm, val);
2588
2589 return 0;
2590 }
2591
2592
2593 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2594 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2595 .name = xname, \
2596 .index = xindex, \
2597 .info = snd_hdspm_info_clock_source, \
2598 .get = snd_hdspm_get_clock_source, \
2599 .put = snd_hdspm_put_clock_source \
2600 }
2601
2602
2603 static int hdspm_clock_source(struct hdspm * hdspm)
2604 {
2605 switch (hdspm->system_sample_rate) {
2606 case 32000: return 0;
2607 case 44100: return 1;
2608 case 48000: return 2;
2609 case 64000: return 3;
2610 case 88200: return 4;
2611 case 96000: return 5;
2612 case 128000: return 6;
2613 case 176400: return 7;
2614 case 192000: return 8;
2615 }
2616
2617 return -1;
2618 }
2619
2620 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2621 {
2622 int rate;
2623 switch (mode) {
2624 case 0:
2625 rate = 32000; break;
2626 case 1:
2627 rate = 44100; break;
2628 case 2:
2629 rate = 48000; break;
2630 case 3:
2631 rate = 64000; break;
2632 case 4:
2633 rate = 88200; break;
2634 case 5:
2635 rate = 96000; break;
2636 case 6:
2637 rate = 128000; break;
2638 case 7:
2639 rate = 176400; break;
2640 case 8:
2641 rate = 192000; break;
2642 default:
2643 rate = 48000;
2644 }
2645 hdspm_set_rate(hdspm, rate, 1);
2646 return 0;
2647 }
2648
2649 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2650 struct snd_ctl_elem_info *uinfo)
2651 {
2652 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2653 uinfo->count = 1;
2654 uinfo->value.enumerated.items = 9;
2655
2656 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2657 uinfo->value.enumerated.item =
2658 uinfo->value.enumerated.items - 1;
2659
2660 strcpy(uinfo->value.enumerated.name,
2661 texts_freq[uinfo->value.enumerated.item+1]);
2662
2663 return 0;
2664 }
2665
2666 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2667 struct snd_ctl_elem_value *ucontrol)
2668 {
2669 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2670
2671 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2672 return 0;
2673 }
2674
2675 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2676 struct snd_ctl_elem_value *ucontrol)
2677 {
2678 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2679 int change;
2680 int val;
2681
2682 if (!snd_hdspm_use_is_exclusive(hdspm))
2683 return -EBUSY;
2684 val = ucontrol->value.enumerated.item[0];
2685 if (val < 0)
2686 val = 0;
2687 if (val > 9)
2688 val = 9;
2689 spin_lock_irq(&hdspm->lock);
2690 if (val != hdspm_clock_source(hdspm))
2691 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2692 else
2693 change = 0;
2694 spin_unlock_irq(&hdspm->lock);
2695 return change;
2696 }
2697
2698
2699 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2700 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2701 .name = xname, \
2702 .index = xindex, \
2703 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2704 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2705 .info = snd_hdspm_info_pref_sync_ref, \
2706 .get = snd_hdspm_get_pref_sync_ref, \
2707 .put = snd_hdspm_put_pref_sync_ref \
2708 }
2709
2710
2711 /**
2712 * Returns the current preferred sync reference setting.
2713 * The semantics of the return value are depending on the
2714 * card, please see the comments for clarification.
2715 **/
2716 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2717 {
2718 switch (hdspm->io_type) {
2719 case AES32:
2720 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2721 case 0: return 0; /* WC */
2722 case HDSPM_SyncRef0: return 1; /* AES 1 */
2723 case HDSPM_SyncRef1: return 2; /* AES 2 */
2724 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2725 case HDSPM_SyncRef2: return 4; /* AES 4 */
2726 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2727 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2728 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2729 return 7; /* AES 7 */
2730 case HDSPM_SyncRef3: return 8; /* AES 8 */
2731 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2732 }
2733 break;
2734
2735 case MADI:
2736 case MADIface:
2737 if (hdspm->tco) {
2738 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2739 case 0: return 0; /* WC */
2740 case HDSPM_SyncRef0: return 1; /* MADI */
2741 case HDSPM_SyncRef1: return 2; /* TCO */
2742 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2743 return 3; /* SYNC_IN */
2744 }
2745 } else {
2746 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2747 case 0: return 0; /* WC */
2748 case HDSPM_SyncRef0: return 1; /* MADI */
2749 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2750 return 2; /* SYNC_IN */
2751 }
2752 }
2753 break;
2754
2755 case RayDAT:
2756 if (hdspm->tco) {
2757 switch ((hdspm->settings_register &
2758 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2759 case 0: return 0; /* WC */
2760 case 3: return 1; /* ADAT 1 */
2761 case 4: return 2; /* ADAT 2 */
2762 case 5: return 3; /* ADAT 3 */
2763 case 6: return 4; /* ADAT 4 */
2764 case 1: return 5; /* AES */
2765 case 2: return 6; /* SPDIF */
2766 case 9: return 7; /* TCO */
2767 case 10: return 8; /* SYNC_IN */
2768 }
2769 } else {
2770 switch ((hdspm->settings_register &
2771 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2772 case 0: return 0; /* WC */
2773 case 3: return 1; /* ADAT 1 */
2774 case 4: return 2; /* ADAT 2 */
2775 case 5: return 3; /* ADAT 3 */
2776 case 6: return 4; /* ADAT 4 */
2777 case 1: return 5; /* AES */
2778 case 2: return 6; /* SPDIF */
2779 case 10: return 7; /* SYNC_IN */
2780 }
2781 }
2782
2783 break;
2784
2785 case AIO:
2786 if (hdspm->tco) {
2787 switch ((hdspm->settings_register &
2788 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2789 case 0: return 0; /* WC */
2790 case 3: return 1; /* ADAT */
2791 case 1: return 2; /* AES */
2792 case 2: return 3; /* SPDIF */
2793 case 9: return 4; /* TCO */
2794 case 10: return 5; /* SYNC_IN */
2795 }
2796 } else {
2797 switch ((hdspm->settings_register &
2798 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2799 case 0: return 0; /* WC */
2800 case 3: return 1; /* ADAT */
2801 case 1: return 2; /* AES */
2802 case 2: return 3; /* SPDIF */
2803 case 10: return 4; /* SYNC_IN */
2804 }
2805 }
2806
2807 break;
2808 }
2809
2810 return -1;
2811 }
2812
2813
2814 /**
2815 * Set the preferred sync reference to <pref>. The semantics
2816 * of <pref> are depending on the card type, see the comments
2817 * for clarification.
2818 **/
2819 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2820 {
2821 int p = 0;
2822
2823 switch (hdspm->io_type) {
2824 case AES32:
2825 hdspm->control_register &= ~HDSPM_SyncRefMask;
2826 switch (pref) {
2827 case 0: /* WC */
2828 break;
2829 case 1: /* AES 1 */
2830 hdspm->control_register |= HDSPM_SyncRef0;
2831 break;
2832 case 2: /* AES 2 */
2833 hdspm->control_register |= HDSPM_SyncRef1;
2834 break;
2835 case 3: /* AES 3 */
2836 hdspm->control_register |=
2837 HDSPM_SyncRef1+HDSPM_SyncRef0;
2838 break;
2839 case 4: /* AES 4 */
2840 hdspm->control_register |= HDSPM_SyncRef2;
2841 break;
2842 case 5: /* AES 5 */
2843 hdspm->control_register |=
2844 HDSPM_SyncRef2+HDSPM_SyncRef0;
2845 break;
2846 case 6: /* AES 6 */
2847 hdspm->control_register |=
2848 HDSPM_SyncRef2+HDSPM_SyncRef1;
2849 break;
2850 case 7: /* AES 7 */
2851 hdspm->control_register |=
2852 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2853 break;
2854 case 8: /* AES 8 */
2855 hdspm->control_register |= HDSPM_SyncRef3;
2856 break;
2857 case 9: /* TCO */
2858 hdspm->control_register |=
2859 HDSPM_SyncRef3+HDSPM_SyncRef0;
2860 break;
2861 default:
2862 return -1;
2863 }
2864
2865 break;
2866
2867 case MADI:
2868 case MADIface:
2869 hdspm->control_register &= ~HDSPM_SyncRefMask;
2870 if (hdspm->tco) {
2871 switch (pref) {
2872 case 0: /* WC */
2873 break;
2874 case 1: /* MADI */
2875 hdspm->control_register |= HDSPM_SyncRef0;
2876 break;
2877 case 2: /* TCO */
2878 hdspm->control_register |= HDSPM_SyncRef1;
2879 break;
2880 case 3: /* SYNC_IN */
2881 hdspm->control_register |=
2882 HDSPM_SyncRef0+HDSPM_SyncRef1;
2883 break;
2884 default:
2885 return -1;
2886 }
2887 } else {
2888 switch (pref) {
2889 case 0: /* WC */
2890 break;
2891 case 1: /* MADI */
2892 hdspm->control_register |= HDSPM_SyncRef0;
2893 break;
2894 case 2: /* SYNC_IN */
2895 hdspm->control_register |=
2896 HDSPM_SyncRef0+HDSPM_SyncRef1;
2897 break;
2898 default:
2899 return -1;
2900 }
2901 }
2902
2903 break;
2904
2905 case RayDAT:
2906 if (hdspm->tco) {
2907 switch (pref) {
2908 case 0: p = 0; break; /* WC */
2909 case 1: p = 3; break; /* ADAT 1 */
2910 case 2: p = 4; break; /* ADAT 2 */
2911 case 3: p = 5; break; /* ADAT 3 */
2912 case 4: p = 6; break; /* ADAT 4 */
2913 case 5: p = 1; break; /* AES */
2914 case 6: p = 2; break; /* SPDIF */
2915 case 7: p = 9; break; /* TCO */
2916 case 8: p = 10; break; /* SYNC_IN */
2917 default: return -1;
2918 }
2919 } else {
2920 switch (pref) {
2921 case 0: p = 0; break; /* WC */
2922 case 1: p = 3; break; /* ADAT 1 */
2923 case 2: p = 4; break; /* ADAT 2 */
2924 case 3: p = 5; break; /* ADAT 3 */
2925 case 4: p = 6; break; /* ADAT 4 */
2926 case 5: p = 1; break; /* AES */
2927 case 6: p = 2; break; /* SPDIF */
2928 case 7: p = 10; break; /* SYNC_IN */
2929 default: return -1;
2930 }
2931 }
2932 break;
2933
2934 case AIO:
2935 if (hdspm->tco) {
2936 switch (pref) {
2937 case 0: p = 0; break; /* WC */
2938 case 1: p = 3; break; /* ADAT */
2939 case 2: p = 1; break; /* AES */
2940 case 3: p = 2; break; /* SPDIF */
2941 case 4: p = 9; break; /* TCO */
2942 case 5: p = 10; break; /* SYNC_IN */
2943 default: return -1;
2944 }
2945 } else {
2946 switch (pref) {
2947 case 0: p = 0; break; /* WC */
2948 case 1: p = 3; break; /* ADAT */
2949 case 2: p = 1; break; /* AES */
2950 case 3: p = 2; break; /* SPDIF */
2951 case 4: p = 10; break; /* SYNC_IN */
2952 default: return -1;
2953 }
2954 }
2955 break;
2956 }
2957
2958 switch (hdspm->io_type) {
2959 case RayDAT:
2960 case AIO:
2961 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2962 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2963 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2964 break;
2965
2966 case MADI:
2967 case MADIface:
2968 case AES32:
2969 hdspm_write(hdspm, HDSPM_controlRegister,
2970 hdspm->control_register);
2971 }
2972
2973 return 0;
2974 }
2975
2976
2977 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2978 struct snd_ctl_elem_info *uinfo)
2979 {
2980 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2981
2982 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2983
2984 return 0;
2985 }
2986
2987 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2988 struct snd_ctl_elem_value *ucontrol)
2989 {
2990 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2991 int psf = hdspm_pref_sync_ref(hdspm);
2992
2993 if (psf >= 0) {
2994 ucontrol->value.enumerated.item[0] = psf;
2995 return 0;
2996 }
2997
2998 return -1;
2999 }
3000
3001 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
3002 struct snd_ctl_elem_value *ucontrol)
3003 {
3004 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3005 int val, change = 0;
3006
3007 if (!snd_hdspm_use_is_exclusive(hdspm))
3008 return -EBUSY;
3009
3010 val = ucontrol->value.enumerated.item[0];
3011
3012 if (val < 0)
3013 val = 0;
3014 else if (val >= hdspm->texts_autosync_items)
3015 val = hdspm->texts_autosync_items-1;
3016
3017 spin_lock_irq(&hdspm->lock);
3018 if (val != hdspm_pref_sync_ref(hdspm))
3019 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3020
3021 spin_unlock_irq(&hdspm->lock);
3022 return change;
3023 }
3024
3025
3026 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3027 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3028 .name = xname, \
3029 .index = xindex, \
3030 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3031 .info = snd_hdspm_info_autosync_ref, \
3032 .get = snd_hdspm_get_autosync_ref, \
3033 }
3034
3035 static int hdspm_autosync_ref(struct hdspm *hdspm)
3036 {
3037 /* This looks at the autosync selected sync reference */
3038 if (AES32 == hdspm->io_type) {
3039
3040 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3041 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3042 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3043 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3044 return syncref;
3045 }
3046 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3047
3048 } else if (MADI == hdspm->io_type) {
3049
3050 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3051 switch (status2 & HDSPM_SelSyncRefMask) {
3052 case HDSPM_SelSyncRef_WORD:
3053 return HDSPM_AUTOSYNC_FROM_WORD;
3054 case HDSPM_SelSyncRef_MADI:
3055 return HDSPM_AUTOSYNC_FROM_MADI;
3056 case HDSPM_SelSyncRef_TCO:
3057 return HDSPM_AUTOSYNC_FROM_TCO;
3058 case HDSPM_SelSyncRef_SyncIn:
3059 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3060 case HDSPM_SelSyncRef_NVALID:
3061 return HDSPM_AUTOSYNC_FROM_NONE;
3062 default:
3063 return HDSPM_AUTOSYNC_FROM_NONE;
3064 }
3065
3066 }
3067 return 0;
3068 }
3069
3070
3071 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3072 struct snd_ctl_elem_info *uinfo)
3073 {
3074 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3075
3076 if (AES32 == hdspm->io_type) {
3077 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3078 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3079
3080 ENUMERATED_CTL_INFO(uinfo, texts);
3081 } else if (MADI == hdspm->io_type) {
3082 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3083 "Sync In", "None" };
3084
3085 ENUMERATED_CTL_INFO(uinfo, texts);
3086 }
3087 return 0;
3088 }
3089
3090 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3091 struct snd_ctl_elem_value *ucontrol)
3092 {
3093 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3094
3095 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3096 return 0;
3097 }
3098
3099
3100
3101 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3102 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3103 .name = xname, \
3104 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3105 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3106 .info = snd_hdspm_info_tco_video_input_format, \
3107 .get = snd_hdspm_get_tco_video_input_format, \
3108 }
3109
3110 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3111 struct snd_ctl_elem_info *uinfo)
3112 {
3113 static const char *const texts[] = {"No video", "NTSC", "PAL"};
3114 ENUMERATED_CTL_INFO(uinfo, texts);
3115 return 0;
3116 }
3117
3118 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3119 struct snd_ctl_elem_value *ucontrol)
3120 {
3121 u32 status;
3122 int ret = 0;
3123
3124 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3125 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3126 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3127 HDSPM_TCO1_Video_Input_Format_PAL)) {
3128 case HDSPM_TCO1_Video_Input_Format_NTSC:
3129 /* ntsc */
3130 ret = 1;
3131 break;
3132 case HDSPM_TCO1_Video_Input_Format_PAL:
3133 /* pal */
3134 ret = 2;
3135 break;
3136 default:
3137 /* no video */
3138 ret = 0;
3139 break;
3140 }
3141 ucontrol->value.enumerated.item[0] = ret;
3142 return 0;
3143 }
3144
3145
3146
3147 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3148 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3149 .name = xname, \
3150 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3151 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3152 .info = snd_hdspm_info_tco_ltc_frames, \
3153 .get = snd_hdspm_get_tco_ltc_frames, \
3154 }
3155
3156 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3157 struct snd_ctl_elem_info *uinfo)
3158 {
3159 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3160 "30 fps"};
3161 ENUMERATED_CTL_INFO(uinfo, texts);
3162 return 0;
3163 }
3164
3165 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3166 {
3167 u32 status;
3168 int ret = 0;
3169
3170 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3171 if (status & HDSPM_TCO1_LTC_Input_valid) {
3172 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3173 HDSPM_TCO1_LTC_Format_MSB)) {
3174 case 0:
3175 /* 24 fps */
3176 ret = fps_24;
3177 break;
3178 case HDSPM_TCO1_LTC_Format_LSB:
3179 /* 25 fps */
3180 ret = fps_25;
3181 break;
3182 case HDSPM_TCO1_LTC_Format_MSB:
3183 /* 29.97 fps */
3184 ret = fps_2997;
3185 break;
3186 default:
3187 /* 30 fps */
3188 ret = fps_30;
3189 break;
3190 }
3191 }
3192
3193 return ret;
3194 }
3195
3196 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3197 struct snd_ctl_elem_value *ucontrol)
3198 {
3199 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3200
3201 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3202 return 0;
3203 }
3204
3205 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3206 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3207 .name = xname, \
3208 .private_value = xindex, \
3209 .info = snd_hdspm_info_toggle_setting, \
3210 .get = snd_hdspm_get_toggle_setting, \
3211 .put = snd_hdspm_put_toggle_setting \
3212 }
3213
3214 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3215 {
3216 u32 reg;
3217
3218 if (hdspm_is_raydat_or_aio(hdspm))
3219 reg = hdspm->settings_register;
3220 else
3221 reg = hdspm->control_register;
3222
3223 return (reg & regmask) ? 1 : 0;
3224 }
3225
3226 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3227 {
3228 u32 *reg;
3229 u32 target_reg;
3230
3231 if (hdspm_is_raydat_or_aio(hdspm)) {
3232 reg = &(hdspm->settings_register);
3233 target_reg = HDSPM_WR_SETTINGS;
3234 } else {
3235 reg = &(hdspm->control_register);
3236 target_reg = HDSPM_controlRegister;
3237 }
3238
3239 if (out)
3240 *reg |= regmask;
3241 else
3242 *reg &= ~regmask;
3243
3244 hdspm_write(hdspm, target_reg, *reg);
3245
3246 return 0;
3247 }
3248
3249 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
3250
3251 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3252 struct snd_ctl_elem_value *ucontrol)
3253 {
3254 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3255 u32 regmask = kcontrol->private_value;
3256
3257 spin_lock_irq(&hdspm->lock);
3258 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3259 spin_unlock_irq(&hdspm->lock);
3260 return 0;
3261 }
3262
3263 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3264 struct snd_ctl_elem_value *ucontrol)
3265 {
3266 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3267 u32 regmask = kcontrol->private_value;
3268 int change;
3269 unsigned int val;
3270
3271 if (!snd_hdspm_use_is_exclusive(hdspm))
3272 return -EBUSY;
3273 val = ucontrol->value.integer.value[0] & 1;
3274 spin_lock_irq(&hdspm->lock);
3275 change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3276 hdspm_set_toggle_setting(hdspm, regmask, val);
3277 spin_unlock_irq(&hdspm->lock);
3278 return change;
3279 }
3280
3281 #define HDSPM_INPUT_SELECT(xname, xindex) \
3282 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3283 .name = xname, \
3284 .index = xindex, \
3285 .info = snd_hdspm_info_input_select, \
3286 .get = snd_hdspm_get_input_select, \
3287 .put = snd_hdspm_put_input_select \
3288 }
3289
3290 static int hdspm_input_select(struct hdspm * hdspm)
3291 {
3292 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3293 }
3294
3295 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3296 {
3297 if (out)
3298 hdspm->control_register |= HDSPM_InputSelect0;
3299 else
3300 hdspm->control_register &= ~HDSPM_InputSelect0;
3301 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3302
3303 return 0;
3304 }
3305
3306 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3307 struct snd_ctl_elem_info *uinfo)
3308 {
3309 static const char *const texts[] = { "optical", "coaxial" };
3310 ENUMERATED_CTL_INFO(uinfo, texts);
3311 return 0;
3312 }
3313
3314 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3315 struct snd_ctl_elem_value *ucontrol)
3316 {
3317 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3318
3319 spin_lock_irq(&hdspm->lock);
3320 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3321 spin_unlock_irq(&hdspm->lock);
3322 return 0;
3323 }
3324
3325 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3326 struct snd_ctl_elem_value *ucontrol)
3327 {
3328 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3329 int change;
3330 unsigned int val;
3331
3332 if (!snd_hdspm_use_is_exclusive(hdspm))
3333 return -EBUSY;
3334 val = ucontrol->value.integer.value[0] & 1;
3335 spin_lock_irq(&hdspm->lock);
3336 change = (int) val != hdspm_input_select(hdspm);
3337 hdspm_set_input_select(hdspm, val);
3338 spin_unlock_irq(&hdspm->lock);
3339 return change;
3340 }
3341
3342
3343 #define HDSPM_DS_WIRE(xname, xindex) \
3344 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3345 .name = xname, \
3346 .index = xindex, \
3347 .info = snd_hdspm_info_ds_wire, \
3348 .get = snd_hdspm_get_ds_wire, \
3349 .put = snd_hdspm_put_ds_wire \
3350 }
3351
3352 static int hdspm_ds_wire(struct hdspm * hdspm)
3353 {
3354 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3355 }
3356
3357 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3358 {
3359 if (ds)
3360 hdspm->control_register |= HDSPM_DS_DoubleWire;
3361 else
3362 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3363 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3364
3365 return 0;
3366 }
3367
3368 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3369 struct snd_ctl_elem_info *uinfo)
3370 {
3371 static const char *const texts[] = { "Single", "Double" };
3372 ENUMERATED_CTL_INFO(uinfo, texts);
3373 return 0;
3374 }
3375
3376 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3377 struct snd_ctl_elem_value *ucontrol)
3378 {
3379 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3380
3381 spin_lock_irq(&hdspm->lock);
3382 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3383 spin_unlock_irq(&hdspm->lock);
3384 return 0;
3385 }
3386
3387 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3388 struct snd_ctl_elem_value *ucontrol)
3389 {
3390 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3391 int change;
3392 unsigned int val;
3393
3394 if (!snd_hdspm_use_is_exclusive(hdspm))
3395 return -EBUSY;
3396 val = ucontrol->value.integer.value[0] & 1;
3397 spin_lock_irq(&hdspm->lock);
3398 change = (int) val != hdspm_ds_wire(hdspm);
3399 hdspm_set_ds_wire(hdspm, val);
3400 spin_unlock_irq(&hdspm->lock);
3401 return change;
3402 }
3403
3404
3405 #define HDSPM_QS_WIRE(xname, xindex) \
3406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3407 .name = xname, \
3408 .index = xindex, \
3409 .info = snd_hdspm_info_qs_wire, \
3410 .get = snd_hdspm_get_qs_wire, \
3411 .put = snd_hdspm_put_qs_wire \
3412 }
3413
3414 static int hdspm_qs_wire(struct hdspm * hdspm)
3415 {
3416 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3417 return 1;
3418 if (hdspm->control_register & HDSPM_QS_QuadWire)
3419 return 2;
3420 return 0;
3421 }
3422
3423 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3424 {
3425 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3426 switch (mode) {
3427 case 0:
3428 break;
3429 case 1:
3430 hdspm->control_register |= HDSPM_QS_DoubleWire;
3431 break;
3432 case 2:
3433 hdspm->control_register |= HDSPM_QS_QuadWire;
3434 break;
3435 }
3436 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3437
3438 return 0;
3439 }
3440
3441 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3442 struct snd_ctl_elem_info *uinfo)
3443 {
3444 static const char *const texts[] = { "Single", "Double", "Quad" };
3445 ENUMERATED_CTL_INFO(uinfo, texts);
3446 return 0;
3447 }
3448
3449 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3450 struct snd_ctl_elem_value *ucontrol)
3451 {
3452 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3453
3454 spin_lock_irq(&hdspm->lock);
3455 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3456 spin_unlock_irq(&hdspm->lock);
3457 return 0;
3458 }
3459
3460 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3461 struct snd_ctl_elem_value *ucontrol)
3462 {
3463 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3464 int change;
3465 int val;
3466
3467 if (!snd_hdspm_use_is_exclusive(hdspm))
3468 return -EBUSY;
3469 val = ucontrol->value.integer.value[0];
3470 if (val < 0)
3471 val = 0;
3472 if (val > 2)
3473 val = 2;
3474 spin_lock_irq(&hdspm->lock);
3475 change = val != hdspm_qs_wire(hdspm);
3476 hdspm_set_qs_wire(hdspm, val);
3477 spin_unlock_irq(&hdspm->lock);
3478 return change;
3479 }
3480
3481 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3482 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3483 .name = xname, \
3484 .private_value = xindex, \
3485 .info = snd_hdspm_info_tristate, \
3486 .get = snd_hdspm_get_tristate, \
3487 .put = snd_hdspm_put_tristate \
3488 }
3489
3490 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3491 {
3492 u32 reg = hdspm->settings_register & (regmask * 3);
3493 return reg / regmask;
3494 }
3495
3496 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3497 {
3498 hdspm->settings_register &= ~(regmask * 3);
3499 hdspm->settings_register |= (regmask * mode);
3500 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3501
3502 return 0;
3503 }
3504
3505 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3506 struct snd_ctl_elem_info *uinfo)
3507 {
3508 u32 regmask = kcontrol->private_value;
3509
3510 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3511 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3512
3513 switch (regmask) {
3514 case HDSPM_c0_Input0:
3515 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3516 break;
3517 default:
3518 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3519 break;
3520 }
3521 return 0;
3522 }
3523
3524 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3525 struct snd_ctl_elem_value *ucontrol)
3526 {
3527 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3528 u32 regmask = kcontrol->private_value;
3529
3530 spin_lock_irq(&hdspm->lock);
3531 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3532 spin_unlock_irq(&hdspm->lock);
3533 return 0;
3534 }
3535
3536 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3537 struct snd_ctl_elem_value *ucontrol)
3538 {
3539 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3540 u32 regmask = kcontrol->private_value;
3541 int change;
3542 int val;
3543
3544 if (!snd_hdspm_use_is_exclusive(hdspm))
3545 return -EBUSY;
3546 val = ucontrol->value.integer.value[0];
3547 if (val < 0)
3548 val = 0;
3549 if (val > 2)
3550 val = 2;
3551
3552 spin_lock_irq(&hdspm->lock);
3553 change = val != hdspm_tristate(hdspm, regmask);
3554 hdspm_set_tristate(hdspm, val, regmask);
3555 spin_unlock_irq(&hdspm->lock);
3556 return change;
3557 }
3558
3559 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3560 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3561 .name = xname, \
3562 .index = xindex, \
3563 .info = snd_hdspm_info_madi_speedmode, \
3564 .get = snd_hdspm_get_madi_speedmode, \
3565 .put = snd_hdspm_put_madi_speedmode \
3566 }
3567
3568 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3569 {
3570 if (hdspm->control_register & HDSPM_QuadSpeed)
3571 return 2;
3572 if (hdspm->control_register & HDSPM_DoubleSpeed)
3573 return 1;
3574 return 0;
3575 }
3576
3577 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3578 {
3579 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3580 switch (mode) {
3581 case 0:
3582 break;
3583 case 1:
3584 hdspm->control_register |= HDSPM_DoubleSpeed;
3585 break;
3586 case 2:
3587 hdspm->control_register |= HDSPM_QuadSpeed;
3588 break;
3589 }
3590 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3591
3592 return 0;
3593 }
3594
3595 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3596 struct snd_ctl_elem_info *uinfo)
3597 {
3598 static const char *const texts[] = { "Single", "Double", "Quad" };
3599 ENUMERATED_CTL_INFO(uinfo, texts);
3600 return 0;
3601 }
3602
3603 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3604 struct snd_ctl_elem_value *ucontrol)
3605 {
3606 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3607
3608 spin_lock_irq(&hdspm->lock);
3609 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3610 spin_unlock_irq(&hdspm->lock);
3611 return 0;
3612 }
3613
3614 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3615 struct snd_ctl_elem_value *ucontrol)
3616 {
3617 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3618 int change;
3619 int val;
3620
3621 if (!snd_hdspm_use_is_exclusive(hdspm))
3622 return -EBUSY;
3623 val = ucontrol->value.integer.value[0];
3624 if (val < 0)
3625 val = 0;
3626 if (val > 2)
3627 val = 2;
3628 spin_lock_irq(&hdspm->lock);
3629 change = val != hdspm_madi_speedmode(hdspm);
3630 hdspm_set_madi_speedmode(hdspm, val);
3631 spin_unlock_irq(&hdspm->lock);
3632 return change;
3633 }
3634
3635 #define HDSPM_MIXER(xname, xindex) \
3636 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3637 .name = xname, \
3638 .index = xindex, \
3639 .device = 0, \
3640 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3641 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3642 .info = snd_hdspm_info_mixer, \
3643 .get = snd_hdspm_get_mixer, \
3644 .put = snd_hdspm_put_mixer \
3645 }
3646
3647 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3648 struct snd_ctl_elem_info *uinfo)
3649 {
3650 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3651 uinfo->count = 3;
3652 uinfo->value.integer.min = 0;
3653 uinfo->value.integer.max = 65535;
3654 uinfo->value.integer.step = 1;
3655 return 0;
3656 }
3657
3658 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3659 struct snd_ctl_elem_value *ucontrol)
3660 {
3661 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3662 int source;
3663 int destination;
3664
3665 source = ucontrol->value.integer.value[0];
3666 if (source < 0)
3667 source = 0;
3668 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3669 source = 2 * HDSPM_MAX_CHANNELS - 1;
3670
3671 destination = ucontrol->value.integer.value[1];
3672 if (destination < 0)
3673 destination = 0;
3674 else if (destination >= HDSPM_MAX_CHANNELS)
3675 destination = HDSPM_MAX_CHANNELS - 1;
3676
3677 spin_lock_irq(&hdspm->lock);
3678 if (source >= HDSPM_MAX_CHANNELS)
3679 ucontrol->value.integer.value[2] =
3680 hdspm_read_pb_gain(hdspm, destination,
3681 source - HDSPM_MAX_CHANNELS);
3682 else
3683 ucontrol->value.integer.value[2] =
3684 hdspm_read_in_gain(hdspm, destination, source);
3685
3686 spin_unlock_irq(&hdspm->lock);
3687
3688 return 0;
3689 }
3690
3691 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3692 struct snd_ctl_elem_value *ucontrol)
3693 {
3694 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3695 int change;
3696 int source;
3697 int destination;
3698 int gain;
3699
3700 if (!snd_hdspm_use_is_exclusive(hdspm))
3701 return -EBUSY;
3702
3703 source = ucontrol->value.integer.value[0];
3704 destination = ucontrol->value.integer.value[1];
3705
3706 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3707 return -1;
3708 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3709 return -1;
3710
3711 gain = ucontrol->value.integer.value[2];
3712
3713 spin_lock_irq(&hdspm->lock);
3714
3715 if (source >= HDSPM_MAX_CHANNELS)
3716 change = gain != hdspm_read_pb_gain(hdspm, destination,
3717 source -
3718 HDSPM_MAX_CHANNELS);
3719 else
3720 change = gain != hdspm_read_in_gain(hdspm, destination,
3721 source);
3722
3723 if (change) {
3724 if (source >= HDSPM_MAX_CHANNELS)
3725 hdspm_write_pb_gain(hdspm, destination,
3726 source - HDSPM_MAX_CHANNELS,
3727 gain);
3728 else
3729 hdspm_write_in_gain(hdspm, destination, source,
3730 gain);
3731 }
3732 spin_unlock_irq(&hdspm->lock);
3733
3734 return change;
3735 }
3736
3737 /* The simple mixer control(s) provide gain control for the
3738 basic 1:1 mappings of playback streams to output
3739 streams.
3740 */
3741
3742 #define HDSPM_PLAYBACK_MIXER \
3743 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3744 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3745 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3746 .info = snd_hdspm_info_playback_mixer, \
3747 .get = snd_hdspm_get_playback_mixer, \
3748 .put = snd_hdspm_put_playback_mixer \
3749 }
3750
3751 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3752 struct snd_ctl_elem_info *uinfo)
3753 {
3754 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3755 uinfo->count = 1;
3756 uinfo->value.integer.min = 0;
3757 uinfo->value.integer.max = 64;
3758 uinfo->value.integer.step = 1;
3759 return 0;
3760 }
3761
3762 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3763 struct snd_ctl_elem_value *ucontrol)
3764 {
3765 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3766 int channel;
3767
3768 channel = ucontrol->id.index - 1;
3769
3770 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3771 return -EINVAL;
3772
3773 spin_lock_irq(&hdspm->lock);
3774 ucontrol->value.integer.value[0] =
3775 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3776 spin_unlock_irq(&hdspm->lock);
3777
3778 return 0;
3779 }
3780
3781 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3782 struct snd_ctl_elem_value *ucontrol)
3783 {
3784 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3785 int change;
3786 int channel;
3787 int gain;
3788
3789 if (!snd_hdspm_use_is_exclusive(hdspm))
3790 return -EBUSY;
3791
3792 channel = ucontrol->id.index - 1;
3793
3794 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3795 return -EINVAL;
3796
3797 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3798
3799 spin_lock_irq(&hdspm->lock);
3800 change =
3801 gain != hdspm_read_pb_gain(hdspm, channel,
3802 channel);
3803 if (change)
3804 hdspm_write_pb_gain(hdspm, channel, channel,
3805 gain);
3806 spin_unlock_irq(&hdspm->lock);
3807 return change;
3808 }
3809
3810 #define HDSPM_SYNC_CHECK(xname, xindex) \
3811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3812 .name = xname, \
3813 .private_value = xindex, \
3814 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3815 .info = snd_hdspm_info_sync_check, \
3816 .get = snd_hdspm_get_sync_check \
3817 }
3818
3819 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3820 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3821 .name = xname, \
3822 .private_value = xindex, \
3823 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3824 .info = snd_hdspm_tco_info_lock_check, \
3825 .get = snd_hdspm_get_sync_check \
3826 }
3827
3828
3829
3830 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3831 struct snd_ctl_elem_info *uinfo)
3832 {
3833 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3834 ENUMERATED_CTL_INFO(uinfo, texts);
3835 return 0;
3836 }
3837
3838 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3839 struct snd_ctl_elem_info *uinfo)
3840 {
3841 static const char *const texts[] = { "No Lock", "Lock" };
3842 ENUMERATED_CTL_INFO(uinfo, texts);
3843 return 0;
3844 }
3845
3846 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3847 {
3848 int status, status2;
3849
3850 switch (hdspm->io_type) {
3851 case AES32:
3852 status = hdspm_read(hdspm, HDSPM_statusRegister);
3853 if (status & HDSPM_AES32_wcLock) {
3854 if (status & HDSPM_AES32_wcSync)
3855 return 2;
3856 else
3857 return 1;
3858 }
3859 return 0;
3860 break;
3861
3862 case MADI:
3863 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3864 if (status2 & HDSPM_wcLock) {
3865 if (status2 & HDSPM_wcSync)
3866 return 2;
3867 else
3868 return 1;
3869 }
3870 return 0;
3871 break;
3872
3873 case RayDAT:
3874 case AIO:
3875 status = hdspm_read(hdspm, HDSPM_statusRegister);
3876
3877 if (status & 0x2000000)
3878 return 2;
3879 else if (status & 0x1000000)
3880 return 1;
3881 return 0;
3882
3883 break;
3884
3885 case MADIface:
3886 break;
3887 }
3888
3889
3890 return 3;
3891 }
3892
3893
3894 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3895 {
3896 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3897 if (status & HDSPM_madiLock) {
3898 if (status & HDSPM_madiSync)
3899 return 2;
3900 else
3901 return 1;
3902 }
3903 return 0;
3904 }
3905
3906
3907 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3908 {
3909 int status, lock, sync;
3910
3911 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3912
3913 lock = (status & (0x1<<idx)) ? 1 : 0;
3914 sync = (status & (0x100<<idx)) ? 1 : 0;
3915
3916 if (lock && sync)
3917 return 2;
3918 else if (lock)
3919 return 1;
3920 return 0;
3921 }
3922
3923
3924 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3925 {
3926 int status, lock = 0, sync = 0;
3927
3928 switch (hdspm->io_type) {
3929 case RayDAT:
3930 case AIO:
3931 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3932 lock = (status & 0x400) ? 1 : 0;
3933 sync = (status & 0x800) ? 1 : 0;
3934 break;
3935
3936 case MADI:
3937 status = hdspm_read(hdspm, HDSPM_statusRegister);
3938 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3939 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3940 break;
3941
3942 case AES32:
3943 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3944 lock = (status & 0x100000) ? 1 : 0;
3945 sync = (status & 0x200000) ? 1 : 0;
3946 break;
3947
3948 case MADIface:
3949 break;
3950 }
3951
3952 if (lock && sync)
3953 return 2;
3954 else if (lock)
3955 return 1;
3956
3957 return 0;
3958 }
3959
3960 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3961 {
3962 int status2, lock, sync;
3963 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3964
3965 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3966 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3967
3968 if (sync)
3969 return 2;
3970 else if (lock)
3971 return 1;
3972 return 0;
3973 }
3974
3975 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3976 {
3977 u32 status;
3978 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3979
3980 return (status & mask) ? 1 : 0;
3981 }
3982
3983
3984 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3985 {
3986 int status;
3987
3988 if (hdspm->tco) {
3989 switch (hdspm->io_type) {
3990 case MADI:
3991 status = hdspm_read(hdspm, HDSPM_statusRegister);
3992 if (status & HDSPM_tcoLockMadi) {
3993 if (status & HDSPM_tcoSync)
3994 return 2;
3995 else
3996 return 1;
3997 }
3998 return 0;
3999 break;
4000 case AES32:
4001 status = hdspm_read(hdspm, HDSPM_statusRegister);
4002 if (status & HDSPM_tcoLockAes) {
4003 if (status & HDSPM_tcoSync)
4004 return 2;
4005 else
4006 return 1;
4007 }
4008 return 0;
4009
4010 break;
4011
4012 case RayDAT:
4013 case AIO:
4014 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
4015
4016 if (status & 0x8000000)
4017 return 2; /* Sync */
4018 if (status & 0x4000000)
4019 return 1; /* Lock */
4020 return 0; /* No signal */
4021 break;
4022
4023 default:
4024 break;
4025 }
4026 }
4027
4028 return 3; /* N/A */
4029 }
4030
4031
4032 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4033 struct snd_ctl_elem_value *ucontrol)
4034 {
4035 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4036 int val = -1;
4037
4038 switch (hdspm->io_type) {
4039 case RayDAT:
4040 switch (kcontrol->private_value) {
4041 case 0: /* WC */
4042 val = hdspm_wc_sync_check(hdspm); break;
4043 case 7: /* TCO */
4044 val = hdspm_tco_sync_check(hdspm); break;
4045 case 8: /* SYNC IN */
4046 val = hdspm_sync_in_sync_check(hdspm); break;
4047 default:
4048 val = hdspm_s1_sync_check(hdspm,
4049 kcontrol->private_value-1);
4050 }
4051 break;
4052
4053 case AIO:
4054 switch (kcontrol->private_value) {
4055 case 0: /* WC */
4056 val = hdspm_wc_sync_check(hdspm); break;
4057 case 4: /* TCO */
4058 val = hdspm_tco_sync_check(hdspm); break;
4059 case 5: /* SYNC IN */
4060 val = hdspm_sync_in_sync_check(hdspm); break;
4061 default:
4062 val = hdspm_s1_sync_check(hdspm,
4063 kcontrol->private_value-1);
4064 }
4065 break;
4066
4067 case MADI:
4068 switch (kcontrol->private_value) {
4069 case 0: /* WC */
4070 val = hdspm_wc_sync_check(hdspm); break;
4071 case 1: /* MADI */
4072 val = hdspm_madi_sync_check(hdspm); break;
4073 case 2: /* TCO */
4074 val = hdspm_tco_sync_check(hdspm); break;
4075 case 3: /* SYNC_IN */
4076 val = hdspm_sync_in_sync_check(hdspm); break;
4077 }
4078 break;
4079
4080 case MADIface:
4081 val = hdspm_madi_sync_check(hdspm); /* MADI */
4082 break;
4083
4084 case AES32:
4085 switch (kcontrol->private_value) {
4086 case 0: /* WC */
4087 val = hdspm_wc_sync_check(hdspm); break;
4088 case 9: /* TCO */
4089 val = hdspm_tco_sync_check(hdspm); break;
4090 case 10 /* SYNC IN */:
4091 val = hdspm_sync_in_sync_check(hdspm); break;
4092 default: /* AES1 to AES8 */
4093 val = hdspm_aes_sync_check(hdspm,
4094 kcontrol->private_value-1);
4095 }
4096 break;
4097
4098 }
4099
4100 if (hdspm->tco) {
4101 switch (kcontrol->private_value) {
4102 case 11:
4103 /* Check TCO for lock state of its current input */
4104 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4105 break;
4106 case 12:
4107 /* Check TCO for valid time code on LTC input. */
4108 val = hdspm_tco_input_check(hdspm,
4109 HDSPM_TCO1_LTC_Input_valid);
4110 break;
4111 default:
4112 break;
4113 }
4114 }
4115
4116 if (-1 == val)
4117 val = 3;
4118
4119 ucontrol->value.enumerated.item[0] = val;
4120 return 0;
4121 }
4122
4123
4124
4125 /**
4126 * TCO controls
4127 **/
4128 static void hdspm_tco_write(struct hdspm *hdspm)
4129 {
4130 unsigned int tc[4] = { 0, 0, 0, 0};
4131
4132 switch (hdspm->tco->input) {
4133 case 0:
4134 tc[2] |= HDSPM_TCO2_set_input_MSB;
4135 break;
4136 case 1:
4137 tc[2] |= HDSPM_TCO2_set_input_LSB;
4138 break;
4139 default:
4140 break;
4141 }
4142
4143 switch (hdspm->tco->framerate) {
4144 case 1:
4145 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4146 break;
4147 case 2:
4148 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4149 break;
4150 case 3:
4151 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4152 HDSPM_TCO1_set_drop_frame_flag;
4153 break;
4154 case 4:
4155 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4156 HDSPM_TCO1_LTC_Format_MSB;
4157 break;
4158 case 5:
4159 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4160 HDSPM_TCO1_LTC_Format_MSB +
4161 HDSPM_TCO1_set_drop_frame_flag;
4162 break;
4163 default:
4164 break;
4165 }
4166
4167 switch (hdspm->tco->wordclock) {
4168 case 1:
4169 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4170 break;
4171 case 2:
4172 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4173 break;
4174 default:
4175 break;
4176 }
4177
4178 switch (hdspm->tco->samplerate) {
4179 case 1:
4180 tc[2] |= HDSPM_TCO2_set_freq;
4181 break;
4182 case 2:
4183 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4184 break;
4185 default:
4186 break;
4187 }
4188
4189 switch (hdspm->tco->pull) {
4190 case 1:
4191 tc[2] |= HDSPM_TCO2_set_pull_up;
4192 break;
4193 case 2:
4194 tc[2] |= HDSPM_TCO2_set_pull_down;
4195 break;
4196 case 3:
4197 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4198 break;
4199 case 4:
4200 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4201 break;
4202 default:
4203 break;
4204 }
4205
4206 if (1 == hdspm->tco->term) {
4207 tc[2] |= HDSPM_TCO2_set_term_75R;
4208 }
4209
4210 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4211 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4212 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4213 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4214 }
4215
4216
4217 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4218 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4219 .name = xname, \
4220 .index = xindex, \
4221 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4222 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4223 .info = snd_hdspm_info_tco_sample_rate, \
4224 .get = snd_hdspm_get_tco_sample_rate, \
4225 .put = snd_hdspm_put_tco_sample_rate \
4226 }
4227
4228 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4229 struct snd_ctl_elem_info *uinfo)
4230 {
4231 /* TODO freq from app could be supported here, see tco->samplerate */
4232 static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4233 ENUMERATED_CTL_INFO(uinfo, texts);
4234 return 0;
4235 }
4236
4237 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4238 struct snd_ctl_elem_value *ucontrol)
4239 {
4240 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4241
4242 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4243
4244 return 0;
4245 }
4246
4247 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4248 struct snd_ctl_elem_value *ucontrol)
4249 {
4250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4251
4252 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4253 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4254
4255 hdspm_tco_write(hdspm);
4256
4257 return 1;
4258 }
4259
4260 return 0;
4261 }
4262
4263
4264 #define HDSPM_TCO_PULL(xname, xindex) \
4265 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4266 .name = xname, \
4267 .index = xindex, \
4268 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4269 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4270 .info = snd_hdspm_info_tco_pull, \
4271 .get = snd_hdspm_get_tco_pull, \
4272 .put = snd_hdspm_put_tco_pull \
4273 }
4274
4275 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4276 struct snd_ctl_elem_info *uinfo)
4277 {
4278 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4279 "+ 4 %", "- 4 %" };
4280 ENUMERATED_CTL_INFO(uinfo, texts);
4281 return 0;
4282 }
4283
4284 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4285 struct snd_ctl_elem_value *ucontrol)
4286 {
4287 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4288
4289 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4290
4291 return 0;
4292 }
4293
4294 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4295 struct snd_ctl_elem_value *ucontrol)
4296 {
4297 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4298
4299 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4300 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4301
4302 hdspm_tco_write(hdspm);
4303
4304 return 1;
4305 }
4306
4307 return 0;
4308 }
4309
4310 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4311 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4312 .name = xname, \
4313 .index = xindex, \
4314 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4315 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4316 .info = snd_hdspm_info_tco_wck_conversion, \
4317 .get = snd_hdspm_get_tco_wck_conversion, \
4318 .put = snd_hdspm_put_tco_wck_conversion \
4319 }
4320
4321 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4322 struct snd_ctl_elem_info *uinfo)
4323 {
4324 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4325 ENUMERATED_CTL_INFO(uinfo, texts);
4326 return 0;
4327 }
4328
4329 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4330 struct snd_ctl_elem_value *ucontrol)
4331 {
4332 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4333
4334 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4335
4336 return 0;
4337 }
4338
4339 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4340 struct snd_ctl_elem_value *ucontrol)
4341 {
4342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4343
4344 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4345 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4346
4347 hdspm_tco_write(hdspm);
4348
4349 return 1;
4350 }
4351
4352 return 0;
4353 }
4354
4355
4356 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4357 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4358 .name = xname, \
4359 .index = xindex, \
4360 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4361 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4362 .info = snd_hdspm_info_tco_frame_rate, \
4363 .get = snd_hdspm_get_tco_frame_rate, \
4364 .put = snd_hdspm_put_tco_frame_rate \
4365 }
4366
4367 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4368 struct snd_ctl_elem_info *uinfo)
4369 {
4370 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4371 "29.97 dfps", "30 fps", "30 dfps" };
4372 ENUMERATED_CTL_INFO(uinfo, texts);
4373 return 0;
4374 }
4375
4376 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4377 struct snd_ctl_elem_value *ucontrol)
4378 {
4379 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4380
4381 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4382
4383 return 0;
4384 }
4385
4386 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4387 struct snd_ctl_elem_value *ucontrol)
4388 {
4389 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4390
4391 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4392 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4393
4394 hdspm_tco_write(hdspm);
4395
4396 return 1;
4397 }
4398
4399 return 0;
4400 }
4401
4402
4403 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4405 .name = xname, \
4406 .index = xindex, \
4407 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4408 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4409 .info = snd_hdspm_info_tco_sync_source, \
4410 .get = snd_hdspm_get_tco_sync_source, \
4411 .put = snd_hdspm_put_tco_sync_source \
4412 }
4413
4414 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4415 struct snd_ctl_elem_info *uinfo)
4416 {
4417 static const char *const texts[] = { "LTC", "Video", "WCK" };
4418 ENUMERATED_CTL_INFO(uinfo, texts);
4419 return 0;
4420 }
4421
4422 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4423 struct snd_ctl_elem_value *ucontrol)
4424 {
4425 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4426
4427 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4428
4429 return 0;
4430 }
4431
4432 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4433 struct snd_ctl_elem_value *ucontrol)
4434 {
4435 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4436
4437 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4438 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4439
4440 hdspm_tco_write(hdspm);
4441
4442 return 1;
4443 }
4444
4445 return 0;
4446 }
4447
4448
4449 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4450 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4451 .name = xname, \
4452 .index = xindex, \
4453 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4454 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4455 .info = snd_hdspm_info_tco_word_term, \
4456 .get = snd_hdspm_get_tco_word_term, \
4457 .put = snd_hdspm_put_tco_word_term \
4458 }
4459
4460 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4461 struct snd_ctl_elem_info *uinfo)
4462 {
4463 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4464 uinfo->count = 1;
4465 uinfo->value.integer.min = 0;
4466 uinfo->value.integer.max = 1;
4467
4468 return 0;
4469 }
4470
4471
4472 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4473 struct snd_ctl_elem_value *ucontrol)
4474 {
4475 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4476
4477 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4478
4479 return 0;
4480 }
4481
4482
4483 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4484 struct snd_ctl_elem_value *ucontrol)
4485 {
4486 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4487
4488 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4489 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4490
4491 hdspm_tco_write(hdspm);
4492
4493 return 1;
4494 }
4495
4496 return 0;
4497 }
4498
4499
4500
4501
4502 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4503 HDSPM_MIXER("Mixer", 0),
4504 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4505 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4506 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4507 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4508 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4509 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4510 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4511 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4512 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4513 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4514 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4515 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4516 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4517 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4518 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4519 HDSPM_INPUT_SELECT("Input Select", 0),
4520 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4521 };
4522
4523
4524 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4525 HDSPM_MIXER("Mixer", 0),
4526 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4527 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4528 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4529 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4530 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4531 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4532 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4533 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4534 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4535 };
4536
4537 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4538 HDSPM_MIXER("Mixer", 0),
4539 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4540 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4541 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4542 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4543 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4544 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4545 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4546 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4547 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4548 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4549 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4550 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4551 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4552 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4553 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4554 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4555 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4556 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4557 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4558 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4559 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4560 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4561 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4562 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4563 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4564 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4565
4566 /*
4567 HDSPM_INPUT_SELECT("Input Select", 0),
4568 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4569 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4570 HDSPM_SPDIF_IN("SPDIF In", 0);
4571 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4572 HDSPM_INPUT_LEVEL("Input Level", 0);
4573 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4574 HDSPM_PHONES("Phones", 0);
4575 */
4576 };
4577
4578 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4579 HDSPM_MIXER("Mixer", 0),
4580 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4581 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4582 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4583 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4584 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4585 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4586 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4587 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4588 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4589 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4590 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4591 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4592 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4593 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4594 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4595 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4596 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4597 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4598 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4599 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4600 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4601 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4602 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4603 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4604 };
4605
4606 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4607 HDSPM_MIXER("Mixer", 0),
4608 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4609 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4610 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4611 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4612 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4613 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4614 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4615 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4616 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4617 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4618 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4619 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4620 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4621 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4622 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4623 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4624 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4625 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4626 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4627 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4628 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4629 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4630 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4631 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4632 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4633 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4634 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4635 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4636 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4637 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4638 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4639 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4640 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4641 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4642 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4643 };
4644
4645
4646
4647 /* Control elements for the optional TCO module */
4648 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4649 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4650 HDSPM_TCO_PULL("TCO Pull", 0),
4651 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4652 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4653 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4654 HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4655 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4656 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4657 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4658 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4659 };
4660
4661
4662 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4663
4664
4665 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4666 {
4667 int i;
4668
4669 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4670 if (hdspm->system_sample_rate > 48000) {
4671 hdspm->playback_mixer_ctls[i]->vd[0].access =
4672 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4673 SNDRV_CTL_ELEM_ACCESS_READ |
4674 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4675 } else {
4676 hdspm->playback_mixer_ctls[i]->vd[0].access =
4677 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4678 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4679 }
4680 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4681 SNDRV_CTL_EVENT_MASK_INFO,
4682 &hdspm->playback_mixer_ctls[i]->id);
4683 }
4684
4685 return 0;
4686 }
4687
4688
4689 static int snd_hdspm_create_controls(struct snd_card *card,
4690 struct hdspm *hdspm)
4691 {
4692 unsigned int idx, limit;
4693 int err;
4694 struct snd_kcontrol *kctl;
4695 struct snd_kcontrol_new *list = NULL;
4696
4697 switch (hdspm->io_type) {
4698 case MADI:
4699 list = snd_hdspm_controls_madi;
4700 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4701 break;
4702 case MADIface:
4703 list = snd_hdspm_controls_madiface;
4704 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4705 break;
4706 case AIO:
4707 list = snd_hdspm_controls_aio;
4708 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4709 break;
4710 case RayDAT:
4711 list = snd_hdspm_controls_raydat;
4712 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4713 break;
4714 case AES32:
4715 list = snd_hdspm_controls_aes32;
4716 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4717 break;
4718 }
4719
4720 if (NULL != list) {
4721 for (idx = 0; idx < limit; idx++) {
4722 err = snd_ctl_add(card,
4723 snd_ctl_new1(&list[idx], hdspm));
4724 if (err < 0)
4725 return err;
4726 }
4727 }
4728
4729
4730 /* create simple 1:1 playback mixer controls */
4731 snd_hdspm_playback_mixer.name = "Chn";
4732 if (hdspm->system_sample_rate >= 128000) {
4733 limit = hdspm->qs_out_channels;
4734 } else if (hdspm->system_sample_rate >= 64000) {
4735 limit = hdspm->ds_out_channels;
4736 } else {
4737 limit = hdspm->ss_out_channels;
4738 }
4739 for (idx = 0; idx < limit; ++idx) {
4740 snd_hdspm_playback_mixer.index = idx + 1;
4741 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4742 err = snd_ctl_add(card, kctl);
4743 if (err < 0)
4744 return err;
4745 hdspm->playback_mixer_ctls[idx] = kctl;
4746 }
4747
4748
4749 if (hdspm->tco) {
4750 /* add tco control elements */
4751 list = snd_hdspm_controls_tco;
4752 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4753 for (idx = 0; idx < limit; idx++) {
4754 err = snd_ctl_add(card,
4755 snd_ctl_new1(&list[idx], hdspm));
4756 if (err < 0)
4757 return err;
4758 }
4759 }
4760
4761 return 0;
4762 }
4763
4764 /*------------------------------------------------------------
4765 /proc interface
4766 ------------------------------------------------------------*/
4767
4768 static void
4769 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4770 struct snd_info_buffer *buffer)
4771 {
4772 struct hdspm *hdspm = entry->private_data;
4773 unsigned int status, control;
4774 int a, ltc, frames, seconds, minutes, hours;
4775 unsigned int period;
4776 u64 freq_const = 0;
4777 u32 rate;
4778
4779 snd_iprintf(buffer, "--- TCO ---\n");
4780
4781 status = hdspm_read(hdspm, HDSPM_statusRegister);
4782 control = hdspm->control_register;
4783
4784
4785 if (status & HDSPM_tco_detect) {
4786 snd_iprintf(buffer, "TCO module detected.\n");
4787 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4788 if (a & HDSPM_TCO1_LTC_Input_valid) {
4789 snd_iprintf(buffer, " LTC valid, ");
4790 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4791 HDSPM_TCO1_LTC_Format_MSB)) {
4792 case 0:
4793 snd_iprintf(buffer, "24 fps, ");
4794 break;
4795 case HDSPM_TCO1_LTC_Format_LSB:
4796 snd_iprintf(buffer, "25 fps, ");
4797 break;
4798 case HDSPM_TCO1_LTC_Format_MSB:
4799 snd_iprintf(buffer, "29.97 fps, ");
4800 break;
4801 default:
4802 snd_iprintf(buffer, "30 fps, ");
4803 break;
4804 }
4805 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4806 snd_iprintf(buffer, "drop frame\n");
4807 } else {
4808 snd_iprintf(buffer, "full frame\n");
4809 }
4810 } else {
4811 snd_iprintf(buffer, " no LTC\n");
4812 }
4813 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4814 snd_iprintf(buffer, " Video: NTSC\n");
4815 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4816 snd_iprintf(buffer, " Video: PAL\n");
4817 } else {
4818 snd_iprintf(buffer, " No video\n");
4819 }
4820 if (a & HDSPM_TCO1_TCO_lock) {
4821 snd_iprintf(buffer, " Sync: lock\n");
4822 } else {
4823 snd_iprintf(buffer, " Sync: no lock\n");
4824 }
4825
4826 switch (hdspm->io_type) {
4827 case MADI:
4828 case AES32:
4829 freq_const = 110069313433624ULL;
4830 break;
4831 case RayDAT:
4832 case AIO:
4833 freq_const = 104857600000000ULL;
4834 break;
4835 case MADIface:
4836 break; /* no TCO possible */
4837 }
4838
4839 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4840 snd_iprintf(buffer, " period: %u\n", period);
4841
4842
4843 /* rate = freq_const/period; */
4844 rate = div_u64(freq_const, period);
4845
4846 if (control & HDSPM_QuadSpeed) {
4847 rate *= 4;
4848 } else if (control & HDSPM_DoubleSpeed) {
4849 rate *= 2;
4850 }
4851
4852 snd_iprintf(buffer, " Frequency: %u Hz\n",
4853 (unsigned int) rate);
4854
4855 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4856 frames = ltc & 0xF;
4857 ltc >>= 4;
4858 frames += (ltc & 0x3) * 10;
4859 ltc >>= 4;
4860 seconds = ltc & 0xF;
4861 ltc >>= 4;
4862 seconds += (ltc & 0x7) * 10;
4863 ltc >>= 4;
4864 minutes = ltc & 0xF;
4865 ltc >>= 4;
4866 minutes += (ltc & 0x7) * 10;
4867 ltc >>= 4;
4868 hours = ltc & 0xF;
4869 ltc >>= 4;
4870 hours += (ltc & 0x3) * 10;
4871 snd_iprintf(buffer,
4872 " LTC In: %02d:%02d:%02d:%02d\n",
4873 hours, minutes, seconds, frames);
4874
4875 } else {
4876 snd_iprintf(buffer, "No TCO module detected.\n");
4877 }
4878 }
4879
4880 static void
4881 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4882 struct snd_info_buffer *buffer)
4883 {
4884 struct hdspm *hdspm = entry->private_data;
4885 unsigned int status, status2, control, freq;
4886
4887 char *pref_sync_ref;
4888 char *autosync_ref;
4889 char *system_clock_mode;
4890 char *insel;
4891 int x, x2;
4892
4893 status = hdspm_read(hdspm, HDSPM_statusRegister);
4894 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4895 control = hdspm->control_register;
4896 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4897
4898 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4899 hdspm->card_name, hdspm->card->number + 1,
4900 hdspm->firmware_rev,
4901 (status2 & HDSPM_version0) |
4902 (status2 & HDSPM_version1) | (status2 &
4903 HDSPM_version2));
4904
4905 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4906 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4907 hdspm->serial);
4908
4909 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4910 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4911
4912 snd_iprintf(buffer, "--- System ---\n");
4913
4914 snd_iprintf(buffer,
4915 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4916 status & HDSPM_audioIRQPending,
4917 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4918 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4919 hdspm->irq_count);
4920 snd_iprintf(buffer,
4921 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4922 "estimated= %ld (bytes)\n",
4923 ((status & HDSPM_BufferID) ? 1 : 0),
4924 (status & HDSPM_BufferPositionMask),
4925 (status & HDSPM_BufferPositionMask) %
4926 (2 * (int)hdspm->period_bytes),
4927 ((status & HDSPM_BufferPositionMask) - 64) %
4928 (2 * (int)hdspm->period_bytes),
4929 (long) hdspm_hw_pointer(hdspm) * 4);
4930
4931 snd_iprintf(buffer,
4932 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4933 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4934 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4935 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4936 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4937 snd_iprintf(buffer,
4938 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4939 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4940 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4941 snd_iprintf(buffer,
4942 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4943 "status2=0x%x\n",
4944 hdspm->control_register, hdspm->control2_register,
4945 status, status2);
4946
4947
4948 snd_iprintf(buffer, "--- Settings ---\n");
4949
4950 x = hdspm_get_latency(hdspm);
4951
4952 snd_iprintf(buffer,
4953 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4954 x, (unsigned long) hdspm->period_bytes);
4955
4956 snd_iprintf(buffer, "Line out: %s\n",
4957 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4958
4959 switch (hdspm->control_register & HDSPM_InputMask) {
4960 case HDSPM_InputOptical:
4961 insel = "Optical";
4962 break;
4963 case HDSPM_InputCoaxial:
4964 insel = "Coaxial";
4965 break;
4966 default:
4967 insel = "Unknown";
4968 }
4969
4970 snd_iprintf(buffer,
4971 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4972 "Auto Input %s\n",
4973 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4974 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4975 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4976
4977
4978 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4979 system_clock_mode = "AutoSync";
4980 else
4981 system_clock_mode = "Master";
4982 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4983
4984 switch (hdspm_pref_sync_ref(hdspm)) {
4985 case HDSPM_SYNC_FROM_WORD:
4986 pref_sync_ref = "Word Clock";
4987 break;
4988 case HDSPM_SYNC_FROM_MADI:
4989 pref_sync_ref = "MADI Sync";
4990 break;
4991 case HDSPM_SYNC_FROM_TCO:
4992 pref_sync_ref = "TCO";
4993 break;
4994 case HDSPM_SYNC_FROM_SYNC_IN:
4995 pref_sync_ref = "Sync In";
4996 break;
4997 default:
4998 pref_sync_ref = "XXXX Clock";
4999 break;
5000 }
5001 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
5002 pref_sync_ref);
5003
5004 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5005 hdspm->system_sample_rate);
5006
5007
5008 snd_iprintf(buffer, "--- Status:\n");
5009
5010 x = status & HDSPM_madiSync;
5011 x2 = status2 & HDSPM_wcSync;
5012
5013 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
5014 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
5015 "NoLock",
5016 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
5017 "NoLock");
5018
5019 switch (hdspm_autosync_ref(hdspm)) {
5020 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
5021 autosync_ref = "Sync In";
5022 break;
5023 case HDSPM_AUTOSYNC_FROM_TCO:
5024 autosync_ref = "TCO";
5025 break;
5026 case HDSPM_AUTOSYNC_FROM_WORD:
5027 autosync_ref = "Word Clock";
5028 break;
5029 case HDSPM_AUTOSYNC_FROM_MADI:
5030 autosync_ref = "MADI Sync";
5031 break;
5032 case HDSPM_AUTOSYNC_FROM_NONE:
5033 autosync_ref = "Input not valid";
5034 break;
5035 default:
5036 autosync_ref = "---";
5037 break;
5038 }
5039 snd_iprintf(buffer,
5040 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5041 autosync_ref, hdspm_external_sample_rate(hdspm),
5042 (status & HDSPM_madiFreqMask) >> 22,
5043 (status2 & HDSPM_wcFreqMask) >> 5);
5044
5045 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5046 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5047 (status & HDSPM_RX_64ch) ? "64 channels" :
5048 "56 channels");
5049
5050 /* call readout function for TCO specific status */
5051 snd_hdspm_proc_read_tco(entry, buffer);
5052
5053 snd_iprintf(buffer, "\n");
5054 }
5055
5056 static void
5057 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5058 struct snd_info_buffer *buffer)
5059 {
5060 struct hdspm *hdspm = entry->private_data;
5061 unsigned int status;
5062 unsigned int status2;
5063 unsigned int timecode;
5064 unsigned int wcLock, wcSync;
5065 int pref_syncref;
5066 char *autosync_ref;
5067 int x;
5068
5069 status = hdspm_read(hdspm, HDSPM_statusRegister);
5070 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5071 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5072
5073 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5074 hdspm->card_name, hdspm->card->number + 1,
5075 hdspm->firmware_rev);
5076
5077 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5078 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5079
5080 snd_iprintf(buffer, "--- System ---\n");
5081
5082 snd_iprintf(buffer,
5083 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5084 status & HDSPM_audioIRQPending,
5085 (status & HDSPM_midi0IRQPending) ? 1 : 0,
5086 (status & HDSPM_midi1IRQPending) ? 1 : 0,
5087 hdspm->irq_count);
5088 snd_iprintf(buffer,
5089 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5090 "estimated= %ld (bytes)\n",
5091 ((status & HDSPM_BufferID) ? 1 : 0),
5092 (status & HDSPM_BufferPositionMask),
5093 (status & HDSPM_BufferPositionMask) %
5094 (2 * (int)hdspm->period_bytes),
5095 ((status & HDSPM_BufferPositionMask) - 64) %
5096 (2 * (int)hdspm->period_bytes),
5097 (long) hdspm_hw_pointer(hdspm) * 4);
5098
5099 snd_iprintf(buffer,
5100 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5101 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5102 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5103 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5104 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5105 snd_iprintf(buffer,
5106 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5107 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5108 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5109 snd_iprintf(buffer,
5110 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5111 "status2=0x%x\n",
5112 hdspm->control_register, hdspm->control2_register,
5113 status, status2);
5114
5115 snd_iprintf(buffer, "--- Settings ---\n");
5116
5117 x = hdspm_get_latency(hdspm);
5118
5119 snd_iprintf(buffer,
5120 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5121 x, (unsigned long) hdspm->period_bytes);
5122
5123 snd_iprintf(buffer, "Line out: %s\n",
5124 (hdspm->
5125 control_register & HDSPM_LineOut) ? "on " : "off");
5126
5127 snd_iprintf(buffer,
5128 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5129 (hdspm->
5130 control_register & HDSPM_clr_tms) ? "on" : "off",
5131 (hdspm->
5132 control_register & HDSPM_Emphasis) ? "on" : "off",
5133 (hdspm->
5134 control_register & HDSPM_Dolby) ? "on" : "off");
5135
5136
5137 pref_syncref = hdspm_pref_sync_ref(hdspm);
5138 if (pref_syncref == 0)
5139 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5140 else
5141 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5142 pref_syncref);
5143
5144 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5145 hdspm->system_sample_rate);
5146
5147 snd_iprintf(buffer, "Double speed: %s\n",
5148 hdspm->control_register & HDSPM_DS_DoubleWire?
5149 "Double wire" : "Single wire");
5150 snd_iprintf(buffer, "Quad speed: %s\n",
5151 hdspm->control_register & HDSPM_QS_DoubleWire?
5152 "Double wire" :
5153 hdspm->control_register & HDSPM_QS_QuadWire?
5154 "Quad wire" : "Single wire");
5155
5156 snd_iprintf(buffer, "--- Status:\n");
5157
5158 wcLock = status & HDSPM_AES32_wcLock;
5159 wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5160
5161 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5162 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
5163 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5164
5165 for (x = 0; x < 8; x++) {
5166 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5167 x+1,
5168 (status2 & (HDSPM_LockAES >> x)) ?
5169 "Sync " : "No Lock",
5170 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5171 }
5172
5173 switch (hdspm_autosync_ref(hdspm)) {
5174 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5175 autosync_ref = "None"; break;
5176 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5177 autosync_ref = "Word Clock"; break;
5178 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5179 autosync_ref = "AES1"; break;
5180 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5181 autosync_ref = "AES2"; break;
5182 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5183 autosync_ref = "AES3"; break;
5184 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5185 autosync_ref = "AES4"; break;
5186 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5187 autosync_ref = "AES5"; break;
5188 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5189 autosync_ref = "AES6"; break;
5190 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5191 autosync_ref = "AES7"; break;
5192 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5193 autosync_ref = "AES8"; break;
5194 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5195 autosync_ref = "TCO"; break;
5196 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5197 autosync_ref = "Sync In"; break;
5198 default:
5199 autosync_ref = "---"; break;
5200 }
5201 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5202
5203 /* call readout function for TCO specific status */
5204 snd_hdspm_proc_read_tco(entry, buffer);
5205
5206 snd_iprintf(buffer, "\n");
5207 }
5208
5209 static void
5210 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5211 struct snd_info_buffer *buffer)
5212 {
5213 struct hdspm *hdspm = entry->private_data;
5214 unsigned int status1, status2, status3, control, i;
5215 unsigned int lock, sync;
5216
5217 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5218 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5219 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5220
5221 control = hdspm->control_register;
5222
5223 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5224 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5225 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5226
5227
5228 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5229
5230 snd_iprintf(buffer, "Clock mode : %s\n",
5231 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5232 snd_iprintf(buffer, "System frequency: %d Hz\n",
5233 hdspm_get_system_sample_rate(hdspm));
5234
5235 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5236
5237 lock = 0x1;
5238 sync = 0x100;
5239
5240 for (i = 0; i < 8; i++) {
5241 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5242 i,
5243 (status1 & lock) ? 1 : 0,
5244 (status1 & sync) ? 1 : 0,
5245 texts_freq[(status2 >> (i * 4)) & 0xF]);
5246
5247 lock = lock<<1;
5248 sync = sync<<1;
5249 }
5250
5251 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5252 (status1 & 0x1000000) ? 1 : 0,
5253 (status1 & 0x2000000) ? 1 : 0,
5254 texts_freq[(status1 >> 16) & 0xF]);
5255
5256 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5257 (status1 & 0x4000000) ? 1 : 0,
5258 (status1 & 0x8000000) ? 1 : 0,
5259 texts_freq[(status1 >> 20) & 0xF]);
5260
5261 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5262 (status3 & 0x400) ? 1 : 0,
5263 (status3 & 0x800) ? 1 : 0,
5264 texts_freq[(status2 >> 12) & 0xF]);
5265
5266 }
5267
5268 #ifdef CONFIG_SND_DEBUG
5269 static void
5270 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5271 struct snd_info_buffer *buffer)
5272 {
5273 struct hdspm *hdspm = entry->private_data;
5274
5275 int j,i;
5276
5277 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5278 snd_iprintf(buffer, "0x%08X: ", i);
5279 for (j = 0; j < 16; j += 4)
5280 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5281 snd_iprintf(buffer, "\n");
5282 }
5283 }
5284 #endif
5285
5286
5287 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5288 struct snd_info_buffer *buffer)
5289 {
5290 struct hdspm *hdspm = entry->private_data;
5291 int i;
5292
5293 snd_iprintf(buffer, "# generated by hdspm\n");
5294
5295 for (i = 0; i < hdspm->max_channels_in; i++) {
5296 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5297 }
5298 }
5299
5300 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5301 struct snd_info_buffer *buffer)
5302 {
5303 struct hdspm *hdspm = entry->private_data;
5304 int i;
5305
5306 snd_iprintf(buffer, "# generated by hdspm\n");
5307
5308 for (i = 0; i < hdspm->max_channels_out; i++) {
5309 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5310 }
5311 }
5312
5313
5314 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5315 {
5316 struct snd_info_entry *entry;
5317
5318 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5319 switch (hdspm->io_type) {
5320 case AES32:
5321 snd_info_set_text_ops(entry, hdspm,
5322 snd_hdspm_proc_read_aes32);
5323 break;
5324 case MADI:
5325 snd_info_set_text_ops(entry, hdspm,
5326 snd_hdspm_proc_read_madi);
5327 break;
5328 case MADIface:
5329 /* snd_info_set_text_ops(entry, hdspm,
5330 snd_hdspm_proc_read_madiface); */
5331 break;
5332 case RayDAT:
5333 snd_info_set_text_ops(entry, hdspm,
5334 snd_hdspm_proc_read_raydat);
5335 break;
5336 case AIO:
5337 break;
5338 }
5339 }
5340
5341 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5342 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5343 }
5344
5345 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5346 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5347 }
5348
5349 #ifdef CONFIG_SND_DEBUG
5350 /* debug file to read all hdspm registers */
5351 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5352 snd_info_set_text_ops(entry, hdspm,
5353 snd_hdspm_proc_read_debug);
5354 #endif
5355 }
5356
5357 /*------------------------------------------------------------
5358 hdspm intitialize
5359 ------------------------------------------------------------*/
5360
5361 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5362 {
5363 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5364 hold it (e.g. during module initialization).
5365 */
5366
5367 /* set defaults: */
5368
5369 hdspm->settings_register = 0;
5370
5371 switch (hdspm->io_type) {
5372 case MADI:
5373 case MADIface:
5374 hdspm->control_register =
5375 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5376 break;
5377
5378 case RayDAT:
5379 case AIO:
5380 hdspm->settings_register = 0x1 + 0x1000;
5381 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5382 * line_out */
5383 hdspm->control_register =
5384 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5385 break;
5386
5387 case AES32:
5388 hdspm->control_register =
5389 HDSPM_ClockModeMaster | /* Master Clock Mode on */
5390 hdspm_encode_latency(7) | /* latency max=8192samples */
5391 HDSPM_SyncRef0 | /* AES1 is syncclock */
5392 HDSPM_LineOut | /* Analog output in */
5393 HDSPM_Professional; /* Professional mode */
5394 break;
5395 }
5396
5397 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5398
5399 if (AES32 == hdspm->io_type) {
5400 /* No control2 register for AES32 */
5401 #ifdef SNDRV_BIG_ENDIAN
5402 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5403 #else
5404 hdspm->control2_register = 0;
5405 #endif
5406
5407 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5408 }
5409 hdspm_compute_period_size(hdspm);
5410
5411 /* silence everything */
5412
5413 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5414
5415 if (hdspm_is_raydat_or_aio(hdspm))
5416 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5417
5418 /* set a default rate so that the channel map is set up. */
5419 hdspm_set_rate(hdspm, 48000, 1);
5420
5421 return 0;
5422 }
5423
5424
5425 /*------------------------------------------------------------
5426 interrupt
5427 ------------------------------------------------------------*/
5428
5429 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5430 {
5431 struct hdspm *hdspm = (struct hdspm *) dev_id;
5432 unsigned int status;
5433 int i, audio, midi, schedule = 0;
5434 /* cycles_t now; */
5435
5436 status = hdspm_read(hdspm, HDSPM_statusRegister);
5437
5438 audio = status & HDSPM_audioIRQPending;
5439 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5440 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5441
5442 /* now = get_cycles(); */
5443 /**
5444 * LAT_2..LAT_0 period counter (win) counter (mac)
5445 * 6 4096 ~256053425 ~514672358
5446 * 5 2048 ~128024983 ~257373821
5447 * 4 1024 ~64023706 ~128718089
5448 * 3 512 ~32005945 ~64385999
5449 * 2 256 ~16003039 ~32260176
5450 * 1 128 ~7998738 ~16194507
5451 * 0 64 ~3998231 ~8191558
5452 **/
5453 /*
5454 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5455 now-hdspm->last_interrupt, status & 0xFFC0);
5456 hdspm->last_interrupt = now;
5457 */
5458
5459 if (!audio && !midi)
5460 return IRQ_NONE;
5461
5462 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5463 hdspm->irq_count++;
5464
5465
5466 if (audio) {
5467 if (hdspm->capture_substream)
5468 snd_pcm_period_elapsed(hdspm->capture_substream);
5469
5470 if (hdspm->playback_substream)
5471 snd_pcm_period_elapsed(hdspm->playback_substream);
5472 }
5473
5474 if (midi) {
5475 i = 0;
5476 while (i < hdspm->midiPorts) {
5477 if ((hdspm_read(hdspm,
5478 hdspm->midi[i].statusIn) & 0xff) &&
5479 (status & hdspm->midi[i].irq)) {
5480 /* we disable interrupts for this input until
5481 * processing is done
5482 */
5483 hdspm->control_register &= ~hdspm->midi[i].ie;
5484 hdspm_write(hdspm, HDSPM_controlRegister,
5485 hdspm->control_register);
5486 hdspm->midi[i].pending = 1;
5487 schedule = 1;
5488 }
5489
5490 i++;
5491 }
5492
5493 if (schedule)
5494 tasklet_hi_schedule(&hdspm->midi_tasklet);
5495 }
5496
5497 return IRQ_HANDLED;
5498 }
5499
5500 /*------------------------------------------------------------
5501 pcm interface
5502 ------------------------------------------------------------*/
5503
5504
5505 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5506 *substream)
5507 {
5508 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5509 return hdspm_hw_pointer(hdspm);
5510 }
5511
5512
5513 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5514 {
5515 struct snd_pcm_runtime *runtime = substream->runtime;
5516 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5517 struct snd_pcm_substream *other;
5518
5519 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5520 other = hdspm->capture_substream;
5521 else
5522 other = hdspm->playback_substream;
5523
5524 if (hdspm->running)
5525 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5526 else
5527 runtime->status->hw_ptr = 0;
5528 if (other) {
5529 struct snd_pcm_substream *s;
5530 struct snd_pcm_runtime *oruntime = other->runtime;
5531 snd_pcm_group_for_each_entry(s, substream) {
5532 if (s == other) {
5533 oruntime->status->hw_ptr =
5534 runtime->status->hw_ptr;
5535 break;
5536 }
5537 }
5538 }
5539 return 0;
5540 }
5541
5542 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5543 struct snd_pcm_hw_params *params)
5544 {
5545 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5546 int err;
5547 int i;
5548 pid_t this_pid;
5549 pid_t other_pid;
5550
5551 spin_lock_irq(&hdspm->lock);
5552
5553 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5554 this_pid = hdspm->playback_pid;
5555 other_pid = hdspm->capture_pid;
5556 } else {
5557 this_pid = hdspm->capture_pid;
5558 other_pid = hdspm->playback_pid;
5559 }
5560
5561 if (other_pid > 0 && this_pid != other_pid) {
5562
5563 /* The other stream is open, and not by the same
5564 task as this one. Make sure that the parameters
5565 that matter are the same.
5566 */
5567
5568 if (params_rate(params) != hdspm->system_sample_rate) {
5569 spin_unlock_irq(&hdspm->lock);
5570 _snd_pcm_hw_param_setempty(params,
5571 SNDRV_PCM_HW_PARAM_RATE);
5572 return -EBUSY;
5573 }
5574
5575 if (params_period_size(params) != hdspm->period_bytes / 4) {
5576 spin_unlock_irq(&hdspm->lock);
5577 _snd_pcm_hw_param_setempty(params,
5578 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5579 return -EBUSY;
5580 }
5581
5582 }
5583 /* We're fine. */
5584 spin_unlock_irq(&hdspm->lock);
5585
5586 /* how to make sure that the rate matches an externally-set one ? */
5587
5588 spin_lock_irq(&hdspm->lock);
5589 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5590 if (err < 0) {
5591 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5592 spin_unlock_irq(&hdspm->lock);
5593 _snd_pcm_hw_param_setempty(params,
5594 SNDRV_PCM_HW_PARAM_RATE);
5595 return err;
5596 }
5597 spin_unlock_irq(&hdspm->lock);
5598
5599 err = hdspm_set_interrupt_interval(hdspm,
5600 params_period_size(params));
5601 if (err < 0) {
5602 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5603 _snd_pcm_hw_param_setempty(params,
5604 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5605 return err;
5606 }
5607
5608 /* Memory allocation, takashi's method, dont know if we should
5609 * spinlock
5610 */
5611 /* malloc all buffer even if not enabled to get sure */
5612 /* Update for MADI rev 204: we need to allocate for all channels,
5613 * otherwise it doesn't work at 96kHz */
5614
5615 err =
5616 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5617 if (err < 0) {
5618 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5619 return err;
5620 }
5621
5622 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5623
5624 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5625 params_channels(params));
5626
5627 for (i = 0; i < params_channels(params); ++i)
5628 snd_hdspm_enable_out(hdspm, i, 1);
5629
5630 hdspm->playback_buffer =
5631 (unsigned char *) substream->runtime->dma_area;
5632 snd_printdd("Allocated sample buffer for playback at %p\n",
5633 hdspm->playback_buffer);
5634 } else {
5635 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5636 params_channels(params));
5637
5638 for (i = 0; i < params_channels(params); ++i)
5639 snd_hdspm_enable_in(hdspm, i, 1);
5640
5641 hdspm->capture_buffer =
5642 (unsigned char *) substream->runtime->dma_area;
5643 snd_printdd("Allocated sample buffer for capture at %p\n",
5644 hdspm->capture_buffer);
5645 }
5646
5647 /*
5648 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5649 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5650 "playback" : "capture",
5651 snd_pcm_sgbuf_get_addr(substream, 0));
5652 */
5653 /*
5654 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5655 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5656 "playback" : "capture",
5657 params_rate(params), params_channels(params),
5658 params_buffer_size(params));
5659 */
5660
5661
5662 /* For AES cards, the float format bit is the same as the
5663 * preferred sync reference. Since we don't want to break
5664 * sync settings, we have to skip the remaining part of this
5665 * function.
5666 */
5667 if (hdspm->io_type == AES32) {
5668 return 0;
5669 }
5670
5671
5672 /* Switch to native float format if requested */
5673 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5674 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5675 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5676
5677 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5678 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5679 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5680 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5681
5682 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5683 }
5684 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5685
5686 return 0;
5687 }
5688
5689 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5690 {
5691 int i;
5692 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5693
5694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5695
5696 /* params_channels(params) should be enough,
5697 but to get sure in case of error */
5698 for (i = 0; i < hdspm->max_channels_out; ++i)
5699 snd_hdspm_enable_out(hdspm, i, 0);
5700
5701 hdspm->playback_buffer = NULL;
5702 } else {
5703 for (i = 0; i < hdspm->max_channels_in; ++i)
5704 snd_hdspm_enable_in(hdspm, i, 0);
5705
5706 hdspm->capture_buffer = NULL;
5707
5708 }
5709
5710 snd_pcm_lib_free_pages(substream);
5711
5712 return 0;
5713 }
5714
5715
5716 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5717 struct snd_pcm_channel_info *info)
5718 {
5719 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5720
5721 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5722 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5723 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5724 return -EINVAL;
5725 }
5726
5727 if (hdspm->channel_map_out[info->channel] < 0) {
5728 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5729 return -EINVAL;
5730 }
5731
5732 info->offset = hdspm->channel_map_out[info->channel] *
5733 HDSPM_CHANNEL_BUFFER_BYTES;
5734 } else {
5735 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5736 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5737 return -EINVAL;
5738 }
5739
5740 if (hdspm->channel_map_in[info->channel] < 0) {
5741 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5742 return -EINVAL;
5743 }
5744
5745 info->offset = hdspm->channel_map_in[info->channel] *
5746 HDSPM_CHANNEL_BUFFER_BYTES;
5747 }
5748
5749 info->first = 0;
5750 info->step = 32;
5751 return 0;
5752 }
5753
5754
5755 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5756 unsigned int cmd, void *arg)
5757 {
5758 switch (cmd) {
5759 case SNDRV_PCM_IOCTL1_RESET:
5760 return snd_hdspm_reset(substream);
5761
5762 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5763 {
5764 struct snd_pcm_channel_info *info = arg;
5765 return snd_hdspm_channel_info(substream, info);
5766 }
5767 default:
5768 break;
5769 }
5770
5771 return snd_pcm_lib_ioctl(substream, cmd, arg);
5772 }
5773
5774 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5775 {
5776 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5777 struct snd_pcm_substream *other;
5778 int running;
5779
5780 spin_lock(&hdspm->lock);
5781 running = hdspm->running;
5782 switch (cmd) {
5783 case SNDRV_PCM_TRIGGER_START:
5784 running |= 1 << substream->stream;
5785 break;
5786 case SNDRV_PCM_TRIGGER_STOP:
5787 running &= ~(1 << substream->stream);
5788 break;
5789 default:
5790 snd_BUG();
5791 spin_unlock(&hdspm->lock);
5792 return -EINVAL;
5793 }
5794 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5795 other = hdspm->capture_substream;
5796 else
5797 other = hdspm->playback_substream;
5798
5799 if (other) {
5800 struct snd_pcm_substream *s;
5801 snd_pcm_group_for_each_entry(s, substream) {
5802 if (s == other) {
5803 snd_pcm_trigger_done(s, substream);
5804 if (cmd == SNDRV_PCM_TRIGGER_START)
5805 running |= 1 << s->stream;
5806 else
5807 running &= ~(1 << s->stream);
5808 goto _ok;
5809 }
5810 }
5811 if (cmd == SNDRV_PCM_TRIGGER_START) {
5812 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5813 && substream->stream ==
5814 SNDRV_PCM_STREAM_CAPTURE)
5815 hdspm_silence_playback(hdspm);
5816 } else {
5817 if (running &&
5818 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5819 hdspm_silence_playback(hdspm);
5820 }
5821 } else {
5822 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5823 hdspm_silence_playback(hdspm);
5824 }
5825 _ok:
5826 snd_pcm_trigger_done(substream, substream);
5827 if (!hdspm->running && running)
5828 hdspm_start_audio(hdspm);
5829 else if (hdspm->running && !running)
5830 hdspm_stop_audio(hdspm);
5831 hdspm->running = running;
5832 spin_unlock(&hdspm->lock);
5833
5834 return 0;
5835 }
5836
5837 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5838 {
5839 return 0;
5840 }
5841
5842 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5843 .info = (SNDRV_PCM_INFO_MMAP |
5844 SNDRV_PCM_INFO_MMAP_VALID |
5845 SNDRV_PCM_INFO_NONINTERLEAVED |
5846 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5847 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5848 .rates = (SNDRV_PCM_RATE_32000 |
5849 SNDRV_PCM_RATE_44100 |
5850 SNDRV_PCM_RATE_48000 |
5851 SNDRV_PCM_RATE_64000 |
5852 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5853 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5854 .rate_min = 32000,
5855 .rate_max = 192000,
5856 .channels_min = 1,
5857 .channels_max = HDSPM_MAX_CHANNELS,
5858 .buffer_bytes_max =
5859 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5860 .period_bytes_min = (32 * 4),
5861 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5862 .periods_min = 2,
5863 .periods_max = 512,
5864 .fifo_size = 0
5865 };
5866
5867 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5868 .info = (SNDRV_PCM_INFO_MMAP |
5869 SNDRV_PCM_INFO_MMAP_VALID |
5870 SNDRV_PCM_INFO_NONINTERLEAVED |
5871 SNDRV_PCM_INFO_SYNC_START),
5872 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5873 .rates = (SNDRV_PCM_RATE_32000 |
5874 SNDRV_PCM_RATE_44100 |
5875 SNDRV_PCM_RATE_48000 |
5876 SNDRV_PCM_RATE_64000 |
5877 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5878 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5879 .rate_min = 32000,
5880 .rate_max = 192000,
5881 .channels_min = 1,
5882 .channels_max = HDSPM_MAX_CHANNELS,
5883 .buffer_bytes_max =
5884 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5885 .period_bytes_min = (32 * 4),
5886 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5887 .periods_min = 2,
5888 .periods_max = 512,
5889 .fifo_size = 0
5890 };
5891
5892 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5893 struct snd_pcm_hw_rule *rule)
5894 {
5895 struct hdspm *hdspm = rule->private;
5896 struct snd_interval *c =
5897 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5898 struct snd_interval *r =
5899 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5900
5901 if (r->min > 96000 && r->max <= 192000) {
5902 struct snd_interval t = {
5903 .min = hdspm->qs_in_channels,
5904 .max = hdspm->qs_in_channels,
5905 .integer = 1,
5906 };
5907 return snd_interval_refine(c, &t);
5908 } else if (r->min > 48000 && r->max <= 96000) {
5909 struct snd_interval t = {
5910 .min = hdspm->ds_in_channels,
5911 .max = hdspm->ds_in_channels,
5912 .integer = 1,
5913 };
5914 return snd_interval_refine(c, &t);
5915 } else if (r->max < 64000) {
5916 struct snd_interval t = {
5917 .min = hdspm->ss_in_channels,
5918 .max = hdspm->ss_in_channels,
5919 .integer = 1,
5920 };
5921 return snd_interval_refine(c, &t);
5922 }
5923
5924 return 0;
5925 }
5926
5927 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5928 struct snd_pcm_hw_rule * rule)
5929 {
5930 struct hdspm *hdspm = rule->private;
5931 struct snd_interval *c =
5932 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5933 struct snd_interval *r =
5934 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5935
5936 if (r->min > 96000 && r->max <= 192000) {
5937 struct snd_interval t = {
5938 .min = hdspm->qs_out_channels,
5939 .max = hdspm->qs_out_channels,
5940 .integer = 1,
5941 };
5942 return snd_interval_refine(c, &t);
5943 } else if (r->min > 48000 && r->max <= 96000) {
5944 struct snd_interval t = {
5945 .min = hdspm->ds_out_channels,
5946 .max = hdspm->ds_out_channels,
5947 .integer = 1,
5948 };
5949 return snd_interval_refine(c, &t);
5950 } else if (r->max < 64000) {
5951 struct snd_interval t = {
5952 .min = hdspm->ss_out_channels,
5953 .max = hdspm->ss_out_channels,
5954 .integer = 1,
5955 };
5956 return snd_interval_refine(c, &t);
5957 } else {
5958 }
5959 return 0;
5960 }
5961
5962 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5963 struct snd_pcm_hw_rule * rule)
5964 {
5965 struct hdspm *hdspm = rule->private;
5966 struct snd_interval *c =
5967 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5968 struct snd_interval *r =
5969 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5970
5971 if (c->min >= hdspm->ss_in_channels) {
5972 struct snd_interval t = {
5973 .min = 32000,
5974 .max = 48000,
5975 .integer = 1,
5976 };
5977 return snd_interval_refine(r, &t);
5978 } else if (c->max <= hdspm->qs_in_channels) {
5979 struct snd_interval t = {
5980 .min = 128000,
5981 .max = 192000,
5982 .integer = 1,
5983 };
5984 return snd_interval_refine(r, &t);
5985 } else if (c->max <= hdspm->ds_in_channels) {
5986 struct snd_interval t = {
5987 .min = 64000,
5988 .max = 96000,
5989 .integer = 1,
5990 };
5991 return snd_interval_refine(r, &t);
5992 }
5993
5994 return 0;
5995 }
5996 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5997 struct snd_pcm_hw_rule *rule)
5998 {
5999 struct hdspm *hdspm = rule->private;
6000 struct snd_interval *c =
6001 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
6002 struct snd_interval *r =
6003 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
6004
6005 if (c->min >= hdspm->ss_out_channels) {
6006 struct snd_interval t = {
6007 .min = 32000,
6008 .max = 48000,
6009 .integer = 1,
6010 };
6011 return snd_interval_refine(r, &t);
6012 } else if (c->max <= hdspm->qs_out_channels) {
6013 struct snd_interval t = {
6014 .min = 128000,
6015 .max = 192000,
6016 .integer = 1,
6017 };
6018 return snd_interval_refine(r, &t);
6019 } else if (c->max <= hdspm->ds_out_channels) {
6020 struct snd_interval t = {
6021 .min = 64000,
6022 .max = 96000,
6023 .integer = 1,
6024 };
6025 return snd_interval_refine(r, &t);
6026 }
6027
6028 return 0;
6029 }
6030
6031 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6032 struct snd_pcm_hw_rule *rule)
6033 {
6034 unsigned int list[3];
6035 struct hdspm *hdspm = rule->private;
6036 struct snd_interval *c = hw_param_interval(params,
6037 SNDRV_PCM_HW_PARAM_CHANNELS);
6038
6039 list[0] = hdspm->qs_in_channels;
6040 list[1] = hdspm->ds_in_channels;
6041 list[2] = hdspm->ss_in_channels;
6042 return snd_interval_list(c, 3, list, 0);
6043 }
6044
6045 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6046 struct snd_pcm_hw_rule *rule)
6047 {
6048 unsigned int list[3];
6049 struct hdspm *hdspm = rule->private;
6050 struct snd_interval *c = hw_param_interval(params,
6051 SNDRV_PCM_HW_PARAM_CHANNELS);
6052
6053 list[0] = hdspm->qs_out_channels;
6054 list[1] = hdspm->ds_out_channels;
6055 list[2] = hdspm->ss_out_channels;
6056 return snd_interval_list(c, 3, list, 0);
6057 }
6058
6059
6060 static unsigned int hdspm_aes32_sample_rates[] = {
6061 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6062 };
6063
6064 static struct snd_pcm_hw_constraint_list
6065 hdspm_hw_constraints_aes32_sample_rates = {
6066 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6067 .list = hdspm_aes32_sample_rates,
6068 .mask = 0
6069 };
6070
6071 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
6072 {
6073 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6074 struct snd_pcm_runtime *runtime = substream->runtime;
6075
6076 spin_lock_irq(&hdspm->lock);
6077
6078 snd_pcm_set_sync(substream);
6079
6080
6081 runtime->hw = snd_hdspm_playback_subinfo;
6082
6083 if (hdspm->capture_substream == NULL)
6084 hdspm_stop_audio(hdspm);
6085
6086 hdspm->playback_pid = current->pid;
6087 hdspm->playback_substream = substream;
6088
6089 spin_unlock_irq(&hdspm->lock);
6090
6091 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6092 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6093
6094 switch (hdspm->io_type) {
6095 case AIO:
6096 case RayDAT:
6097 snd_pcm_hw_constraint_minmax(runtime,
6098 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6099 32, 4096);
6100 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6101 snd_pcm_hw_constraint_minmax(runtime,
6102 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6103 16384, 16384);
6104 break;
6105
6106 default:
6107 snd_pcm_hw_constraint_minmax(runtime,
6108 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6109 64, 8192);
6110 break;
6111 }
6112
6113 if (AES32 == hdspm->io_type) {
6114 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6115 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6116 &hdspm_hw_constraints_aes32_sample_rates);
6117 } else {
6118 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6119 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6120 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6121 }
6122
6123 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6124 snd_hdspm_hw_rule_out_channels, hdspm,
6125 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6126
6127 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6128 snd_hdspm_hw_rule_out_channels_rate, hdspm,
6129 SNDRV_PCM_HW_PARAM_RATE, -1);
6130
6131 return 0;
6132 }
6133
6134 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6135 {
6136 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6137
6138 spin_lock_irq(&hdspm->lock);
6139
6140 hdspm->playback_pid = -1;
6141 hdspm->playback_substream = NULL;
6142
6143 spin_unlock_irq(&hdspm->lock);
6144
6145 return 0;
6146 }
6147
6148
6149 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6150 {
6151 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6152 struct snd_pcm_runtime *runtime = substream->runtime;
6153
6154 spin_lock_irq(&hdspm->lock);
6155 snd_pcm_set_sync(substream);
6156 runtime->hw = snd_hdspm_capture_subinfo;
6157
6158 if (hdspm->playback_substream == NULL)
6159 hdspm_stop_audio(hdspm);
6160
6161 hdspm->capture_pid = current->pid;
6162 hdspm->capture_substream = substream;
6163
6164 spin_unlock_irq(&hdspm->lock);
6165
6166 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6167 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6168
6169 switch (hdspm->io_type) {
6170 case AIO:
6171 case RayDAT:
6172 snd_pcm_hw_constraint_minmax(runtime,
6173 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6174 32, 4096);
6175 snd_pcm_hw_constraint_minmax(runtime,
6176 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6177 16384, 16384);
6178 break;
6179
6180 default:
6181 snd_pcm_hw_constraint_minmax(runtime,
6182 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6183 64, 8192);
6184 break;
6185 }
6186
6187 if (AES32 == hdspm->io_type) {
6188 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6189 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6190 &hdspm_hw_constraints_aes32_sample_rates);
6191 } else {
6192 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6193 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6194 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6195 }
6196
6197 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6198 snd_hdspm_hw_rule_in_channels, hdspm,
6199 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6200
6201 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6202 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6203 SNDRV_PCM_HW_PARAM_RATE, -1);
6204
6205 return 0;
6206 }
6207
6208 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6209 {
6210 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6211
6212 spin_lock_irq(&hdspm->lock);
6213
6214 hdspm->capture_pid = -1;
6215 hdspm->capture_substream = NULL;
6216
6217 spin_unlock_irq(&hdspm->lock);
6218 return 0;
6219 }
6220
6221 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6222 {
6223 /* we have nothing to initialize but the call is required */
6224 return 0;
6225 }
6226
6227 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6228 {
6229 u32 val = readl(src);
6230 return copy_to_user(dest, &val, 4);
6231 }
6232
6233 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6234 unsigned int cmd, unsigned long arg)
6235 {
6236 void __user *argp = (void __user *)arg;
6237 struct hdspm *hdspm = hw->private_data;
6238 struct hdspm_mixer_ioctl mixer;
6239 struct hdspm_config info;
6240 struct hdspm_status status;
6241 struct hdspm_version hdspm_version;
6242 struct hdspm_peak_rms *levels;
6243 struct hdspm_ltc ltc;
6244 unsigned int statusregister;
6245 long unsigned int s;
6246 int i = 0;
6247
6248 switch (cmd) {
6249
6250 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6251 levels = &hdspm->peak_rms;
6252 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6253 levels->input_peaks[i] =
6254 readl(hdspm->iobase +
6255 HDSPM_MADI_INPUT_PEAK + i*4);
6256 levels->playback_peaks[i] =
6257 readl(hdspm->iobase +
6258 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6259 levels->output_peaks[i] =
6260 readl(hdspm->iobase +
6261 HDSPM_MADI_OUTPUT_PEAK + i*4);
6262
6263 levels->input_rms[i] =
6264 ((uint64_t) readl(hdspm->iobase +
6265 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6266 (uint64_t) readl(hdspm->iobase +
6267 HDSPM_MADI_INPUT_RMS_L + i*4);
6268 levels->playback_rms[i] =
6269 ((uint64_t)readl(hdspm->iobase +
6270 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6271 (uint64_t)readl(hdspm->iobase +
6272 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6273 levels->output_rms[i] =
6274 ((uint64_t)readl(hdspm->iobase +
6275 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6276 (uint64_t)readl(hdspm->iobase +
6277 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6278 }
6279
6280 if (hdspm->system_sample_rate > 96000) {
6281 levels->speed = qs;
6282 } else if (hdspm->system_sample_rate > 48000) {
6283 levels->speed = ds;
6284 } else {
6285 levels->speed = ss;
6286 }
6287 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6288
6289 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6290 if (0 != s) {
6291 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6292 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6293 */
6294 return -EFAULT;
6295 }
6296 break;
6297
6298 case SNDRV_HDSPM_IOCTL_GET_LTC:
6299 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6300 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6301 if (i & HDSPM_TCO1_LTC_Input_valid) {
6302 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6303 HDSPM_TCO1_LTC_Format_MSB)) {
6304 case 0:
6305 ltc.format = fps_24;
6306 break;
6307 case HDSPM_TCO1_LTC_Format_LSB:
6308 ltc.format = fps_25;
6309 break;
6310 case HDSPM_TCO1_LTC_Format_MSB:
6311 ltc.format = fps_2997;
6312 break;
6313 default:
6314 ltc.format = fps_30;
6315 break;
6316 }
6317 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6318 ltc.frame = drop_frame;
6319 } else {
6320 ltc.frame = full_frame;
6321 }
6322 } else {
6323 ltc.format = format_invalid;
6324 ltc.frame = frame_invalid;
6325 }
6326 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6327 ltc.input_format = ntsc;
6328 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6329 ltc.input_format = pal;
6330 } else {
6331 ltc.input_format = no_video;
6332 }
6333
6334 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6335 if (0 != s) {
6336 /*
6337 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6338 return -EFAULT;
6339 }
6340
6341 break;
6342
6343 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6344
6345 memset(&info, 0, sizeof(info));
6346 spin_lock_irq(&hdspm->lock);
6347 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6348 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6349
6350 info.system_sample_rate = hdspm->system_sample_rate;
6351 info.autosync_sample_rate =
6352 hdspm_external_sample_rate(hdspm);
6353 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6354 info.clock_source = hdspm_clock_source(hdspm);
6355 info.autosync_ref = hdspm_autosync_ref(hdspm);
6356 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6357 info.passthru = 0;
6358 spin_unlock_irq(&hdspm->lock);
6359 if (copy_to_user(argp, &info, sizeof(info)))
6360 return -EFAULT;
6361 break;
6362
6363 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6364 memset(&status, 0, sizeof(status));
6365
6366 status.card_type = hdspm->io_type;
6367
6368 status.autosync_source = hdspm_autosync_ref(hdspm);
6369
6370 status.card_clock = 110069313433624ULL;
6371 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6372
6373 switch (hdspm->io_type) {
6374 case MADI:
6375 case MADIface:
6376 status.card_specific.madi.sync_wc =
6377 hdspm_wc_sync_check(hdspm);
6378 status.card_specific.madi.sync_madi =
6379 hdspm_madi_sync_check(hdspm);
6380 status.card_specific.madi.sync_tco =
6381 hdspm_tco_sync_check(hdspm);
6382 status.card_specific.madi.sync_in =
6383 hdspm_sync_in_sync_check(hdspm);
6384
6385 statusregister =
6386 hdspm_read(hdspm, HDSPM_statusRegister);
6387 status.card_specific.madi.madi_input =
6388 (statusregister & HDSPM_AB_int) ? 1 : 0;
6389 status.card_specific.madi.channel_format =
6390 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6391 /* TODO: Mac driver sets it when f_s>48kHz */
6392 status.card_specific.madi.frame_format = 0;
6393
6394 default:
6395 break;
6396 }
6397
6398 if (copy_to_user(argp, &status, sizeof(status)))
6399 return -EFAULT;
6400
6401
6402 break;
6403
6404 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6405 memset(&hdspm_version, 0, sizeof(hdspm_version));
6406
6407 hdspm_version.card_type = hdspm->io_type;
6408 strncpy(hdspm_version.cardname, hdspm->card_name,
6409 sizeof(hdspm_version.cardname));
6410 hdspm_version.serial = hdspm->serial;
6411 hdspm_version.firmware_rev = hdspm->firmware_rev;
6412 hdspm_version.addons = 0;
6413 if (hdspm->tco)
6414 hdspm_version.addons |= HDSPM_ADDON_TCO;
6415
6416 if (copy_to_user(argp, &hdspm_version,
6417 sizeof(hdspm_version)))
6418 return -EFAULT;
6419 break;
6420
6421 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6422 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6423 return -EFAULT;
6424 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6425 sizeof(struct hdspm_mixer)))
6426 return -EFAULT;
6427 break;
6428
6429 default:
6430 return -EINVAL;
6431 }
6432 return 0;
6433 }
6434
6435 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6436 .open = snd_hdspm_playback_open,
6437 .close = snd_hdspm_playback_release,
6438 .ioctl = snd_hdspm_ioctl,
6439 .hw_params = snd_hdspm_hw_params,
6440 .hw_free = snd_hdspm_hw_free,
6441 .prepare = snd_hdspm_prepare,
6442 .trigger = snd_hdspm_trigger,
6443 .pointer = snd_hdspm_hw_pointer,
6444 .page = snd_pcm_sgbuf_ops_page,
6445 };
6446
6447 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6448 .open = snd_hdspm_capture_open,
6449 .close = snd_hdspm_capture_release,
6450 .ioctl = snd_hdspm_ioctl,
6451 .hw_params = snd_hdspm_hw_params,
6452 .hw_free = snd_hdspm_hw_free,
6453 .prepare = snd_hdspm_prepare,
6454 .trigger = snd_hdspm_trigger,
6455 .pointer = snd_hdspm_hw_pointer,
6456 .page = snd_pcm_sgbuf_ops_page,
6457 };
6458
6459 static int snd_hdspm_create_hwdep(struct snd_card *card,
6460 struct hdspm *hdspm)
6461 {
6462 struct snd_hwdep *hw;
6463 int err;
6464
6465 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6466 if (err < 0)
6467 return err;
6468
6469 hdspm->hwdep = hw;
6470 hw->private_data = hdspm;
6471 strcpy(hw->name, "HDSPM hwdep interface");
6472
6473 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6474 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6475 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6476 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6477
6478 return 0;
6479 }
6480
6481
6482 /*------------------------------------------------------------
6483 memory interface
6484 ------------------------------------------------------------*/
6485 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6486 {
6487 int err;
6488 struct snd_pcm *pcm;
6489 size_t wanted;
6490
6491 pcm = hdspm->pcm;
6492
6493 wanted = HDSPM_DMA_AREA_BYTES;
6494
6495 err =
6496 snd_pcm_lib_preallocate_pages_for_all(pcm,
6497 SNDRV_DMA_TYPE_DEV_SG,
6498 snd_dma_pci_data(hdspm->pci),
6499 wanted,
6500 wanted);
6501 if (err < 0) {
6502 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6503
6504 return err;
6505 } else
6506 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6507
6508 return 0;
6509 }
6510
6511
6512 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6513 struct snd_pcm_substream *substream,
6514 unsigned int reg, int channels)
6515 {
6516 int i;
6517
6518 /* continuous memory segment */
6519 for (i = 0; i < (channels * 16); i++)
6520 hdspm_write(hdspm, reg + 4 * i,
6521 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6522 }
6523
6524
6525 /* ------------- ALSA Devices ---------------------------- */
6526 static int snd_hdspm_create_pcm(struct snd_card *card,
6527 struct hdspm *hdspm)
6528 {
6529 struct snd_pcm *pcm;
6530 int err;
6531
6532 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6533 if (err < 0)
6534 return err;
6535
6536 hdspm->pcm = pcm;
6537 pcm->private_data = hdspm;
6538 strcpy(pcm->name, hdspm->card_name);
6539
6540 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6541 &snd_hdspm_playback_ops);
6542 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6543 &snd_hdspm_capture_ops);
6544
6545 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6546
6547 err = snd_hdspm_preallocate_memory(hdspm);
6548 if (err < 0)
6549 return err;
6550
6551 return 0;
6552 }
6553
6554 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6555 {
6556 int i;
6557
6558 for (i = 0; i < hdspm->midiPorts; i++)
6559 snd_hdspm_flush_midi_input(hdspm, i);
6560 }
6561
6562 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6563 struct hdspm *hdspm)
6564 {
6565 int err, i;
6566
6567 snd_printdd("Create card...\n");
6568 err = snd_hdspm_create_pcm(card, hdspm);
6569 if (err < 0)
6570 return err;
6571
6572 i = 0;
6573 while (i < hdspm->midiPorts) {
6574 err = snd_hdspm_create_midi(card, hdspm, i);
6575 if (err < 0) {
6576 return err;
6577 }
6578 i++;
6579 }
6580
6581 err = snd_hdspm_create_controls(card, hdspm);
6582 if (err < 0)
6583 return err;
6584
6585 err = snd_hdspm_create_hwdep(card, hdspm);
6586 if (err < 0)
6587 return err;
6588
6589 snd_printdd("proc init...\n");
6590 snd_hdspm_proc_init(hdspm);
6591
6592 hdspm->system_sample_rate = -1;
6593 hdspm->last_external_sample_rate = -1;
6594 hdspm->last_internal_sample_rate = -1;
6595 hdspm->playback_pid = -1;
6596 hdspm->capture_pid = -1;
6597 hdspm->capture_substream = NULL;
6598 hdspm->playback_substream = NULL;
6599
6600 snd_printdd("Set defaults...\n");
6601 err = snd_hdspm_set_defaults(hdspm);
6602 if (err < 0)
6603 return err;
6604
6605 snd_printdd("Update mixer controls...\n");
6606 hdspm_update_simple_mixer_controls(hdspm);
6607
6608 snd_printdd("Initializeing complete ???\n");
6609
6610 err = snd_card_register(card);
6611 if (err < 0) {
6612 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6613 return err;
6614 }
6615
6616 snd_printdd("... yes now\n");
6617
6618 return 0;
6619 }
6620
6621 static int snd_hdspm_create(struct snd_card *card,
6622 struct hdspm *hdspm)
6623 {
6624
6625 struct pci_dev *pci = hdspm->pci;
6626 int err;
6627 unsigned long io_extent;
6628
6629 hdspm->irq = -1;
6630 hdspm->card = card;
6631
6632 spin_lock_init(&hdspm->lock);
6633
6634 pci_read_config_word(hdspm->pci,
6635 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6636
6637 strcpy(card->mixername, "Xilinx FPGA");
6638 strcpy(card->driver, "HDSPM");
6639
6640 switch (hdspm->firmware_rev) {
6641 case HDSPM_RAYDAT_REV:
6642 hdspm->io_type = RayDAT;
6643 hdspm->card_name = "RME RayDAT";
6644 hdspm->midiPorts = 2;
6645 break;
6646 case HDSPM_AIO_REV:
6647 hdspm->io_type = AIO;
6648 hdspm->card_name = "RME AIO";
6649 hdspm->midiPorts = 1;
6650 break;
6651 case HDSPM_MADIFACE_REV:
6652 hdspm->io_type = MADIface;
6653 hdspm->card_name = "RME MADIface";
6654 hdspm->midiPorts = 1;
6655 break;
6656 default:
6657 if ((hdspm->firmware_rev == 0xf0) ||
6658 ((hdspm->firmware_rev >= 0xe6) &&
6659 (hdspm->firmware_rev <= 0xea))) {
6660 hdspm->io_type = AES32;
6661 hdspm->card_name = "RME AES32";
6662 hdspm->midiPorts = 2;
6663 } else if ((hdspm->firmware_rev == 0xd2) ||
6664 ((hdspm->firmware_rev >= 0xc8) &&
6665 (hdspm->firmware_rev <= 0xcf))) {
6666 hdspm->io_type = MADI;
6667 hdspm->card_name = "RME MADI";
6668 hdspm->midiPorts = 3;
6669 } else {
6670 snd_printk(KERN_ERR
6671 "HDSPM: unknown firmware revision %x\n",
6672 hdspm->firmware_rev);
6673 return -ENODEV;
6674 }
6675 }
6676
6677 err = pci_enable_device(pci);
6678 if (err < 0)
6679 return err;
6680
6681 pci_set_master(hdspm->pci);
6682
6683 err = pci_request_regions(pci, "hdspm");
6684 if (err < 0)
6685 return err;
6686
6687 hdspm->port = pci_resource_start(pci, 0);
6688 io_extent = pci_resource_len(pci, 0);
6689
6690 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6691 hdspm->port, hdspm->port + io_extent - 1);
6692
6693 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6694 if (!hdspm->iobase) {
6695 snd_printk(KERN_ERR "HDSPM: "
6696 "unable to remap region 0x%lx-0x%lx\n",
6697 hdspm->port, hdspm->port + io_extent - 1);
6698 return -EBUSY;
6699 }
6700 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6701 (unsigned long)hdspm->iobase, hdspm->port,
6702 hdspm->port + io_extent - 1);
6703
6704 if (request_irq(pci->irq, snd_hdspm_interrupt,
6705 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6706 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6707 return -EBUSY;
6708 }
6709
6710 snd_printdd("use IRQ %d\n", pci->irq);
6711
6712 hdspm->irq = pci->irq;
6713
6714 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6715 sizeof(struct hdspm_mixer));
6716 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6717 if (!hdspm->mixer) {
6718 snd_printk(KERN_ERR "HDSPM: "
6719 "unable to kmalloc Mixer memory of %d Bytes\n",
6720 (int)sizeof(struct hdspm_mixer));
6721 return -ENOMEM;
6722 }
6723
6724 hdspm->port_names_in = NULL;
6725 hdspm->port_names_out = NULL;
6726
6727 switch (hdspm->io_type) {
6728 case AES32:
6729 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6730 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6731 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6732
6733 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6734 channel_map_aes32;
6735 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6736 channel_map_aes32;
6737 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6738 channel_map_aes32;
6739 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6740 texts_ports_aes32;
6741 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6742 texts_ports_aes32;
6743 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6744 texts_ports_aes32;
6745
6746 hdspm->max_channels_out = hdspm->max_channels_in =
6747 AES32_CHANNELS;
6748 hdspm->port_names_in = hdspm->port_names_out =
6749 texts_ports_aes32;
6750 hdspm->channel_map_in = hdspm->channel_map_out =
6751 channel_map_aes32;
6752
6753 break;
6754
6755 case MADI:
6756 case MADIface:
6757 hdspm->ss_in_channels = hdspm->ss_out_channels =
6758 MADI_SS_CHANNELS;
6759 hdspm->ds_in_channels = hdspm->ds_out_channels =
6760 MADI_DS_CHANNELS;
6761 hdspm->qs_in_channels = hdspm->qs_out_channels =
6762 MADI_QS_CHANNELS;
6763
6764 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6765 channel_map_unity_ss;
6766 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6767 channel_map_unity_ss;
6768 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6769 channel_map_unity_ss;
6770
6771 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6772 texts_ports_madi;
6773 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6774 texts_ports_madi;
6775 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6776 texts_ports_madi;
6777 break;
6778
6779 case AIO:
6780 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6781 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6782 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6783 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6784 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6785 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6786
6787 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6788 snd_printk(KERN_INFO "HDSPM: AEB input board found\n");
6789 hdspm->ss_in_channels += 4;
6790 hdspm->ds_in_channels += 4;
6791 hdspm->qs_in_channels += 4;
6792 }
6793
6794 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6795 snd_printk(KERN_INFO "HDSPM: AEB output board found\n");
6796 hdspm->ss_out_channels += 4;
6797 hdspm->ds_out_channels += 4;
6798 hdspm->qs_out_channels += 4;
6799 }
6800
6801 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6802 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6803 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6804
6805 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6806 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6807 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6808
6809 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6810 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6811 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6812 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6813 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6814 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6815
6816 break;
6817
6818 case RayDAT:
6819 hdspm->ss_in_channels = hdspm->ss_out_channels =
6820 RAYDAT_SS_CHANNELS;
6821 hdspm->ds_in_channels = hdspm->ds_out_channels =
6822 RAYDAT_DS_CHANNELS;
6823 hdspm->qs_in_channels = hdspm->qs_out_channels =
6824 RAYDAT_QS_CHANNELS;
6825
6826 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6827 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6828
6829 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6830 channel_map_raydat_ss;
6831 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6832 channel_map_raydat_ds;
6833 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6834 channel_map_raydat_qs;
6835 hdspm->channel_map_in = hdspm->channel_map_out =
6836 channel_map_raydat_ss;
6837
6838 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6839 texts_ports_raydat_ss;
6840 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6841 texts_ports_raydat_ds;
6842 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6843 texts_ports_raydat_qs;
6844
6845
6846 break;
6847
6848 }
6849
6850 /* TCO detection */
6851 switch (hdspm->io_type) {
6852 case AIO:
6853 case RayDAT:
6854 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6855 HDSPM_s2_tco_detect) {
6856 hdspm->midiPorts++;
6857 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6858 GFP_KERNEL);
6859 if (NULL != hdspm->tco) {
6860 hdspm_tco_write(hdspm);
6861 }
6862 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6863 } else {
6864 hdspm->tco = NULL;
6865 }
6866 break;
6867
6868 case MADI:
6869 case AES32:
6870 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6871 hdspm->midiPorts++;
6872 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6873 GFP_KERNEL);
6874 if (NULL != hdspm->tco) {
6875 hdspm_tco_write(hdspm);
6876 }
6877 snd_printk(KERN_INFO "HDSPM: MADI/AES TCO module found\n");
6878 } else {
6879 hdspm->tco = NULL;
6880 }
6881 break;
6882
6883 default:
6884 hdspm->tco = NULL;
6885 }
6886
6887 /* texts */
6888 switch (hdspm->io_type) {
6889 case AES32:
6890 if (hdspm->tco) {
6891 hdspm->texts_autosync = texts_autosync_aes_tco;
6892 hdspm->texts_autosync_items =
6893 ARRAY_SIZE(texts_autosync_aes_tco);
6894 } else {
6895 hdspm->texts_autosync = texts_autosync_aes;
6896 hdspm->texts_autosync_items =
6897 ARRAY_SIZE(texts_autosync_aes);
6898 }
6899 break;
6900
6901 case MADI:
6902 if (hdspm->tco) {
6903 hdspm->texts_autosync = texts_autosync_madi_tco;
6904 hdspm->texts_autosync_items = 4;
6905 } else {
6906 hdspm->texts_autosync = texts_autosync_madi;
6907 hdspm->texts_autosync_items = 3;
6908 }
6909 break;
6910
6911 case MADIface:
6912
6913 break;
6914
6915 case RayDAT:
6916 if (hdspm->tco) {
6917 hdspm->texts_autosync = texts_autosync_raydat_tco;
6918 hdspm->texts_autosync_items = 9;
6919 } else {
6920 hdspm->texts_autosync = texts_autosync_raydat;
6921 hdspm->texts_autosync_items = 8;
6922 }
6923 break;
6924
6925 case AIO:
6926 if (hdspm->tco) {
6927 hdspm->texts_autosync = texts_autosync_aio_tco;
6928 hdspm->texts_autosync_items = 6;
6929 } else {
6930 hdspm->texts_autosync = texts_autosync_aio;
6931 hdspm->texts_autosync_items = 5;
6932 }
6933 break;
6934
6935 }
6936
6937 tasklet_init(&hdspm->midi_tasklet,
6938 hdspm_midi_tasklet, (unsigned long) hdspm);
6939
6940
6941 if (hdspm->io_type != MADIface) {
6942 hdspm->serial = (hdspm_read(hdspm,
6943 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6944 /* id contains either a user-provided value or the default
6945 * NULL. If it's the default, we're safe to
6946 * fill card->id with the serial number.
6947 *
6948 * If the serial number is 0xFFFFFF, then we're dealing with
6949 * an old PCI revision that comes without a sane number. In
6950 * this case, we don't set card->id to avoid collisions
6951 * when running with multiple cards.
6952 */
6953 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6954 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6955 snd_card_set_id(card, card->id);
6956 }
6957 }
6958
6959 snd_printdd("create alsa devices.\n");
6960 err = snd_hdspm_create_alsa_devices(card, hdspm);
6961 if (err < 0)
6962 return err;
6963
6964 snd_hdspm_initialize_midi_flush(hdspm);
6965
6966 return 0;
6967 }
6968
6969
6970 static int snd_hdspm_free(struct hdspm * hdspm)
6971 {
6972
6973 if (hdspm->port) {
6974
6975 /* stop th audio, and cancel all interrupts */
6976 hdspm->control_register &=
6977 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6978 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6979 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6980 hdspm_write(hdspm, HDSPM_controlRegister,
6981 hdspm->control_register);
6982 }
6983
6984 if (hdspm->irq >= 0)
6985 free_irq(hdspm->irq, (void *) hdspm);
6986
6987 kfree(hdspm->mixer);
6988
6989 if (hdspm->iobase)
6990 iounmap(hdspm->iobase);
6991
6992 if (hdspm->port)
6993 pci_release_regions(hdspm->pci);
6994
6995 pci_disable_device(hdspm->pci);
6996 return 0;
6997 }
6998
6999
7000 static void snd_hdspm_card_free(struct snd_card *card)
7001 {
7002 struct hdspm *hdspm = card->private_data;
7003
7004 if (hdspm)
7005 snd_hdspm_free(hdspm);
7006 }
7007
7008
7009 static int snd_hdspm_probe(struct pci_dev *pci,
7010 const struct pci_device_id *pci_id)
7011 {
7012 static int dev;
7013 struct hdspm *hdspm;
7014 struct snd_card *card;
7015 int err;
7016
7017 if (dev >= SNDRV_CARDS)
7018 return -ENODEV;
7019 if (!enable[dev]) {
7020 dev++;
7021 return -ENOENT;
7022 }
7023
7024 err = snd_card_create(index[dev], id[dev],
7025 THIS_MODULE, sizeof(struct hdspm), &card);
7026 if (err < 0)
7027 return err;
7028
7029 hdspm = card->private_data;
7030 card->private_free = snd_hdspm_card_free;
7031 hdspm->dev = dev;
7032 hdspm->pci = pci;
7033
7034 snd_card_set_dev(card, &pci->dev);
7035
7036 err = snd_hdspm_create(card, hdspm);
7037 if (err < 0) {
7038 snd_card_free(card);
7039 return err;
7040 }
7041
7042 if (hdspm->io_type != MADIface) {
7043 sprintf(card->shortname, "%s_%x",
7044 hdspm->card_name,
7045 hdspm->serial);
7046 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
7047 hdspm->card_name,
7048 hdspm->serial,
7049 hdspm->port, hdspm->irq);
7050 } else {
7051 sprintf(card->shortname, "%s", hdspm->card_name);
7052 sprintf(card->longname, "%s at 0x%lx, irq %d",
7053 hdspm->card_name, hdspm->port, hdspm->irq);
7054 }
7055
7056 err = snd_card_register(card);
7057 if (err < 0) {
7058 snd_card_free(card);
7059 return err;
7060 }
7061
7062 pci_set_drvdata(pci, card);
7063
7064 dev++;
7065 return 0;
7066 }
7067
7068 static void snd_hdspm_remove(struct pci_dev *pci)
7069 {
7070 snd_card_free(pci_get_drvdata(pci));
7071 }
7072
7073 static struct pci_driver hdspm_driver = {
7074 .name = KBUILD_MODNAME,
7075 .id_table = snd_hdspm_ids,
7076 .probe = snd_hdspm_probe,
7077 .remove = snd_hdspm_remove,
7078 };
7079
7080 module_pci_driver(hdspm_driver);
Linux kernel - Deliverables
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