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Merge remote-tracking branches 'asoc/topic/intel', 'asoc/topic/kirkwood', 'asoc/topic...
[deliverable/linux.git] / sound / soc / codecs / cs42l56.c
1 /*
2 * cs42l56.c -- CS42L56 ALSA SoC audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/input.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <linux/platform_device.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/soc-dapm.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
36 #include <sound/cs42l56.h>
37 #include "cs42l56.h"
38
39 #define CS42L56_NUM_SUPPLIES 3
40 static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
41 "VA",
42 "VCP",
43 "VLDO",
44 };
45
46 struct cs42l56_private {
47 struct regmap *regmap;
48 struct snd_soc_codec *codec;
49 struct device *dev;
50 struct cs42l56_platform_data pdata;
51 struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
52 u32 mclk;
53 u8 mclk_prediv;
54 u8 mclk_div2;
55 u8 mclk_ratio;
56 u8 iface;
57 u8 iface_fmt;
58 u8 iface_inv;
59 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
60 struct input_dev *beep;
61 struct work_struct beep_work;
62 int beep_rate;
63 #endif
64 };
65
66 static const struct reg_default cs42l56_reg_defaults[] = {
67 { 1, 0x56 }, /* r01 - ID 1 */
68 { 2, 0x04 }, /* r02 - ID 2 */
69 { 3, 0x7f }, /* r03 - Power Ctl 1 */
70 { 4, 0xff }, /* r04 - Power Ctl 2 */
71 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
72 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
73 { 7, 0x00 }, /* r07 - Serial Format */
74 { 8, 0x05 }, /* r08 - Class H Ctl */
75 { 9, 0x0c }, /* r09 - Misc Ctl */
76 { 10, 0x80 }, /* r0a - INT Status */
77 { 11, 0x00 }, /* r0b - Playback Ctl */
78 { 12, 0x0c }, /* r0c - DSP Mute Ctl */
79 { 13, 0x00 }, /* r0d - ADCA Mixer Volume */
80 { 14, 0x00 }, /* r0e - ADCB Mixer Volume */
81 { 15, 0x00 }, /* r0f - PCMA Mixer Volume */
82 { 16, 0x00 }, /* r10 - PCMB Mixer Volume */
83 { 17, 0x00 }, /* r11 - Analog Input Advisory Volume */
84 { 18, 0x00 }, /* r12 - Digital Input Advisory Volume */
85 { 19, 0x00 }, /* r13 - Master A Volume */
86 { 20, 0x00 }, /* r14 - Master B Volume */
87 { 21, 0x00 }, /* r15 - Beep Freq / On Time */
88 { 22, 0x00 }, /* r16 - Beep Volume / Off Time */
89 { 23, 0x00 }, /* r17 - Beep Tone Ctl */
90 { 24, 0x88 }, /* r18 - Tone Ctl */
91 { 25, 0x00 }, /* r19 - Channel Mixer & Swap */
92 { 26, 0x00 }, /* r1a - AIN Ref Config / ADC Mux */
93 { 27, 0xa0 }, /* r1b - High-Pass Filter Ctl */
94 { 28, 0x00 }, /* r1c - Misc ADC Ctl */
95 { 29, 0x00 }, /* r1d - Gain & Bias Ctl */
96 { 30, 0x00 }, /* r1e - PGAA Mux & Volume */
97 { 31, 0x00 }, /* r1f - PGAB Mux & Volume */
98 { 32, 0x00 }, /* r20 - ADCA Attenuator */
99 { 33, 0x00 }, /* r21 - ADCB Attenuator */
100 { 34, 0x00 }, /* r22 - ALC Enable & Attack Rate */
101 { 35, 0xbf }, /* r23 - ALC Release Rate */
102 { 36, 0x00 }, /* r24 - ALC Threshold */
103 { 37, 0x00 }, /* r25 - Noise Gate Ctl */
104 { 38, 0x00 }, /* r26 - ALC, Limiter, SFT, ZeroCross */
105 { 39, 0x00 }, /* r27 - Analog Mute, LO & HP Mux */
106 { 40, 0x00 }, /* r28 - HP A Volume */
107 { 41, 0x00 }, /* r29 - HP B Volume */
108 { 42, 0x00 }, /* r2a - LINEOUT A Volume */
109 { 43, 0x00 }, /* r2b - LINEOUT B Volume */
110 { 44, 0x00 }, /* r2c - Limit Threshold Ctl */
111 { 45, 0x7f }, /* r2d - Limiter Ctl & Release Rate */
112 { 46, 0x00 }, /* r2e - Limiter Attack Rate */
113 };
114
115 static bool cs42l56_readable_register(struct device *dev, unsigned int reg)
116 {
117 switch (reg) {
118 case CS42L56_CHIP_ID_1 ... CS42L56_LIM_ATTACK_RATE:
119 return true;
120 default:
121 return false;
122 }
123 }
124
125 static bool cs42l56_volatile_register(struct device *dev, unsigned int reg)
126 {
127 switch (reg) {
128 case CS42L56_INT_STATUS:
129 return true;
130 default:
131 return false;
132 }
133 }
134
135 static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 200, 0);
136 static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 0);
137 static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 50, 0);
138 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, 0);
139 static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
140 static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 1000, 0);
141 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
142
143 static const unsigned int ngnb_tlv[] = {
144 TLV_DB_RANGE_HEAD(2),
145 0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0),
146 2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0),
147 };
148 static const unsigned int ngb_tlv[] = {
149 TLV_DB_RANGE_HEAD(2),
150 0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0),
151 3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0),
152 };
153 static const unsigned int alc_tlv[] = {
154 TLV_DB_RANGE_HEAD(2),
155 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
156 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
157 };
158
159 static const char * const beep_config_text[] = {
160 "Off", "Single", "Multiple", "Continuous"
161 };
162
163 static const struct soc_enum beep_config_enum =
164 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 6,
165 ARRAY_SIZE(beep_config_text), beep_config_text);
166
167 static const char * const beep_pitch_text[] = {
168 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
169 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
170 };
171
172 static const struct soc_enum beep_pitch_enum =
173 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 4,
174 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
175
176 static const char * const beep_ontime_text[] = {
177 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
178 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
179 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
180 };
181
182 static const struct soc_enum beep_ontime_enum =
183 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 0,
184 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
185
186 static const char * const beep_offtime_text[] = {
187 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
188 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
189 };
190
191 static const struct soc_enum beep_offtime_enum =
192 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFTIME, 5,
193 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
194
195 static const char * const beep_treble_text[] = {
196 "5kHz", "7kHz", "10kHz", "15kHz"
197 };
198
199 static const struct soc_enum beep_treble_enum =
200 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 3,
201 ARRAY_SIZE(beep_treble_text), beep_treble_text);
202
203 static const char * const beep_bass_text[] = {
204 "50Hz", "100Hz", "200Hz", "250Hz"
205 };
206
207 static const struct soc_enum beep_bass_enum =
208 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 1,
209 ARRAY_SIZE(beep_bass_text), beep_bass_text);
210
211 static const char * const adc_swap_text[] = {
212 "None", "A+B/2", "A-B/2", "Swap"
213 };
214
215 static const struct soc_enum adc_swap_enum =
216 SOC_ENUM_SINGLE(CS42L56_MISC_ADC_CTL, 3,
217 ARRAY_SIZE(adc_swap_text), adc_swap_text);
218
219 static const char * const pgaa_mux_text[] = {
220 "AIN1A", "AIN2A", "AIN3A"};
221
222 static const struct soc_enum pgaa_mux_enum =
223 SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUME, 0,
224 ARRAY_SIZE(pgaa_mux_text),
225 pgaa_mux_text);
226
227 static const struct snd_kcontrol_new pgaa_mux =
228 SOC_DAPM_ENUM("Route", pgaa_mux_enum);
229
230 static const char * const pgab_mux_text[] = {
231 "AIN1B", "AIN2B", "AIN3B"};
232
233 static const struct soc_enum pgab_mux_enum =
234 SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUME, 0,
235 ARRAY_SIZE(pgab_mux_text),
236 pgab_mux_text);
237
238 static const struct snd_kcontrol_new pgab_mux =
239 SOC_DAPM_ENUM("Route", pgab_mux_enum);
240
241 static const char * const adca_mux_text[] = {
242 "PGAA", "AIN1A", "AIN2A", "AIN3A"};
243
244 static const struct soc_enum adca_mux_enum =
245 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 0,
246 ARRAY_SIZE(adca_mux_text),
247 adca_mux_text);
248
249 static const struct snd_kcontrol_new adca_mux =
250 SOC_DAPM_ENUM("Route", adca_mux_enum);
251
252 static const char * const adcb_mux_text[] = {
253 "PGAB", "AIN1B", "AIN2B", "AIN3B"};
254
255 static const struct soc_enum adcb_mux_enum =
256 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 2,
257 ARRAY_SIZE(adcb_mux_text),
258 adcb_mux_text);
259
260 static const struct snd_kcontrol_new adcb_mux =
261 SOC_DAPM_ENUM("Route", adcb_mux_enum);
262
263 static const char * const left_swap_text[] = {
264 "Left", "LR 2", "Right"};
265
266 static const char * const right_swap_text[] = {
267 "Right", "LR 2", "Left"};
268
269 static const unsigned int swap_values[] = { 0, 1, 3 };
270
271 static const struct soc_enum adca_swap_enum =
272 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 0, 3,
273 ARRAY_SIZE(left_swap_text),
274 left_swap_text,
275 swap_values);
276 static const struct snd_kcontrol_new adca_swap_mux =
277 SOC_DAPM_ENUM("Route", adca_swap_enum);
278
279 static const struct soc_enum pcma_swap_enum =
280 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 4, 3,
281 ARRAY_SIZE(left_swap_text),
282 left_swap_text,
283 swap_values);
284 static const struct snd_kcontrol_new pcma_swap_mux =
285 SOC_DAPM_ENUM("Route", pcma_swap_enum);
286
287 static const struct soc_enum adcb_swap_enum =
288 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 2, 3,
289 ARRAY_SIZE(right_swap_text),
290 right_swap_text,
291 swap_values);
292 static const struct snd_kcontrol_new adcb_swap_mux =
293 SOC_DAPM_ENUM("Route", adcb_swap_enum);
294
295 static const struct soc_enum pcmb_swap_enum =
296 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 6, 3,
297 ARRAY_SIZE(right_swap_text),
298 right_swap_text,
299 swap_values);
300 static const struct snd_kcontrol_new pcmb_swap_mux =
301 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
302
303 static const struct snd_kcontrol_new hpa_switch =
304 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 6, 1, 1);
305
306 static const struct snd_kcontrol_new hpb_switch =
307 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 4, 1, 1);
308
309 static const struct snd_kcontrol_new loa_switch =
310 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 2, 1, 1);
311
312 static const struct snd_kcontrol_new lob_switch =
313 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 0, 1, 1);
314
315 static const char * const hploa_input_text[] = {
316 "DACA", "PGAA"};
317
318 static const struct soc_enum lineouta_input_enum =
319 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 2,
320 ARRAY_SIZE(hploa_input_text),
321 hploa_input_text);
322
323 static const struct snd_kcontrol_new lineouta_input =
324 SOC_DAPM_ENUM("Route", lineouta_input_enum);
325
326 static const struct soc_enum hpa_input_enum =
327 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 0,
328 ARRAY_SIZE(hploa_input_text),
329 hploa_input_text);
330
331 static const struct snd_kcontrol_new hpa_input =
332 SOC_DAPM_ENUM("Route", hpa_input_enum);
333
334 static const char * const hplob_input_text[] = {
335 "DACB", "PGAB"};
336
337 static const struct soc_enum lineoutb_input_enum =
338 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 3,
339 ARRAY_SIZE(hplob_input_text),
340 hplob_input_text);
341
342 static const struct snd_kcontrol_new lineoutb_input =
343 SOC_DAPM_ENUM("Route", lineoutb_input_enum);
344
345 static const struct soc_enum hpb_input_enum =
346 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 1,
347 ARRAY_SIZE(hplob_input_text),
348 hplob_input_text);
349
350 static const struct snd_kcontrol_new hpb_input =
351 SOC_DAPM_ENUM("Route", hpb_input_enum);
352
353 static const char * const dig_mux_text[] = {
354 "ADC", "DSP"};
355
356 static const struct soc_enum dig_mux_enum =
357 SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
358 ARRAY_SIZE(dig_mux_text),
359 dig_mux_text);
360
361 static const struct snd_kcontrol_new dig_mux =
362 SOC_DAPM_ENUM("Route", dig_mux_enum);
363
364 static const char * const hpf_freq_text[] = {
365 "1.8Hz", "119Hz", "236Hz", "464Hz"
366 };
367
368 static const struct soc_enum hpfa_freq_enum =
369 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
370 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
371
372 static const struct soc_enum hpfb_freq_enum =
373 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
374 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
375
376 static const char * const ng_delay_text[] = {
377 "50ms", "100ms", "150ms", "200ms"
378 };
379
380 static const struct soc_enum ng_delay_enum =
381 SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL, 0,
382 ARRAY_SIZE(ng_delay_text), ng_delay_text);
383
384 static const struct snd_kcontrol_new cs42l56_snd_controls[] = {
385
386 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L56_MASTER_A_VOLUME,
387 CS42L56_MASTER_B_VOLUME, 0, 0x34, 0xE4, adv_tlv),
388 SOC_DOUBLE("Master Mute Switch", CS42L56_DSP_MUTE_CTL, 0, 1, 1, 1),
389
390 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", CS42L56_ADCA_MIX_VOLUME,
391 CS42L56_ADCB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
392 SOC_DOUBLE("ADC Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 6, 7, 1, 1),
393
394 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", CS42L56_PCMA_MIX_VOLUME,
395 CS42L56_PCMB_MIX_VOLUME, 0, 0x88, 0x90, hl_tlv),
396 SOC_DOUBLE("PCM Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 4, 5, 1, 1),
397
398 SOC_SINGLE_TLV("Analog Advisory Volume",
399 CS42L56_ANAINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
400 SOC_SINGLE_TLV("Digital Advisory Volume",
401 CS42L56_DIGINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
402
403 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L56_PGAA_MUX_VOLUME,
404 CS42L56_PGAB_MUX_VOLUME, 0, 0x34, 0x24, pga_tlv),
405 SOC_DOUBLE_R_TLV("ADC Volume", CS42L56_ADCA_ATTENUATOR,
406 CS42L56_ADCB_ATTENUATOR, 0, 0x00, 1, adc_tlv),
407 SOC_DOUBLE("ADC Mute Switch", CS42L56_MISC_ADC_CTL, 2, 3, 1, 1),
408 SOC_DOUBLE("ADC Boost Switch", CS42L56_GAIN_BIAS_CTL, 3, 2, 1, 1),
409
410 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L56_HPA_VOLUME,
411 CS42L56_HPB_VOLUME, 0, 0x84, 0x48, hl_tlv),
412 SOC_DOUBLE_R_SX_TLV("LineOut Volume", CS42L56_LOA_VOLUME,
413 CS42L56_LOB_VOLUME, 0, 0x84, 0x48, hl_tlv),
414
415 SOC_SINGLE_TLV("Bass Shelving Volume", CS42L56_TONE_CTL,
416 0, 0x00, 1, tone_tlv),
417 SOC_SINGLE_TLV("Treble Shelving Volume", CS42L56_TONE_CTL,
418 4, 0x00, 1, tone_tlv),
419
420 SOC_DOUBLE_TLV("PGA Preamp Volume", CS42L56_GAIN_BIAS_CTL,
421 4, 6, 0x02, 1, preamp_tlv),
422
423 SOC_SINGLE("DSP Switch", CS42L56_PLAYBACK_CTL, 7, 1, 1),
424 SOC_SINGLE("Gang Playback Switch", CS42L56_PLAYBACK_CTL, 4, 1, 1),
425 SOC_SINGLE("Gang ADC Switch", CS42L56_MISC_ADC_CTL, 7, 1, 1),
426 SOC_SINGLE("Gang PGA Switch", CS42L56_MISC_ADC_CTL, 6, 1, 1),
427
428 SOC_SINGLE("PCMA Invert", CS42L56_PLAYBACK_CTL, 2, 1, 1),
429 SOC_SINGLE("PCMB Invert", CS42L56_PLAYBACK_CTL, 3, 1, 1),
430 SOC_SINGLE("ADCA Invert", CS42L56_MISC_ADC_CTL, 2, 1, 1),
431 SOC_SINGLE("ADCB Invert", CS42L56_MISC_ADC_CTL, 3, 1, 1),
432
433 SOC_DOUBLE("HPF Switch", CS42L56_HPF_CTL, 5, 7, 1, 1),
434 SOC_DOUBLE("HPF Freeze Switch", CS42L56_HPF_CTL, 4, 6, 1, 1),
435 SOC_ENUM("HPFA Corner Freq", hpfa_freq_enum),
436 SOC_ENUM("HPFB Corner Freq", hpfb_freq_enum),
437
438 SOC_SINGLE("Analog Soft Ramp", CS42L56_MISC_CTL, 4, 1, 1),
439 SOC_DOUBLE("Analog Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
440 7, 5, 1, 1),
441 SOC_SINGLE("Analog Zero Cross", CS42L56_MISC_CTL, 3, 1, 1),
442 SOC_DOUBLE("Analog Zero Cross Disable", CS42L56_ALC_LIM_SFT_ZC,
443 6, 4, 1, 1),
444 SOC_SINGLE("Digital Soft Ramp", CS42L56_MISC_CTL, 2, 1, 1),
445 SOC_SINGLE("Digital Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
446 3, 1, 1),
447
448 SOC_SINGLE("HL Deemphasis", CS42L56_PLAYBACK_CTL, 6, 1, 1),
449
450 SOC_SINGLE("ALC Switch", CS42L56_ALC_EN_ATTACK_RATE, 6, 1, 1),
451 SOC_SINGLE("ALC Limit All Switch", CS42L56_ALC_RELEASE_RATE, 7, 1, 1),
452 SOC_SINGLE_RANGE("ALC Attack", CS42L56_ALC_EN_ATTACK_RATE,
453 0, 0, 0x3f, 0),
454 SOC_SINGLE_RANGE("ALC Release", CS42L56_ALC_RELEASE_RATE,
455 0, 0x3f, 0, 0),
456 SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_THRESHOLD,
457 5, 0x07, 1, alc_tlv),
458 SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_THRESHOLD,
459 2, 0x07, 1, alc_tlv),
460
461 SOC_SINGLE("Limiter Switch", CS42L56_LIM_CTL_RELEASE_RATE, 7, 1, 1),
462 SOC_SINGLE("Limit All Switch", CS42L56_LIM_CTL_RELEASE_RATE, 6, 1, 1),
463 SOC_SINGLE_RANGE("Limiter Attack", CS42L56_LIM_ATTACK_RATE,
464 0, 0, 0x3f, 0),
465 SOC_SINGLE_RANGE("Limiter Release", CS42L56_LIM_CTL_RELEASE_RATE,
466 0, 0x3f, 0, 0),
467 SOC_SINGLE_TLV("Limiter MAX", CS42L56_LIM_THRESHOLD_CTL,
468 5, 0x07, 1, alc_tlv),
469 SOC_SINGLE_TLV("Limiter Cushion", CS42L56_ALC_THRESHOLD,
470 2, 0x07, 1, alc_tlv),
471
472 SOC_SINGLE("NG Switch", CS42L56_NOISE_GATE_CTL, 6, 1, 1),
473 SOC_SINGLE("NG All Switch", CS42L56_NOISE_GATE_CTL, 7, 1, 1),
474 SOC_SINGLE("NG Boost Switch", CS42L56_NOISE_GATE_CTL, 5, 1, 1),
475 SOC_SINGLE_TLV("NG Unboost Threshold", CS42L56_NOISE_GATE_CTL,
476 2, 0x07, 1, ngnb_tlv),
477 SOC_SINGLE_TLV("NG Boost Threshold", CS42L56_NOISE_GATE_CTL,
478 2, 0x07, 1, ngb_tlv),
479 SOC_ENUM("NG Delay", ng_delay_enum),
480
481 SOC_ENUM("Beep Config", beep_config_enum),
482 SOC_ENUM("Beep Pitch", beep_pitch_enum),
483 SOC_ENUM("Beep on Time", beep_ontime_enum),
484 SOC_ENUM("Beep off Time", beep_offtime_enum),
485 SOC_SINGLE_SX_TLV("Beep Volume", CS42L56_BEEP_FREQ_OFFTIME,
486 0, 0x07, 0x23, beep_tlv),
487 SOC_SINGLE("Beep Tone Ctl Switch", CS42L56_BEEP_TONE_CFG, 0, 1, 1),
488 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
489 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
490
491 };
492
493 static const struct snd_soc_dapm_widget cs42l56_dapm_widgets[] = {
494
495 SND_SOC_DAPM_SIGGEN("Beep"),
496 SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PWRCTL_1, 5, 1, NULL, 0),
497 SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42L56_PWRCTL_1, 4, 1),
498 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L56_PWRCTL_1, 3, 1, NULL, 0),
499
500 SND_SOC_DAPM_INPUT("AIN1A"),
501 SND_SOC_DAPM_INPUT("AIN2A"),
502 SND_SOC_DAPM_INPUT("AIN1B"),
503 SND_SOC_DAPM_INPUT("AIN2B"),
504 SND_SOC_DAPM_INPUT("AIN3A"),
505 SND_SOC_DAPM_INPUT("AIN3B"),
506
507 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0,
508 SND_SOC_NOPM, 0, 0),
509
510 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0,
511 SND_SOC_NOPM, 0, 0),
512
513 SND_SOC_DAPM_MUX("Digital Output Mux", SND_SOC_NOPM,
514 0, 0, &dig_mux),
515
516 SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 0, 0, NULL, 0),
517 SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 0, 0, NULL, 0),
518 SND_SOC_DAPM_MUX("PGAA Input Mux",
519 SND_SOC_NOPM, 0, 0, &pgaa_mux),
520 SND_SOC_DAPM_MUX("PGAB Input Mux",
521 SND_SOC_NOPM, 0, 0, &pgab_mux),
522
523 SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_NOPM,
524 0, 0, &adca_mux),
525 SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_NOPM,
526 0, 0, &adcb_mux),
527
528 SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56_PWRCTL_1, 1, 1),
529 SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56_PWRCTL_1, 2, 1),
530
531 SND_SOC_DAPM_MUX("ADCA Swap Mux", SND_SOC_NOPM, 0, 0,
532 &adca_swap_mux),
533 SND_SOC_DAPM_MUX("ADCB Swap Mux", SND_SOC_NOPM, 0, 0,
534 &adcb_swap_mux),
535
536 SND_SOC_DAPM_MUX("PCMA Swap Mux", SND_SOC_NOPM, 0, 0,
537 &pcma_swap_mux),
538 SND_SOC_DAPM_MUX("PCMB Swap Mux", SND_SOC_NOPM, 0, 0,
539 &pcmb_swap_mux),
540
541 SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC_NOPM, 0, 0),
542 SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC_NOPM, 0, 0),
543
544 SND_SOC_DAPM_OUTPUT("HPA"),
545 SND_SOC_DAPM_OUTPUT("LOA"),
546 SND_SOC_DAPM_OUTPUT("HPB"),
547 SND_SOC_DAPM_OUTPUT("LOB"),
548
549 SND_SOC_DAPM_SWITCH("Headphone Right",
550 CS42L56_PWRCTL_2, 4, 1, &hpb_switch),
551 SND_SOC_DAPM_SWITCH("Headphone Left",
552 CS42L56_PWRCTL_2, 6, 1, &hpa_switch),
553
554 SND_SOC_DAPM_SWITCH("Lineout Right",
555 CS42L56_PWRCTL_2, 0, 1, &lob_switch),
556 SND_SOC_DAPM_SWITCH("Lineout Left",
557 CS42L56_PWRCTL_2, 2, 1, &loa_switch),
558
559 SND_SOC_DAPM_MUX("LINEOUTA Input Mux", SND_SOC_NOPM,
560 0, 0, &lineouta_input),
561 SND_SOC_DAPM_MUX("LINEOUTB Input Mux", SND_SOC_NOPM,
562 0, 0, &lineoutb_input),
563 SND_SOC_DAPM_MUX("HPA Input Mux", SND_SOC_NOPM,
564 0, 0, &hpa_input),
565 SND_SOC_DAPM_MUX("HPB Input Mux", SND_SOC_NOPM,
566 0, 0, &hpb_input),
567
568 };
569
570 static const struct snd_soc_dapm_route cs42l56_audio_map[] = {
571
572 {"HiFi Capture", "DSP", "Digital Output Mux"},
573 {"HiFi Capture", "ADC", "Digital Output Mux"},
574
575 {"Digital Output Mux", NULL, "ADCA"},
576 {"Digital Output Mux", NULL, "ADCB"},
577
578 {"ADCB", NULL, "ADCB Swap Mux"},
579 {"ADCA", NULL, "ADCA Swap Mux"},
580
581 {"ADCA Swap Mux", NULL, "ADCA"},
582 {"ADCB Swap Mux", NULL, "ADCB"},
583
584 {"DACA", "Left", "ADCA Swap Mux"},
585 {"DACA", "LR 2", "ADCA Swap Mux"},
586 {"DACA", "Right", "ADCA Swap Mux"},
587
588 {"DACB", "Left", "ADCB Swap Mux"},
589 {"DACB", "LR 2", "ADCB Swap Mux"},
590 {"DACB", "Right", "ADCB Swap Mux"},
591
592 {"ADCA Mux", NULL, "AIN3A"},
593 {"ADCA Mux", NULL, "AIN2A"},
594 {"ADCA Mux", NULL, "AIN1A"},
595 {"ADCA Mux", NULL, "PGAA"},
596 {"ADCB Mux", NULL, "AIN3B"},
597 {"ADCB Mux", NULL, "AIN2B"},
598 {"ADCB Mux", NULL, "AIN1B"},
599 {"ADCB Mux", NULL, "PGAB"},
600
601 {"PGAA", "AIN1A", "PGAA Input Mux"},
602 {"PGAA", "AIN2A", "PGAA Input Mux"},
603 {"PGAA", "AIN3A", "PGAA Input Mux"},
604 {"PGAB", "AIN1B", "PGAB Input Mux"},
605 {"PGAB", "AIN2B", "PGAB Input Mux"},
606 {"PGAB", "AIN3B", "PGAB Input Mux"},
607
608 {"PGAA Input Mux", NULL, "AIN1A"},
609 {"PGAA Input Mux", NULL, "AIN2A"},
610 {"PGAA Input Mux", NULL, "AIN3A"},
611 {"PGAB Input Mux", NULL, "AIN1B"},
612 {"PGAB Input Mux", NULL, "AIN2B"},
613 {"PGAB Input Mux", NULL, "AIN3B"},
614
615 {"LOB", "Switch", "LINEOUTB Input Mux"},
616 {"LOA", "Switch", "LINEOUTA Input Mux"},
617
618 {"LINEOUTA Input Mux", "PGAA", "PGAA"},
619 {"LINEOUTB Input Mux", "PGAB", "PGAB"},
620 {"LINEOUTA Input Mux", "DACA", "DACA"},
621 {"LINEOUTB Input Mux", "DACB", "DACB"},
622
623 {"HPA", "Switch", "HPB Input Mux"},
624 {"HPB", "Switch", "HPA Input Mux"},
625
626 {"HPA Input Mux", "PGAA", "PGAA"},
627 {"HPB Input Mux", "PGAB", "PGAB"},
628 {"HPA Input Mux", "DACA", "DACA"},
629 {"HPB Input Mux", "DACB", "DACB"},
630
631 {"DACA", NULL, "PCMA Swap Mux"},
632 {"DACB", NULL, "PCMB Swap Mux"},
633
634 {"PCMB Swap Mux", "Left", "HiFi Playback"},
635 {"PCMB Swap Mux", "LR 2", "HiFi Playback"},
636 {"PCMB Swap Mux", "Right", "HiFi Playback"},
637
638 {"PCMA Swap Mux", "Left", "HiFi Playback"},
639 {"PCMA Swap Mux", "LR 2", "HiFi Playback"},
640 {"PCMA Swap Mux", "Right", "HiFi Playback"},
641
642 };
643
644 struct cs42l56_clk_para {
645 u32 mclk;
646 u32 srate;
647 u8 ratio;
648 };
649
650 static const struct cs42l56_clk_para clk_ratio_table[] = {
651 /* 8k */
652 { 6000000, 8000, CS42L56_MCLK_LRCLK_768 },
653 { 6144000, 8000, CS42L56_MCLK_LRCLK_750 },
654 { 12000000, 8000, CS42L56_MCLK_LRCLK_768 },
655 { 12288000, 8000, CS42L56_MCLK_LRCLK_750 },
656 { 24000000, 8000, CS42L56_MCLK_LRCLK_768 },
657 { 24576000, 8000, CS42L56_MCLK_LRCLK_750 },
658 /* 11.025k */
659 { 5644800, 11025, CS42L56_MCLK_LRCLK_512},
660 { 11289600, 11025, CS42L56_MCLK_LRCLK_512},
661 { 22579200, 11025, CS42L56_MCLK_LRCLK_512 },
662 /* 11.0294k */
663 { 6000000, 110294, CS42L56_MCLK_LRCLK_544 },
664 { 12000000, 110294, CS42L56_MCLK_LRCLK_544 },
665 { 24000000, 110294, CS42L56_MCLK_LRCLK_544 },
666 /* 12k */
667 { 6000000, 12000, CS42L56_MCLK_LRCLK_500 },
668 { 6144000, 12000, CS42L56_MCLK_LRCLK_512 },
669 { 12000000, 12000, CS42L56_MCLK_LRCLK_500 },
670 { 12288000, 12000, CS42L56_MCLK_LRCLK_512 },
671 { 24000000, 12000, CS42L56_MCLK_LRCLK_500 },
672 { 24576000, 12000, CS42L56_MCLK_LRCLK_512 },
673 /* 16k */
674 { 6000000, 16000, CS42L56_MCLK_LRCLK_375 },
675 { 6144000, 16000, CS42L56_MCLK_LRCLK_384 },
676 { 12000000, 16000, CS42L56_MCLK_LRCLK_375 },
677 { 12288000, 16000, CS42L56_MCLK_LRCLK_384 },
678 { 24000000, 16000, CS42L56_MCLK_LRCLK_375 },
679 { 24576000, 16000, CS42L56_MCLK_LRCLK_384 },
680 /* 22.050k */
681 { 5644800, 22050, CS42L56_MCLK_LRCLK_256 },
682 { 11289600, 22050, CS42L56_MCLK_LRCLK_256 },
683 { 22579200, 22050, CS42L56_MCLK_LRCLK_256 },
684 /* 22.0588k */
685 { 6000000, 220588, CS42L56_MCLK_LRCLK_272 },
686 { 12000000, 220588, CS42L56_MCLK_LRCLK_272 },
687 { 24000000, 220588, CS42L56_MCLK_LRCLK_272 },
688 /* 24k */
689 { 6000000, 24000, CS42L56_MCLK_LRCLK_250 },
690 { 6144000, 24000, CS42L56_MCLK_LRCLK_256 },
691 { 12000000, 24000, CS42L56_MCLK_LRCLK_250 },
692 { 12288000, 24000, CS42L56_MCLK_LRCLK_256 },
693 { 24000000, 24000, CS42L56_MCLK_LRCLK_250 },
694 { 24576000, 24000, CS42L56_MCLK_LRCLK_256 },
695 /* 32k */
696 { 6000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
697 { 6144000, 32000, CS42L56_MCLK_LRCLK_192 },
698 { 12000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
699 { 12288000, 32000, CS42L56_MCLK_LRCLK_192 },
700 { 24000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
701 { 24576000, 32000, CS42L56_MCLK_LRCLK_192 },
702 /* 44.118k */
703 { 6000000, 44118, CS42L56_MCLK_LRCLK_136 },
704 { 12000000, 44118, CS42L56_MCLK_LRCLK_136 },
705 { 24000000, 44118, CS42L56_MCLK_LRCLK_136 },
706 /* 44.1k */
707 { 5644800, 44100, CS42L56_MCLK_LRCLK_128 },
708 { 11289600, 44100, CS42L56_MCLK_LRCLK_128 },
709 { 22579200, 44100, CS42L56_MCLK_LRCLK_128 },
710 /* 48k */
711 { 6000000, 48000, CS42L56_MCLK_LRCLK_125 },
712 { 6144000, 48000, CS42L56_MCLK_LRCLK_128 },
713 { 12000000, 48000, CS42L56_MCLK_LRCLK_125 },
714 { 12288000, 48000, CS42L56_MCLK_LRCLK_128 },
715 { 24000000, 48000, CS42L56_MCLK_LRCLK_125 },
716 { 24576000, 48000, CS42L56_MCLK_LRCLK_128 },
717 };
718
719 static int cs42l56_get_mclk_ratio(int mclk, int rate)
720 {
721 int i;
722
723 for (i = 0; i < ARRAY_SIZE(clk_ratio_table); i++) {
724 if (clk_ratio_table[i].mclk == mclk &&
725 clk_ratio_table[i].srate == rate)
726 return clk_ratio_table[i].ratio;
727 }
728 return -EINVAL;
729 }
730
731 static int cs42l56_set_sysclk(struct snd_soc_dai *codec_dai,
732 int clk_id, unsigned int freq, int dir)
733 {
734 struct snd_soc_codec *codec = codec_dai->codec;
735 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
736
737 switch (freq) {
738 case CS42L56_MCLK_5P6448MHZ:
739 case CS42L56_MCLK_6MHZ:
740 case CS42L56_MCLK_6P144MHZ:
741 cs42l56->mclk_div2 = 0;
742 cs42l56->mclk_prediv = 0;
743 break;
744 case CS42L56_MCLK_11P2896MHZ:
745 case CS42L56_MCLK_12MHZ:
746 case CS42L56_MCLK_12P288MHZ:
747 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
748 cs42l56->mclk_prediv = 0;
749 break;
750 case CS42L56_MCLK_22P5792MHZ:
751 case CS42L56_MCLK_24MHZ:
752 case CS42L56_MCLK_24P576MHZ:
753 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
754 cs42l56->mclk_prediv = CS42L56_MCLK_PREDIV;
755 break;
756 default:
757 return -EINVAL;
758 }
759 cs42l56->mclk = freq;
760
761 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
762 CS42L56_MCLK_PREDIV_MASK,
763 cs42l56->mclk_prediv);
764 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
765 CS42L56_MCLK_DIV2_MASK,
766 cs42l56->mclk_div2);
767
768 return 0;
769 }
770
771 static int cs42l56_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
772 {
773 struct snd_soc_codec *codec = codec_dai->codec;
774 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
775
776 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
777 case SND_SOC_DAIFMT_CBM_CFM:
778 cs42l56->iface = CS42L56_MASTER_MODE;
779 break;
780 case SND_SOC_DAIFMT_CBS_CFS:
781 cs42l56->iface = CS42L56_SLAVE_MODE;
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 /* interface format */
788 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
789 case SND_SOC_DAIFMT_I2S:
790 cs42l56->iface_fmt = CS42L56_DIG_FMT_I2S;
791 break;
792 case SND_SOC_DAIFMT_LEFT_J:
793 cs42l56->iface_fmt = CS42L56_DIG_FMT_LEFT_J;
794 break;
795 default:
796 return -EINVAL;
797 }
798
799 /* sclk inversion */
800 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
801 case SND_SOC_DAIFMT_NB_NF:
802 cs42l56->iface_inv = 0;
803 break;
804 case SND_SOC_DAIFMT_IB_NF:
805 cs42l56->iface_inv = CS42L56_SCLK_INV;
806 break;
807 default:
808 return -EINVAL;
809 }
810
811 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
812 CS42L56_MS_MODE_MASK, cs42l56->iface);
813 snd_soc_update_bits(codec, CS42L56_SERIAL_FMT,
814 CS42L56_DIG_FMT_MASK, cs42l56->iface_fmt);
815 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
816 CS42L56_SCLK_INV_MASK, cs42l56->iface_inv);
817 return 0;
818 }
819
820 static int cs42l56_digital_mute(struct snd_soc_dai *dai, int mute)
821 {
822 struct snd_soc_codec *codec = dai->codec;
823
824 if (mute) {
825 /* Hit the DSP Mixer first */
826 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
827 CS42L56_ADCAMIX_MUTE_MASK |
828 CS42L56_ADCBMIX_MUTE_MASK |
829 CS42L56_PCMAMIX_MUTE_MASK |
830 CS42L56_PCMBMIX_MUTE_MASK |
831 CS42L56_MSTB_MUTE_MASK |
832 CS42L56_MSTA_MUTE_MASK,
833 CS42L56_MUTE_ALL);
834 /* Mute ADC's */
835 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
836 CS42L56_ADCA_MUTE_MASK |
837 CS42L56_ADCB_MUTE_MASK,
838 CS42L56_MUTE_ALL);
839 /* HP And LO */
840 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
841 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
842 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
843 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
844 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
845 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
846 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
847 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
848 } else {
849 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
850 CS42L56_ADCAMIX_MUTE_MASK |
851 CS42L56_ADCBMIX_MUTE_MASK |
852 CS42L56_PCMAMIX_MUTE_MASK |
853 CS42L56_PCMBMIX_MUTE_MASK |
854 CS42L56_MSTB_MUTE_MASK |
855 CS42L56_MSTA_MUTE_MASK,
856 CS42L56_UNMUTE);
857
858 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
859 CS42L56_ADCA_MUTE_MASK |
860 CS42L56_ADCB_MUTE_MASK,
861 CS42L56_UNMUTE);
862
863 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
864 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
865 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
866 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
867 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
868 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
869 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
870 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
871 }
872 return 0;
873 }
874
875 static int cs42l56_pcm_hw_params(struct snd_pcm_substream *substream,
876 struct snd_pcm_hw_params *params,
877 struct snd_soc_dai *dai)
878 {
879 struct snd_soc_codec *codec = dai->codec;
880 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
881 int ratio;
882
883 ratio = cs42l56_get_mclk_ratio(cs42l56->mclk, params_rate(params));
884 if (ratio >= 0) {
885 snd_soc_update_bits(codec, CS42L56_CLKCTL_2,
886 CS42L56_CLK_RATIO_MASK, ratio);
887 } else {
888 dev_err(codec->dev, "unsupported mclk/sclk/lrclk ratio\n");
889 return -EINVAL;
890 }
891
892 return 0;
893 }
894
895 static int cs42l56_set_bias_level(struct snd_soc_codec *codec,
896 enum snd_soc_bias_level level)
897 {
898 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
899 int ret;
900
901 switch (level) {
902 case SND_SOC_BIAS_ON:
903 break;
904 case SND_SOC_BIAS_PREPARE:
905 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
906 CS42L56_MCLK_DIS_MASK, 0);
907 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
908 CS42L56_PDN_ALL_MASK, 0);
909 break;
910 case SND_SOC_BIAS_STANDBY:
911 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
912 regcache_cache_only(cs42l56->regmap, false);
913 regcache_sync(cs42l56->regmap);
914 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
915 cs42l56->supplies);
916 if (ret != 0) {
917 dev_err(cs42l56->dev,
918 "Failed to enable regulators: %d\n",
919 ret);
920 return ret;
921 }
922 }
923 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
924 CS42L56_PDN_ALL_MASK, 1);
925 break;
926 case SND_SOC_BIAS_OFF:
927 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
928 CS42L56_PDN_ALL_MASK, 1);
929 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
930 CS42L56_MCLK_DIS_MASK, 1);
931 regcache_cache_only(cs42l56->regmap, true);
932 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
933 cs42l56->supplies);
934 break;
935 }
936
937 return 0;
938 }
939
940 #define CS42L56_RATES (SNDRV_PCM_RATE_8000_48000)
941
942 #define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
943 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
944 SNDRV_PCM_FMTBIT_S32_LE)
945
946
947 static const struct snd_soc_dai_ops cs42l56_ops = {
948 .hw_params = cs42l56_pcm_hw_params,
949 .digital_mute = cs42l56_digital_mute,
950 .set_fmt = cs42l56_set_dai_fmt,
951 .set_sysclk = cs42l56_set_sysclk,
952 };
953
954 static struct snd_soc_dai_driver cs42l56_dai = {
955 .name = "cs42l56",
956 .playback = {
957 .stream_name = "HiFi Playback",
958 .channels_min = 1,
959 .channels_max = 2,
960 .rates = CS42L56_RATES,
961 .formats = CS42L56_FORMATS,
962 },
963 .capture = {
964 .stream_name = "HiFi Capture",
965 .channels_min = 1,
966 .channels_max = 2,
967 .rates = CS42L56_RATES,
968 .formats = CS42L56_FORMATS,
969 },
970 .ops = &cs42l56_ops,
971 };
972
973 static int beep_freq[] = {
974 261, 522, 585, 667, 706, 774, 889, 1000,
975 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
976 };
977
978 static void cs42l56_beep_work(struct work_struct *work)
979 {
980 struct cs42l56_private *cs42l56 =
981 container_of(work, struct cs42l56_private, beep_work);
982 struct snd_soc_codec *codec = cs42l56->codec;
983 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
984 int i;
985 int val = 0;
986 int best = 0;
987
988 if (cs42l56->beep_rate) {
989 for (i = 0; i < ARRAY_SIZE(beep_freq); i++) {
990 if (abs(cs42l56->beep_rate - beep_freq[i]) <
991 abs(cs42l56->beep_rate - beep_freq[best]))
992 best = i;
993 }
994
995 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
996 beep_freq[best], cs42l56->beep_rate);
997
998 val = (best << CS42L56_BEEP_RATE_SHIFT);
999
1000 snd_soc_dapm_enable_pin(dapm, "Beep");
1001 } else {
1002 dev_dbg(codec->dev, "Disabling beep\n");
1003 snd_soc_dapm_disable_pin(dapm, "Beep");
1004 }
1005
1006 snd_soc_update_bits(codec, CS42L56_BEEP_FREQ_ONTIME,
1007 CS42L56_BEEP_FREQ_MASK, val);
1008
1009 snd_soc_dapm_sync(dapm);
1010 }
1011
1012 /* For usability define a way of injecting beep events for the device -
1013 * many systems will not have a keyboard.
1014 */
1015 static int cs42l56_beep_event(struct input_dev *dev, unsigned int type,
1016 unsigned int code, int hz)
1017 {
1018 struct snd_soc_codec *codec = input_get_drvdata(dev);
1019 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1020
1021 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1022
1023 switch (code) {
1024 case SND_BELL:
1025 if (hz)
1026 hz = 261;
1027 case SND_TONE:
1028 break;
1029 default:
1030 return -1;
1031 }
1032
1033 /* Kick the beep from a workqueue */
1034 cs42l56->beep_rate = hz;
1035 schedule_work(&cs42l56->beep_work);
1036 return 0;
1037 }
1038
1039 static ssize_t cs42l56_beep_set(struct device *dev,
1040 struct device_attribute *attr,
1041 const char *buf, size_t count)
1042 {
1043 struct cs42l56_private *cs42l56 = dev_get_drvdata(dev);
1044 long int time;
1045 int ret;
1046
1047 ret = kstrtol(buf, 10, &time);
1048 if (ret != 0)
1049 return ret;
1050
1051 input_event(cs42l56->beep, EV_SND, SND_TONE, time);
1052
1053 return count;
1054 }
1055
1056 static DEVICE_ATTR(beep, 0200, NULL, cs42l56_beep_set);
1057
1058 static void cs42l56_init_beep(struct snd_soc_codec *codec)
1059 {
1060 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1061 int ret;
1062
1063 cs42l56->beep = devm_input_allocate_device(codec->dev);
1064 if (!cs42l56->beep) {
1065 dev_err(codec->dev, "Failed to allocate beep device\n");
1066 return;
1067 }
1068
1069 INIT_WORK(&cs42l56->beep_work, cs42l56_beep_work);
1070 cs42l56->beep_rate = 0;
1071
1072 cs42l56->beep->name = "CS42L56 Beep Generator";
1073 cs42l56->beep->phys = dev_name(codec->dev);
1074 cs42l56->beep->id.bustype = BUS_I2C;
1075
1076 cs42l56->beep->evbit[0] = BIT_MASK(EV_SND);
1077 cs42l56->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1078 cs42l56->beep->event = cs42l56_beep_event;
1079 cs42l56->beep->dev.parent = codec->dev;
1080 input_set_drvdata(cs42l56->beep, codec);
1081
1082 ret = input_register_device(cs42l56->beep);
1083 if (ret != 0) {
1084 cs42l56->beep = NULL;
1085 dev_err(codec->dev, "Failed to register beep device\n");
1086 }
1087
1088 ret = device_create_file(codec->dev, &dev_attr_beep);
1089 if (ret != 0) {
1090 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1091 ret);
1092 }
1093 }
1094
1095 static void cs42l56_free_beep(struct snd_soc_codec *codec)
1096 {
1097 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1098
1099 device_remove_file(codec->dev, &dev_attr_beep);
1100 cancel_work_sync(&cs42l56->beep_work);
1101 cs42l56->beep = NULL;
1102
1103 snd_soc_update_bits(codec, CS42L56_BEEP_TONE_CFG,
1104 CS42L56_BEEP_EN_MASK, 0);
1105 }
1106
1107 static int cs42l56_probe(struct snd_soc_codec *codec)
1108 {
1109 cs42l56_init_beep(codec);
1110
1111 return 0;
1112 }
1113
1114 static int cs42l56_remove(struct snd_soc_codec *codec)
1115 {
1116 cs42l56_free_beep(codec);
1117
1118 return 0;
1119 }
1120
1121 static const struct snd_soc_codec_driver soc_codec_dev_cs42l56 = {
1122 .probe = cs42l56_probe,
1123 .remove = cs42l56_remove,
1124 .set_bias_level = cs42l56_set_bias_level,
1125 .suspend_bias_off = true,
1126
1127 .dapm_widgets = cs42l56_dapm_widgets,
1128 .num_dapm_widgets = ARRAY_SIZE(cs42l56_dapm_widgets),
1129 .dapm_routes = cs42l56_audio_map,
1130 .num_dapm_routes = ARRAY_SIZE(cs42l56_audio_map),
1131
1132 .controls = cs42l56_snd_controls,
1133 .num_controls = ARRAY_SIZE(cs42l56_snd_controls),
1134 };
1135
1136 static const struct regmap_config cs42l56_regmap = {
1137 .reg_bits = 8,
1138 .val_bits = 8,
1139
1140 .max_register = CS42L56_MAX_REGISTER,
1141 .reg_defaults = cs42l56_reg_defaults,
1142 .num_reg_defaults = ARRAY_SIZE(cs42l56_reg_defaults),
1143 .readable_reg = cs42l56_readable_register,
1144 .volatile_reg = cs42l56_volatile_register,
1145 .cache_type = REGCACHE_RBTREE,
1146 };
1147
1148 static int cs42l56_handle_of_data(struct i2c_client *i2c_client,
1149 struct cs42l56_platform_data *pdata)
1150 {
1151 struct device_node *np = i2c_client->dev.of_node;
1152 u32 val32;
1153
1154 if (of_property_read_bool(np, "cirrus,ain1a-reference-cfg"))
1155 pdata->ain1a_ref_cfg = true;
1156
1157 if (of_property_read_bool(np, "cirrus,ain2a-reference-cfg"))
1158 pdata->ain2a_ref_cfg = true;
1159
1160 if (of_property_read_bool(np, "cirrus,ain1b-reference-cfg"))
1161 pdata->ain1b_ref_cfg = true;
1162
1163 if (of_property_read_bool(np, "cirrus,ain2b-reference-cfg"))
1164 pdata->ain2b_ref_cfg = true;
1165
1166 if (of_property_read_u32(np, "cirrus,micbias-lvl", &val32) >= 0)
1167 pdata->micbias_lvl = val32;
1168
1169 if (of_property_read_u32(np, "cirrus,chgfreq-divisor", &val32) >= 0)
1170 pdata->chgfreq = val32;
1171
1172 if (of_property_read_u32(np, "cirrus,adaptive-pwr-cfg", &val32) >= 0)
1173 pdata->adaptive_pwr = val32;
1174
1175 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1176 pdata->hpfa_freq = val32;
1177
1178 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1179 pdata->hpfb_freq = val32;
1180
1181 pdata->gpio_nreset = of_get_named_gpio(np, "cirrus,gpio-nreset", 0);
1182
1183 return 0;
1184 }
1185
1186 static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
1187 const struct i2c_device_id *id)
1188 {
1189 struct cs42l56_private *cs42l56;
1190 struct cs42l56_platform_data *pdata =
1191 dev_get_platdata(&i2c_client->dev);
1192 int ret, i;
1193 unsigned int devid = 0;
1194 unsigned int alpha_rev, metal_rev;
1195 unsigned int reg;
1196
1197 cs42l56 = devm_kzalloc(&i2c_client->dev,
1198 sizeof(struct cs42l56_private),
1199 GFP_KERNEL);
1200 if (cs42l56 == NULL)
1201 return -ENOMEM;
1202 cs42l56->dev = &i2c_client->dev;
1203
1204 cs42l56->regmap = devm_regmap_init_i2c(i2c_client, &cs42l56_regmap);
1205 if (IS_ERR(cs42l56->regmap)) {
1206 ret = PTR_ERR(cs42l56->regmap);
1207 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1208 return ret;
1209 }
1210
1211 if (pdata) {
1212 cs42l56->pdata = *pdata;
1213 } else {
1214 pdata = devm_kzalloc(&i2c_client->dev,
1215 sizeof(struct cs42l56_platform_data),
1216 GFP_KERNEL);
1217 if (!pdata) {
1218 dev_err(&i2c_client->dev,
1219 "could not allocate pdata\n");
1220 return -ENOMEM;
1221 }
1222 if (i2c_client->dev.of_node) {
1223 ret = cs42l56_handle_of_data(i2c_client,
1224 &cs42l56->pdata);
1225 if (ret != 0)
1226 return ret;
1227 }
1228 cs42l56->pdata = *pdata;
1229 }
1230
1231 if (cs42l56->pdata.gpio_nreset) {
1232 ret = gpio_request_one(cs42l56->pdata.gpio_nreset,
1233 GPIOF_OUT_INIT_HIGH, "CS42L56 /RST");
1234 if (ret < 0) {
1235 dev_err(&i2c_client->dev,
1236 "Failed to request /RST %d: %d\n",
1237 cs42l56->pdata.gpio_nreset, ret);
1238 return ret;
1239 }
1240 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 0);
1241 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 1);
1242 }
1243
1244
1245 i2c_set_clientdata(i2c_client, cs42l56);
1246
1247 for (i = 0; i < ARRAY_SIZE(cs42l56->supplies); i++)
1248 cs42l56->supplies[i].supply = cs42l56_supply_names[i];
1249
1250 ret = devm_regulator_bulk_get(&i2c_client->dev,
1251 ARRAY_SIZE(cs42l56->supplies),
1252 cs42l56->supplies);
1253 if (ret != 0) {
1254 dev_err(&i2c_client->dev,
1255 "Failed to request supplies: %d\n", ret);
1256 return ret;
1257 }
1258
1259 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1260 cs42l56->supplies);
1261 if (ret != 0) {
1262 dev_err(&i2c_client->dev,
1263 "Failed to enable supplies: %d\n", ret);
1264 return ret;
1265 }
1266
1267 regcache_cache_bypass(cs42l56->regmap, true);
1268
1269 ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, &reg);
1270 devid = reg & CS42L56_CHIP_ID_MASK;
1271 if (devid != CS42L56_DEVID) {
1272 dev_err(&i2c_client->dev,
1273 "CS42L56 Device ID (%X). Expected %X\n",
1274 devid, CS42L56_DEVID);
1275 goto err_enable;
1276 }
1277 alpha_rev = reg & CS42L56_AREV_MASK;
1278 metal_rev = reg & CS42L56_MTLREV_MASK;
1279
1280 dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1281 dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1282 alpha_rev, metal_rev);
1283
1284 regcache_cache_bypass(cs42l56->regmap, false);
1285
1286 if (cs42l56->pdata.ain1a_ref_cfg)
1287 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1288 CS42L56_AIN1A_REF_MASK, 1);
1289
1290 if (cs42l56->pdata.ain1b_ref_cfg)
1291 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1292 CS42L56_AIN1B_REF_MASK, 1);
1293
1294 if (cs42l56->pdata.ain2a_ref_cfg)
1295 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1296 CS42L56_AIN2A_REF_MASK, 1);
1297
1298 if (cs42l56->pdata.ain2b_ref_cfg)
1299 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1300 CS42L56_AIN2B_REF_MASK, 1);
1301
1302 if (cs42l56->pdata.micbias_lvl)
1303 regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1304 CS42L56_MIC_BIAS_MASK,
1305 cs42l56->pdata.micbias_lvl);
1306
1307 if (cs42l56->pdata.chgfreq)
1308 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1309 CS42L56_CHRG_FREQ_MASK,
1310 cs42l56->pdata.chgfreq);
1311
1312 if (cs42l56->pdata.hpfb_freq)
1313 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1314 CS42L56_HPFB_FREQ_MASK,
1315 cs42l56->pdata.hpfb_freq);
1316
1317 if (cs42l56->pdata.hpfa_freq)
1318 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1319 CS42L56_HPFA_FREQ_MASK,
1320 cs42l56->pdata.hpfa_freq);
1321
1322 if (cs42l56->pdata.adaptive_pwr)
1323 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1324 CS42L56_ADAPT_PWR_MASK,
1325 cs42l56->pdata.adaptive_pwr);
1326
1327 ret = snd_soc_register_codec(&i2c_client->dev,
1328 &soc_codec_dev_cs42l56, &cs42l56_dai, 1);
1329 if (ret < 0)
1330 return ret;
1331
1332 return 0;
1333
1334 err_enable:
1335 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1336 cs42l56->supplies);
1337 return ret;
1338 }
1339
1340 static int cs42l56_i2c_remove(struct i2c_client *client)
1341 {
1342 struct cs42l56_private *cs42l56 = i2c_get_clientdata(client);
1343
1344 snd_soc_unregister_codec(&client->dev);
1345 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1346 cs42l56->supplies);
1347 return 0;
1348 }
1349
1350 static const struct of_device_id cs42l56_of_match[] = {
1351 { .compatible = "cirrus,cs42l56", },
1352 { }
1353 };
1354 MODULE_DEVICE_TABLE(of, cs42l56_of_match);
1355
1356
1357 static const struct i2c_device_id cs42l56_id[] = {
1358 { "cs42l56", 0 },
1359 { }
1360 };
1361 MODULE_DEVICE_TABLE(i2c, cs42l56_id);
1362
1363 static struct i2c_driver cs42l56_i2c_driver = {
1364 .driver = {
1365 .name = "cs42l56",
1366 .of_match_table = cs42l56_of_match,
1367 },
1368 .id_table = cs42l56_id,
1369 .probe = cs42l56_i2c_probe,
1370 .remove = cs42l56_i2c_remove,
1371 };
1372
1373 module_i2c_driver(cs42l56_i2c_driver);
1374
1375 MODULE_DESCRIPTION("ASoC CS42L56 driver");
1376 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1377 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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