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Merge remote-tracking branches 'asoc/topic/rt298', 'asoc/topic/rt5640', 'asoc/topic...
[deliverable/linux.git] / sound / soc / codecs / max98095.c
1 /*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/mutex.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/initval.h>
25 #include <sound/tlv.h>
26 #include <linux/slab.h>
27 #include <asm/div64.h>
28 #include <sound/max98095.h>
29 #include <sound/jack.h>
30 #include "max98095.h"
31
32 enum max98095_type {
33 MAX98095,
34 };
35
36 struct max98095_cdata {
37 unsigned int rate;
38 unsigned int fmt;
39 int eq_sel;
40 int bq_sel;
41 };
42
43 struct max98095_priv {
44 struct regmap *regmap;
45 enum max98095_type devtype;
46 struct max98095_pdata *pdata;
47 struct clk *mclk;
48 unsigned int sysclk;
49 struct max98095_cdata dai[3];
50 const char **eq_texts;
51 const char **bq_texts;
52 struct soc_enum eq_enum;
53 struct soc_enum bq_enum;
54 int eq_textcnt;
55 int bq_textcnt;
56 u8 lin_state;
57 unsigned int mic1pre;
58 unsigned int mic2pre;
59 struct snd_soc_jack *headphone_jack;
60 struct snd_soc_jack *mic_jack;
61 struct mutex lock;
62 };
63
64 static const struct reg_default max98095_reg_def[] = {
65 { 0xf, 0x00 }, /* 0F */
66 { 0x10, 0x00 }, /* 10 */
67 { 0x11, 0x00 }, /* 11 */
68 { 0x12, 0x00 }, /* 12 */
69 { 0x13, 0x00 }, /* 13 */
70 { 0x14, 0x00 }, /* 14 */
71 { 0x15, 0x00 }, /* 15 */
72 { 0x16, 0x00 }, /* 16 */
73 { 0x17, 0x00 }, /* 17 */
74 { 0x18, 0x00 }, /* 18 */
75 { 0x19, 0x00 }, /* 19 */
76 { 0x1a, 0x00 }, /* 1A */
77 { 0x1b, 0x00 }, /* 1B */
78 { 0x1c, 0x00 }, /* 1C */
79 { 0x1d, 0x00 }, /* 1D */
80 { 0x1e, 0x00 }, /* 1E */
81 { 0x1f, 0x00 }, /* 1F */
82 { 0x20, 0x00 }, /* 20 */
83 { 0x21, 0x00 }, /* 21 */
84 { 0x22, 0x00 }, /* 22 */
85 { 0x23, 0x00 }, /* 23 */
86 { 0x24, 0x00 }, /* 24 */
87 { 0x25, 0x00 }, /* 25 */
88 { 0x26, 0x00 }, /* 26 */
89 { 0x27, 0x00 }, /* 27 */
90 { 0x28, 0x00 }, /* 28 */
91 { 0x29, 0x00 }, /* 29 */
92 { 0x2a, 0x00 }, /* 2A */
93 { 0x2b, 0x00 }, /* 2B */
94 { 0x2c, 0x00 }, /* 2C */
95 { 0x2d, 0x00 }, /* 2D */
96 { 0x2e, 0x00 }, /* 2E */
97 { 0x2f, 0x00 }, /* 2F */
98 { 0x30, 0x00 }, /* 30 */
99 { 0x31, 0x00 }, /* 31 */
100 { 0x32, 0x00 }, /* 32 */
101 { 0x33, 0x00 }, /* 33 */
102 { 0x34, 0x00 }, /* 34 */
103 { 0x35, 0x00 }, /* 35 */
104 { 0x36, 0x00 }, /* 36 */
105 { 0x37, 0x00 }, /* 37 */
106 { 0x38, 0x00 }, /* 38 */
107 { 0x39, 0x00 }, /* 39 */
108 { 0x3a, 0x00 }, /* 3A */
109 { 0x3b, 0x00 }, /* 3B */
110 { 0x3c, 0x00 }, /* 3C */
111 { 0x3d, 0x00 }, /* 3D */
112 { 0x3e, 0x00 }, /* 3E */
113 { 0x3f, 0x00 }, /* 3F */
114 { 0x40, 0x00 }, /* 40 */
115 { 0x41, 0x00 }, /* 41 */
116 { 0x42, 0x00 }, /* 42 */
117 { 0x43, 0x00 }, /* 43 */
118 { 0x44, 0x00 }, /* 44 */
119 { 0x45, 0x00 }, /* 45 */
120 { 0x46, 0x00 }, /* 46 */
121 { 0x47, 0x00 }, /* 47 */
122 { 0x48, 0x00 }, /* 48 */
123 { 0x49, 0x00 }, /* 49 */
124 { 0x4a, 0x00 }, /* 4A */
125 { 0x4b, 0x00 }, /* 4B */
126 { 0x4c, 0x00 }, /* 4C */
127 { 0x4d, 0x00 }, /* 4D */
128 { 0x4e, 0x00 }, /* 4E */
129 { 0x4f, 0x00 }, /* 4F */
130 { 0x50, 0x00 }, /* 50 */
131 { 0x51, 0x00 }, /* 51 */
132 { 0x52, 0x00 }, /* 52 */
133 { 0x53, 0x00 }, /* 53 */
134 { 0x54, 0x00 }, /* 54 */
135 { 0x55, 0x00 }, /* 55 */
136 { 0x56, 0x00 }, /* 56 */
137 { 0x57, 0x00 }, /* 57 */
138 { 0x58, 0x00 }, /* 58 */
139 { 0x59, 0x00 }, /* 59 */
140 { 0x5a, 0x00 }, /* 5A */
141 { 0x5b, 0x00 }, /* 5B */
142 { 0x5c, 0x00 }, /* 5C */
143 { 0x5d, 0x00 }, /* 5D */
144 { 0x5e, 0x00 }, /* 5E */
145 { 0x5f, 0x00 }, /* 5F */
146 { 0x60, 0x00 }, /* 60 */
147 { 0x61, 0x00 }, /* 61 */
148 { 0x62, 0x00 }, /* 62 */
149 { 0x63, 0x00 }, /* 63 */
150 { 0x64, 0x00 }, /* 64 */
151 { 0x65, 0x00 }, /* 65 */
152 { 0x66, 0x00 }, /* 66 */
153 { 0x67, 0x00 }, /* 67 */
154 { 0x68, 0x00 }, /* 68 */
155 { 0x69, 0x00 }, /* 69 */
156 { 0x6a, 0x00 }, /* 6A */
157 { 0x6b, 0x00 }, /* 6B */
158 { 0x6c, 0x00 }, /* 6C */
159 { 0x6d, 0x00 }, /* 6D */
160 { 0x6e, 0x00 }, /* 6E */
161 { 0x6f, 0x00 }, /* 6F */
162 { 0x70, 0x00 }, /* 70 */
163 { 0x71, 0x00 }, /* 71 */
164 { 0x72, 0x00 }, /* 72 */
165 { 0x73, 0x00 }, /* 73 */
166 { 0x74, 0x00 }, /* 74 */
167 { 0x75, 0x00 }, /* 75 */
168 { 0x76, 0x00 }, /* 76 */
169 { 0x77, 0x00 }, /* 77 */
170 { 0x78, 0x00 }, /* 78 */
171 { 0x79, 0x00 }, /* 79 */
172 { 0x7a, 0x00 }, /* 7A */
173 { 0x7b, 0x00 }, /* 7B */
174 { 0x7c, 0x00 }, /* 7C */
175 { 0x7d, 0x00 }, /* 7D */
176 { 0x7e, 0x00 }, /* 7E */
177 { 0x7f, 0x00 }, /* 7F */
178 { 0x80, 0x00 }, /* 80 */
179 { 0x81, 0x00 }, /* 81 */
180 { 0x82, 0x00 }, /* 82 */
181 { 0x83, 0x00 }, /* 83 */
182 { 0x84, 0x00 }, /* 84 */
183 { 0x85, 0x00 }, /* 85 */
184 { 0x86, 0x00 }, /* 86 */
185 { 0x87, 0x00 }, /* 87 */
186 { 0x88, 0x00 }, /* 88 */
187 { 0x89, 0x00 }, /* 89 */
188 { 0x8a, 0x00 }, /* 8A */
189 { 0x8b, 0x00 }, /* 8B */
190 { 0x8c, 0x00 }, /* 8C */
191 { 0x8d, 0x00 }, /* 8D */
192 { 0x8e, 0x00 }, /* 8E */
193 { 0x8f, 0x00 }, /* 8F */
194 { 0x90, 0x00 }, /* 90 */
195 { 0x91, 0x00 }, /* 91 */
196 { 0x92, 0x30 }, /* 92 */
197 { 0x93, 0xF0 }, /* 93 */
198 { 0x94, 0x00 }, /* 94 */
199 { 0x95, 0x00 }, /* 95 */
200 { 0x96, 0x3F }, /* 96 */
201 { 0x97, 0x00 }, /* 97 */
202 { 0xff, 0x00 }, /* FF */
203 };
204
205 static bool max98095_readable(struct device *dev, unsigned int reg)
206 {
207 switch (reg) {
208 case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS:
209 case M98095_0FF_REV_ID:
210 return true;
211 default:
212 return false;
213 }
214 }
215
216 static bool max98095_writeable(struct device *dev, unsigned int reg)
217 {
218 switch (reg) {
219 case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS:
220 return true;
221 default:
222 return false;
223 }
224 }
225
226 static bool max98095_volatile(struct device *dev, unsigned int reg)
227 {
228 switch (reg) {
229 case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS:
230 case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID:
231 return true;
232 default:
233 return false;
234 }
235 }
236
237 static const struct regmap_config max98095_regmap = {
238 .reg_bits = 8,
239 .val_bits = 8,
240
241 .reg_defaults = max98095_reg_def,
242 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
243 .max_register = M98095_0FF_REV_ID,
244 .cache_type = REGCACHE_RBTREE,
245
246 .readable_reg = max98095_readable,
247 .writeable_reg = max98095_writeable,
248 .volatile_reg = max98095_volatile,
249 };
250
251 /*
252 * Load equalizer DSP coefficient configurations registers
253 */
254 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
255 unsigned int band, u16 *coefs)
256 {
257 unsigned int eq_reg;
258 unsigned int i;
259
260 if (WARN_ON(band > 4) ||
261 WARN_ON(dai > 1))
262 return;
263
264 /* Load the base register address */
265 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE;
266
267 /* Add the band address offset, note adjustment for word address */
268 eq_reg += band * (M98095_COEFS_PER_BAND << 1);
269
270 /* Step through the registers and coefs */
271 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
272 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
273 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
274 }
275 }
276
277 /*
278 * Load biquad filter coefficient configurations registers
279 */
280 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
281 unsigned int band, u16 *coefs)
282 {
283 unsigned int bq_reg;
284 unsigned int i;
285
286 if (WARN_ON(band > 1) ||
287 WARN_ON(dai > 1))
288 return;
289
290 /* Load the base register address */
291 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE;
292
293 /* Add the band address offset, note adjustment for word address */
294 bq_reg += band * (M98095_COEFS_PER_BAND << 1);
295
296 /* Step through the registers and coefs */
297 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
298 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
299 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
300 }
301 }
302
303 static const char * const max98095_fltr_mode[] = { "Voice", "Music" };
304 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum,
305 M98095_02E_DAI1_FILTERS, 7,
306 max98095_fltr_mode);
307 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum,
308 M98095_038_DAI2_FILTERS, 7,
309 max98095_fltr_mode);
310
311 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" };
312
313 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum,
314 M98095_087_CFG_MIC, 0,
315 max98095_extmic_text);
316
317 static const struct snd_kcontrol_new max98095_extmic_mux =
318 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum);
319
320 static const char * const max98095_linein_text[] = { "INA", "INB" };
321
322 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum,
323 M98095_086_CFG_LINE, 6,
324 max98095_linein_text);
325
326 static const struct snd_kcontrol_new max98095_linein_mux =
327 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum);
328
329 static const char * const max98095_line_mode_text[] = {
330 "Stereo", "Differential"};
331
332 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum,
333 M98095_086_CFG_LINE, 7,
334 max98095_line_mode_text);
335
336 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum,
337 M98095_086_CFG_LINE, 4,
338 max98095_line_mode_text);
339
340 static const char * const max98095_dai_fltr[] = {
341 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k",
342 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"};
343 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum,
344 M98095_02E_DAI1_FILTERS, 0,
345 max98095_dai_fltr);
346 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum,
347 M98095_038_DAI2_FILTERS, 0,
348 max98095_dai_fltr);
349 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
350 M98095_042_DAI3_FILTERS, 0,
351 max98095_dai_fltr);
352
353 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355 {
356 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
357 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
358 unsigned int sel = ucontrol->value.integer.value[0];
359
360 max98095->mic1pre = sel;
361 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK,
362 (1+sel)<<M98095_MICPRE_SHIFT);
363
364 return 0;
365 }
366
367 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
368 struct snd_ctl_elem_value *ucontrol)
369 {
370 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
371 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
372
373 ucontrol->value.integer.value[0] = max98095->mic1pre;
374 return 0;
375 }
376
377 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
378 struct snd_ctl_elem_value *ucontrol)
379 {
380 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
381 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
382 unsigned int sel = ucontrol->value.integer.value[0];
383
384 max98095->mic2pre = sel;
385 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK,
386 (1+sel)<<M98095_MICPRE_SHIFT);
387
388 return 0;
389 }
390
391 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_value *ucontrol)
393 {
394 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
395 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
396
397 ucontrol->value.integer.value[0] = max98095->mic2pre;
398 return 0;
399 }
400
401 static const unsigned int max98095_micboost_tlv[] = {
402 TLV_DB_RANGE_HEAD(2),
403 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
404 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
405 };
406
407 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0);
408 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0);
409 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0);
410
411 static const unsigned int max98095_hp_tlv[] = {
412 TLV_DB_RANGE_HEAD(5),
413 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
414 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
415 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
416 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
417 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
418 };
419
420 static const unsigned int max98095_spk_tlv[] = {
421 TLV_DB_RANGE_HEAD(4),
422 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0),
423 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0),
424 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0),
425 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0),
426 };
427
428 static const unsigned int max98095_rcv_lout_tlv[] = {
429 TLV_DB_RANGE_HEAD(5),
430 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
431 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
432 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
433 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
434 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
435 };
436
437 static const unsigned int max98095_lin_tlv[] = {
438 TLV_DB_RANGE_HEAD(3),
439 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0),
440 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0),
441 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
442 };
443
444 static const struct snd_kcontrol_new max98095_snd_controls[] = {
445
446 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L,
447 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv),
448
449 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L,
450 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv),
451
452 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV,
453 0, 31, 0, max98095_rcv_lout_tlv),
454
455 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1,
456 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv),
457
458 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L,
459 M98095_065_LVL_HP_R, 7, 1, 1),
460
461 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L,
462 M98095_068_LVL_SPK_R, 7, 1, 1),
463
464 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1),
465
466 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1,
467 M98095_063_LVL_LINEOUT2, 7, 1, 1),
468
469 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1,
470 max98095_mic_tlv),
471
472 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1,
473 max98095_mic_tlv),
474
475 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
476 M98095_05F_LVL_MIC1, 5, 2, 0,
477 max98095_mic1pre_get, max98095_mic1pre_set,
478 max98095_micboost_tlv),
479 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
480 M98095_060_LVL_MIC2, 5, 2, 0,
481 max98095_mic2pre_get, max98095_mic2pre_set,
482 max98095_micboost_tlv),
483
484 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1,
485 max98095_lin_tlv),
486
487 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1,
488 max98095_adc_tlv),
489 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
490 max98095_adc_tlv),
491
492 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0,
493 max98095_adcboost_tlv),
494 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
495 max98095_adcboost_tlv),
496
497 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0),
498 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0),
499
500 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0),
501 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0),
502
503 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum),
504 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum),
505 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum),
506 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum),
507 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum),
508
509 SOC_ENUM("Linein Mode", max98095_linein_mode_enum),
510 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum),
511 };
512
513 /* Left speaker mixer switch */
514 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = {
515 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0),
516 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0),
517 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
518 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0),
519 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0),
520 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0),
521 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0),
522 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0),
523 };
524
525 /* Right speaker mixer switch */
526 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = {
527 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0),
528 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0),
529 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
530 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0),
531 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0),
532 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0),
533 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0),
534 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0),
535 };
536
537 /* Left headphone mixer switch */
538 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = {
539 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0),
540 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0),
541 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0),
542 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0),
543 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0),
544 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0),
545 };
546
547 /* Right headphone mixer switch */
548 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = {
549 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0),
550 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0),
551 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0),
552 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0),
553 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0),
554 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0),
555 };
556
557 /* Receiver earpiece mixer switch */
558 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = {
559 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0),
560 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0),
561 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0),
562 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0),
563 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0),
564 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0),
565 };
566
567 /* Left lineout mixer switch */
568 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = {
569 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0),
570 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0),
571 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0),
572 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0),
573 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0),
574 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0),
575 };
576
577 /* Right lineout mixer switch */
578 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = {
579 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0),
580 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0),
581 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0),
582 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0),
583 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0),
584 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0),
585 };
586
587 /* Left ADC mixer switch */
588 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = {
589 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0),
590 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0),
591 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0),
592 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0),
593 };
594
595 /* Right ADC mixer switch */
596 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = {
597 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0),
598 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0),
599 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0),
600 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0),
601 };
602
603 static int max98095_mic_event(struct snd_soc_dapm_widget *w,
604 struct snd_kcontrol *kcontrol, int event)
605 {
606 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
607 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
608
609 switch (event) {
610 case SND_SOC_DAPM_POST_PMU:
611 if (w->reg == M98095_05F_LVL_MIC1) {
612 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
613 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT);
614 } else {
615 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK,
616 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT);
617 }
618 break;
619 case SND_SOC_DAPM_POST_PMD:
620 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0);
621 break;
622 default:
623 return -EINVAL;
624 }
625
626 return 0;
627 }
628
629 /*
630 * The line inputs are stereo inputs with the left and right
631 * channels sharing a common PGA power control signal.
632 */
633 static int max98095_line_pga(struct snd_soc_dapm_widget *w,
634 int event, u8 channel)
635 {
636 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
637 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
638 u8 *state;
639
640 if (WARN_ON(!(channel == 1 || channel == 2)))
641 return -EINVAL;
642
643 state = &max98095->lin_state;
644
645 switch (event) {
646 case SND_SOC_DAPM_POST_PMU:
647 *state |= channel;
648 snd_soc_update_bits(codec, w->reg,
649 (1 << w->shift), (1 << w->shift));
650 break;
651 case SND_SOC_DAPM_POST_PMD:
652 *state &= ~channel;
653 if (*state == 0) {
654 snd_soc_update_bits(codec, w->reg,
655 (1 << w->shift), 0);
656 }
657 break;
658 default:
659 return -EINVAL;
660 }
661
662 return 0;
663 }
664
665 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w,
666 struct snd_kcontrol *k, int event)
667 {
668 return max98095_line_pga(w, event, 1);
669 }
670
671 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w,
672 struct snd_kcontrol *k, int event)
673 {
674 return max98095_line_pga(w, event, 2);
675 }
676
677 /*
678 * The stereo line out mixer outputs to two stereo line outs.
679 * The 2nd pair has a separate set of enables.
680 */
681 static int max98095_lineout_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683 {
684 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
685
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 snd_soc_update_bits(codec, w->reg,
689 (1 << (w->shift+2)), (1 << (w->shift+2)));
690 break;
691 case SND_SOC_DAPM_POST_PMD:
692 snd_soc_update_bits(codec, w->reg,
693 (1 << (w->shift+2)), 0);
694 break;
695 default:
696 return -EINVAL;
697 }
698
699 return 0;
700 }
701
702 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = {
703
704 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0),
705 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
706
707 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback",
708 M98095_091_PWR_EN_OUT, 0, 0),
709 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback",
710 M98095_091_PWR_EN_OUT, 1, 0),
711 SND_SOC_DAPM_DAC("DACM2", "Aux Playback",
712 M98095_091_PWR_EN_OUT, 2, 0),
713 SND_SOC_DAPM_DAC("DACM3", "Voice Playback",
714 M98095_091_PWR_EN_OUT, 2, 0),
715
716 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT,
717 6, 0, NULL, 0),
718 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT,
719 7, 0, NULL, 0),
720
721 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT,
722 4, 0, NULL, 0),
723 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT,
724 5, 0, NULL, 0),
725
726 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT,
727 3, 0, NULL, 0),
728
729 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT,
730 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
731 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT,
732 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD),
733
734 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
735 &max98095_extmic_mux),
736
737 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0,
738 &max98095_linein_mux),
739
740 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
741 &max98095_left_hp_mixer_controls[0],
742 ARRAY_SIZE(max98095_left_hp_mixer_controls)),
743
744 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
745 &max98095_right_hp_mixer_controls[0],
746 ARRAY_SIZE(max98095_right_hp_mixer_controls)),
747
748 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
749 &max98095_left_speaker_mixer_controls[0],
750 ARRAY_SIZE(max98095_left_speaker_mixer_controls)),
751
752 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
753 &max98095_right_speaker_mixer_controls[0],
754 ARRAY_SIZE(max98095_right_speaker_mixer_controls)),
755
756 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0,
757 &max98095_mono_rcv_mixer_controls[0],
758 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)),
759
760 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
761 &max98095_left_lineout_mixer_controls[0],
762 ARRAY_SIZE(max98095_left_lineout_mixer_controls)),
763
764 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
765 &max98095_right_lineout_mixer_controls[0],
766 ARRAY_SIZE(max98095_right_lineout_mixer_controls)),
767
768 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
769 &max98095_left_ADC_mixer_controls[0],
770 ARRAY_SIZE(max98095_left_ADC_mixer_controls)),
771
772 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
773 &max98095_right_ADC_mixer_controls[0],
774 ARRAY_SIZE(max98095_right_ADC_mixer_controls)),
775
776 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1,
777 5, 0, NULL, 0, max98095_mic_event,
778 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
779
780 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2,
781 5, 0, NULL, 0, max98095_mic_event,
782 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
783
784 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN,
785 7, 0, NULL, 0, max98095_pga_in1_event,
786 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
787
788 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN,
789 7, 0, NULL, 0, max98095_pga_in2_event,
790 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
791
792 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0),
793 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0),
794
795 SND_SOC_DAPM_OUTPUT("HPL"),
796 SND_SOC_DAPM_OUTPUT("HPR"),
797 SND_SOC_DAPM_OUTPUT("SPKL"),
798 SND_SOC_DAPM_OUTPUT("SPKR"),
799 SND_SOC_DAPM_OUTPUT("RCV"),
800 SND_SOC_DAPM_OUTPUT("OUT1"),
801 SND_SOC_DAPM_OUTPUT("OUT2"),
802 SND_SOC_DAPM_OUTPUT("OUT3"),
803 SND_SOC_DAPM_OUTPUT("OUT4"),
804
805 SND_SOC_DAPM_INPUT("MIC1"),
806 SND_SOC_DAPM_INPUT("MIC2"),
807 SND_SOC_DAPM_INPUT("INA1"),
808 SND_SOC_DAPM_INPUT("INA2"),
809 SND_SOC_DAPM_INPUT("INB1"),
810 SND_SOC_DAPM_INPUT("INB2"),
811 };
812
813 static const struct snd_soc_dapm_route max98095_audio_map[] = {
814 /* Left headphone output mixer */
815 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"},
816 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"},
817 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
818 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
819 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"},
820 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"},
821
822 /* Right headphone output mixer */
823 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"},
824 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"},
825 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
826 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
827 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"},
828 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"},
829
830 /* Left speaker output mixer */
831 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"},
832 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"},
833 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
834 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
835 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
836 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
837 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"},
838 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"},
839
840 /* Right speaker output mixer */
841 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"},
842 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"},
843 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"},
844 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"},
845 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
846 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
847 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"},
848 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"},
849
850 /* Earpiece/Receiver output mixer */
851 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"},
852 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"},
853 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
854 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
855 {"Receiver Mixer", "IN1 Switch", "IN1 Input"},
856 {"Receiver Mixer", "IN2 Switch", "IN2 Input"},
857
858 /* Left Lineout output mixer */
859 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"},
860 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"},
861 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
862 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
863 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"},
864 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"},
865
866 /* Right lineout output mixer */
867 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"},
868 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"},
869 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"},
870 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"},
871 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"},
872 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"},
873
874 {"HP Left Out", NULL, "Left Headphone Mixer"},
875 {"HP Right Out", NULL, "Right Headphone Mixer"},
876 {"SPK Left Out", NULL, "Left Speaker Mixer"},
877 {"SPK Right Out", NULL, "Right Speaker Mixer"},
878 {"RCV Mono Out", NULL, "Receiver Mixer"},
879 {"LINE Left Out", NULL, "Left Lineout Mixer"},
880 {"LINE Right Out", NULL, "Right Lineout Mixer"},
881
882 {"HPL", NULL, "HP Left Out"},
883 {"HPR", NULL, "HP Right Out"},
884 {"SPKL", NULL, "SPK Left Out"},
885 {"SPKR", NULL, "SPK Right Out"},
886 {"RCV", NULL, "RCV Mono Out"},
887 {"OUT1", NULL, "LINE Left Out"},
888 {"OUT2", NULL, "LINE Right Out"},
889 {"OUT3", NULL, "LINE Left Out"},
890 {"OUT4", NULL, "LINE Right Out"},
891
892 /* Left ADC input mixer */
893 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
894 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
895 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"},
896 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"},
897
898 /* Right ADC input mixer */
899 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
900 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
901 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"},
902 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"},
903
904 /* Inputs */
905 {"ADCL", NULL, "Left ADC Mixer"},
906 {"ADCR", NULL, "Right ADC Mixer"},
907
908 {"IN1 Input", NULL, "INA1"},
909 {"IN2 Input", NULL, "INA2"},
910
911 {"MIC1 Input", NULL, "MIC1"},
912 {"MIC2 Input", NULL, "MIC2"},
913 };
914
915 /* codec mclk clock divider coefficients */
916 static const struct {
917 u32 rate;
918 u8 sr;
919 } rate_table[] = {
920 {8000, 0x01},
921 {11025, 0x02},
922 {16000, 0x03},
923 {22050, 0x04},
924 {24000, 0x05},
925 {32000, 0x06},
926 {44100, 0x07},
927 {48000, 0x08},
928 {88200, 0x09},
929 {96000, 0x0A},
930 };
931
932 static int rate_value(int rate, u8 *value)
933 {
934 int i;
935
936 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
937 if (rate_table[i].rate >= rate) {
938 *value = rate_table[i].sr;
939 return 0;
940 }
941 }
942 *value = rate_table[0].sr;
943 return -EINVAL;
944 }
945
946 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream,
947 struct snd_pcm_hw_params *params,
948 struct snd_soc_dai *dai)
949 {
950 struct snd_soc_codec *codec = dai->codec;
951 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
952 struct max98095_cdata *cdata;
953 unsigned long long ni;
954 unsigned int rate;
955 u8 regval;
956
957 cdata = &max98095->dai[0];
958
959 rate = params_rate(params);
960
961 switch (params_width(params)) {
962 case 16:
963 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
964 M98095_DAI_WS, 0);
965 break;
966 case 24:
967 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
968 M98095_DAI_WS, M98095_DAI_WS);
969 break;
970 default:
971 return -EINVAL;
972 }
973
974 if (rate_value(rate, &regval))
975 return -EINVAL;
976
977 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE,
978 M98095_CLKMODE_MASK, regval);
979 cdata->rate = rate;
980
981 /* Configure NI when operating as master */
982 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
983 if (max98095->sysclk == 0) {
984 dev_err(codec->dev, "Invalid system clock frequency\n");
985 return -EINVAL;
986 }
987 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
988 * (unsigned long long int)rate;
989 do_div(ni, (unsigned long long int)max98095->sysclk);
990 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
991 (ni >> 8) & 0x7F);
992 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
993 ni & 0xFF);
994 }
995
996 /* Update sample rate mode */
997 if (rate < 50000)
998 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
999 M98095_DAI_DHF, 0);
1000 else
1001 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS,
1002 M98095_DAI_DHF, M98095_DAI_DHF);
1003
1004 return 0;
1005 }
1006
1007 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream,
1008 struct snd_pcm_hw_params *params,
1009 struct snd_soc_dai *dai)
1010 {
1011 struct snd_soc_codec *codec = dai->codec;
1012 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1013 struct max98095_cdata *cdata;
1014 unsigned long long ni;
1015 unsigned int rate;
1016 u8 regval;
1017
1018 cdata = &max98095->dai[1];
1019
1020 rate = params_rate(params);
1021
1022 switch (params_width(params)) {
1023 case 16:
1024 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1025 M98095_DAI_WS, 0);
1026 break;
1027 case 24:
1028 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1029 M98095_DAI_WS, M98095_DAI_WS);
1030 break;
1031 default:
1032 return -EINVAL;
1033 }
1034
1035 if (rate_value(rate, &regval))
1036 return -EINVAL;
1037
1038 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE,
1039 M98095_CLKMODE_MASK, regval);
1040 cdata->rate = rate;
1041
1042 /* Configure NI when operating as master */
1043 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1044 if (max98095->sysclk == 0) {
1045 dev_err(codec->dev, "Invalid system clock frequency\n");
1046 return -EINVAL;
1047 }
1048 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1049 * (unsigned long long int)rate;
1050 do_div(ni, (unsigned long long int)max98095->sysclk);
1051 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1052 (ni >> 8) & 0x7F);
1053 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1054 ni & 0xFF);
1055 }
1056
1057 /* Update sample rate mode */
1058 if (rate < 50000)
1059 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1060 M98095_DAI_DHF, 0);
1061 else
1062 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS,
1063 M98095_DAI_DHF, M98095_DAI_DHF);
1064
1065 return 0;
1066 }
1067
1068 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream,
1069 struct snd_pcm_hw_params *params,
1070 struct snd_soc_dai *dai)
1071 {
1072 struct snd_soc_codec *codec = dai->codec;
1073 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1074 struct max98095_cdata *cdata;
1075 unsigned long long ni;
1076 unsigned int rate;
1077 u8 regval;
1078
1079 cdata = &max98095->dai[2];
1080
1081 rate = params_rate(params);
1082
1083 switch (params_width(params)) {
1084 case 16:
1085 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1086 M98095_DAI_WS, 0);
1087 break;
1088 case 24:
1089 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1090 M98095_DAI_WS, M98095_DAI_WS);
1091 break;
1092 default:
1093 return -EINVAL;
1094 }
1095
1096 if (rate_value(rate, &regval))
1097 return -EINVAL;
1098
1099 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE,
1100 M98095_CLKMODE_MASK, regval);
1101 cdata->rate = rate;
1102
1103 /* Configure NI when operating as master */
1104 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1105 if (max98095->sysclk == 0) {
1106 dev_err(codec->dev, "Invalid system clock frequency\n");
1107 return -EINVAL;
1108 }
1109 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1110 * (unsigned long long int)rate;
1111 do_div(ni, (unsigned long long int)max98095->sysclk);
1112 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1113 (ni >> 8) & 0x7F);
1114 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1115 ni & 0xFF);
1116 }
1117
1118 /* Update sample rate mode */
1119 if (rate < 50000)
1120 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1121 M98095_DAI_DHF, 0);
1122 else
1123 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS,
1124 M98095_DAI_DHF, M98095_DAI_DHF);
1125
1126 return 0;
1127 }
1128
1129 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1130 int clk_id, unsigned int freq, int dir)
1131 {
1132 struct snd_soc_codec *codec = dai->codec;
1133 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1134
1135 /* Requested clock frequency is already setup */
1136 if (freq == max98095->sysclk)
1137 return 0;
1138
1139 if (!IS_ERR(max98095->mclk)) {
1140 freq = clk_round_rate(max98095->mclk, freq);
1141 clk_set_rate(max98095->mclk, freq);
1142 }
1143
1144 /* Setup clocks for slave mode, and using the PLL
1145 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1146 * 0x02 (when master clk is 20MHz to 40MHz)..
1147 * 0x03 (when master clk is 40MHz to 60MHz)..
1148 */
1149 if ((freq >= 10000000) && (freq < 20000000)) {
1150 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10);
1151 } else if ((freq >= 20000000) && (freq < 40000000)) {
1152 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20);
1153 } else if ((freq >= 40000000) && (freq < 60000000)) {
1154 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30);
1155 } else {
1156 dev_err(codec->dev, "Invalid master clock frequency\n");
1157 return -EINVAL;
1158 }
1159
1160 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1161
1162 max98095->sysclk = freq;
1163 return 0;
1164 }
1165
1166 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1167 unsigned int fmt)
1168 {
1169 struct snd_soc_codec *codec = codec_dai->codec;
1170 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1171 struct max98095_cdata *cdata;
1172 u8 regval = 0;
1173
1174 cdata = &max98095->dai[0];
1175
1176 if (fmt != cdata->fmt) {
1177 cdata->fmt = fmt;
1178
1179 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1180 case SND_SOC_DAIFMT_CBS_CFS:
1181 /* Slave mode PLL */
1182 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI,
1183 0x80);
1184 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO,
1185 0x00);
1186 break;
1187 case SND_SOC_DAIFMT_CBM_CFM:
1188 /* Set to master mode */
1189 regval |= M98095_DAI_MAS;
1190 break;
1191 case SND_SOC_DAIFMT_CBS_CFM:
1192 case SND_SOC_DAIFMT_CBM_CFS:
1193 default:
1194 dev_err(codec->dev, "Clock mode unsupported");
1195 return -EINVAL;
1196 }
1197
1198 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1199 case SND_SOC_DAIFMT_I2S:
1200 regval |= M98095_DAI_DLY;
1201 break;
1202 case SND_SOC_DAIFMT_LEFT_J:
1203 break;
1204 default:
1205 return -EINVAL;
1206 }
1207
1208 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1209 case SND_SOC_DAIFMT_NB_NF:
1210 break;
1211 case SND_SOC_DAIFMT_NB_IF:
1212 regval |= M98095_DAI_WCI;
1213 break;
1214 case SND_SOC_DAIFMT_IB_NF:
1215 regval |= M98095_DAI_BCI;
1216 break;
1217 case SND_SOC_DAIFMT_IB_IF:
1218 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1219 break;
1220 default:
1221 return -EINVAL;
1222 }
1223
1224 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT,
1225 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1226 M98095_DAI_WCI, regval);
1227
1228 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64);
1229 }
1230
1231 return 0;
1232 }
1233
1234 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1235 unsigned int fmt)
1236 {
1237 struct snd_soc_codec *codec = codec_dai->codec;
1238 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1239 struct max98095_cdata *cdata;
1240 u8 regval = 0;
1241
1242 cdata = &max98095->dai[1];
1243
1244 if (fmt != cdata->fmt) {
1245 cdata->fmt = fmt;
1246
1247 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1248 case SND_SOC_DAIFMT_CBS_CFS:
1249 /* Slave mode PLL */
1250 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI,
1251 0x80);
1252 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO,
1253 0x00);
1254 break;
1255 case SND_SOC_DAIFMT_CBM_CFM:
1256 /* Set to master mode */
1257 regval |= M98095_DAI_MAS;
1258 break;
1259 case SND_SOC_DAIFMT_CBS_CFM:
1260 case SND_SOC_DAIFMT_CBM_CFS:
1261 default:
1262 dev_err(codec->dev, "Clock mode unsupported");
1263 return -EINVAL;
1264 }
1265
1266 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1267 case SND_SOC_DAIFMT_I2S:
1268 regval |= M98095_DAI_DLY;
1269 break;
1270 case SND_SOC_DAIFMT_LEFT_J:
1271 break;
1272 default:
1273 return -EINVAL;
1274 }
1275
1276 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1277 case SND_SOC_DAIFMT_NB_NF:
1278 break;
1279 case SND_SOC_DAIFMT_NB_IF:
1280 regval |= M98095_DAI_WCI;
1281 break;
1282 case SND_SOC_DAIFMT_IB_NF:
1283 regval |= M98095_DAI_BCI;
1284 break;
1285 case SND_SOC_DAIFMT_IB_IF:
1286 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1287 break;
1288 default:
1289 return -EINVAL;
1290 }
1291
1292 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT,
1293 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1294 M98095_DAI_WCI, regval);
1295
1296 snd_soc_write(codec, M98095_035_DAI2_CLOCK,
1297 M98095_DAI_BSEL64);
1298 }
1299
1300 return 0;
1301 }
1302
1303 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1304 unsigned int fmt)
1305 {
1306 struct snd_soc_codec *codec = codec_dai->codec;
1307 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1308 struct max98095_cdata *cdata;
1309 u8 regval = 0;
1310
1311 cdata = &max98095->dai[2];
1312
1313 if (fmt != cdata->fmt) {
1314 cdata->fmt = fmt;
1315
1316 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1317 case SND_SOC_DAIFMT_CBS_CFS:
1318 /* Slave mode PLL */
1319 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI,
1320 0x80);
1321 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO,
1322 0x00);
1323 break;
1324 case SND_SOC_DAIFMT_CBM_CFM:
1325 /* Set to master mode */
1326 regval |= M98095_DAI_MAS;
1327 break;
1328 case SND_SOC_DAIFMT_CBS_CFM:
1329 case SND_SOC_DAIFMT_CBM_CFS:
1330 default:
1331 dev_err(codec->dev, "Clock mode unsupported");
1332 return -EINVAL;
1333 }
1334
1335 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1336 case SND_SOC_DAIFMT_I2S:
1337 regval |= M98095_DAI_DLY;
1338 break;
1339 case SND_SOC_DAIFMT_LEFT_J:
1340 break;
1341 default:
1342 return -EINVAL;
1343 }
1344
1345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1346 case SND_SOC_DAIFMT_NB_NF:
1347 break;
1348 case SND_SOC_DAIFMT_NB_IF:
1349 regval |= M98095_DAI_WCI;
1350 break;
1351 case SND_SOC_DAIFMT_IB_NF:
1352 regval |= M98095_DAI_BCI;
1353 break;
1354 case SND_SOC_DAIFMT_IB_IF:
1355 regval |= M98095_DAI_BCI|M98095_DAI_WCI;
1356 break;
1357 default:
1358 return -EINVAL;
1359 }
1360
1361 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT,
1362 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
1363 M98095_DAI_WCI, regval);
1364
1365 snd_soc_write(codec, M98095_03F_DAI3_CLOCK,
1366 M98095_DAI_BSEL64);
1367 }
1368
1369 return 0;
1370 }
1371
1372 static int max98095_set_bias_level(struct snd_soc_codec *codec,
1373 enum snd_soc_bias_level level)
1374 {
1375 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1376 int ret;
1377
1378 switch (level) {
1379 case SND_SOC_BIAS_ON:
1380 break;
1381
1382 case SND_SOC_BIAS_PREPARE:
1383 /*
1384 * SND_SOC_BIAS_PREPARE is called while preparing for a
1385 * transition to ON or away from ON. If current bias_level
1386 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1387 * away from ON. Disable the clock in that case, otherwise
1388 * enable it.
1389 */
1390 if (IS_ERR(max98095->mclk))
1391 break;
1392
1393 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
1394 clk_disable_unprepare(max98095->mclk);
1395 } else {
1396 ret = clk_prepare_enable(max98095->mclk);
1397 if (ret)
1398 return ret;
1399 }
1400 break;
1401
1402 case SND_SOC_BIAS_STANDBY:
1403 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1404 ret = regcache_sync(max98095->regmap);
1405
1406 if (ret != 0) {
1407 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1408 return ret;
1409 }
1410 }
1411
1412 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1413 M98095_MBEN, M98095_MBEN);
1414 break;
1415
1416 case SND_SOC_BIAS_OFF:
1417 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1418 M98095_MBEN, 0);
1419 regcache_mark_dirty(max98095->regmap);
1420 break;
1421 }
1422 return 0;
1423 }
1424
1425 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000
1426 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1427
1428 static const struct snd_soc_dai_ops max98095_dai1_ops = {
1429 .set_sysclk = max98095_dai_set_sysclk,
1430 .set_fmt = max98095_dai1_set_fmt,
1431 .hw_params = max98095_dai1_hw_params,
1432 };
1433
1434 static const struct snd_soc_dai_ops max98095_dai2_ops = {
1435 .set_sysclk = max98095_dai_set_sysclk,
1436 .set_fmt = max98095_dai2_set_fmt,
1437 .hw_params = max98095_dai2_hw_params,
1438 };
1439
1440 static const struct snd_soc_dai_ops max98095_dai3_ops = {
1441 .set_sysclk = max98095_dai_set_sysclk,
1442 .set_fmt = max98095_dai3_set_fmt,
1443 .hw_params = max98095_dai3_hw_params,
1444 };
1445
1446 static struct snd_soc_dai_driver max98095_dai[] = {
1447 {
1448 .name = "HiFi",
1449 .playback = {
1450 .stream_name = "HiFi Playback",
1451 .channels_min = 1,
1452 .channels_max = 2,
1453 .rates = MAX98095_RATES,
1454 .formats = MAX98095_FORMATS,
1455 },
1456 .capture = {
1457 .stream_name = "HiFi Capture",
1458 .channels_min = 1,
1459 .channels_max = 2,
1460 .rates = MAX98095_RATES,
1461 .formats = MAX98095_FORMATS,
1462 },
1463 .ops = &max98095_dai1_ops,
1464 },
1465 {
1466 .name = "Aux",
1467 .playback = {
1468 .stream_name = "Aux Playback",
1469 .channels_min = 1,
1470 .channels_max = 1,
1471 .rates = MAX98095_RATES,
1472 .formats = MAX98095_FORMATS,
1473 },
1474 .ops = &max98095_dai2_ops,
1475 },
1476 {
1477 .name = "Voice",
1478 .playback = {
1479 .stream_name = "Voice Playback",
1480 .channels_min = 1,
1481 .channels_max = 1,
1482 .rates = MAX98095_RATES,
1483 .formats = MAX98095_FORMATS,
1484 },
1485 .ops = &max98095_dai3_ops,
1486 }
1487
1488 };
1489
1490 static int max98095_get_eq_channel(const char *name)
1491 {
1492 if (strcmp(name, "EQ1 Mode") == 0)
1493 return 0;
1494 if (strcmp(name, "EQ2 Mode") == 0)
1495 return 1;
1496 return -EINVAL;
1497 }
1498
1499 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1500 struct snd_ctl_elem_value *ucontrol)
1501 {
1502 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1503 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1504 struct max98095_pdata *pdata = max98095->pdata;
1505 int channel = max98095_get_eq_channel(kcontrol->id.name);
1506 struct max98095_cdata *cdata;
1507 unsigned int sel = ucontrol->value.integer.value[0];
1508 struct max98095_eq_cfg *coef_set;
1509 int fs, best, best_val, i;
1510 int regmask, regsave;
1511
1512 if (WARN_ON(channel > 1))
1513 return -EINVAL;
1514
1515 if (!pdata || !max98095->eq_textcnt)
1516 return 0;
1517
1518 if (sel >= pdata->eq_cfgcnt)
1519 return -EINVAL;
1520
1521 cdata = &max98095->dai[channel];
1522 cdata->eq_sel = sel;
1523 fs = cdata->rate;
1524
1525 /* Find the selected configuration with nearest sample rate */
1526 best = 0;
1527 best_val = INT_MAX;
1528 for (i = 0; i < pdata->eq_cfgcnt; i++) {
1529 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 &&
1530 abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1531 best = i;
1532 best_val = abs(pdata->eq_cfg[i].rate - fs);
1533 }
1534 }
1535
1536 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1537 pdata->eq_cfg[best].name,
1538 pdata->eq_cfg[best].rate, fs);
1539
1540 coef_set = &pdata->eq_cfg[best];
1541
1542 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
1543
1544 /* Disable filter while configuring, and save current on/off state */
1545 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1546 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1547
1548 mutex_lock(&max98095->lock);
1549 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1550 m98095_eq_band(codec, channel, 0, coef_set->band1);
1551 m98095_eq_band(codec, channel, 1, coef_set->band2);
1552 m98095_eq_band(codec, channel, 2, coef_set->band3);
1553 m98095_eq_band(codec, channel, 3, coef_set->band4);
1554 m98095_eq_band(codec, channel, 4, coef_set->band5);
1555 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1556 mutex_unlock(&max98095->lock);
1557
1558 /* Restore the original on/off state */
1559 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1560 return 0;
1561 }
1562
1563 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol)
1565 {
1566 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1567 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1568 int channel = max98095_get_eq_channel(kcontrol->id.name);
1569 struct max98095_cdata *cdata;
1570
1571 cdata = &max98095->dai[channel];
1572 ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1573
1574 return 0;
1575 }
1576
1577 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec)
1578 {
1579 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1580 struct max98095_pdata *pdata = max98095->pdata;
1581 struct max98095_eq_cfg *cfg;
1582 unsigned int cfgcnt;
1583 int i, j;
1584 const char **t;
1585 int ret;
1586
1587 struct snd_kcontrol_new controls[] = {
1588 SOC_ENUM_EXT("EQ1 Mode",
1589 max98095->eq_enum,
1590 max98095_get_eq_enum,
1591 max98095_put_eq_enum),
1592 SOC_ENUM_EXT("EQ2 Mode",
1593 max98095->eq_enum,
1594 max98095_get_eq_enum,
1595 max98095_put_eq_enum),
1596 };
1597
1598 cfg = pdata->eq_cfg;
1599 cfgcnt = pdata->eq_cfgcnt;
1600
1601 /* Setup an array of texts for the equalizer enum.
1602 * This is based on Mark Brown's equalizer driver code.
1603 */
1604 max98095->eq_textcnt = 0;
1605 max98095->eq_texts = NULL;
1606 for (i = 0; i < cfgcnt; i++) {
1607 for (j = 0; j < max98095->eq_textcnt; j++) {
1608 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0)
1609 break;
1610 }
1611
1612 if (j != max98095->eq_textcnt)
1613 continue;
1614
1615 /* Expand the array */
1616 t = krealloc(max98095->eq_texts,
1617 sizeof(char *) * (max98095->eq_textcnt + 1),
1618 GFP_KERNEL);
1619 if (t == NULL)
1620 continue;
1621
1622 /* Store the new entry */
1623 t[max98095->eq_textcnt] = cfg[i].name;
1624 max98095->eq_textcnt++;
1625 max98095->eq_texts = t;
1626 }
1627
1628 /* Now point the soc_enum to .texts array items */
1629 max98095->eq_enum.texts = max98095->eq_texts;
1630 max98095->eq_enum.items = max98095->eq_textcnt;
1631
1632 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
1633 if (ret != 0)
1634 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret);
1635 }
1636
1637 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"};
1638
1639 static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1640 const char *name)
1641 {
1642 int i;
1643
1644 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++)
1645 if (strcmp(name, bq_mode_name[i]) == 0)
1646 return i;
1647
1648 /* Shouldn't happen */
1649 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name);
1650 return -EINVAL;
1651 }
1652
1653 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1654 struct snd_ctl_elem_value *ucontrol)
1655 {
1656 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1657 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1658 struct max98095_pdata *pdata = max98095->pdata;
1659 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
1660 struct max98095_cdata *cdata;
1661 unsigned int sel = ucontrol->value.integer.value[0];
1662 struct max98095_biquad_cfg *coef_set;
1663 int fs, best, best_val, i;
1664 int regmask, regsave;
1665
1666 if (channel < 0)
1667 return channel;
1668
1669 if (!pdata || !max98095->bq_textcnt)
1670 return 0;
1671
1672 if (sel >= pdata->bq_cfgcnt)
1673 return -EINVAL;
1674
1675 cdata = &max98095->dai[channel];
1676 cdata->bq_sel = sel;
1677 fs = cdata->rate;
1678
1679 /* Find the selected configuration with nearest sample rate */
1680 best = 0;
1681 best_val = INT_MAX;
1682 for (i = 0; i < pdata->bq_cfgcnt; i++) {
1683 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 &&
1684 abs(pdata->bq_cfg[i].rate - fs) < best_val) {
1685 best = i;
1686 best_val = abs(pdata->bq_cfg[i].rate - fs);
1687 }
1688 }
1689
1690 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n",
1691 pdata->bq_cfg[best].name,
1692 pdata->bq_cfg[best].rate, fs);
1693
1694 coef_set = &pdata->bq_cfg[best];
1695
1696 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
1697
1698 /* Disable filter while configuring, and save current on/off state */
1699 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL);
1700 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0);
1701
1702 mutex_lock(&max98095->lock);
1703 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG);
1704 m98095_biquad_band(codec, channel, 0, coef_set->band1);
1705 m98095_biquad_band(codec, channel, 1, coef_set->band2);
1706 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0);
1707 mutex_unlock(&max98095->lock);
1708
1709 /* Restore the original on/off state */
1710 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave);
1711 return 0;
1712 }
1713
1714 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1715 struct snd_ctl_elem_value *ucontrol)
1716 {
1717 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1718 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1719 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
1720 struct max98095_cdata *cdata;
1721
1722 if (channel < 0)
1723 return channel;
1724
1725 cdata = &max98095->dai[channel];
1726 ucontrol->value.enumerated.item[0] = cdata->bq_sel;
1727
1728 return 0;
1729 }
1730
1731 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec)
1732 {
1733 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1734 struct max98095_pdata *pdata = max98095->pdata;
1735 struct max98095_biquad_cfg *cfg;
1736 unsigned int cfgcnt;
1737 int i, j;
1738 const char **t;
1739 int ret;
1740
1741 struct snd_kcontrol_new controls[] = {
1742 SOC_ENUM_EXT((char *)bq_mode_name[0],
1743 max98095->bq_enum,
1744 max98095_get_bq_enum,
1745 max98095_put_bq_enum),
1746 SOC_ENUM_EXT((char *)bq_mode_name[1],
1747 max98095->bq_enum,
1748 max98095_get_bq_enum,
1749 max98095_put_bq_enum),
1750 };
1751 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name));
1752
1753 cfg = pdata->bq_cfg;
1754 cfgcnt = pdata->bq_cfgcnt;
1755
1756 /* Setup an array of texts for the biquad enum.
1757 * This is based on Mark Brown's equalizer driver code.
1758 */
1759 max98095->bq_textcnt = 0;
1760 max98095->bq_texts = NULL;
1761 for (i = 0; i < cfgcnt; i++) {
1762 for (j = 0; j < max98095->bq_textcnt; j++) {
1763 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0)
1764 break;
1765 }
1766
1767 if (j != max98095->bq_textcnt)
1768 continue;
1769
1770 /* Expand the array */
1771 t = krealloc(max98095->bq_texts,
1772 sizeof(char *) * (max98095->bq_textcnt + 1),
1773 GFP_KERNEL);
1774 if (t == NULL)
1775 continue;
1776
1777 /* Store the new entry */
1778 t[max98095->bq_textcnt] = cfg[i].name;
1779 max98095->bq_textcnt++;
1780 max98095->bq_texts = t;
1781 }
1782
1783 /* Now point the soc_enum to .texts array items */
1784 max98095->bq_enum.texts = max98095->bq_texts;
1785 max98095->bq_enum.items = max98095->bq_textcnt;
1786
1787 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
1788 if (ret != 0)
1789 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret);
1790 }
1791
1792 static void max98095_handle_pdata(struct snd_soc_codec *codec)
1793 {
1794 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1795 struct max98095_pdata *pdata = max98095->pdata;
1796 u8 regval = 0;
1797
1798 if (!pdata) {
1799 dev_dbg(codec->dev, "No platform data\n");
1800 return;
1801 }
1802
1803 /* Configure mic for analog/digital mic mode */
1804 if (pdata->digmic_left_mode)
1805 regval |= M98095_DIGMIC_L;
1806
1807 if (pdata->digmic_right_mode)
1808 regval |= M98095_DIGMIC_R;
1809
1810 snd_soc_write(codec, M98095_087_CFG_MIC, regval);
1811
1812 /* Configure equalizers */
1813 if (pdata->eq_cfgcnt)
1814 max98095_handle_eq_pdata(codec);
1815
1816 /* Configure bi-quad filters */
1817 if (pdata->bq_cfgcnt)
1818 max98095_handle_bq_pdata(codec);
1819 }
1820
1821 static irqreturn_t max98095_report_jack(int irq, void *data)
1822 {
1823 struct snd_soc_codec *codec = data;
1824 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1825 unsigned int value;
1826 int hp_report = 0;
1827 int mic_report = 0;
1828
1829 /* Read the Jack Status Register */
1830 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
1831
1832 /* If ddone is not set, then detection isn't finished yet */
1833 if ((value & M98095_DDONE) == 0)
1834 return IRQ_NONE;
1835
1836 /* if hp, check its bit, and if set, clear it */
1837 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
1838 max98095->headphone_jack)
1839 hp_report |= SND_JACK_HEADPHONE;
1840
1841 /* if mic, check its bit, and if set, clear it */
1842 if ((value & M98095_MIC_IN) && max98095->mic_jack)
1843 mic_report |= SND_JACK_MICROPHONE;
1844
1845 if (max98095->headphone_jack == max98095->mic_jack) {
1846 snd_soc_jack_report(max98095->headphone_jack,
1847 hp_report | mic_report,
1848 SND_JACK_HEADSET);
1849 } else {
1850 if (max98095->headphone_jack)
1851 snd_soc_jack_report(max98095->headphone_jack,
1852 hp_report, SND_JACK_HEADPHONE);
1853 if (max98095->mic_jack)
1854 snd_soc_jack_report(max98095->mic_jack,
1855 mic_report, SND_JACK_MICROPHONE);
1856 }
1857
1858 return IRQ_HANDLED;
1859 }
1860
1861 static int max98095_jack_detect_enable(struct snd_soc_codec *codec)
1862 {
1863 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1864 int ret = 0;
1865 int detect_enable = M98095_JDEN;
1866 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
1867
1868 if (max98095->pdata->jack_detect_pin5en)
1869 detect_enable |= M98095_PIN5EN;
1870
1871 if (max98095->pdata->jack_detect_delay)
1872 slew = max98095->pdata->jack_detect_delay;
1873
1874 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
1875 if (ret < 0) {
1876 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
1877 return ret;
1878 }
1879
1880 /* configure auto detection to be enabled */
1881 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
1882 if (ret < 0) {
1883 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
1884 return ret;
1885 }
1886
1887 return ret;
1888 }
1889
1890 static int max98095_jack_detect_disable(struct snd_soc_codec *codec)
1891 {
1892 int ret = 0;
1893
1894 /* configure auto detection to be disabled */
1895 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
1896 if (ret < 0) {
1897 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
1898 return ret;
1899 }
1900
1901 return ret;
1902 }
1903
1904 int max98095_jack_detect(struct snd_soc_codec *codec,
1905 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
1906 {
1907 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1908 struct i2c_client *client = to_i2c_client(codec->dev);
1909 int ret = 0;
1910
1911 max98095->headphone_jack = hp_jack;
1912 max98095->mic_jack = mic_jack;
1913
1914 /* only progress if we have at least 1 jack pointer */
1915 if (!hp_jack && !mic_jack)
1916 return -EINVAL;
1917
1918 max98095_jack_detect_enable(codec);
1919
1920 /* enable interrupts for headphone jack detection */
1921 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
1922 M98095_IDDONE, M98095_IDDONE);
1923 if (ret < 0) {
1924 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
1925 return ret;
1926 }
1927
1928 max98095_report_jack(client->irq, codec);
1929 return 0;
1930 }
1931 EXPORT_SYMBOL_GPL(max98095_jack_detect);
1932
1933 #ifdef CONFIG_PM
1934 static int max98095_suspend(struct snd_soc_codec *codec)
1935 {
1936 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1937
1938 if (max98095->headphone_jack || max98095->mic_jack)
1939 max98095_jack_detect_disable(codec);
1940
1941 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1942
1943 return 0;
1944 }
1945
1946 static int max98095_resume(struct snd_soc_codec *codec)
1947 {
1948 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1949 struct i2c_client *client = to_i2c_client(codec->dev);
1950
1951 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
1952
1953 if (max98095->headphone_jack || max98095->mic_jack) {
1954 max98095_jack_detect_enable(codec);
1955 max98095_report_jack(client->irq, codec);
1956 }
1957
1958 return 0;
1959 }
1960 #else
1961 #define max98095_suspend NULL
1962 #define max98095_resume NULL
1963 #endif
1964
1965 static int max98095_reset(struct snd_soc_codec *codec)
1966 {
1967 int i, ret;
1968
1969 /* Gracefully reset the DSP core and the codec hardware
1970 * in a proper sequence */
1971 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0);
1972 if (ret < 0) {
1973 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret);
1974 return ret;
1975 }
1976
1977 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0);
1978 if (ret < 0) {
1979 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
1980 return ret;
1981 }
1982
1983 /* Reset to hardware default for registers, as there is not
1984 * a soft reset hardware control register */
1985 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1986 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
1987 if (ret < 0) {
1988 dev_err(codec->dev, "Failed to reset: %d\n", ret);
1989 return ret;
1990 }
1991 }
1992
1993 return ret;
1994 }
1995
1996 static int max98095_probe(struct snd_soc_codec *codec)
1997 {
1998 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1999 struct max98095_cdata *cdata;
2000 struct i2c_client *client;
2001 int ret = 0;
2002
2003 max98095->mclk = devm_clk_get(codec->dev, "mclk");
2004 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
2005 return -EPROBE_DEFER;
2006
2007 /* reset the codec, the DSP core, and disable all interrupts */
2008 max98095_reset(codec);
2009
2010 client = to_i2c_client(codec->dev);
2011
2012 /* initialize private data */
2013
2014 max98095->sysclk = (unsigned)-1;
2015 max98095->eq_textcnt = 0;
2016 max98095->bq_textcnt = 0;
2017
2018 cdata = &max98095->dai[0];
2019 cdata->rate = (unsigned)-1;
2020 cdata->fmt = (unsigned)-1;
2021 cdata->eq_sel = 0;
2022 cdata->bq_sel = 0;
2023
2024 cdata = &max98095->dai[1];
2025 cdata->rate = (unsigned)-1;
2026 cdata->fmt = (unsigned)-1;
2027 cdata->eq_sel = 0;
2028 cdata->bq_sel = 0;
2029
2030 cdata = &max98095->dai[2];
2031 cdata->rate = (unsigned)-1;
2032 cdata->fmt = (unsigned)-1;
2033 cdata->eq_sel = 0;
2034 cdata->bq_sel = 0;
2035
2036 max98095->lin_state = 0;
2037 max98095->mic1pre = 0;
2038 max98095->mic2pre = 0;
2039
2040 if (client->irq) {
2041 /* register an audio interrupt */
2042 ret = request_threaded_irq(client->irq, NULL,
2043 max98095_report_jack,
2044 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
2045 IRQF_ONESHOT, "max98095", codec);
2046 if (ret) {
2047 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2048 goto err_access;
2049 }
2050 }
2051
2052 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2053 if (ret < 0) {
2054 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
2055 ret);
2056 goto err_irq;
2057 }
2058 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2059
2060 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV);
2061
2062 snd_soc_write(codec, M98095_048_MIX_DAC_LR,
2063 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR);
2064
2065 snd_soc_write(codec, M98095_049_MIX_DAC_M,
2066 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM);
2067
2068 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM);
2069 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL);
2070 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL);
2071
2072 snd_soc_write(codec, M98095_02C_DAI1_IOCFG,
2073 M98095_S1NORMAL|M98095_SDATA);
2074
2075 snd_soc_write(codec, M98095_036_DAI2_IOCFG,
2076 M98095_S2NORMAL|M98095_SDATA);
2077
2078 snd_soc_write(codec, M98095_040_DAI3_IOCFG,
2079 M98095_S3NORMAL|M98095_SDATA);
2080
2081 max98095_handle_pdata(codec);
2082
2083 /* take the codec out of the shut down */
2084 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2085 M98095_SHDNRUN);
2086
2087 return 0;
2088
2089 err_irq:
2090 if (client->irq)
2091 free_irq(client->irq, codec);
2092 err_access:
2093 return ret;
2094 }
2095
2096 static int max98095_remove(struct snd_soc_codec *codec)
2097 {
2098 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2099 struct i2c_client *client = to_i2c_client(codec->dev);
2100
2101 if (max98095->headphone_jack || max98095->mic_jack)
2102 max98095_jack_detect_disable(codec);
2103
2104 if (client->irq)
2105 free_irq(client->irq, codec);
2106
2107 return 0;
2108 }
2109
2110 static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2111 .probe = max98095_probe,
2112 .remove = max98095_remove,
2113 .suspend = max98095_suspend,
2114 .resume = max98095_resume,
2115 .set_bias_level = max98095_set_bias_level,
2116 .controls = max98095_snd_controls,
2117 .num_controls = ARRAY_SIZE(max98095_snd_controls),
2118 .dapm_widgets = max98095_dapm_widgets,
2119 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2120 .dapm_routes = max98095_audio_map,
2121 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map),
2122 };
2123
2124 static int max98095_i2c_probe(struct i2c_client *i2c,
2125 const struct i2c_device_id *id)
2126 {
2127 struct max98095_priv *max98095;
2128 int ret;
2129
2130 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv),
2131 GFP_KERNEL);
2132 if (max98095 == NULL)
2133 return -ENOMEM;
2134
2135 mutex_init(&max98095->lock);
2136
2137 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2138 if (IS_ERR(max98095->regmap)) {
2139 ret = PTR_ERR(max98095->regmap);
2140 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2141 return ret;
2142 }
2143
2144 max98095->devtype = id->driver_data;
2145 i2c_set_clientdata(i2c, max98095);
2146 max98095->pdata = i2c->dev.platform_data;
2147
2148 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095,
2149 max98095_dai, ARRAY_SIZE(max98095_dai));
2150 return ret;
2151 }
2152
2153 static int max98095_i2c_remove(struct i2c_client *client)
2154 {
2155 snd_soc_unregister_codec(&client->dev);
2156 return 0;
2157 }
2158
2159 static const struct i2c_device_id max98095_i2c_id[] = {
2160 { "max98095", MAX98095 },
2161 { }
2162 };
2163 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2164
2165 static const struct of_device_id max98095_of_match[] = {
2166 { .compatible = "maxim,max98095", },
2167 { }
2168 };
2169 MODULE_DEVICE_TABLE(of, max98095_of_match);
2170
2171 static struct i2c_driver max98095_i2c_driver = {
2172 .driver = {
2173 .name = "max98095",
2174 .of_match_table = of_match_ptr(max98095_of_match),
2175 },
2176 .probe = max98095_i2c_probe,
2177 .remove = max98095_i2c_remove,
2178 .id_table = max98095_i2c_id,
2179 };
2180
2181 module_i2c_driver(max98095_i2c_driver);
2182
2183 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver");
2184 MODULE_AUTHOR("Peter Hsiang");
2185 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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