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ASoC: nau8825: mark pm functions __maybe_unused
[deliverable/linux.git] / sound / soc / codecs / nau8825.c
1 /*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/acpi.h>
20 #include <linux/math64.h>
21 #include <linux/semaphore.h>
22
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30
31
32 #include "nau8825.h"
33
34
35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
36
37 #define NAU_FREF_MAX 13500000
38 #define NAU_FVCO_MAX 124000000
39 #define NAU_FVCO_MIN 90000000
40
41 /* cross talk suppression detection */
42 #define LOG10_MAGIC 646456993
43 #define GAIN_AUGMENT 22500
44 #define SIDETONE_BASE 207000
45
46
47 static int nau8825_configure_sysclk(struct nau8825 *nau8825,
48 int clk_id, unsigned int freq);
49
50 struct nau8825_fll {
51 int mclk_src;
52 int ratio;
53 int fll_frac;
54 int fll_int;
55 int clk_ref_div;
56 };
57
58 struct nau8825_fll_attr {
59 unsigned int param;
60 unsigned int val;
61 };
62
63 /* scaling for mclk from sysclk_src output */
64 static const struct nau8825_fll_attr mclk_src_scaling[] = {
65 { 1, 0x0 },
66 { 2, 0x2 },
67 { 4, 0x3 },
68 { 8, 0x4 },
69 { 16, 0x5 },
70 { 32, 0x6 },
71 { 3, 0x7 },
72 { 6, 0xa },
73 { 12, 0xb },
74 { 24, 0xc },
75 { 48, 0xd },
76 { 96, 0xe },
77 { 5, 0xf },
78 };
79
80 /* ratio for input clk freq */
81 static const struct nau8825_fll_attr fll_ratio[] = {
82 { 512000, 0x01 },
83 { 256000, 0x02 },
84 { 128000, 0x04 },
85 { 64000, 0x08 },
86 { 32000, 0x10 },
87 { 8000, 0x20 },
88 { 4000, 0x40 },
89 };
90
91 static const struct nau8825_fll_attr fll_pre_scalar[] = {
92 { 1, 0x0 },
93 { 2, 0x1 },
94 { 4, 0x2 },
95 { 8, 0x3 },
96 };
97
98 static const struct reg_default nau8825_reg_defaults[] = {
99 { NAU8825_REG_ENA_CTRL, 0x00ff },
100 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
101 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
102 { NAU8825_REG_FLL1, 0x0 },
103 { NAU8825_REG_FLL2, 0x3126 },
104 { NAU8825_REG_FLL3, 0x0008 },
105 { NAU8825_REG_FLL4, 0x0010 },
106 { NAU8825_REG_FLL5, 0x0 },
107 { NAU8825_REG_FLL6, 0x6000 },
108 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
109 { NAU8825_REG_HSD_CTRL, 0x000c },
110 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
111 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
112 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
113 { NAU8825_REG_SAR_CTRL, 0x0015 },
114 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
115 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
116 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
117 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
118 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
119 { NAU8825_REG_GPIO34_CTRL, 0x0 },
120 { NAU8825_REG_GPIO12_CTRL, 0x0 },
121 { NAU8825_REG_TDM_CTRL, 0x0 },
122 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
123 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
124 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
125 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
126 { NAU8825_REG_BIQ_CTRL, 0x0 },
127 { NAU8825_REG_BIQ_COF1, 0x0 },
128 { NAU8825_REG_BIQ_COF2, 0x0 },
129 { NAU8825_REG_BIQ_COF3, 0x0 },
130 { NAU8825_REG_BIQ_COF4, 0x0 },
131 { NAU8825_REG_BIQ_COF5, 0x0 },
132 { NAU8825_REG_BIQ_COF6, 0x0 },
133 { NAU8825_REG_BIQ_COF7, 0x0 },
134 { NAU8825_REG_BIQ_COF8, 0x0 },
135 { NAU8825_REG_BIQ_COF9, 0x0 },
136 { NAU8825_REG_BIQ_COF10, 0x0 },
137 { NAU8825_REG_ADC_RATE, 0x0010 },
138 { NAU8825_REG_DAC_CTRL1, 0x0001 },
139 { NAU8825_REG_DAC_CTRL2, 0x0 },
140 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
141 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
142 { NAU8825_REG_MUTE_CTRL, 0x0 },
143 { NAU8825_REG_HSVOL_CTRL, 0x0 },
144 { NAU8825_REG_DACL_CTRL, 0x02cf },
145 { NAU8825_REG_DACR_CTRL, 0x00cf },
146 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
147 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
148 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
149 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
150 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
151 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
152 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
153 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
154 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
155 { NAU8825_REG_CLASSG_CTRL, 0x0 },
156 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
157 { NAU8825_REG_MISC_CTRL, 0x0 },
158 { NAU8825_REG_BIAS_ADJ, 0x0 },
159 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
160 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
161 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
162 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
163 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
164 { NAU8825_REG_RDAC, 0x0008 },
165 { NAU8825_REG_MIC_BIAS, 0x0006 },
166 { NAU8825_REG_BOOST, 0x0 },
167 { NAU8825_REG_FEPGA, 0x0 },
168 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
169 { NAU8825_REG_CHARGE_PUMP, 0x0 },
170 };
171
172 /* register backup table when cross talk detection */
173 static struct reg_default nau8825_xtalk_baktab[] = {
174 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
175 { NAU8825_REG_HSVOL_CTRL, 0 },
176 { NAU8825_REG_DACL_CTRL, 0 },
177 { NAU8825_REG_DACR_CTRL, 0 },
178 };
179
180 static const unsigned short logtable[256] = {
181 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
182 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
183 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
184 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
185 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
186 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
187 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
188 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
189 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
190 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
191 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
192 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
193 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
194 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
195 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
196 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
197 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
198 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
199 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
200 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
201 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
202 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
203 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
204 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
205 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
206 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
207 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
208 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
209 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
210 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
211 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
212 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
213 };
214
215 static struct snd_soc_dai *nau8825_get_codec_dai(struct nau8825 *nau8825)
216 {
217 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(nau8825->dapm);
218 struct snd_soc_component *component = &codec->component;
219 struct snd_soc_dai *codec_dai, *_dai;
220
221 list_for_each_entry_safe(codec_dai, _dai, &component->dai_list, list) {
222 if (!strncmp(codec_dai->name, NUVOTON_CODEC_DAI,
223 strlen(NUVOTON_CODEC_DAI)))
224 return codec_dai;
225 }
226 return NULL;
227 }
228
229 static bool nau8825_dai_is_active(struct nau8825 *nau8825)
230 {
231 struct snd_soc_dai *codec_dai = nau8825_get_codec_dai(nau8825);
232
233 if (codec_dai) {
234 if (codec_dai->playback_active || codec_dai->capture_active)
235 return true;
236 }
237 return false;
238 }
239
240 /**
241 * nau8825_sema_acquire - acquire the semaphore of nau88l25
242 * @nau8825: component to register the codec private data with
243 * @timeout: how long in jiffies to wait before failure or zero to wait
244 * until release
245 *
246 * Attempts to acquire the semaphore with number of jiffies. If no more
247 * tasks are allowed to acquire the semaphore, calling this function will
248 * put the task to sleep. If the semaphore is not released within the
249 * specified number of jiffies, this function returns.
250 * Acquires the semaphore without jiffies. If no more tasks are allowed
251 * to acquire the semaphore, calling this function will put the task to
252 * sleep until the semaphore is released.
253 * It returns if the semaphore was acquired.
254 */
255 static void nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
256 {
257 int ret;
258
259 if (timeout)
260 ret = down_timeout(&nau8825->xtalk_sem, timeout);
261 else
262 ret = down_interruptible(&nau8825->xtalk_sem);
263
264 if (ret < 0)
265 dev_warn(nau8825->dev, "Acquire semaphone fail\n");
266 }
267
268 /**
269 * nau8825_sema_release - release the semaphore of nau88l25
270 * @nau8825: component to register the codec private data with
271 *
272 * Release the semaphore which may be called from any context and
273 * even by tasks which have never called down().
274 */
275 static inline void nau8825_sema_release(struct nau8825 *nau8825)
276 {
277 up(&nau8825->xtalk_sem);
278 }
279
280 /**
281 * nau8825_sema_reset - reset the semaphore for nau88l25
282 * @nau8825: component to register the codec private data with
283 *
284 * Reset the counter of the semaphore. Call this function to restart
285 * a new round task management.
286 */
287 static inline void nau8825_sema_reset(struct nau8825 *nau8825)
288 {
289 nau8825->xtalk_sem.count = 1;
290 }
291
292 /**
293 * Ramp up the headphone volume change gradually to target level.
294 *
295 * @nau8825: component to register the codec private data with
296 * @vol_from: the volume to start up
297 * @vol_to: the target volume
298 * @step: the volume span to move on
299 *
300 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
301 * If the volume changes sharp, there is a pop noise heard in headphone. We
302 * provide the function to ramp up the volume up or down by delaying 10ms
303 * per step.
304 */
305 static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
306 unsigned int vol_from, unsigned int vol_to, unsigned int step)
307 {
308 unsigned int value, volume, ramp_up, from, to;
309
310 if (vol_from == vol_to || step == 0) {
311 return;
312 } else if (vol_from < vol_to) {
313 ramp_up = true;
314 from = vol_from;
315 to = vol_to;
316 } else {
317 ramp_up = false;
318 from = vol_to;
319 to = vol_from;
320 }
321 /* only handle volume from 0dB to minimum -54dB */
322 if (to > NAU8825_HP_VOL_MIN)
323 to = NAU8825_HP_VOL_MIN;
324
325 for (volume = from; volume < to; volume += step) {
326 if (ramp_up)
327 value = volume;
328 else
329 value = to - volume + from;
330 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
331 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
332 (value << NAU8825_HPL_VOL_SFT) | value);
333 usleep_range(10000, 10500);
334 }
335 if (ramp_up)
336 value = to;
337 else
338 value = from;
339 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
340 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
341 (value << NAU8825_HPL_VOL_SFT) | value);
342 }
343
344 /**
345 * Computes log10 of a value; the result is round off to 3 decimal. This func-
346 * tion takes reference to dvb-math. The source code locates as the following.
347 * Linux/drivers/media/dvb-core/dvb_math.c
348 *
349 * return log10(value) * 1000
350 */
351 static u32 nau8825_intlog10_dec3(u32 value)
352 {
353 u32 msb, logentry, significand, interpolation, log10val;
354 u64 log2val;
355
356 /* first detect the msb (count begins at 0) */
357 msb = fls(value) - 1;
358 /**
359 * now we use a logtable after the following method:
360 *
361 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
362 * where x = msb and therefore 1 <= y < 2
363 * first y is determined by shifting the value left
364 * so that msb is bit 31
365 * 0x00231f56 -> 0x8C7D5800
366 * the result is y * 2^31 -> "significand"
367 * then the highest 9 bits are used for a table lookup
368 * the highest bit is discarded because it's always set
369 * the highest nine bits in our example are 100011000
370 * so we would use the entry 0x18
371 */
372 significand = value << (31 - msb);
373 logentry = (significand >> 23) & 0xff;
374 /**
375 * last step we do is interpolation because of the
376 * limitations of the log table the error is that part of
377 * the significand which isn't used for lookup then we
378 * compute the ratio between the error and the next table entry
379 * and interpolate it between the log table entry used and the
380 * next one the biggest error possible is 0x7fffff
381 * (in our example it's 0x7D5800)
382 * needed value for next table entry is 0x800000
383 * so the interpolation is
384 * (error / 0x800000) * (logtable_next - logtable_current)
385 * in the implementation the division is moved to the end for
386 * better accuracy there is also an overflow correction if
387 * logtable_next is 256
388 */
389 interpolation = ((significand & 0x7fffff) *
390 ((logtable[(logentry + 1) & 0xff] -
391 logtable[logentry]) & 0xffff)) >> 15;
392
393 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
394 /**
395 * log10(x) = log2(x) * log10(2)
396 */
397 log10val = (log2val * LOG10_MAGIC) >> 31;
398 /**
399 * the result is round off to 3 decimal
400 */
401 return log10val / ((1 << 24) / 1000);
402 }
403
404 /**
405 * computes cross talk suppression sidetone gain.
406 *
407 * @sig_org: orignal signal level
408 * @sig_cros: cross talk signal level
409 *
410 * The orignal and cross talk signal vlues need to be characterized.
411 * Once these values have been characterized, this sidetone value
412 * can be converted to decibel with the equation below.
413 * sidetone = 20 * log (original signal level / crosstalk signal level)
414 *
415 * return cross talk sidetone gain
416 */
417 static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
418 {
419 u32 gain, sidetone;
420
421 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
422 WARN_ON(1);
423 return 0;
424 }
425
426 sig_org = nau8825_intlog10_dec3(sig_org);
427 sig_cros = nau8825_intlog10_dec3(sig_cros);
428 if (sig_org >= sig_cros)
429 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
430 else
431 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
432 sidetone = SIDETONE_BASE - gain * 2;
433 sidetone /= 1000;
434
435 return sidetone;
436 }
437
438 static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
439 {
440 int index;
441
442 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
443 if (nau8825_xtalk_baktab[index].reg == reg)
444 return index;
445 return -EINVAL;
446 }
447
448 static void nau8825_xtalk_backup(struct nau8825 *nau8825)
449 {
450 int i;
451
452 /* Backup some register values to backup table */
453 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
454 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
455 &nau8825_xtalk_baktab[i].def);
456 }
457
458 static void nau8825_xtalk_restore(struct nau8825 *nau8825)
459 {
460 int i, volume;
461
462 /* Restore register values from backup table; When the driver restores
463 * the headphone volumem, it needs recover to original level gradually
464 * with 3dB per step for less pop noise.
465 */
466 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
467 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
468 /* Ramping up the volume change to reduce pop noise */
469 volume = nau8825_xtalk_baktab[i].def &
470 NAU8825_HPR_VOL_MASK;
471 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
472 continue;
473 }
474 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
475 nau8825_xtalk_baktab[i].def);
476 }
477 }
478
479 static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
480 {
481 /* Enable power of DAC path */
482 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
483 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
484 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
485 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
486 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
487 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
488 /* Prevent startup click by letting charge pump to ramp up and
489 * change bump enable
490 */
491 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
492 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
493 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
494 /* Enable clock sync of DAC and DAC clock */
495 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
496 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
497 NAU8825_RDAC_FS_BCLK_ENB,
498 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
499 /* Power up output driver with 2 stage */
500 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
501 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
502 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
503 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
504 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
505 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
506 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
507 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
508 /* HP outputs not shouted to ground */
509 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
510 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
511 /* Enable HP boost driver */
512 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
513 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
514 /* Enable class G compare path to supply 1.8V or 0.9V. */
515 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
516 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
517 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
518 }
519
520 static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
521 {
522 /* Power up left ADC and raise 5dB than Vmid for Vref */
523 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
524 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
525 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
526 }
527
528 static void nau8825_xtalk_clock(struct nau8825 *nau8825)
529 {
530 /* Recover FLL default value */
531 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
532 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
533 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
534 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
535 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
536 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
537 /* Enable internal VCO clock for detection signal generated */
538 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
539 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
540 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
541 NAU8825_DCO_EN);
542 /* Given specific clock frequency of internal clock to
543 * generate signal.
544 */
545 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
546 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
547 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
548 NAU8825_FLL_RATIO_MASK, 0x10);
549 }
550
551 static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
552 {
553 int volume, index;
554
555 /* Backup those registers changed by cross talk detection */
556 nau8825_xtalk_backup(nau8825);
557 /* Config IIS as master to output signal by codec */
558 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
559 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
560 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
561 (0x2 << NAU8825_I2S_DRV_SFT) | 0x1);
562 /* Ramp up headphone volume to 0dB to get better performance and
563 * avoid pop noise in headphone.
564 */
565 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
566 if (index != -EINVAL) {
567 volume = nau8825_xtalk_baktab[index].def &
568 NAU8825_HPR_VOL_MASK;
569 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
570 }
571 nau8825_xtalk_clock(nau8825);
572 nau8825_xtalk_prepare_dac(nau8825);
573 nau8825_xtalk_prepare_adc(nau8825);
574 /* Config channel path and digital gain */
575 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
576 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
577 NAU8825_DACL_CH_SEL_L | 0xab);
578 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
579 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
580 NAU8825_DACR_CH_SEL_R | 0xab);
581 /* Config cross talk parameters and generate the 23Hz sine wave with
582 * 1/16 full scale of signal level for impedance measurement.
583 */
584 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
585 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
586 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
587 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
588 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
589 /* RMS intrruption enable */
590 regmap_update_bits(nau8825->regmap,
591 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
592 /* Power up left and right DAC */
593 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
594 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
595 }
596
597 static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
598 {
599 /* Disable HP boost driver */
600 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
601 NAU8825_HP_BOOST_DIS, 0);
602 /* HP outputs shouted to ground */
603 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
604 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
605 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
606 /* Power down left and right DAC */
607 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
608 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
609 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
610 /* Enable the TESTDAC and disable L/R HP impedance */
611 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
612 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
613 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
614 /* Power down output driver with 2 stage */
615 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
616 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
617 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
618 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
619 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
620 /* Disable clock sync of DAC and DAC clock */
621 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
622 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
623 /* Disable charge pump ramp up function and change bump */
624 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
625 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
626 /* Disable power of DAC path */
627 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
628 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
629 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
630 if (!nau8825->irq)
631 regmap_update_bits(nau8825->regmap,
632 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
633 }
634
635 static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
636 {
637 /* Power down left ADC and restore voltage to Vmid */
638 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
639 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
640 }
641
642 static void nau8825_xtalk_clean(struct nau8825 *nau8825)
643 {
644 /* Enable internal VCO needed for interruptions */
645 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
646 nau8825_xtalk_clean_dac(nau8825);
647 nau8825_xtalk_clean_adc(nau8825);
648 /* Clear cross talk parameters and disable */
649 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
650 /* RMS intrruption disable */
651 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
652 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
653 /* Recover default value for IIS */
654 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
655 NAU8825_I2S_MS_MASK | NAU8825_I2S_DRV_MASK |
656 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
657 /* Restore value of specific register for cross talk */
658 nau8825_xtalk_restore(nau8825);
659 }
660
661 static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
662 {
663 /* Apply ADC volume for better cross talk performance */
664 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
665 NAU8825_ADC_DIG_VOL_MASK, vol);
666 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
667 * Do it before sending signal in order to erase pop noise.
668 */
669 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
670 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
671 NAU8825_BIAS_TESTDACL_EN);
672 switch (nau8825->xtalk_state) {
673 case NAU8825_XTALK_HPR_R2L:
674 /* Enable right headphone impedance */
675 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
676 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
677 NAU8825_BIAS_HPR_IMP);
678 break;
679 case NAU8825_XTALK_HPL_R2L:
680 /* Enable left headphone impedance */
681 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
682 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
683 NAU8825_BIAS_HPL_IMP);
684 break;
685 default:
686 break;
687 }
688 msleep(100);
689 /* Impedance measurement mode enable */
690 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
691 NAU8825_IMM_EN, NAU8825_IMM_EN);
692 }
693
694 static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
695 {
696 /* Impedance measurement mode disable */
697 regmap_update_bits(nau8825->regmap,
698 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
699 }
700
701 /* The cross talk measurement function can reduce cross talk across the
702 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
703 * level to determine what cross talk reduction gain is. This system works by
704 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
705 * the PGA. The output of the PGA is then connected to an internal current
706 * sense which measures the attenuated 23Hz signal and passing the output to
707 * an ADC which converts the measurement to a binary code. With two separated
708 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
709 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
710 * Thus, the measurement function has four states to complete whole sequence.
711 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
712 * IMM stat to make JKR1(HPR) impedance measure.
713 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
714 * to HPL IMM state to make JKTIP(HPL) impedance measure.
715 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
716 * transfer to IMM state to determine suppression sidetone gain.
717 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
718 * and cross talk signal level. Apply this gain and then restore codec
719 * configuration. Then transfer to Done state for ending.
720 */
721 static void nau8825_xtalk_measure(struct nau8825 *nau8825)
722 {
723 u32 sidetone;
724
725 switch (nau8825->xtalk_state) {
726 case NAU8825_XTALK_PREPARE:
727 /* In prepare state, set up clock, intrruption, DAC path, ADC
728 * path and cross talk detection parameters for preparation.
729 */
730 nau8825_xtalk_prepare(nau8825);
731 msleep(280);
732 /* Trigger right headphone impedance detection */
733 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
734 nau8825_xtalk_imm_start(nau8825, 0x00d2);
735 break;
736 case NAU8825_XTALK_HPR_R2L:
737 /* In right headphone IMM state, read out right headphone
738 * impedance measure result, and then start up left side.
739 */
740 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
741 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
742 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
743 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
744 /* Disable then re-enable IMM mode to update */
745 nau8825_xtalk_imm_stop(nau8825);
746 /* Trigger left headphone impedance detection */
747 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
748 nau8825_xtalk_imm_start(nau8825, 0x00ff);
749 break;
750 case NAU8825_XTALK_HPL_R2L:
751 /* In left headphone IMM state, read out left headphone
752 * impedance measure result, and delay some time to wait
753 * detection sine wave output finish. Then, we can calculate
754 * the cross talk suppresstion side tone according to the L/R
755 * headphone imedance.
756 */
757 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
758 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
759 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
760 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
761 nau8825_xtalk_imm_stop(nau8825);
762 msleep(150);
763 nau8825->xtalk_state = NAU8825_XTALK_IMM;
764 break;
765 case NAU8825_XTALK_IMM:
766 /* In impedance measure state, the orignal and cross talk
767 * signal level vlues are ready. The side tone gain is deter-
768 * mined with these signal level. After all, restore codec
769 * configuration.
770 */
771 sidetone = nau8825_xtalk_sidetone(
772 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
773 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
774 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
775 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
776 (sidetone << 8) | sidetone);
777 nau8825_xtalk_clean(nau8825);
778 nau8825->xtalk_state = NAU8825_XTALK_DONE;
779 break;
780 default:
781 break;
782 }
783 }
784
785 static void nau8825_xtalk_work(struct work_struct *work)
786 {
787 struct nau8825 *nau8825 = container_of(
788 work, struct nau8825, xtalk_work);
789
790 nau8825_xtalk_measure(nau8825);
791 /* To determine the cross talk side tone gain when reach
792 * the impedance measure state.
793 */
794 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
795 nau8825_xtalk_measure(nau8825);
796
797 /* Delay jack report until cross talk detection process
798 * completed. It can avoid application to do playback
799 * preparation before cross talk detection is still working.
800 * Meanwhile, the protection of the cross talk detection
801 * is released.
802 */
803 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
804 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
805 nau8825->xtalk_event_mask);
806 nau8825_sema_release(nau8825);
807 nau8825->xtalk_protect = false;
808 }
809 }
810
811 static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
812 {
813 /* If the xtalk_protect is true, that means the process is still
814 * on going. The driver forces to cancel the cross talk task and
815 * restores the configuration to original status.
816 */
817 if (nau8825->xtalk_protect) {
818 cancel_work_sync(&nau8825->xtalk_work);
819 nau8825_xtalk_clean(nau8825);
820 }
821 /* Reset parameters for cross talk suppression function */
822 nau8825_sema_reset(nau8825);
823 nau8825->xtalk_state = NAU8825_XTALK_DONE;
824 nau8825->xtalk_protect = false;
825 }
826
827 static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
828 {
829 switch (reg) {
830 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
831 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
832 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
833 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
834 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
835 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
836 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
837 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
838 case NAU8825_REG_MISC_CTRL:
839 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
840 case NAU8825_REG_BIAS_ADJ:
841 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
842 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
843 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
844 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
845 return true;
846 default:
847 return false;
848 }
849
850 }
851
852 static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
853 {
854 switch (reg) {
855 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
856 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
857 case NAU8825_REG_INTERRUPT_MASK:
858 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
859 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
860 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
861 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
862 case NAU8825_REG_IMM_MODE_CTRL:
863 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
864 case NAU8825_REG_MISC_CTRL:
865 case NAU8825_REG_BIAS_ADJ:
866 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
867 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
868 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
869 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
870 return true;
871 default:
872 return false;
873 }
874 }
875
876 static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
877 {
878 switch (reg) {
879 case NAU8825_REG_RESET:
880 case NAU8825_REG_IRQ_STATUS:
881 case NAU8825_REG_INT_CLR_KEY_STATUS:
882 case NAU8825_REG_IMM_RMS_L:
883 case NAU8825_REG_IMM_RMS_R:
884 case NAU8825_REG_I2C_DEVICE_ID:
885 case NAU8825_REG_SARDOUT_RAM_STATUS:
886 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
887 case NAU8825_REG_GENERAL_STATUS:
888 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
889 return true;
890 default:
891 return false;
892 }
893 }
894
895 static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
896 struct snd_kcontrol *kcontrol, int event)
897 {
898 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
899 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
900
901 switch (event) {
902 case SND_SOC_DAPM_POST_PMU:
903 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
904 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
905 break;
906 case SND_SOC_DAPM_POST_PMD:
907 if (!nau8825->irq)
908 regmap_update_bits(nau8825->regmap,
909 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
910 break;
911 default:
912 return -EINVAL;
913 }
914
915 return 0;
916 }
917
918 static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
919 struct snd_kcontrol *kcontrol, int event)
920 {
921 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
922 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
923
924 switch (event) {
925 case SND_SOC_DAPM_POST_PMU:
926 /* Prevent startup click by letting charge pump to ramp up */
927 msleep(10);
928 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
929 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
930 break;
931 case SND_SOC_DAPM_PRE_PMD:
932 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
933 NAU8825_JAMNODCLOW, 0);
934 break;
935 default:
936 return -EINVAL;
937 }
938
939 return 0;
940 }
941
942 static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
943 struct snd_kcontrol *kcontrol, int event)
944 {
945 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
946 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
947
948 switch (event) {
949 case SND_SOC_DAPM_PRE_PMU:
950 /* Disables the TESTDAC to let DAC signal pass through. */
951 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
952 NAU8825_BIAS_TESTDAC_EN, 0);
953 break;
954 case SND_SOC_DAPM_POST_PMD:
955 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
956 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 return 0;
963 }
964
965 static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
966 struct snd_ctl_elem_value *ucontrol)
967 {
968 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
969 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
970
971 if (!component->regmap)
972 return -EINVAL;
973
974 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
975 ucontrol->value.bytes.data, params->max);
976 return 0;
977 }
978
979 static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
980 struct snd_ctl_elem_value *ucontrol)
981 {
982 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
983 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
984 void *data;
985
986 if (!component->regmap)
987 return -EINVAL;
988
989 data = kmemdup(ucontrol->value.bytes.data,
990 params->max, GFP_KERNEL | GFP_DMA);
991 if (!data)
992 return -ENOMEM;
993
994 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
995 NAU8825_BIQ_WRT_EN, 0);
996 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
997 data, params->max);
998 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
999 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1000
1001 kfree(data);
1002 return 0;
1003 }
1004
1005 static const char * const nau8825_biq_path[] = {
1006 "ADC", "DAC"
1007 };
1008
1009 static const struct soc_enum nau8825_biq_path_enum =
1010 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1011 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1012
1013 static const char * const nau8825_adc_decimation[] = {
1014 "32", "64", "128", "256"
1015 };
1016
1017 static const struct soc_enum nau8825_adc_decimation_enum =
1018 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1019 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1020
1021 static const char * const nau8825_dac_oversampl[] = {
1022 "64", "256", "128", "", "32"
1023 };
1024
1025 static const struct soc_enum nau8825_dac_oversampl_enum =
1026 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1027 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1028
1029 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1030 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1031 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1032 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1033 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1034
1035 static const struct snd_kcontrol_new nau8825_controls[] = {
1036 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1037 0, 0xff, 0, adc_vol_tlv),
1038 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1039 12, 8, 0x0f, 0, sidetone_vol_tlv),
1040 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1041 6, 0, 0x3f, 1, dac_vol_tlv),
1042 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1043 8, 37, 0, fepga_gain_tlv),
1044 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1045 0, 8, 0xff, 0, crosstalk_vol_tlv),
1046
1047 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1048 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1049 /* programmable biquad filter */
1050 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1051 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1052 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1053 };
1054
1055 /* DAC Mux 0x33[9] and 0x34[9] */
1056 static const char * const nau8825_dac_src[] = {
1057 "DACL", "DACR",
1058 };
1059
1060 static SOC_ENUM_SINGLE_DECL(
1061 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1062 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1063
1064 static SOC_ENUM_SINGLE_DECL(
1065 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1066 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1067
1068 static const struct snd_kcontrol_new nau8825_dacl_mux =
1069 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1070
1071 static const struct snd_kcontrol_new nau8825_dacr_mux =
1072 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1073
1074
1075 static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1076 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1077 15, 1),
1078
1079 SND_SOC_DAPM_INPUT("MIC"),
1080 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1081
1082 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1083 NULL, 0),
1084
1085 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1086 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1087 SND_SOC_DAPM_POST_PMD),
1088 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1089 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1090 0),
1091
1092 /* ADC for button press detection. A dapm supply widget is used to
1093 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1094 * during suspend.
1095 */
1096 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1097 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1098
1099 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1100 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1101 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1102 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1103
1104 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1105 NAU8825_ENABLE_DACR_SFT, 0),
1106 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1107 NAU8825_ENABLE_DACL_SFT, 0),
1108 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1109
1110 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1111 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1112
1113 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1114 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1115 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1116 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1117
1118 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1119 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1120 SND_SOC_DAPM_PRE_PMD),
1121
1122 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1123 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1124 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1125 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1126 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1127 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1128 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1129 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1130 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1131 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1132 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1133 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1134
1135 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1136 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1137 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1139 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1140 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1141
1142 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1143 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1144 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1145 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1146 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1147
1148 /* High current HPOL/R boost driver */
1149 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1150 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1151
1152 /* Class G operation control*/
1153 SND_SOC_DAPM_PGA_S("Class G", 10,
1154 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1155
1156 SND_SOC_DAPM_OUTPUT("HPOL"),
1157 SND_SOC_DAPM_OUTPUT("HPOR"),
1158 };
1159
1160 static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1161 {"Frontend PGA", NULL, "MIC"},
1162 {"ADC", NULL, "Frontend PGA"},
1163 {"ADC", NULL, "ADC Clock"},
1164 {"ADC", NULL, "ADC Power"},
1165 {"AIFTX", NULL, "ADC"},
1166
1167 {"DDACL", NULL, "Playback"},
1168 {"DDACR", NULL, "Playback"},
1169 {"DDACL", NULL, "DDAC Clock"},
1170 {"DDACR", NULL, "DDAC Clock"},
1171 {"DACL Mux", "DACL", "DDACL"},
1172 {"DACL Mux", "DACR", "DDACR"},
1173 {"DACR Mux", "DACL", "DDACL"},
1174 {"DACR Mux", "DACR", "DDACR"},
1175 {"HP amp L", NULL, "DACL Mux"},
1176 {"HP amp R", NULL, "DACR Mux"},
1177 {"Charge Pump", NULL, "HP amp L"},
1178 {"Charge Pump", NULL, "HP amp R"},
1179 {"ADACL", NULL, "Charge Pump"},
1180 {"ADACR", NULL, "Charge Pump"},
1181 {"ADACL Clock", NULL, "ADACL"},
1182 {"ADACR Clock", NULL, "ADACR"},
1183 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1184 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1185 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1186 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1187 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1188 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1189 {"Output DACL", NULL, "Output Driver L Stage 3"},
1190 {"Output DACR", NULL, "Output Driver R Stage 3"},
1191 {"HPOL Pulldown", NULL, "Output DACL"},
1192 {"HPOR Pulldown", NULL, "Output DACR"},
1193 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1194 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1195 {"Class G", NULL, "HP Boost Driver"},
1196 {"HPOL", NULL, "Class G"},
1197 {"HPOR", NULL, "Class G"},
1198 };
1199
1200 static int nau8825_hw_params(struct snd_pcm_substream *substream,
1201 struct snd_pcm_hw_params *params,
1202 struct snd_soc_dai *dai)
1203 {
1204 struct snd_soc_codec *codec = dai->codec;
1205 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1206 unsigned int val_len = 0;
1207
1208 switch (params_width(params)) {
1209 case 16:
1210 val_len |= NAU8825_I2S_DL_16;
1211 break;
1212 case 20:
1213 val_len |= NAU8825_I2S_DL_20;
1214 break;
1215 case 24:
1216 val_len |= NAU8825_I2S_DL_24;
1217 break;
1218 case 32:
1219 val_len |= NAU8825_I2S_DL_32;
1220 break;
1221 default:
1222 return -EINVAL;
1223 }
1224
1225 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1226 NAU8825_I2S_DL_MASK, val_len);
1227
1228 return 0;
1229 }
1230
1231 static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1232 {
1233 struct snd_soc_codec *codec = codec_dai->codec;
1234 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1235 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1236
1237 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1238 case SND_SOC_DAIFMT_CBM_CFM:
1239 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1240 break;
1241 case SND_SOC_DAIFMT_CBS_CFS:
1242 break;
1243 default:
1244 return -EINVAL;
1245 }
1246
1247 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1248 case SND_SOC_DAIFMT_NB_NF:
1249 break;
1250 case SND_SOC_DAIFMT_IB_NF:
1251 ctrl1_val |= NAU8825_I2S_BP_INV;
1252 break;
1253 default:
1254 return -EINVAL;
1255 }
1256
1257 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1258 case SND_SOC_DAIFMT_I2S:
1259 ctrl1_val |= NAU8825_I2S_DF_I2S;
1260 break;
1261 case SND_SOC_DAIFMT_LEFT_J:
1262 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1263 break;
1264 case SND_SOC_DAIFMT_RIGHT_J:
1265 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1266 break;
1267 case SND_SOC_DAIFMT_DSP_A:
1268 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1269 break;
1270 case SND_SOC_DAIFMT_DSP_B:
1271 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1272 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1273 break;
1274 default:
1275 return -EINVAL;
1276 }
1277
1278 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1279 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1280 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1281 ctrl1_val);
1282 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1283 NAU8825_I2S_MS_MASK, ctrl2_val);
1284
1285 return 0;
1286 }
1287
1288 static const struct snd_soc_dai_ops nau8825_dai_ops = {
1289 .hw_params = nau8825_hw_params,
1290 .set_fmt = nau8825_set_dai_fmt,
1291 };
1292
1293 #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1294 #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1295 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1296
1297 static struct snd_soc_dai_driver nau8825_dai = {
1298 .name = "nau8825-hifi",
1299 .playback = {
1300 .stream_name = "Playback",
1301 .channels_min = 1,
1302 .channels_max = 2,
1303 .rates = NAU8825_RATES,
1304 .formats = NAU8825_FORMATS,
1305 },
1306 .capture = {
1307 .stream_name = "Capture",
1308 .channels_min = 1,
1309 .channels_max = 1,
1310 .rates = NAU8825_RATES,
1311 .formats = NAU8825_FORMATS,
1312 },
1313 .ops = &nau8825_dai_ops,
1314 };
1315
1316 /**
1317 * nau8825_enable_jack_detect - Specify a jack for event reporting
1318 *
1319 * @component: component to register the jack with
1320 * @jack: jack to use to report headset and button events on
1321 *
1322 * After this function has been called the headset insert/remove and button
1323 * events will be routed to the given jack. Jack can be null to stop
1324 * reporting.
1325 */
1326 int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1327 struct snd_soc_jack *jack)
1328 {
1329 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1330 struct regmap *regmap = nau8825->regmap;
1331
1332 nau8825->jack = jack;
1333
1334 /* Ground HP Outputs[1:0], needed for headset auto detection
1335 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1336 */
1337 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1338 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1339 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1340
1341 return 0;
1342 }
1343 EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1344
1345
1346 static bool nau8825_is_jack_inserted(struct regmap *regmap)
1347 {
1348 int status;
1349
1350 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1351 return !(status & NAU8825_GPIO2JD1);
1352 }
1353
1354 static void nau8825_restart_jack_detection(struct regmap *regmap)
1355 {
1356 /* this will restart the entire jack detection process including MIC/GND
1357 * switching and create interrupts. We have to go from 0 to 1 and back
1358 * to 0 to restart.
1359 */
1360 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1361 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1362 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1363 NAU8825_JACK_DET_RESTART, 0);
1364 }
1365
1366 static void nau8825_int_status_clear_all(struct regmap *regmap)
1367 {
1368 int active_irq, clear_irq, i;
1369
1370 /* Reset the intrruption status from rightmost bit if the corres-
1371 * ponding irq event occurs.
1372 */
1373 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1374 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1375 clear_irq = (0x1 << i);
1376 if (active_irq & clear_irq)
1377 regmap_write(regmap,
1378 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1379 }
1380 }
1381
1382 static void nau8825_eject_jack(struct nau8825 *nau8825)
1383 {
1384 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1385 struct regmap *regmap = nau8825->regmap;
1386
1387 /* Force to cancel the cross talk detection process */
1388 nau8825_xtalk_cancel(nau8825);
1389
1390 snd_soc_dapm_disable_pin(dapm, "SAR");
1391 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1392 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1393 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1394 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1395 /* ground HPL/HPR, MICGRND1/2 */
1396 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1397
1398 snd_soc_dapm_sync(dapm);
1399
1400 /* Clear all interruption status */
1401 nau8825_int_status_clear_all(regmap);
1402
1403 /* Enable the insertion interruption, disable the ejection inter-
1404 * ruption, and then bypass de-bounce circuit.
1405 */
1406 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1407 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1408 NAU8825_IRQ_EJECT_DIS);
1409 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1410 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1411 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1412 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1413 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1414 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1415 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1416
1417 /* Disable ADC needed for interruptions at audo mode */
1418 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1419 NAU8825_ENABLE_ADC, 0);
1420
1421 /* Close clock for jack type detection at manual mode */
1422 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1423 }
1424
1425 /* Enable audo mode interruptions with internal clock. */
1426 static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1427 {
1428 struct regmap *regmap = nau8825->regmap;
1429
1430 /* Enable headset jack type detection complete interruption and
1431 * jack ejection interruption.
1432 */
1433 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1434 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1435
1436 /* Enable internal VCO needed for interruptions */
1437 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1438
1439 /* Enable ADC needed for interruptions */
1440 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1441 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1442
1443 /* Chip needs one FSCLK cycle in order to generate interruptions,
1444 * as we cannot guarantee one will be provided by the system. Turning
1445 * master mode on then off enables us to generate that FSCLK cycle
1446 * with a minimum of contention on the clock bus.
1447 */
1448 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1449 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1450 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1451 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1452
1453 /* Not bypass de-bounce circuit */
1454 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1455 NAU8825_JACK_DET_DB_BYPASS, 0);
1456
1457 /* Unmask all interruptions */
1458 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1459
1460 /* Restart the jack detection process at auto mode */
1461 nau8825_restart_jack_detection(regmap);
1462 }
1463
1464 static int nau8825_button_decode(int value)
1465 {
1466 int buttons = 0;
1467
1468 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1469 if (value & BIT(0))
1470 buttons |= SND_JACK_BTN_0;
1471 if (value & BIT(1))
1472 buttons |= SND_JACK_BTN_1;
1473 if (value & BIT(2))
1474 buttons |= SND_JACK_BTN_2;
1475 if (value & BIT(3))
1476 buttons |= SND_JACK_BTN_3;
1477 if (value & BIT(4))
1478 buttons |= SND_JACK_BTN_4;
1479 if (value & BIT(5))
1480 buttons |= SND_JACK_BTN_5;
1481
1482 return buttons;
1483 }
1484
1485 static int nau8825_jack_insert(struct nau8825 *nau8825)
1486 {
1487 struct regmap *regmap = nau8825->regmap;
1488 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1489 int jack_status_reg, mic_detected;
1490 int type = 0;
1491
1492 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1493 mic_detected = (jack_status_reg >> 10) & 3;
1494 /* The JKSLV and JKR2 all detected in high impedance headset */
1495 if (mic_detected == 0x3)
1496 nau8825->high_imped = true;
1497 else
1498 nau8825->high_imped = false;
1499
1500 switch (mic_detected) {
1501 case 0:
1502 /* no mic */
1503 type = SND_JACK_HEADPHONE;
1504 break;
1505 case 1:
1506 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1507 type = SND_JACK_HEADSET;
1508
1509 /* Unground MICGND1 */
1510 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1511 1 << 2);
1512 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1513 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1514 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1515 NAU8825_MICBIAS_JKR2);
1516 /* Attach SARADC to MICGND1 */
1517 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1518 NAU8825_SAR_INPUT_MASK,
1519 NAU8825_SAR_INPUT_JKR2);
1520
1521 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1522 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1523 snd_soc_dapm_sync(dapm);
1524 break;
1525 case 2:
1526 case 3:
1527 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1528 type = SND_JACK_HEADSET;
1529
1530 /* Unground MICGND2 */
1531 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1532 2 << 2);
1533 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1534 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1535 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1536 NAU8825_MICBIAS_JKSLV);
1537 /* Attach SARADC to MICGND2 */
1538 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1539 NAU8825_SAR_INPUT_MASK,
1540 NAU8825_SAR_INPUT_JKSLV);
1541
1542 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1543 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1544 snd_soc_dapm_sync(dapm);
1545 break;
1546 }
1547
1548 /* Leaving HPOL/R grounded after jack insert by default. They will be
1549 * ungrounded as part of the widget power up sequence at the beginning
1550 * of playback to reduce pop.
1551 */
1552 return type;
1553 }
1554
1555 #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1556 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1557
1558 static irqreturn_t nau8825_interrupt(int irq, void *data)
1559 {
1560 struct nau8825 *nau8825 = (struct nau8825 *)data;
1561 struct regmap *regmap = nau8825->regmap;
1562 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1563
1564 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1565 dev_err(nau8825->dev, "failed to read irq status\n");
1566 return IRQ_NONE;
1567 }
1568
1569 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1570 NAU8825_JACK_EJECTION_DETECTED) {
1571
1572 nau8825_eject_jack(nau8825);
1573 event_mask |= SND_JACK_HEADSET;
1574 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1575 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1576 int key_status;
1577
1578 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1579 &key_status);
1580
1581 /* upper 8 bits of the register are for short pressed keys,
1582 * lower 8 bits - for long pressed buttons
1583 */
1584 nau8825->button_pressed = nau8825_button_decode(
1585 key_status >> 8);
1586
1587 event |= nau8825->button_pressed;
1588 event_mask |= NAU8825_BUTTONS;
1589 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1590 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1591 event_mask = NAU8825_BUTTONS;
1592 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1593 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1594 if (nau8825_is_jack_inserted(regmap)) {
1595 event |= nau8825_jack_insert(nau8825);
1596 if (!nau8825->high_imped) {
1597 /* Apply the cross talk suppression in the
1598 * headset without high impedance.
1599 */
1600 if (!nau8825->xtalk_protect) {
1601 /* Raise protection for cross talk de-
1602 * tection if no protection before.
1603 * The driver has to cancel the pro-
1604 * cess and restore changes if process
1605 * is ongoing when ejection.
1606 */
1607 nau8825->xtalk_protect = true;
1608 nau8825_sema_acquire(nau8825, 0);
1609 }
1610 /* Startup cross talk detection process */
1611 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1612 schedule_work(&nau8825->xtalk_work);
1613 } else {
1614 /* The cross talk suppression shouldn't apply
1615 * in the headset with high impedance. Thus,
1616 * relieve the protection raised before.
1617 */
1618 if (nau8825->xtalk_protect) {
1619 nau8825_sema_release(nau8825);
1620 nau8825->xtalk_protect = false;
1621 }
1622 }
1623 } else {
1624 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1625 nau8825_eject_jack(nau8825);
1626 }
1627
1628 event_mask |= SND_JACK_HEADSET;
1629 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1630 /* Record the interruption report event for driver to report
1631 * the event later. The jack report will delay until cross
1632 * talk detection process is done.
1633 */
1634 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1635 nau8825->xtalk_event = event;
1636 nau8825->xtalk_event_mask = event_mask;
1637 }
1638 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1639 schedule_work(&nau8825->xtalk_work);
1640 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1641 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1642 NAU8825_JACK_INSERTION_DETECTED) {
1643 /* One more step to check GPIO status directly. Thus, the
1644 * driver can confirm the real insertion interruption because
1645 * the intrruption at manual mode has bypassed debounce
1646 * circuit which can get rid of unstable status.
1647 */
1648 if (nau8825_is_jack_inserted(regmap)) {
1649 /* Turn off insertion interruption at manual mode */
1650 regmap_update_bits(regmap,
1651 NAU8825_REG_INTERRUPT_DIS_CTRL,
1652 NAU8825_IRQ_INSERT_DIS,
1653 NAU8825_IRQ_INSERT_DIS);
1654 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1655 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1656 /* Enable interruption for jack type detection at audo
1657 * mode which can detect microphone and jack type.
1658 */
1659 nau8825_setup_auto_irq(nau8825);
1660 }
1661 }
1662
1663 if (!clear_irq)
1664 clear_irq = active_irq;
1665 /* clears the rightmost interruption */
1666 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1667
1668 /* Delay jack report until cross talk detection is done. It can avoid
1669 * application to do playback preparation when cross talk detection
1670 * process is still working. Otherwise, the resource like clock and
1671 * power will be issued by them at the same time and conflict happens.
1672 */
1673 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1674 snd_soc_jack_report(nau8825->jack, event, event_mask);
1675
1676 return IRQ_HANDLED;
1677 }
1678
1679 static void nau8825_setup_buttons(struct nau8825 *nau8825)
1680 {
1681 struct regmap *regmap = nau8825->regmap;
1682
1683 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1684 NAU8825_SAR_TRACKING_GAIN_MASK,
1685 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1686 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1687 NAU8825_SAR_COMPARE_TIME_MASK,
1688 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1689 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1690 NAU8825_SAR_SAMPLING_TIME_MASK,
1691 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1692
1693 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1694 NAU8825_KEYDET_LEVELS_NR_MASK,
1695 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1696 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1697 NAU8825_KEYDET_HYSTERESIS_MASK,
1698 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1699 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1700 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1701 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1702
1703 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1704 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1705 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1706 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1707 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1708 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1709 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1710 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1711
1712 /* Enable short press and release interruptions */
1713 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1714 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1715 0);
1716 }
1717
1718 static void nau8825_init_regs(struct nau8825 *nau8825)
1719 {
1720 struct regmap *regmap = nau8825->regmap;
1721
1722 /* Latch IIC LSB value */
1723 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1724 /* Enable Bias/Vmid */
1725 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1726 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1727 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1728 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1729
1730 /* VMID Tieoff */
1731 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1732 NAU8825_BIAS_VMID_SEL_MASK,
1733 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1734 /* Disable Boost Driver, Automatic Short circuit protection enable */
1735 regmap_update_bits(regmap, NAU8825_REG_BOOST,
1736 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1737 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1738 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1739 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1740
1741 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1742 NAU8825_JKDET_OUTPUT_EN,
1743 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1744 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1745 NAU8825_JKDET_PULL_EN,
1746 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1747 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1748 NAU8825_JKDET_PULL_UP,
1749 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1750 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1751 NAU8825_JACK_POLARITY,
1752 /* jkdet_polarity - 1 is for active-low */
1753 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1754
1755 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1756 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1757 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1758 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1759 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1760 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1761
1762 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1763 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1764
1765 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1766 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1767
1768 if (nau8825->sar_threshold_num)
1769 nau8825_setup_buttons(nau8825);
1770
1771 /* Default oversampling/decimations settings are unusable
1772 * (audible hiss). Set it to something better.
1773 */
1774 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1775 NAU8825_ADC_SYNC_DOWN_MASK, NAU8825_ADC_SYNC_DOWN_128);
1776 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1777 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_128);
1778 /* Disable DACR/L power */
1779 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1780 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1781 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1782 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1783 * signal to avoid any glitches due to power up transients in both
1784 * the analog and digital DAC circuit.
1785 */
1786 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1787 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1788 /* CICCLP off */
1789 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1790 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1791
1792 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1793 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1794 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1795 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1796 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1797 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1798 /* Class G timer 64ms */
1799 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1800 NAU8825_CLASSG_TIMER_MASK,
1801 0x20 << NAU8825_CLASSG_TIMER_SFT);
1802 /* DAC clock delay 2ns, VREF */
1803 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1804 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1805 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1806 (0x3 << NAU8825_RDAC_VREF_SFT));
1807 /* Config L/R channel */
1808 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1809 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1810 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1811 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1812 }
1813
1814 static const struct regmap_config nau8825_regmap_config = {
1815 .val_bits = NAU8825_REG_DATA_LEN,
1816 .reg_bits = NAU8825_REG_ADDR_LEN,
1817
1818 .max_register = NAU8825_REG_MAX,
1819 .readable_reg = nau8825_readable_reg,
1820 .writeable_reg = nau8825_writeable_reg,
1821 .volatile_reg = nau8825_volatile_reg,
1822
1823 .cache_type = REGCACHE_RBTREE,
1824 .reg_defaults = nau8825_reg_defaults,
1825 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1826 };
1827
1828 static int nau8825_codec_probe(struct snd_soc_codec *codec)
1829 {
1830 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1831 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1832
1833 nau8825->dapm = dapm;
1834
1835 return 0;
1836 }
1837
1838 static int nau8825_codec_remove(struct snd_soc_codec *codec)
1839 {
1840 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1841
1842 /* Cancel and reset cross tak suppresstion detection funciton */
1843 nau8825_xtalk_cancel(nau8825);
1844
1845 return 0;
1846 }
1847
1848 /**
1849 * nau8825_calc_fll_param - Calculate FLL parameters.
1850 * @fll_in: external clock provided to codec.
1851 * @fs: sampling rate.
1852 * @fll_param: Pointer to structure of FLL parameters.
1853 *
1854 * Calculate FLL parameters to configure codec.
1855 *
1856 * Returns 0 for success or negative error code.
1857 */
1858 static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1859 struct nau8825_fll *fll_param)
1860 {
1861 u64 fvco, fvco_max;
1862 unsigned int fref, i, fvco_sel;
1863
1864 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1865 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1866 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1867 */
1868 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1869 fref = fll_in / fll_pre_scalar[i].param;
1870 if (fref <= NAU_FREF_MAX)
1871 break;
1872 }
1873 if (i == ARRAY_SIZE(fll_pre_scalar))
1874 return -EINVAL;
1875 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1876
1877 /* Choose the FLL ratio based on FREF */
1878 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1879 if (fref >= fll_ratio[i].param)
1880 break;
1881 }
1882 if (i == ARRAY_SIZE(fll_ratio))
1883 return -EINVAL;
1884 fll_param->ratio = fll_ratio[i].val;
1885
1886 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1887 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1888 * guaranteed across the full range of operation.
1889 * FDCO = freq_out * 2 * mclk_src_scaling
1890 */
1891 fvco_max = 0;
1892 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1893 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1894 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1895 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1896 fvco_max < fvco) {
1897 fvco_max = fvco;
1898 fvco_sel = i;
1899 }
1900 }
1901 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1902 return -EINVAL;
1903 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1904
1905 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1906 * input based on FDCO, FREF and FLL ratio.
1907 */
1908 fvco = div_u64(fvco << 16, fref * fll_param->ratio);
1909 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1910 fll_param->fll_frac = fvco & 0xFFFF;
1911 return 0;
1912 }
1913
1914 static void nau8825_fll_apply(struct nau8825 *nau8825,
1915 struct nau8825_fll *fll_param)
1916 {
1917 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1918 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
1919 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
1920 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
1921 NAU8825_FLL_RATIO_MASK, fll_param->ratio);
1922 /* FLL 16-bit fractional input */
1923 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
1924 /* FLL 10-bit integer input */
1925 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
1926 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
1927 /* FLL pre-scaler */
1928 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
1929 NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
1930 /* select divided VCO input */
1931 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1932 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
1933 /* Disable free-running mode */
1934 regmap_update_bits(nau8825->regmap,
1935 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
1936 if (fll_param->fll_frac) {
1937 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1938 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1939 NAU8825_FLL_FTR_SW_MASK,
1940 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1941 NAU8825_FLL_FTR_SW_FILTER);
1942 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
1943 NAU8825_SDM_EN, NAU8825_SDM_EN);
1944 } else {
1945 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
1946 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
1947 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
1948 regmap_update_bits(nau8825->regmap,
1949 NAU8825_REG_FLL6, NAU8825_SDM_EN, 0);
1950 }
1951 }
1952
1953 /* freq_out must be 256*Fs in order to achieve the best performance */
1954 static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
1955 unsigned int freq_in, unsigned int freq_out)
1956 {
1957 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1958 struct nau8825_fll fll_param;
1959 int ret, fs;
1960
1961 fs = freq_out / 256;
1962 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
1963 if (ret < 0) {
1964 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
1965 return ret;
1966 }
1967 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1968 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1969 fll_param.fll_int, fll_param.clk_ref_div);
1970
1971 nau8825_fll_apply(nau8825, &fll_param);
1972 mdelay(2);
1973 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1974 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
1975 return 0;
1976 }
1977
1978 static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
1979 {
1980 int ret = 0;
1981
1982 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
1983 if (IS_ERR(nau8825->mclk)) {
1984 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
1985 return 0;
1986 }
1987
1988 if (!nau8825->mclk_freq) {
1989 ret = clk_prepare_enable(nau8825->mclk);
1990 if (ret) {
1991 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
1992 return ret;
1993 }
1994 }
1995
1996 if (nau8825->mclk_freq != freq) {
1997 freq = clk_round_rate(nau8825->mclk, freq);
1998 ret = clk_set_rate(nau8825->mclk, freq);
1999 if (ret) {
2000 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2001 return ret;
2002 }
2003 nau8825->mclk_freq = freq;
2004 }
2005
2006 return 0;
2007 }
2008
2009 static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2010 {
2011 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2012 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2013 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2014 NAU8825_DCO_EN, 0);
2015 }
2016
2017 static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2018 unsigned int freq)
2019 {
2020 struct regmap *regmap = nau8825->regmap;
2021 int ret;
2022
2023 switch (clk_id) {
2024 case NAU8825_CLK_DIS:
2025 /* Clock provided externally and disable internal VCO clock */
2026 nau8825_configure_mclk_as_sysclk(regmap);
2027 if (nau8825->mclk_freq) {
2028 clk_disable_unprepare(nau8825->mclk);
2029 nau8825->mclk_freq = 0;
2030 }
2031
2032 break;
2033 case NAU8825_CLK_MCLK:
2034 /* Acquire the semaphone to synchronize the playback and
2035 * interrupt handler. In order to avoid the playback inter-
2036 * fered by cross talk process, the driver make the playback
2037 * preparation halted until cross talk process finish.
2038 */
2039 nau8825_sema_acquire(nau8825, 2 * HZ);
2040 nau8825_configure_mclk_as_sysclk(regmap);
2041 /* MCLK not changed by clock tree */
2042 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2043 NAU8825_CLK_MCLK_SRC_MASK, 0);
2044 /* Release the semaphone. */
2045 nau8825_sema_release(nau8825);
2046
2047 ret = nau8825_mclk_prepare(nau8825, freq);
2048 if (ret)
2049 return ret;
2050
2051 break;
2052 case NAU8825_CLK_INTERNAL:
2053 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2054 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2055 NAU8825_DCO_EN, NAU8825_DCO_EN);
2056 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2057 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2058 /* Decrease the VCO frequency for power saving */
2059 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2060 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2061 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2062 NAU8825_FLL_RATIO_MASK, 0x10);
2063 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2064 NAU8825_SDM_EN, NAU8825_SDM_EN);
2065 } else {
2066 /* The clock turns off intentionally for power saving
2067 * when no headset connected.
2068 */
2069 nau8825_configure_mclk_as_sysclk(regmap);
2070 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2071 }
2072 if (nau8825->mclk_freq) {
2073 clk_disable_unprepare(nau8825->mclk);
2074 nau8825->mclk_freq = 0;
2075 }
2076
2077 break;
2078 case NAU8825_CLK_FLL_MCLK:
2079 /* Acquire the semaphone to synchronize the playback and
2080 * interrupt handler. In order to avoid the playback inter-
2081 * fered by cross talk process, the driver make the playback
2082 * preparation halted until cross talk process finish.
2083 */
2084 nau8825_sema_acquire(nau8825, 2 * HZ);
2085 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2086 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_MCLK);
2087 /* Release the semaphone. */
2088 nau8825_sema_release(nau8825);
2089
2090 ret = nau8825_mclk_prepare(nau8825, freq);
2091 if (ret)
2092 return ret;
2093
2094 break;
2095 case NAU8825_CLK_FLL_BLK:
2096 /* Acquire the semaphone to synchronize the playback and
2097 * interrupt handler. In order to avoid the playback inter-
2098 * fered by cross talk process, the driver make the playback
2099 * preparation halted until cross talk process finish.
2100 */
2101 nau8825_sema_acquire(nau8825, 2 * HZ);
2102 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2103 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_BLK);
2104 /* Release the semaphone. */
2105 nau8825_sema_release(nau8825);
2106
2107 if (nau8825->mclk_freq) {
2108 clk_disable_unprepare(nau8825->mclk);
2109 nau8825->mclk_freq = 0;
2110 }
2111
2112 break;
2113 case NAU8825_CLK_FLL_FS:
2114 /* Acquire the semaphone to synchronize the playback and
2115 * interrupt handler. In order to avoid the playback inter-
2116 * fered by cross talk process, the driver make the playback
2117 * preparation halted until cross talk process finish.
2118 */
2119 nau8825_sema_acquire(nau8825, 2 * HZ);
2120 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2121 NAU8825_FLL_CLK_SRC_MASK, NAU8825_FLL_CLK_SRC_FS);
2122 /* Release the semaphone. */
2123 nau8825_sema_release(nau8825);
2124
2125 if (nau8825->mclk_freq) {
2126 clk_disable_unprepare(nau8825->mclk);
2127 nau8825->mclk_freq = 0;
2128 }
2129
2130 break;
2131 default:
2132 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2133 return -EINVAL;
2134 }
2135
2136 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2137 clk_id);
2138 return 0;
2139 }
2140
2141 static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2142 int source, unsigned int freq, int dir)
2143 {
2144 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2145
2146 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2147 }
2148
2149 static int nau8825_resume_setup(struct nau8825 *nau8825)
2150 {
2151 struct regmap *regmap = nau8825->regmap;
2152
2153 /* Close clock when jack type detection at manual mode */
2154 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2155
2156 /* Clear all interruption status */
2157 nau8825_int_status_clear_all(regmap);
2158
2159 /* Enable both insertion and ejection interruptions, and then
2160 * bypass de-bounce circuit.
2161 */
2162 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2163 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2164 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2165 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2166 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2167 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2168 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2169 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2170
2171 return 0;
2172 }
2173
2174 static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2175 enum snd_soc_bias_level level)
2176 {
2177 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2178 int ret;
2179
2180 switch (level) {
2181 case SND_SOC_BIAS_ON:
2182 break;
2183
2184 case SND_SOC_BIAS_PREPARE:
2185 break;
2186
2187 case SND_SOC_BIAS_STANDBY:
2188 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2189 if (nau8825->mclk_freq) {
2190 ret = clk_prepare_enable(nau8825->mclk);
2191 if (ret) {
2192 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2193 return ret;
2194 }
2195 }
2196 /* Setup codec configuration after resume */
2197 nau8825_resume_setup(nau8825);
2198 }
2199 break;
2200
2201 case SND_SOC_BIAS_OFF:
2202 /* Cancel and reset cross talk detection funciton */
2203 nau8825_xtalk_cancel(nau8825);
2204 /* Turn off all interruptions before system shutdown. Keep the
2205 * interruption quiet before resume setup completes.
2206 */
2207 regmap_write(nau8825->regmap,
2208 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2209 /* Disable ADC needed for interruptions at audo mode */
2210 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2211 NAU8825_ENABLE_ADC, 0);
2212 if (nau8825->mclk_freq)
2213 clk_disable_unprepare(nau8825->mclk);
2214 break;
2215 }
2216 return 0;
2217 }
2218
2219 static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2220 {
2221 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2222
2223 disable_irq(nau8825->irq);
2224 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2225 regcache_cache_only(nau8825->regmap, true);
2226 regcache_mark_dirty(nau8825->regmap);
2227
2228 return 0;
2229 }
2230
2231 static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2232 {
2233 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2234
2235 regcache_cache_only(nau8825->regmap, false);
2236 regcache_sync(nau8825->regmap);
2237 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2238 /* If the jack is inserted, we need to check whether the play-
2239 * back is active before suspend. If active, the driver has to
2240 * raise the protection for cross talk function to avoid the
2241 * playback recovers before cross talk process finish. Other-
2242 * wise, the playback will be interfered by cross talk func-
2243 * tion. It is better to apply hardware related parameters
2244 * before starting playback or record.
2245 */
2246 if (nau8825_dai_is_active(nau8825)) {
2247 nau8825->xtalk_protect = true;
2248 nau8825_sema_acquire(nau8825, 0);
2249 }
2250 }
2251 enable_irq(nau8825->irq);
2252
2253 return 0;
2254 }
2255
2256 static struct snd_soc_codec_driver nau8825_codec_driver = {
2257 .probe = nau8825_codec_probe,
2258 .remove = nau8825_codec_remove,
2259 .set_sysclk = nau8825_set_sysclk,
2260 .set_pll = nau8825_set_pll,
2261 .set_bias_level = nau8825_set_bias_level,
2262 .suspend_bias_off = true,
2263 .suspend = nau8825_suspend,
2264 .resume = nau8825_resume,
2265
2266 .controls = nau8825_controls,
2267 .num_controls = ARRAY_SIZE(nau8825_controls),
2268 .dapm_widgets = nau8825_dapm_widgets,
2269 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2270 .dapm_routes = nau8825_dapm_routes,
2271 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2272 };
2273
2274 static void nau8825_reset_chip(struct regmap *regmap)
2275 {
2276 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2277 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2278 }
2279
2280 static void nau8825_print_device_properties(struct nau8825 *nau8825)
2281 {
2282 int i;
2283 struct device *dev = nau8825->dev;
2284
2285 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2286 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2287 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2288 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2289 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2290 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2291
2292 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2293 for (i = 0; i < nau8825->sar_threshold_num; i++)
2294 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2295 nau8825->sar_threshold[i]);
2296
2297 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2298 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2299 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2300 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2301 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2302 dev_dbg(dev, "jack-insert-debounce: %d\n",
2303 nau8825->jack_insert_debounce);
2304 dev_dbg(dev, "jack-eject-debounce: %d\n",
2305 nau8825->jack_eject_debounce);
2306 }
2307
2308 static int nau8825_read_device_properties(struct device *dev,
2309 struct nau8825 *nau8825) {
2310
2311 nau8825->jkdet_enable = device_property_read_bool(dev,
2312 "nuvoton,jkdet-enable");
2313 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2314 "nuvoton,jkdet-pull-enable");
2315 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2316 "nuvoton,jkdet-pull-up");
2317 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2318 &nau8825->jkdet_polarity);
2319 device_property_read_u32(dev, "nuvoton,micbias-voltage",
2320 &nau8825->micbias_voltage);
2321 device_property_read_u32(dev, "nuvoton,vref-impedance",
2322 &nau8825->vref_impedance);
2323 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2324 &nau8825->sar_threshold_num);
2325 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2326 nau8825->sar_threshold, nau8825->sar_threshold_num);
2327 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2328 &nau8825->sar_hysteresis);
2329 device_property_read_u32(dev, "nuvoton,sar-voltage",
2330 &nau8825->sar_voltage);
2331 device_property_read_u32(dev, "nuvoton,sar-compare-time",
2332 &nau8825->sar_compare_time);
2333 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2334 &nau8825->sar_sampling_time);
2335 device_property_read_u32(dev, "nuvoton,short-key-debounce",
2336 &nau8825->key_debounce);
2337 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2338 &nau8825->jack_insert_debounce);
2339 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2340 &nau8825->jack_eject_debounce);
2341
2342 nau8825->mclk = devm_clk_get(dev, "mclk");
2343 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2344 return -EPROBE_DEFER;
2345 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2346 /* The MCLK is managed externally or not used at all */
2347 nau8825->mclk = NULL;
2348 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2349 } else if (IS_ERR(nau8825->mclk)) {
2350 return -EINVAL;
2351 }
2352
2353 return 0;
2354 }
2355
2356 static int nau8825_setup_irq(struct nau8825 *nau8825)
2357 {
2358 int ret;
2359
2360 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2361 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2362 "nau8825", nau8825);
2363
2364 if (ret) {
2365 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2366 nau8825->irq, ret);
2367 return ret;
2368 }
2369
2370 return 0;
2371 }
2372
2373 static int nau8825_i2c_probe(struct i2c_client *i2c,
2374 const struct i2c_device_id *id)
2375 {
2376 struct device *dev = &i2c->dev;
2377 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2378 int ret, value;
2379
2380 if (!nau8825) {
2381 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2382 if (!nau8825)
2383 return -ENOMEM;
2384 ret = nau8825_read_device_properties(dev, nau8825);
2385 if (ret)
2386 return ret;
2387 }
2388
2389 i2c_set_clientdata(i2c, nau8825);
2390
2391 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2392 if (IS_ERR(nau8825->regmap))
2393 return PTR_ERR(nau8825->regmap);
2394 nau8825->dev = dev;
2395 nau8825->irq = i2c->irq;
2396 /* Initiate parameters, semaphone and work queue which are needed in
2397 * cross talk suppression measurment function.
2398 */
2399 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2400 nau8825->xtalk_protect = false;
2401 sema_init(&nau8825->xtalk_sem, 1);
2402 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2403
2404 nau8825_print_device_properties(nau8825);
2405
2406 nau8825_reset_chip(nau8825->regmap);
2407 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2408 if (ret < 0) {
2409 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2410 ret);
2411 return ret;
2412 }
2413 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2414 NAU8825_SOFTWARE_ID_NAU8825) {
2415 dev_err(dev, "Not a NAU8825 chip\n");
2416 return -ENODEV;
2417 }
2418
2419 nau8825_init_regs(nau8825);
2420
2421 if (i2c->irq)
2422 nau8825_setup_irq(nau8825);
2423
2424 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2425 &nau8825_dai, 1);
2426 }
2427
2428 static int nau8825_i2c_remove(struct i2c_client *client)
2429 {
2430 snd_soc_unregister_codec(&client->dev);
2431 return 0;
2432 }
2433
2434 static const struct i2c_device_id nau8825_i2c_ids[] = {
2435 { "nau8825", 0 },
2436 { }
2437 };
2438 MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2439
2440 #ifdef CONFIG_OF
2441 static const struct of_device_id nau8825_of_ids[] = {
2442 { .compatible = "nuvoton,nau8825", },
2443 {}
2444 };
2445 MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2446 #endif
2447
2448 #ifdef CONFIG_ACPI
2449 static const struct acpi_device_id nau8825_acpi_match[] = {
2450 { "10508825", 0 },
2451 {},
2452 };
2453 MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2454 #endif
2455
2456 static struct i2c_driver nau8825_driver = {
2457 .driver = {
2458 .name = "nau8825",
2459 .of_match_table = of_match_ptr(nau8825_of_ids),
2460 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2461 },
2462 .probe = nau8825_i2c_probe,
2463 .remove = nau8825_i2c_remove,
2464 .id_table = nau8825_i2c_ids,
2465 };
2466 module_i2c_driver(nau8825_driver);
2467
2468 MODULE_DESCRIPTION("ASoC nau8825 driver");
2469 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2470 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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