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ASoC: tlv320aic3x: extending registers cache
[deliverable/linux.git] / sound / soc / codecs / tlv320aic3x.c
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/slab.h>
44 #include <sound/core.h>
45 #include <sound/pcm.h>
46 #include <sound/pcm_params.h>
47 #include <sound/soc.h>
48 #include <sound/initval.h>
49 #include <sound/tlv.h>
50 #include <sound/tlv320aic3x.h>
51
52 #include "tlv320aic3x.h"
53
54 #define AIC3X_NUM_SUPPLIES 4
55 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
56 "IOVDD", /* I/O Voltage */
57 "DVDD", /* Digital Core Voltage */
58 "AVDD", /* Analog DAC Voltage */
59 "DRVDD", /* ADC Analog and Output Driver Voltage */
60 };
61
62 static LIST_HEAD(reset_list);
63
64 struct aic3x_priv;
65
66 struct aic3x_disable_nb {
67 struct notifier_block nb;
68 struct aic3x_priv *aic3x;
69 };
70
71 /* codec private data */
72 struct aic3x_priv {
73 struct snd_soc_codec *codec;
74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
76 enum snd_soc_control_type control_type;
77 struct aic3x_setup_data *setup;
78 unsigned int sysclk;
79 struct list_head list;
80 int master;
81 int gpio_reset;
82 int power;
83 #define AIC3X_MODEL_3X 0
84 #define AIC3X_MODEL_33 1
85 #define AIC3X_MODEL_3007 2
86 u16 model;
87 };
88
89 /*
90 * AIC3X register cache
91 * We can't read the AIC3X register space when we are
92 * using 2 wire for device control, so we cache them instead.
93 * There is no point in caching the reset register
94 */
95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
96 0x00, 0x00, 0x00, 0x10, /* 0 */
97 0x04, 0x00, 0x00, 0x00, /* 4 */
98 0x00, 0x00, 0x00, 0x01, /* 8 */
99 0x00, 0x00, 0x00, 0x80, /* 12 */
100 0x80, 0xff, 0xff, 0x78, /* 16 */
101 0x78, 0x78, 0x78, 0x78, /* 20 */
102 0x78, 0x00, 0x00, 0xfe, /* 24 */
103 0x00, 0x00, 0xfe, 0x00, /* 28 */
104 0x18, 0x18, 0x00, 0x00, /* 32 */
105 0x00, 0x00, 0x00, 0x00, /* 36 */
106 0x00, 0x00, 0x00, 0x80, /* 40 */
107 0x80, 0x00, 0x00, 0x00, /* 44 */
108 0x00, 0x00, 0x00, 0x04, /* 48 */
109 0x00, 0x00, 0x00, 0x00, /* 52 */
110 0x00, 0x00, 0x04, 0x00, /* 56 */
111 0x00, 0x00, 0x00, 0x00, /* 60 */
112 0x00, 0x04, 0x00, 0x00, /* 64 */
113 0x00, 0x00, 0x00, 0x00, /* 68 */
114 0x04, 0x00, 0x00, 0x00, /* 72 */
115 0x00, 0x00, 0x00, 0x00, /* 76 */
116 0x00, 0x00, 0x00, 0x00, /* 80 */
117 0x00, 0x00, 0x00, 0x00, /* 84 */
118 0x00, 0x00, 0x00, 0x00, /* 88 */
119 0x00, 0x00, 0x00, 0x00, /* 92 */
120 0x00, 0x00, 0x00, 0x00, /* 96 */
121 0x00, 0x00, 0x02, 0x00, /* 100 */
122 0x00, 0x00, 0x00, 0x00, /* 104 */
123 0x00, 0x00, /* 108 */
124 };
125
126 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
128 .info = snd_soc_info_volsw, \
129 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
130 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
131
132 /*
133 * All input lines are connected when !0xf and disconnected with 0xf bit field,
134 * so we have to use specific dapm_put call for input mixer
135 */
136 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
137 struct snd_ctl_elem_value *ucontrol)
138 {
139 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
140 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
141 struct soc_mixer_control *mc =
142 (struct soc_mixer_control *)kcontrol->private_value;
143 unsigned int reg = mc->reg;
144 unsigned int shift = mc->shift;
145 int max = mc->max;
146 unsigned int mask = (1 << fls(max)) - 1;
147 unsigned int invert = mc->invert;
148 unsigned short val, val_mask;
149 int ret;
150 struct snd_soc_dapm_path *path;
151 int found = 0;
152
153 val = (ucontrol->value.integer.value[0] & mask);
154
155 mask = 0xf;
156 if (val)
157 val = mask;
158
159 if (invert)
160 val = mask - val;
161 val_mask = mask << shift;
162 val = val << shift;
163
164 mutex_lock(&widget->codec->mutex);
165
166 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
167 /* find dapm widget path assoc with kcontrol */
168 list_for_each_entry(path, &widget->dapm->card->paths, list) {
169 if (path->kcontrol != kcontrol)
170 continue;
171
172 /* found, now check type */
173 found = 1;
174 if (val)
175 /* new connection */
176 path->connect = invert ? 0 : 1;
177 else
178 /* old connection must be powered down */
179 path->connect = invert ? 1 : 0;
180
181 dapm_mark_dirty(path->source, "tlv320aic3x source");
182 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
183
184 break;
185 }
186
187 if (found)
188 snd_soc_dapm_sync(widget->dapm);
189 }
190
191 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
192
193 mutex_unlock(&widget->codec->mutex);
194 return ret;
195 }
196
197 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
198 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
199 static const char *aic3x_left_hpcom_mux[] =
200 { "differential of HPLOUT", "constant VCM", "single-ended" };
201 static const char *aic3x_right_hpcom_mux[] =
202 { "differential of HPROUT", "constant VCM", "single-ended",
203 "differential of HPLCOM", "external feedback" };
204 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
205 static const char *aic3x_adc_hpf[] =
206 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
207
208 #define LDAC_ENUM 0
209 #define RDAC_ENUM 1
210 #define LHPCOM_ENUM 2
211 #define RHPCOM_ENUM 3
212 #define LINE1L_2_L_ENUM 4
213 #define LINE1L_2_R_ENUM 5
214 #define LINE1R_2_L_ENUM 6
215 #define LINE1R_2_R_ENUM 7
216 #define LINE2L_ENUM 8
217 #define LINE2R_ENUM 9
218 #define ADC_HPF_ENUM 10
219
220 static const struct soc_enum aic3x_enum[] = {
221 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
222 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
223 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
224 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
225 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
226 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
227 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
229 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
230 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
231 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
232 };
233
234 /*
235 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
236 */
237 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
238 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
239 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
240 /*
241 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
242 * Step size is approximately 0.5 dB over most of the scale but increasing
243 * near the very low levels.
244 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
245 * but having increasing dB difference below that (and where it doesn't count
246 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
247 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
248 */
249 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
250
251 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
252 /* Output */
253 SOC_DOUBLE_R_TLV("PCM Playback Volume",
254 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
255
256 /*
257 * Output controls that map to output mixer switches. Note these are
258 * only for swapped L-to-R and R-to-L routes. See below stereo controls
259 * for direct L-to-L and R-to-R routes.
260 */
261 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
262 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
263 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
264 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
265 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
266 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
267
268 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
269 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
270 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
271 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
272 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
273 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
274
275 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
276 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
277 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
278 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
279 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
280 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
281
282 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
283 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
284 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
285 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
287 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
288
289 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
290 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
291 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
292 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
293 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
294 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
295
296 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
297 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
298 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
299 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
300 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
301 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
302
303 /* Stereo output controls for direct L-to-L and R-to-R routes */
304 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
305 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
306 0, 118, 1, output_stage_tlv),
307 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
308 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
309 0, 118, 1, output_stage_tlv),
310 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
311 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
312 0, 118, 1, output_stage_tlv),
313
314 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
315 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
316 0, 118, 1, output_stage_tlv),
317 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
318 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
319 0, 118, 1, output_stage_tlv),
320 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
321 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
322 0, 118, 1, output_stage_tlv),
323
324 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
325 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
326 0, 118, 1, output_stage_tlv),
327 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
328 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
329 0, 118, 1, output_stage_tlv),
330 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
331 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
332 0, 118, 1, output_stage_tlv),
333
334 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
335 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
336 0, 118, 1, output_stage_tlv),
337 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
338 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
339 0, 118, 1, output_stage_tlv),
340 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
341 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
342 0, 118, 1, output_stage_tlv),
343
344 /* Output pin mute controls */
345 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
346 0x01, 0),
347 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
348 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
349 0x01, 0),
350 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
351 0x01, 0),
352
353 /*
354 * Note: enable Automatic input Gain Controller with care. It can
355 * adjust PGA to max value when ADC is on and will never go back.
356 */
357 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
358
359 /* Input */
360 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
361 0, 119, 0, adc_tlv),
362 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
363
364 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
365 };
366
367 /*
368 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
369 */
370 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
371
372 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
373 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
374
375 /* Left DAC Mux */
376 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
377 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
378
379 /* Right DAC Mux */
380 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
381 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
382
383 /* Left HPCOM Mux */
384 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
385 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
386
387 /* Right HPCOM Mux */
388 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
389 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
390
391 /* Left Line Mixer */
392 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
393 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
394 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
395 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
396 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
397 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
398 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
399 };
400
401 /* Right Line Mixer */
402 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
403 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
404 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
405 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
406 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
409 };
410
411 /* Mono Mixer */
412 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
413 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
414 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
415 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
416 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
419 };
420
421 /* Left HP Mixer */
422 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
423 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
424 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
429 };
430
431 /* Right HP Mixer */
432 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
433 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
439 };
440
441 /* Left HPCOM Mixer */
442 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
443 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
449 };
450
451 /* Right HPCOM Mixer */
452 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
453 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
459 };
460
461 /* Left PGA Mixer */
462 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
463 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
464 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
465 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
466 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
467 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
468 };
469
470 /* Right PGA Mixer */
471 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
472 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
473 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
474 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
475 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
476 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
477 };
478
479 /* Left Line1 Mux */
480 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
481 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
482 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
483 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
484
485 /* Right Line1 Mux */
486 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
487 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
488 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
489 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
490
491 /* Left Line2 Mux */
492 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
493 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
494
495 /* Right Line2 Mux */
496 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
497 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
498
499 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
500 /* Left DAC to Left Outputs */
501 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
502 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
503 &aic3x_left_dac_mux_controls),
504 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
505 &aic3x_left_hpcom_mux_controls),
506 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
507 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
508 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
509
510 /* Right DAC to Right Outputs */
511 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
512 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
513 &aic3x_right_dac_mux_controls),
514 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
515 &aic3x_right_hpcom_mux_controls),
516 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
517 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
518 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
519
520 /* Mono Output */
521 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
522
523 /* Inputs to Left ADC */
524 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
525 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
526 &aic3x_left_pga_mixer_controls[0],
527 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
528 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
529 &aic3x_left_line1l_mux_controls),
530 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
531 &aic3x_left_line1r_mux_controls),
532 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
533 &aic3x_left_line2_mux_controls),
534
535 /* Inputs to Right ADC */
536 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
537 LINE1R_2_RADC_CTRL, 2, 0),
538 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
539 &aic3x_right_pga_mixer_controls[0],
540 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
541 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
542 &aic3x_right_line1l_mux_controls),
543 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
544 &aic3x_right_line1r_mux_controls),
545 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
546 &aic3x_right_line2_mux_controls),
547
548 /*
549 * Not a real mic bias widget but similar function. This is for dynamic
550 * control of GPIO1 digital mic modulator clock output function when
551 * using digital mic.
552 */
553 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
554 AIC3X_GPIO1_REG, 4, 0xf,
555 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
556 AIC3X_GPIO1_FUNC_DISABLED),
557
558 /*
559 * Also similar function like mic bias. Selects digital mic with
560 * configurable oversampling rate instead of ADC converter.
561 */
562 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
563 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
565 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
566 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
567 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
568
569 /* Mic Bias */
570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
571 MICBIAS_CTRL, 6, 3, 1, 0),
572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
573 MICBIAS_CTRL, 6, 3, 2, 0),
574 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
575 MICBIAS_CTRL, 6, 3, 3, 0),
576
577 /* Output mixers */
578 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
579 &aic3x_left_line_mixer_controls[0],
580 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
581 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
582 &aic3x_right_line_mixer_controls[0],
583 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
584 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
585 &aic3x_mono_mixer_controls[0],
586 ARRAY_SIZE(aic3x_mono_mixer_controls)),
587 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
588 &aic3x_left_hp_mixer_controls[0],
589 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
590 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
591 &aic3x_right_hp_mixer_controls[0],
592 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
593 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
594 &aic3x_left_hpcom_mixer_controls[0],
595 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
596 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
597 &aic3x_right_hpcom_mixer_controls[0],
598 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
599
600 SND_SOC_DAPM_OUTPUT("LLOUT"),
601 SND_SOC_DAPM_OUTPUT("RLOUT"),
602 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
603 SND_SOC_DAPM_OUTPUT("HPLOUT"),
604 SND_SOC_DAPM_OUTPUT("HPROUT"),
605 SND_SOC_DAPM_OUTPUT("HPLCOM"),
606 SND_SOC_DAPM_OUTPUT("HPRCOM"),
607
608 SND_SOC_DAPM_INPUT("MIC3L"),
609 SND_SOC_DAPM_INPUT("MIC3R"),
610 SND_SOC_DAPM_INPUT("LINE1L"),
611 SND_SOC_DAPM_INPUT("LINE1R"),
612 SND_SOC_DAPM_INPUT("LINE2L"),
613 SND_SOC_DAPM_INPUT("LINE2R"),
614
615 /*
616 * Virtual output pin to detection block inside codec. This can be
617 * used to keep codec bias on if gpio or detection features are needed.
618 * Force pin on or construct a path with an input jack and mic bias
619 * widgets.
620 */
621 SND_SOC_DAPM_OUTPUT("Detection"),
622 };
623
624 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
625 /* Class-D outputs */
626 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
627 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
628
629 SND_SOC_DAPM_OUTPUT("SPOP"),
630 SND_SOC_DAPM_OUTPUT("SPOM"),
631 };
632
633 static const struct snd_soc_dapm_route intercon[] = {
634 /* Left Input */
635 {"Left Line1L Mux", "single-ended", "LINE1L"},
636 {"Left Line1L Mux", "differential", "LINE1L"},
637
638 {"Left Line2L Mux", "single-ended", "LINE2L"},
639 {"Left Line2L Mux", "differential", "LINE2L"},
640
641 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
642 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
643 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
644 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
645 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
646
647 {"Left ADC", NULL, "Left PGA Mixer"},
648 {"Left ADC", NULL, "GPIO1 dmic modclk"},
649
650 /* Right Input */
651 {"Right Line1R Mux", "single-ended", "LINE1R"},
652 {"Right Line1R Mux", "differential", "LINE1R"},
653
654 {"Right Line2R Mux", "single-ended", "LINE2R"},
655 {"Right Line2R Mux", "differential", "LINE2R"},
656
657 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
658 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
659 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
660 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
661 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
662
663 {"Right ADC", NULL, "Right PGA Mixer"},
664 {"Right ADC", NULL, "GPIO1 dmic modclk"},
665
666 /*
667 * Logical path between digital mic enable and GPIO1 modulator clock
668 * output function
669 */
670 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
671 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
672 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
673
674 /* Left DAC Output */
675 {"Left DAC Mux", "DAC_L1", "Left DAC"},
676 {"Left DAC Mux", "DAC_L2", "Left DAC"},
677 {"Left DAC Mux", "DAC_L3", "Left DAC"},
678
679 /* Right DAC Output */
680 {"Right DAC Mux", "DAC_R1", "Right DAC"},
681 {"Right DAC Mux", "DAC_R2", "Right DAC"},
682 {"Right DAC Mux", "DAC_R3", "Right DAC"},
683
684 /* Left Line Output */
685 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
686 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
687 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
688 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
689 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
690 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
691
692 {"Left Line Out", NULL, "Left Line Mixer"},
693 {"Left Line Out", NULL, "Left DAC Mux"},
694 {"LLOUT", NULL, "Left Line Out"},
695
696 /* Right Line Output */
697 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
698 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
699 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
700 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
701 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
702 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
703
704 {"Right Line Out", NULL, "Right Line Mixer"},
705 {"Right Line Out", NULL, "Right DAC Mux"},
706 {"RLOUT", NULL, "Right Line Out"},
707
708 /* Mono Output */
709 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
710 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
711 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
712 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
713 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
714 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
715
716 {"Mono Out", NULL, "Mono Mixer"},
717 {"MONO_LOUT", NULL, "Mono Out"},
718
719 /* Left HP Output */
720 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
721 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
722 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
723 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
724 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
725 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
726
727 {"Left HP Out", NULL, "Left HP Mixer"},
728 {"Left HP Out", NULL, "Left DAC Mux"},
729 {"HPLOUT", NULL, "Left HP Out"},
730
731 /* Right HP Output */
732 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
733 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
734 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
735 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
736 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
737 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
738
739 {"Right HP Out", NULL, "Right HP Mixer"},
740 {"Right HP Out", NULL, "Right DAC Mux"},
741 {"HPROUT", NULL, "Right HP Out"},
742
743 /* Left HPCOM Output */
744 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
745 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
746 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
747 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
748 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
749 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
750
751 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
752 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
753 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
754 {"Left HP Com", NULL, "Left HPCOM Mux"},
755 {"HPLCOM", NULL, "Left HP Com"},
756
757 /* Right HPCOM Output */
758 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
759 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
760 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
761 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
762 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
763 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
764
765 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
766 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
767 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
768 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
769 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
770 {"Right HP Com", NULL, "Right HPCOM Mux"},
771 {"HPRCOM", NULL, "Right HP Com"},
772 };
773
774 static const struct snd_soc_dapm_route intercon_3007[] = {
775 /* Class-D outputs */
776 {"Left Class-D Out", NULL, "Left Line Out"},
777 {"Right Class-D Out", NULL, "Left Line Out"},
778 {"SPOP", NULL, "Left Class-D Out"},
779 {"SPOM", NULL, "Right Class-D Out"},
780 };
781
782 static int aic3x_add_widgets(struct snd_soc_codec *codec)
783 {
784 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
785 struct snd_soc_dapm_context *dapm = &codec->dapm;
786
787 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
788 ARRAY_SIZE(aic3x_dapm_widgets));
789
790 /* set up audio path interconnects */
791 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
792
793 if (aic3x->model == AIC3X_MODEL_3007) {
794 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
795 ARRAY_SIZE(aic3007_dapm_widgets));
796 snd_soc_dapm_add_routes(dapm, intercon_3007,
797 ARRAY_SIZE(intercon_3007));
798 }
799
800 return 0;
801 }
802
803 static int aic3x_hw_params(struct snd_pcm_substream *substream,
804 struct snd_pcm_hw_params *params,
805 struct snd_soc_dai *dai)
806 {
807 struct snd_soc_codec *codec = dai->codec;
808 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
809 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
810 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
811 u16 d, pll_d = 1;
812 int clk;
813
814 /* select data word length */
815 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
816 switch (params_format(params)) {
817 case SNDRV_PCM_FORMAT_S16_LE:
818 break;
819 case SNDRV_PCM_FORMAT_S20_3LE:
820 data |= (0x01 << 4);
821 break;
822 case SNDRV_PCM_FORMAT_S24_LE:
823 data |= (0x02 << 4);
824 break;
825 case SNDRV_PCM_FORMAT_S32_LE:
826 data |= (0x03 << 4);
827 break;
828 }
829 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
830
831 /* Fsref can be 44100 or 48000 */
832 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
833
834 /* Try to find a value for Q which allows us to bypass the PLL and
835 * generate CODEC_CLK directly. */
836 for (pll_q = 2; pll_q < 18; pll_q++)
837 if (aic3x->sysclk / (128 * pll_q) == fsref) {
838 bypass_pll = 1;
839 break;
840 }
841
842 if (bypass_pll) {
843 pll_q &= 0xf;
844 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
845 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
846 /* disable PLL if it is bypassed */
847 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
848
849 } else {
850 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
851 /* enable PLL when it is used */
852 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
853 PLL_ENABLE, PLL_ENABLE);
854 }
855
856 /* Route Left DAC to left channel input and
857 * right DAC to right channel input */
858 data = (LDAC2LCH | RDAC2RCH);
859 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
860 if (params_rate(params) >= 64000)
861 data |= DUAL_RATE_MODE;
862 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
863
864 /* codec sample rate select */
865 data = (fsref * 20) / params_rate(params);
866 if (params_rate(params) < 64000)
867 data /= 2;
868 data /= 5;
869 data -= 2;
870 data |= (data << 4);
871 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
872
873 if (bypass_pll)
874 return 0;
875
876 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
877 * one wins the game. Try with d==0 first, next with d!=0.
878 * Constraints for j are according to the datasheet.
879 * The sysclk is divided by 1000 to prevent integer overflows.
880 */
881
882 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
883
884 for (r = 1; r <= 16; r++)
885 for (p = 1; p <= 8; p++) {
886 for (j = 4; j <= 55; j++) {
887 /* This is actually 1000*((j+(d/10000))*r)/p
888 * The term had to be converted to get
889 * rid of the division by 10000; d = 0 here
890 */
891 int tmp_clk = (1000 * j * r) / p;
892
893 /* Check whether this values get closer than
894 * the best ones we had before
895 */
896 if (abs(codec_clk - tmp_clk) <
897 abs(codec_clk - last_clk)) {
898 pll_j = j; pll_d = 0;
899 pll_r = r; pll_p = p;
900 last_clk = tmp_clk;
901 }
902
903 /* Early exit for exact matches */
904 if (tmp_clk == codec_clk)
905 goto found;
906 }
907 }
908
909 /* try with d != 0 */
910 for (p = 1; p <= 8; p++) {
911 j = codec_clk * p / 1000;
912
913 if (j < 4 || j > 11)
914 continue;
915
916 /* do not use codec_clk here since we'd loose precision */
917 d = ((2048 * p * fsref) - j * aic3x->sysclk)
918 * 100 / (aic3x->sysclk/100);
919
920 clk = (10000 * j + d) / (10 * p);
921
922 /* check whether this values get closer than the best
923 * ones we had before */
924 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
925 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
926 last_clk = clk;
927 }
928
929 /* Early exit for exact matches */
930 if (clk == codec_clk)
931 goto found;
932 }
933
934 if (last_clk == 0) {
935 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
936 return -EINVAL;
937 }
938
939 found:
940 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
941 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
942 data | (pll_p << PLLP_SHIFT));
943 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
944 pll_r << PLLR_SHIFT);
945 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
946 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
947 (pll_d >> 6) << PLLD_MSB_SHIFT);
948 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
949 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
950
951 return 0;
952 }
953
954 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
955 {
956 struct snd_soc_codec *codec = dai->codec;
957 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
958 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
959
960 if (mute) {
961 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
962 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
963 } else {
964 snd_soc_write(codec, LDAC_VOL, ldac_reg);
965 snd_soc_write(codec, RDAC_VOL, rdac_reg);
966 }
967
968 return 0;
969 }
970
971 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
972 int clk_id, unsigned int freq, int dir)
973 {
974 struct snd_soc_codec *codec = codec_dai->codec;
975 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
976
977 aic3x->sysclk = freq;
978 return 0;
979 }
980
981 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
982 unsigned int fmt)
983 {
984 struct snd_soc_codec *codec = codec_dai->codec;
985 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
986 u8 iface_areg, iface_breg;
987 int delay = 0;
988
989 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
990 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
991
992 /* set master/slave audio interface */
993 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
994 case SND_SOC_DAIFMT_CBM_CFM:
995 aic3x->master = 1;
996 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
997 break;
998 case SND_SOC_DAIFMT_CBS_CFS:
999 aic3x->master = 0;
1000 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1001 break;
1002 default:
1003 return -EINVAL;
1004 }
1005
1006 /*
1007 * match both interface format and signal polarities since they
1008 * are fixed
1009 */
1010 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1011 SND_SOC_DAIFMT_INV_MASK)) {
1012 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1013 break;
1014 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1015 delay = 1;
1016 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1017 iface_breg |= (0x01 << 6);
1018 break;
1019 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1020 iface_breg |= (0x02 << 6);
1021 break;
1022 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1023 iface_breg |= (0x03 << 6);
1024 break;
1025 default:
1026 return -EINVAL;
1027 }
1028
1029 /* set iface */
1030 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1031 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1032 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1033
1034 return 0;
1035 }
1036
1037 static int aic3x_init_3007(struct snd_soc_codec *codec)
1038 {
1039 u8 tmp1, tmp2, *cache = codec->reg_cache;
1040
1041 /*
1042 * There is no need to cache writes to undocumented page 0xD but
1043 * respective page 0 register cache entries must be preserved
1044 */
1045 tmp1 = cache[0xD];
1046 tmp2 = cache[0x8];
1047 /* Class-D speaker driver init; datasheet p. 46 */
1048 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1049 snd_soc_write(codec, 0xD, 0x0D);
1050 snd_soc_write(codec, 0x8, 0x5C);
1051 snd_soc_write(codec, 0x8, 0x5D);
1052 snd_soc_write(codec, 0x8, 0x5C);
1053 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1054 cache[0xD] = tmp1;
1055 cache[0x8] = tmp2;
1056
1057 return 0;
1058 }
1059
1060 static int aic3x_regulator_event(struct notifier_block *nb,
1061 unsigned long event, void *data)
1062 {
1063 struct aic3x_disable_nb *disable_nb =
1064 container_of(nb, struct aic3x_disable_nb, nb);
1065 struct aic3x_priv *aic3x = disable_nb->aic3x;
1066
1067 if (event & REGULATOR_EVENT_DISABLE) {
1068 /*
1069 * Put codec to reset and require cache sync as at least one
1070 * of the supplies was disabled
1071 */
1072 if (gpio_is_valid(aic3x->gpio_reset))
1073 gpio_set_value(aic3x->gpio_reset, 0);
1074 aic3x->codec->cache_sync = 1;
1075 }
1076
1077 return 0;
1078 }
1079
1080 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1081 {
1082 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1083 int i, ret;
1084 u8 *cache = codec->reg_cache;
1085
1086 if (power) {
1087 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1088 aic3x->supplies);
1089 if (ret)
1090 goto out;
1091 aic3x->power = 1;
1092 /*
1093 * Reset release and cache sync is necessary only if some
1094 * supply was off or if there were cached writes
1095 */
1096 if (!codec->cache_sync)
1097 goto out;
1098
1099 if (gpio_is_valid(aic3x->gpio_reset)) {
1100 udelay(1);
1101 gpio_set_value(aic3x->gpio_reset, 1);
1102 }
1103
1104 /* Sync reg_cache with the hardware */
1105 codec->cache_only = 0;
1106 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
1107 snd_soc_write(codec, i, cache[i]);
1108 if (aic3x->model == AIC3X_MODEL_3007)
1109 aic3x_init_3007(codec);
1110 codec->cache_sync = 0;
1111 } else {
1112 /*
1113 * Do soft reset to this codec instance in order to clear
1114 * possible VDD leakage currents in case the supply regulators
1115 * remain on
1116 */
1117 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1118 codec->cache_sync = 1;
1119 aic3x->power = 0;
1120 /* HW writes are needless when bias is off */
1121 codec->cache_only = 1;
1122 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1123 aic3x->supplies);
1124 }
1125 out:
1126 return ret;
1127 }
1128
1129 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1130 enum snd_soc_bias_level level)
1131 {
1132 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1133
1134 switch (level) {
1135 case SND_SOC_BIAS_ON:
1136 break;
1137 case SND_SOC_BIAS_PREPARE:
1138 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1139 aic3x->master) {
1140 /* enable pll */
1141 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1142 PLL_ENABLE, PLL_ENABLE);
1143 }
1144 break;
1145 case SND_SOC_BIAS_STANDBY:
1146 if (!aic3x->power)
1147 aic3x_set_power(codec, 1);
1148 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1149 aic3x->master) {
1150 /* disable pll */
1151 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1152 PLL_ENABLE, 0);
1153 }
1154 break;
1155 case SND_SOC_BIAS_OFF:
1156 if (aic3x->power)
1157 aic3x_set_power(codec, 0);
1158 break;
1159 }
1160 codec->dapm.bias_level = level;
1161
1162 return 0;
1163 }
1164
1165 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1166 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1167 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1168
1169 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1170 .hw_params = aic3x_hw_params,
1171 .digital_mute = aic3x_mute,
1172 .set_sysclk = aic3x_set_dai_sysclk,
1173 .set_fmt = aic3x_set_dai_fmt,
1174 };
1175
1176 static struct snd_soc_dai_driver aic3x_dai = {
1177 .name = "tlv320aic3x-hifi",
1178 .playback = {
1179 .stream_name = "Playback",
1180 .channels_min = 1,
1181 .channels_max = 2,
1182 .rates = AIC3X_RATES,
1183 .formats = AIC3X_FORMATS,},
1184 .capture = {
1185 .stream_name = "Capture",
1186 .channels_min = 1,
1187 .channels_max = 2,
1188 .rates = AIC3X_RATES,
1189 .formats = AIC3X_FORMATS,},
1190 .ops = &aic3x_dai_ops,
1191 .symmetric_rates = 1,
1192 };
1193
1194 static int aic3x_suspend(struct snd_soc_codec *codec)
1195 {
1196 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1197
1198 return 0;
1199 }
1200
1201 static int aic3x_resume(struct snd_soc_codec *codec)
1202 {
1203 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1204
1205 return 0;
1206 }
1207
1208 /*
1209 * initialise the AIC3X driver
1210 * register the mixer and dsp interfaces with the kernel
1211 */
1212 static int aic3x_init(struct snd_soc_codec *codec)
1213 {
1214 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1215
1216 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1217 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1218
1219 /* DAC default volume and mute */
1220 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1221 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1222
1223 /* DAC to HP default volume and route to Output mixer */
1224 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1225 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1226 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1227 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1228 /* DAC to Line Out default volume and route to Output mixer */
1229 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1230 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1231 /* DAC to Mono Line Out default volume and route to Output mixer */
1232 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1233 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1234
1235 /* unmute all outputs */
1236 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1237 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1238 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1239 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1240 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1241 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1242 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1243
1244 /* ADC default volume and unmute */
1245 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1246 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1247 /* By default route Line1 to ADC PGA mixer */
1248 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1249 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1250
1251 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1252 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1253 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1254 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1255 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1256 /* PGA to Line Out default volume, disconnect from Output Mixer */
1257 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1258 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1259 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1260 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1261 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1262
1263 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1264 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1265 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1266 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1267 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1268 /* Line2 Line Out default volume, disconnect from Output Mixer */
1269 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1270 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1271 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1272 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1273 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1274
1275 if (aic3x->model == AIC3X_MODEL_3007) {
1276 aic3x_init_3007(codec);
1277 snd_soc_write(codec, CLASSD_CTRL, 0);
1278 }
1279
1280 return 0;
1281 }
1282
1283 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1284 {
1285 struct aic3x_priv *a;
1286
1287 list_for_each_entry(a, &reset_list, list) {
1288 if (gpio_is_valid(aic3x->gpio_reset) &&
1289 aic3x->gpio_reset == a->gpio_reset)
1290 return true;
1291 }
1292
1293 return false;
1294 }
1295
1296 static int aic3x_probe(struct snd_soc_codec *codec)
1297 {
1298 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1299 int ret, i;
1300
1301 INIT_LIST_HEAD(&aic3x->list);
1302 aic3x->codec = codec;
1303
1304 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1305 if (ret != 0) {
1306 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1307 return ret;
1308 }
1309
1310 if (gpio_is_valid(aic3x->gpio_reset) &&
1311 !aic3x_is_shared_reset(aic3x)) {
1312 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1313 if (ret != 0)
1314 goto err_gpio;
1315 gpio_direction_output(aic3x->gpio_reset, 0);
1316 }
1317
1318 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1319 aic3x->supplies[i].supply = aic3x_supply_names[i];
1320
1321 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1322 aic3x->supplies);
1323 if (ret != 0) {
1324 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1325 goto err_get;
1326 }
1327 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1328 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1329 aic3x->disable_nb[i].aic3x = aic3x;
1330 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1331 &aic3x->disable_nb[i].nb);
1332 if (ret) {
1333 dev_err(codec->dev,
1334 "Failed to request regulator notifier: %d\n",
1335 ret);
1336 goto err_notif;
1337 }
1338 }
1339
1340 codec->cache_only = 1;
1341 aic3x_init(codec);
1342
1343 if (aic3x->setup) {
1344 /* setup GPIO functions */
1345 snd_soc_write(codec, AIC3X_GPIO1_REG,
1346 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1347 snd_soc_write(codec, AIC3X_GPIO2_REG,
1348 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1349 }
1350
1351 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
1352 ARRAY_SIZE(aic3x_snd_controls));
1353 if (aic3x->model == AIC3X_MODEL_3007)
1354 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1355
1356 aic3x_add_widgets(codec);
1357 list_add(&aic3x->list, &reset_list);
1358
1359 return 0;
1360
1361 err_notif:
1362 while (i--)
1363 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1364 &aic3x->disable_nb[i].nb);
1365 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1366 err_get:
1367 if (gpio_is_valid(aic3x->gpio_reset) &&
1368 !aic3x_is_shared_reset(aic3x))
1369 gpio_free(aic3x->gpio_reset);
1370 err_gpio:
1371 return ret;
1372 }
1373
1374 static int aic3x_remove(struct snd_soc_codec *codec)
1375 {
1376 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1377 int i;
1378
1379 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1380 list_del(&aic3x->list);
1381 if (gpio_is_valid(aic3x->gpio_reset) &&
1382 !aic3x_is_shared_reset(aic3x)) {
1383 gpio_set_value(aic3x->gpio_reset, 0);
1384 gpio_free(aic3x->gpio_reset);
1385 }
1386 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1387 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1388 &aic3x->disable_nb[i].nb);
1389 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1390
1391 return 0;
1392 }
1393
1394 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1395 .set_bias_level = aic3x_set_bias_level,
1396 .idle_bias_off = true,
1397 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1398 .reg_word_size = sizeof(u8),
1399 .reg_cache_default = aic3x_reg,
1400 .probe = aic3x_probe,
1401 .remove = aic3x_remove,
1402 .suspend = aic3x_suspend,
1403 .resume = aic3x_resume,
1404 };
1405
1406 /*
1407 * AIC3X 2 wire address can be up to 4 devices with device addresses
1408 * 0x18, 0x19, 0x1A, 0x1B
1409 */
1410
1411 static const struct i2c_device_id aic3x_i2c_id[] = {
1412 { "tlv320aic3x", AIC3X_MODEL_3X },
1413 { "tlv320aic33", AIC3X_MODEL_33 },
1414 { "tlv320aic3007", AIC3X_MODEL_3007 },
1415 { }
1416 };
1417 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1418
1419 /*
1420 * If the i2c layer weren't so broken, we could pass this kind of data
1421 * around
1422 */
1423 static int aic3x_i2c_probe(struct i2c_client *i2c,
1424 const struct i2c_device_id *id)
1425 {
1426 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1427 struct aic3x_priv *aic3x;
1428 int ret;
1429
1430 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1431 if (aic3x == NULL) {
1432 dev_err(&i2c->dev, "failed to create private data\n");
1433 return -ENOMEM;
1434 }
1435
1436 aic3x->control_type = SND_SOC_I2C;
1437
1438 i2c_set_clientdata(i2c, aic3x);
1439 if (pdata) {
1440 aic3x->gpio_reset = pdata->gpio_reset;
1441 aic3x->setup = pdata->setup;
1442 } else {
1443 aic3x->gpio_reset = -1;
1444 }
1445
1446 aic3x->model = id->driver_data;
1447
1448 ret = snd_soc_register_codec(&i2c->dev,
1449 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1450 return ret;
1451 }
1452
1453 static int aic3x_i2c_remove(struct i2c_client *client)
1454 {
1455 snd_soc_unregister_codec(&client->dev);
1456 return 0;
1457 }
1458
1459 /* machine i2c codec control layer */
1460 static struct i2c_driver aic3x_i2c_driver = {
1461 .driver = {
1462 .name = "tlv320aic3x-codec",
1463 .owner = THIS_MODULE,
1464 },
1465 .probe = aic3x_i2c_probe,
1466 .remove = aic3x_i2c_remove,
1467 .id_table = aic3x_i2c_id,
1468 };
1469
1470 static int __init aic3x_modinit(void)
1471 {
1472 int ret = 0;
1473 ret = i2c_add_driver(&aic3x_i2c_driver);
1474 if (ret != 0) {
1475 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1476 ret);
1477 }
1478 return ret;
1479 }
1480 module_init(aic3x_modinit);
1481
1482 static void __exit aic3x_exit(void)
1483 {
1484 i2c_del_driver(&aic3x_i2c_driver);
1485 }
1486 module_exit(aic3x_exit);
1487
1488 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1489 MODULE_AUTHOR("Vladimir Barinov");
1490 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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