2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/interrupt.h>
31 #include <linux/gpio.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/slab.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/initval.h>
39 #include <sound/tlv.h>
41 #include <sound/tlv320dac33-plat.h>
42 #include "tlv320dac33.h"
45 * The internal FIFO is 24576 bytes long
46 * It can be configured to hold 16bit or 24bit samples
47 * In 16bit configuration the FIFO can hold 6144 stereo samples
48 * In 24bit configuration the FIFO can hold 4096 stereo samples
50 #define DAC33_FIFO_SIZE_16BIT 6144
51 #define DAC33_FIFO_SIZE_24BIT 4096
52 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
54 #define BURST_BASEFREQ_HZ 49152000
56 #define SAMPLES_TO_US(rate, samples) \
57 (1000000000 / (((rate) * 1000) / (samples)))
59 #define US_TO_SAMPLES(rate, us) \
60 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000)))
62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
65 static void dac33_calculate_times(struct snd_pcm_substream
*substream
);
66 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
);
75 enum dac33_fifo_modes
{
76 DAC33_FIFO_BYPASS
= 0,
82 #define DAC33_NUM_SUPPLIES 3
83 static const char *dac33_supply_names
[DAC33_NUM_SUPPLIES
] = {
89 struct tlv320dac33_priv
{
91 struct workqueue_struct
*dac33_wq
;
92 struct work_struct work
;
93 struct snd_soc_codec
*codec
;
94 struct regulator_bulk_data supplies
[DAC33_NUM_SUPPLIES
];
95 struct snd_pcm_substream
*substream
;
101 unsigned int alarm_threshold
; /* set to be half of LATENCY_TIME_MS */
102 enum dac33_fifo_modes fifo_mode
;/* FIFO mode selection */
103 unsigned int fifo_size
; /* Size of the FIFO in samples */
104 unsigned int nsample
; /* burst read amount from host */
105 int mode1_latency
; /* latency caused by the i2c writes in
107 u8 burst_bclkdiv
; /* BCLK divider value in burst mode */
108 unsigned int burst_rate
; /* Interface speed in Burst modes */
110 int keep_bclk
; /* Keep the BCLK continuously running
113 unsigned long long t_stamp1
; /* Time stamp for FIFO modes to */
114 unsigned long long t_stamp2
; /* calculate the FIFO caused delay */
116 unsigned int mode1_us_burst
; /* Time to burst read n number of
118 unsigned int mode7_us_to_lthr
; /* Time to reach lthr from uthr */
122 enum dac33_state state
;
123 enum snd_soc_control_type control_type
;
127 static const u8 dac33_reg
[DAC33_CACHEREGNUM
] = {
128 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
129 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
130 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
131 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
132 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
133 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
134 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
135 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
136 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
137 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
138 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
139 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
140 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
141 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
142 0x00, 0x00, /* 0x38 - 0x39 */
143 /* Registers 0x3a - 0x3f are reserved */
144 0x00, 0x00, /* 0x3a - 0x3b */
145 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
147 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
148 0x00, 0x80, /* 0x44 - 0x45 */
149 /* Registers 0x46 - 0x47 are reserved */
150 0x80, 0x80, /* 0x46 - 0x47 */
152 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
153 /* Registers 0x4b - 0x7c are reserved */
155 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
156 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
157 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
158 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
159 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
160 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
161 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
162 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
163 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
164 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
165 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
166 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
169 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
172 /* Register read and write */
173 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec
*codec
,
176 u8
*cache
= codec
->reg_cache
;
177 if (reg
>= DAC33_CACHEREGNUM
)
183 static inline void dac33_write_reg_cache(struct snd_soc_codec
*codec
,
186 u8
*cache
= codec
->reg_cache
;
187 if (reg
>= DAC33_CACHEREGNUM
)
193 static int dac33_read(struct snd_soc_codec
*codec
, unsigned int reg
,
196 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
201 /* If powered off, return the cached value */
202 if (dac33
->chip_power
) {
203 val
= i2c_smbus_read_byte_data(codec
->control_data
, value
[0]);
205 dev_err(codec
->dev
, "Read failed (%d)\n", val
);
206 value
[0] = dac33_read_reg_cache(codec
, reg
);
210 dac33_write_reg_cache(codec
, reg
, val
);
213 value
[0] = dac33_read_reg_cache(codec
, reg
);
219 static int dac33_write(struct snd_soc_codec
*codec
, unsigned int reg
,
222 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
228 * D15..D8 dac33 register offset
229 * D7...D0 register data
231 data
[0] = reg
& 0xff;
232 data
[1] = value
& 0xff;
234 dac33_write_reg_cache(codec
, data
[0], data
[1]);
235 if (dac33
->chip_power
) {
236 ret
= codec
->hw_write(codec
->control_data
, data
, 2);
238 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
246 static int dac33_write_locked(struct snd_soc_codec
*codec
, unsigned int reg
,
249 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
252 mutex_lock(&dac33
->mutex
);
253 ret
= dac33_write(codec
, reg
, value
);
254 mutex_unlock(&dac33
->mutex
);
259 #define DAC33_I2C_ADDR_AUTOINC 0x80
260 static int dac33_write16(struct snd_soc_codec
*codec
, unsigned int reg
,
263 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
269 * D23..D16 dac33 register offset
270 * D15..D8 register data MSB
271 * D7...D0 register data LSB
273 data
[0] = reg
& 0xff;
274 data
[1] = (value
>> 8) & 0xff;
275 data
[2] = value
& 0xff;
277 dac33_write_reg_cache(codec
, data
[0], data
[1]);
278 dac33_write_reg_cache(codec
, data
[0] + 1, data
[2]);
280 if (dac33
->chip_power
) {
281 /* We need to set autoincrement mode for 16 bit writes */
282 data
[0] |= DAC33_I2C_ADDR_AUTOINC
;
283 ret
= codec
->hw_write(codec
->control_data
, data
, 3);
285 dev_err(codec
->dev
, "Write failed (%d)\n", ret
);
293 static void dac33_init_chip(struct snd_soc_codec
*codec
)
295 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
297 if (unlikely(!dac33
->chip_power
))
300 /* A : DAC sample rate Fsref/1.5 */
301 dac33_write(codec
, DAC33_DAC_CTRL_A
, DAC33_DACRATE(0));
302 /* B : DAC src=normal, not muted */
303 dac33_write(codec
, DAC33_DAC_CTRL_B
, DAC33_DACSRCR_RIGHT
|
306 dac33_write(codec
, DAC33_DAC_CTRL_C
, 0x00);
308 /* 73 : volume soft stepping control,
309 clock source = internal osc (?) */
310 dac33_write(codec
, DAC33_ANA_VOL_SOFT_STEP_CTRL
, DAC33_VOLCLKEN
);
312 /* Restore only selected registers (gains mostly) */
313 dac33_write(codec
, DAC33_LDAC_DIG_VOL_CTRL
,
314 dac33_read_reg_cache(codec
, DAC33_LDAC_DIG_VOL_CTRL
));
315 dac33_write(codec
, DAC33_RDAC_DIG_VOL_CTRL
,
316 dac33_read_reg_cache(codec
, DAC33_RDAC_DIG_VOL_CTRL
));
318 dac33_write(codec
, DAC33_LINEL_TO_LLO_VOL
,
319 dac33_read_reg_cache(codec
, DAC33_LINEL_TO_LLO_VOL
));
320 dac33_write(codec
, DAC33_LINER_TO_RLO_VOL
,
321 dac33_read_reg_cache(codec
, DAC33_LINER_TO_RLO_VOL
));
323 dac33_write(codec
, DAC33_OUT_AMP_CTRL
,
324 dac33_read_reg_cache(codec
, DAC33_OUT_AMP_CTRL
));
326 dac33_write(codec
, DAC33_LDAC_PWR_CTRL
,
327 dac33_read_reg_cache(codec
, DAC33_LDAC_PWR_CTRL
));
328 dac33_write(codec
, DAC33_RDAC_PWR_CTRL
,
329 dac33_read_reg_cache(codec
, DAC33_RDAC_PWR_CTRL
));
332 static inline int dac33_read_id(struct snd_soc_codec
*codec
)
337 for (i
= 0; i
< 3; i
++) {
338 ret
= dac33_read(codec
, DAC33_DEVICE_ID_MSB
+ i
, ®
);
346 static inline void dac33_soft_power(struct snd_soc_codec
*codec
, int power
)
350 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
352 reg
|= DAC33_PDNALLB
;
354 reg
&= ~(DAC33_PDNALLB
| DAC33_OSCPDNB
|
355 DAC33_DACRPDNB
| DAC33_DACLPDNB
);
356 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
359 static inline void dac33_disable_digital(struct snd_soc_codec
*codec
)
363 /* Stop the DAI clock */
364 reg
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
365 reg
&= ~DAC33_BCLKON
;
366 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, reg
);
368 /* Power down the Oscillator, and DACs */
369 reg
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
370 reg
&= ~(DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
);
371 dac33_write(codec
, DAC33_PWR_CTRL
, reg
);
374 static int dac33_hard_power(struct snd_soc_codec
*codec
, int power
)
376 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
379 mutex_lock(&dac33
->mutex
);
382 if (unlikely(power
== dac33
->chip_power
)) {
383 dev_dbg(codec
->dev
, "Trying to set the same power state: %s\n",
384 power
? "ON" : "OFF");
389 ret
= regulator_bulk_enable(ARRAY_SIZE(dac33
->supplies
),
393 "Failed to enable supplies: %d\n", ret
);
397 if (dac33
->power_gpio
>= 0)
398 gpio_set_value(dac33
->power_gpio
, 1);
400 dac33
->chip_power
= 1;
402 dac33_soft_power(codec
, 0);
403 if (dac33
->power_gpio
>= 0)
404 gpio_set_value(dac33
->power_gpio
, 0);
406 ret
= regulator_bulk_disable(ARRAY_SIZE(dac33
->supplies
),
410 "Failed to disable supplies: %d\n", ret
);
414 dac33
->chip_power
= 0;
418 mutex_unlock(&dac33
->mutex
);
422 static int dac33_playback_event(struct snd_soc_dapm_widget
*w
,
423 struct snd_kcontrol
*kcontrol
, int event
)
425 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(w
->codec
);
428 case SND_SOC_DAPM_PRE_PMU
:
429 if (likely(dac33
->substream
)) {
430 dac33_calculate_times(dac33
->substream
);
431 dac33_prepare_chip(dac33
->substream
);
434 case SND_SOC_DAPM_POST_PMD
:
435 dac33_disable_digital(w
->codec
);
441 static int dac33_get_fifo_mode(struct snd_kcontrol
*kcontrol
,
442 struct snd_ctl_elem_value
*ucontrol
)
444 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
445 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
447 ucontrol
->value
.integer
.value
[0] = dac33
->fifo_mode
;
452 static int dac33_set_fifo_mode(struct snd_kcontrol
*kcontrol
,
453 struct snd_ctl_elem_value
*ucontrol
)
455 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
456 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
459 if (dac33
->fifo_mode
== ucontrol
->value
.integer
.value
[0])
461 /* Do not allow changes while stream is running*/
465 if (ucontrol
->value
.integer
.value
[0] < 0 ||
466 ucontrol
->value
.integer
.value
[0] >= DAC33_FIFO_LAST_MODE
)
469 dac33
->fifo_mode
= ucontrol
->value
.integer
.value
[0];
474 /* Codec operation modes */
475 static const char *dac33_fifo_mode_texts
[] = {
476 "Bypass", "Mode 1", "Mode 7"
479 static const struct soc_enum dac33_fifo_mode_enum
=
480 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts
),
481 dac33_fifo_mode_texts
);
483 /* L/R Line Output Gain */
484 static const char *lr_lineout_gain_texts
[] = {
485 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
486 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
489 static const struct soc_enum l_lineout_gain_enum
=
490 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL
, 0,
491 ARRAY_SIZE(lr_lineout_gain_texts
),
492 lr_lineout_gain_texts
);
494 static const struct soc_enum r_lineout_gain_enum
=
495 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL
, 0,
496 ARRAY_SIZE(lr_lineout_gain_texts
),
497 lr_lineout_gain_texts
);
500 * DACL/R digital volume control:
501 * from 0 dB to -63.5 in 0.5 dB steps
502 * Need to be inverted later on:
506 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv
, -6350, 50, 0);
508 static const struct snd_kcontrol_new dac33_snd_controls
[] = {
509 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
510 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
,
511 0, 0x7f, 1, dac_digivol_tlv
),
512 SOC_DOUBLE_R("DAC Digital Playback Switch",
513 DAC33_LDAC_DIG_VOL_CTRL
, DAC33_RDAC_DIG_VOL_CTRL
, 7, 1, 1),
514 SOC_DOUBLE_R("Line to Line Out Volume",
515 DAC33_LINEL_TO_LLO_VOL
, DAC33_LINER_TO_RLO_VOL
, 0, 127, 1),
516 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum
),
517 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum
),
520 static const struct snd_kcontrol_new dac33_mode_snd_controls
[] = {
521 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum
,
522 dac33_get_fifo_mode
, dac33_set_fifo_mode
),
526 static const struct snd_kcontrol_new dac33_dapm_abypassl_control
=
527 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL
, 7, 1, 1);
529 static const struct snd_kcontrol_new dac33_dapm_abypassr_control
=
530 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL
, 7, 1, 1);
532 /* LOP L/R invert selection */
533 static const char *dac33_lr_lom_texts
[] = {"DAC", "LOP"};
535 static const struct soc_enum dac33_left_lom_enum
=
536 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL
, 3,
537 ARRAY_SIZE(dac33_lr_lom_texts
),
540 static const struct snd_kcontrol_new dac33_dapm_left_lom_control
=
541 SOC_DAPM_ENUM("Route", dac33_left_lom_enum
);
543 static const struct soc_enum dac33_right_lom_enum
=
544 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL
, 2,
545 ARRAY_SIZE(dac33_lr_lom_texts
),
548 static const struct snd_kcontrol_new dac33_dapm_right_lom_control
=
549 SOC_DAPM_ENUM("Route", dac33_right_lom_enum
);
551 static const struct snd_soc_dapm_widget dac33_dapm_widgets
[] = {
552 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
553 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
555 SND_SOC_DAPM_INPUT("LINEL"),
556 SND_SOC_DAPM_INPUT("LINER"),
558 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM
, 0, 0),
559 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM
, 0, 0),
562 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM
, 0, 0,
563 &dac33_dapm_abypassl_control
),
564 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM
, 0, 0,
565 &dac33_dapm_abypassr_control
),
567 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM
, 0, 0,
568 &dac33_dapm_left_lom_control
),
569 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM
, 0, 0,
570 &dac33_dapm_right_lom_control
),
572 * For DAPM path, when only the anlog bypass path is enabled, and the
573 * LOP inverted from the corresponding DAC side.
574 * This is needed, so we can attach the DAC power supply in this case.
576 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
577 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM
, 0, 0, NULL
, 0),
579 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Left Amplifier",
580 DAC33_OUT_AMP_PWR_CTRL
, 6, 3, 3, 0),
581 SND_SOC_DAPM_REG(snd_soc_dapm_mixer
, "Output Right Amplifier",
582 DAC33_OUT_AMP_PWR_CTRL
, 4, 3, 3, 0),
584 SND_SOC_DAPM_SUPPLY("Left DAC Power",
585 DAC33_LDAC_PWR_CTRL
, 2, 0, NULL
, 0),
586 SND_SOC_DAPM_SUPPLY("Right DAC Power",
587 DAC33_RDAC_PWR_CTRL
, 2, 0, NULL
, 0),
589 SND_SOC_DAPM_SUPPLY("Codec Power",
590 DAC33_PWR_CTRL
, 4, 0, NULL
, 0),
592 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event
),
593 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event
),
596 static const struct snd_soc_dapm_route audio_map
[] = {
598 {"Analog Left Bypass", "Switch", "LINEL"},
599 {"Analog Right Bypass", "Switch", "LINER"},
601 {"Output Left Amplifier", NULL
, "DACL"},
602 {"Output Right Amplifier", NULL
, "DACR"},
604 {"Left Bypass PGA", NULL
, "Analog Left Bypass"},
605 {"Right Bypass PGA", NULL
, "Analog Right Bypass"},
607 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
608 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
609 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
610 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
612 {"Output Left Amplifier", NULL
, "Left LOM Inverted From"},
613 {"Output Right Amplifier", NULL
, "Right LOM Inverted From"},
615 {"DACL", NULL
, "Left DAC Power"},
616 {"DACR", NULL
, "Right DAC Power"},
618 {"Left Bypass PGA", NULL
, "Left DAC Power"},
619 {"Right Bypass PGA", NULL
, "Right DAC Power"},
622 {"LEFT_LO", NULL
, "Output Left Amplifier"},
623 {"RIGHT_LO", NULL
, "Output Right Amplifier"},
625 {"LEFT_LO", NULL
, "Codec Power"},
626 {"RIGHT_LO", NULL
, "Codec Power"},
629 static int dac33_set_bias_level(struct snd_soc_codec
*codec
,
630 enum snd_soc_bias_level level
)
635 case SND_SOC_BIAS_ON
:
637 case SND_SOC_BIAS_PREPARE
:
639 case SND_SOC_BIAS_STANDBY
:
640 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
641 /* Coming from OFF, switch on the codec */
642 ret
= dac33_hard_power(codec
, 1);
646 dac33_init_chip(codec
);
649 case SND_SOC_BIAS_OFF
:
650 /* Do not power off, when the codec is already off */
651 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
)
653 ret
= dac33_hard_power(codec
, 0);
658 codec
->dapm
.bias_level
= level
;
663 static inline void dac33_prefill_handler(struct tlv320dac33_priv
*dac33
)
665 struct snd_soc_codec
*codec
= dac33
->codec
;
669 switch (dac33
->fifo_mode
) {
670 case DAC33_FIFO_MODE1
:
671 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
672 DAC33_THRREG(dac33
->nsample
));
674 /* Take the timestamps */
675 spin_lock_irqsave(&dac33
->lock
, flags
);
676 dac33
->t_stamp2
= ktime_to_us(ktime_get());
677 dac33
->t_stamp1
= dac33
->t_stamp2
;
678 spin_unlock_irqrestore(&dac33
->lock
, flags
);
680 dac33_write16(codec
, DAC33_PREFILL_MSB
,
681 DAC33_THRREG(dac33
->alarm_threshold
));
682 /* Enable Alarm Threshold IRQ with a delay */
683 delay
= SAMPLES_TO_US(dac33
->burst_rate
,
684 dac33
->alarm_threshold
) + 1000;
685 usleep_range(delay
, delay
+ 500);
686 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MAT
);
688 case DAC33_FIFO_MODE7
:
689 /* Take the timestamp */
690 spin_lock_irqsave(&dac33
->lock
, flags
);
691 dac33
->t_stamp1
= ktime_to_us(ktime_get());
692 /* Move back the timestamp with drain time */
693 dac33
->t_stamp1
-= dac33
->mode7_us_to_lthr
;
694 spin_unlock_irqrestore(&dac33
->lock
, flags
);
696 dac33_write16(codec
, DAC33_PREFILL_MSB
,
697 DAC33_THRREG(DAC33_MODE7_MARGIN
));
699 /* Enable Upper Threshold IRQ */
700 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, DAC33_MUT
);
703 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
709 static inline void dac33_playback_handler(struct tlv320dac33_priv
*dac33
)
711 struct snd_soc_codec
*codec
= dac33
->codec
;
714 switch (dac33
->fifo_mode
) {
715 case DAC33_FIFO_MODE1
:
716 /* Take the timestamp */
717 spin_lock_irqsave(&dac33
->lock
, flags
);
718 dac33
->t_stamp2
= ktime_to_us(ktime_get());
719 spin_unlock_irqrestore(&dac33
->lock
, flags
);
721 dac33_write16(codec
, DAC33_NSAMPLE_MSB
,
722 DAC33_THRREG(dac33
->nsample
));
724 case DAC33_FIFO_MODE7
:
725 /* At the moment we are not using interrupts in mode7 */
728 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
734 static void dac33_work(struct work_struct
*work
)
736 struct snd_soc_codec
*codec
;
737 struct tlv320dac33_priv
*dac33
;
740 dac33
= container_of(work
, struct tlv320dac33_priv
, work
);
741 codec
= dac33
->codec
;
743 mutex_lock(&dac33
->mutex
);
744 switch (dac33
->state
) {
746 dac33
->state
= DAC33_PLAYBACK
;
747 dac33_prefill_handler(dac33
);
750 dac33_playback_handler(dac33
);
755 dac33
->state
= DAC33_IDLE
;
756 /* Mask all interrupts from dac33 */
757 dac33_write(codec
, DAC33_FIFO_IRQ_MASK
, 0);
760 reg
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
761 reg
|= DAC33_FIFOFLUSH
;
762 dac33_write(codec
, DAC33_FIFO_CTRL_A
, reg
);
765 mutex_unlock(&dac33
->mutex
);
768 static irqreturn_t
dac33_interrupt_handler(int irq
, void *dev
)
770 struct snd_soc_codec
*codec
= dev
;
771 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
774 spin_lock_irqsave(&dac33
->lock
, flags
);
775 dac33
->t_stamp1
= ktime_to_us(ktime_get());
776 spin_unlock_irqrestore(&dac33
->lock
, flags
);
778 /* Do not schedule the workqueue in Mode7 */
779 if (dac33
->fifo_mode
!= DAC33_FIFO_MODE7
)
780 queue_work(dac33
->dac33_wq
, &dac33
->work
);
785 static void dac33_oscwait(struct snd_soc_codec
*codec
)
791 usleep_range(1000, 2000);
792 dac33_read(codec
, DAC33_INT_OSC_STATUS
, ®
);
793 } while (((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
) && timeout
--);
794 if ((reg
& 0x03) != DAC33_OSCSTATUS_NORMAL
)
796 "internal oscillator calibration failed\n");
799 static int dac33_startup(struct snd_pcm_substream
*substream
,
800 struct snd_soc_dai
*dai
)
802 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
803 struct snd_soc_codec
*codec
= rtd
->codec
;
804 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
806 /* Stream started, save the substream pointer */
807 dac33
->substream
= substream
;
812 static void dac33_shutdown(struct snd_pcm_substream
*substream
,
813 struct snd_soc_dai
*dai
)
815 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
816 struct snd_soc_codec
*codec
= rtd
->codec
;
817 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
819 dac33
->substream
= NULL
;
822 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
823 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
824 static int dac33_hw_params(struct snd_pcm_substream
*substream
,
825 struct snd_pcm_hw_params
*params
,
826 struct snd_soc_dai
*dai
)
828 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
829 struct snd_soc_codec
*codec
= rtd
->codec
;
830 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
832 /* Check parameters for validity */
833 switch (params_rate(params
)) {
838 dev_err(codec
->dev
, "unsupported rate %d\n",
839 params_rate(params
));
843 switch (params_format(params
)) {
844 case SNDRV_PCM_FORMAT_S16_LE
:
845 dac33
->fifo_size
= DAC33_FIFO_SIZE_16BIT
;
846 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 32);
848 case SNDRV_PCM_FORMAT_S32_LE
:
849 dac33
->fifo_size
= DAC33_FIFO_SIZE_24BIT
;
850 dac33
->burst_rate
= CALC_BURST_RATE(dac33
->burst_bclkdiv
, 64);
853 dev_err(codec
->dev
, "unsupported format %d\n",
854 params_format(params
));
861 #define CALC_OSCSET(rate, refclk) ( \
862 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
863 #define CALC_RATIOSET(rate, refclk) ( \
864 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
867 * tlv320dac33 is strict on the sequence of the register writes, if the register
868 * writes happens in different order, than dac33 might end up in unknown state.
869 * Use the known, working sequence of register writes to initialize the dac33.
871 static int dac33_prepare_chip(struct snd_pcm_substream
*substream
)
873 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
874 struct snd_soc_codec
*codec
= rtd
->codec
;
875 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
876 unsigned int oscset
, ratioset
, pwr_ctrl
, reg_tmp
;
877 u8 aictrl_a
, aictrl_b
, fifoctrl_a
;
879 switch (substream
->runtime
->rate
) {
882 oscset
= CALC_OSCSET(substream
->runtime
->rate
, dac33
->refclk
);
883 ratioset
= CALC_RATIOSET(substream
->runtime
->rate
,
887 dev_err(codec
->dev
, "unsupported rate %d\n",
888 substream
->runtime
->rate
);
893 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
894 aictrl_a
&= ~(DAC33_NCYCL_MASK
| DAC33_WLEN_MASK
);
895 /* Read FIFO control A, and clear FIFO flush bit */
896 fifoctrl_a
= dac33_read_reg_cache(codec
, DAC33_FIFO_CTRL_A
);
897 fifoctrl_a
&= ~DAC33_FIFOFLUSH
;
899 fifoctrl_a
&= ~DAC33_WIDTH
;
900 switch (substream
->runtime
->format
) {
901 case SNDRV_PCM_FORMAT_S16_LE
:
902 aictrl_a
|= (DAC33_NCYCL_16
| DAC33_WLEN_16
);
903 fifoctrl_a
|= DAC33_WIDTH
;
905 case SNDRV_PCM_FORMAT_S32_LE
:
906 aictrl_a
|= (DAC33_NCYCL_32
| DAC33_WLEN_24
);
909 dev_err(codec
->dev
, "unsupported format %d\n",
910 substream
->runtime
->format
);
914 mutex_lock(&dac33
->mutex
);
916 if (!dac33
->chip_power
) {
918 * Chip is not powered yet.
919 * Do the init in the dac33_set_bias_level later.
921 mutex_unlock(&dac33
->mutex
);
925 dac33_soft_power(codec
, 0);
926 dac33_soft_power(codec
, 1);
928 reg_tmp
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
929 dac33_write(codec
, DAC33_INT_OSC_CTRL
, reg_tmp
);
931 /* Write registers 0x08 and 0x09 (MSB, LSB) */
932 dac33_write16(codec
, DAC33_INT_OSC_FREQ_RAT_A
, oscset
);
934 /* OSC calibration time */
935 dac33_write(codec
, DAC33_CALIB_TIME
, 96);
937 /* adjustment treshold & step */
938 dac33_write(codec
, DAC33_INT_OSC_CTRL_B
, DAC33_ADJTHRSHLD(2) |
941 /* div=4 / gain=1 / div */
942 dac33_write(codec
, DAC33_INT_OSC_CTRL_C
, DAC33_REFDIV(4));
944 pwr_ctrl
= dac33_read_reg_cache(codec
, DAC33_PWR_CTRL
);
945 pwr_ctrl
|= DAC33_OSCPDNB
| DAC33_DACRPDNB
| DAC33_DACLPDNB
;
946 dac33_write(codec
, DAC33_PWR_CTRL
, pwr_ctrl
);
948 dac33_oscwait(codec
);
950 if (dac33
->fifo_mode
) {
951 /* Generic for all FIFO modes */
952 /* 50-51 : ASRC Control registers */
953 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCLKDIV(1));
954 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 1); /* ??? */
956 /* Write registers 0x34 and 0x35 (MSB, LSB) */
957 dac33_write16(codec
, DAC33_SRC_REF_CLK_RATIO_A
, ratioset
);
959 /* Set interrupts to high active */
960 dac33_write(codec
, DAC33_INTP_CTRL_A
, DAC33_INTPM_AHIGH
);
962 /* FIFO bypass mode */
963 /* 50-51 : ASRC Control registers */
964 dac33_write(codec
, DAC33_ASRC_CTRL_A
, DAC33_SRCBYP
);
965 dac33_write(codec
, DAC33_ASRC_CTRL_B
, 0); /* ??? */
968 /* Interrupt behaviour configuration */
969 switch (dac33
->fifo_mode
) {
970 case DAC33_FIFO_MODE1
:
971 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_B
,
972 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL
));
974 case DAC33_FIFO_MODE7
:
975 dac33_write(codec
, DAC33_FIFO_IRQ_MODE_A
,
976 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL
));
979 /* in FIFO bypass mode, the interrupts are not used */
983 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
985 switch (dac33
->fifo_mode
) {
986 case DAC33_FIFO_MODE1
:
989 * Disable the FIFO bypass (Enable the use of FIFO)
990 * Select nSample mode
991 * BCLK is only running when data is needed by DAC33
993 fifoctrl_a
&= ~DAC33_FBYPAS
;
994 fifoctrl_a
&= ~DAC33_FAUTO
;
995 if (dac33
->keep_bclk
)
996 aictrl_b
|= DAC33_BCLKON
;
998 aictrl_b
&= ~DAC33_BCLKON
;
1000 case DAC33_FIFO_MODE7
:
1003 * Disable the FIFO bypass (Enable the use of FIFO)
1004 * Select Threshold mode
1005 * BCLK is only running when data is needed by DAC33
1007 fifoctrl_a
&= ~DAC33_FBYPAS
;
1008 fifoctrl_a
|= DAC33_FAUTO
;
1009 if (dac33
->keep_bclk
)
1010 aictrl_b
|= DAC33_BCLKON
;
1012 aictrl_b
&= ~DAC33_BCLKON
;
1016 * For FIFO bypass mode:
1017 * Enable the FIFO bypass (Disable the FIFO use)
1018 * Set the BCLK as continuous
1020 fifoctrl_a
|= DAC33_FBYPAS
;
1021 aictrl_b
|= DAC33_BCLKON
;
1025 dac33_write(codec
, DAC33_FIFO_CTRL_A
, fifoctrl_a
);
1026 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1027 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1038 if (dac33
->fifo_mode
)
1039 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
,
1040 dac33
->burst_bclkdiv
);
1042 if (substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
)
1043 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 32);
1045 dac33_write(codec
, DAC33_SER_AUDIOIF_CTRL_C
, 16);
1047 switch (dac33
->fifo_mode
) {
1048 case DAC33_FIFO_MODE1
:
1049 dac33_write16(codec
, DAC33_ATHR_MSB
,
1050 DAC33_THRREG(dac33
->alarm_threshold
));
1052 case DAC33_FIFO_MODE7
:
1054 * Configure the threshold levels, and leave 10 sample space
1055 * at the bottom, and also at the top of the FIFO
1057 dac33_write16(codec
, DAC33_UTHR_MSB
, DAC33_THRREG(dac33
->uthr
));
1058 dac33_write16(codec
, DAC33_LTHR_MSB
,
1059 DAC33_THRREG(DAC33_MODE7_MARGIN
));
1065 mutex_unlock(&dac33
->mutex
);
1070 static void dac33_calculate_times(struct snd_pcm_substream
*substream
)
1072 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1073 struct snd_soc_codec
*codec
= rtd
->codec
;
1074 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1075 unsigned int period_size
= substream
->runtime
->period_size
;
1076 unsigned int rate
= substream
->runtime
->rate
;
1077 unsigned int nsample_limit
;
1079 /* In bypass mode we don't need to calculate */
1080 if (!dac33
->fifo_mode
)
1083 switch (dac33
->fifo_mode
) {
1084 case DAC33_FIFO_MODE1
:
1085 /* Number of samples under i2c latency */
1086 dac33
->alarm_threshold
= US_TO_SAMPLES(rate
,
1087 dac33
->mode1_latency
);
1088 nsample_limit
= dac33
->fifo_size
- dac33
->alarm_threshold
;
1090 if (period_size
<= dac33
->alarm_threshold
)
1092 * Configure nSamaple to number of periods,
1093 * which covers the latency requironment.
1095 dac33
->nsample
= period_size
*
1096 ((dac33
->alarm_threshold
/ period_size
) +
1097 (dac33
->alarm_threshold
% period_size
?
1099 else if (period_size
> nsample_limit
)
1100 dac33
->nsample
= nsample_limit
;
1102 dac33
->nsample
= period_size
;
1104 dac33
->mode1_us_burst
= SAMPLES_TO_US(dac33
->burst_rate
,
1106 dac33
->t_stamp1
= 0;
1107 dac33
->t_stamp2
= 0;
1109 case DAC33_FIFO_MODE7
:
1110 dac33
->uthr
= UTHR_FROM_PERIOD_SIZE(period_size
, rate
,
1111 dac33
->burst_rate
) + 9;
1112 if (dac33
->uthr
> (dac33
->fifo_size
- DAC33_MODE7_MARGIN
))
1113 dac33
->uthr
= dac33
->fifo_size
- DAC33_MODE7_MARGIN
;
1114 if (dac33
->uthr
< (DAC33_MODE7_MARGIN
+ 10))
1115 dac33
->uthr
= (DAC33_MODE7_MARGIN
+ 10);
1117 dac33
->mode7_us_to_lthr
=
1118 SAMPLES_TO_US(substream
->runtime
->rate
,
1119 dac33
->uthr
- DAC33_MODE7_MARGIN
+ 1);
1120 dac33
->t_stamp1
= 0;
1128 static int dac33_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
,
1129 struct snd_soc_dai
*dai
)
1131 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1132 struct snd_soc_codec
*codec
= rtd
->codec
;
1133 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1137 case SNDRV_PCM_TRIGGER_START
:
1138 case SNDRV_PCM_TRIGGER_RESUME
:
1139 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1140 if (dac33
->fifo_mode
) {
1141 dac33
->state
= DAC33_PREFILL
;
1142 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1145 case SNDRV_PCM_TRIGGER_STOP
:
1146 case SNDRV_PCM_TRIGGER_SUSPEND
:
1147 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1148 if (dac33
->fifo_mode
) {
1149 dac33
->state
= DAC33_FLUSH
;
1150 queue_work(dac33
->dac33_wq
, &dac33
->work
);
1160 static snd_pcm_sframes_t
dac33_dai_delay(
1161 struct snd_pcm_substream
*substream
,
1162 struct snd_soc_dai
*dai
)
1164 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
1165 struct snd_soc_codec
*codec
= rtd
->codec
;
1166 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1167 unsigned long long t0
, t1
, t_now
;
1168 unsigned int time_delta
, uthr
;
1169 int samples_out
, samples_in
, samples
;
1170 snd_pcm_sframes_t delay
= 0;
1171 unsigned long flags
;
1173 switch (dac33
->fifo_mode
) {
1174 case DAC33_FIFO_BYPASS
:
1176 case DAC33_FIFO_MODE1
:
1177 spin_lock_irqsave(&dac33
->lock
, flags
);
1178 t0
= dac33
->t_stamp1
;
1179 t1
= dac33
->t_stamp2
;
1180 spin_unlock_irqrestore(&dac33
->lock
, flags
);
1181 t_now
= ktime_to_us(ktime_get());
1183 /* We have not started to fill the FIFO yet, delay is 0 */
1190 * After Alarm threshold, and before nSample write
1192 time_delta
= t_now
- t0
;
1193 samples_out
= time_delta
? US_TO_SAMPLES(
1194 substream
->runtime
->rate
,
1197 if (likely(dac33
->alarm_threshold
> samples_out
))
1198 delay
= dac33
->alarm_threshold
- samples_out
;
1201 } else if ((t_now
- t1
) <= dac33
->mode1_us_burst
) {
1204 * After nSample write (during burst operation)
1206 time_delta
= t_now
- t0
;
1207 samples_out
= time_delta
? US_TO_SAMPLES(
1208 substream
->runtime
->rate
,
1211 time_delta
= t_now
- t1
;
1212 samples_in
= time_delta
? US_TO_SAMPLES(
1216 samples
= dac33
->alarm_threshold
;
1217 samples
+= (samples_in
- samples_out
);
1219 if (likely(samples
> 0))
1226 * After burst operation, before next alarm threshold
1228 time_delta
= t_now
- t0
;
1229 samples_out
= time_delta
? US_TO_SAMPLES(
1230 substream
->runtime
->rate
,
1233 samples_in
= dac33
->nsample
;
1234 samples
= dac33
->alarm_threshold
;
1235 samples
+= (samples_in
- samples_out
);
1237 if (likely(samples
> 0))
1238 delay
= samples
> dac33
->fifo_size
?
1239 dac33
->fifo_size
: samples
;
1244 case DAC33_FIFO_MODE7
:
1245 spin_lock_irqsave(&dac33
->lock
, flags
);
1246 t0
= dac33
->t_stamp1
;
1248 spin_unlock_irqrestore(&dac33
->lock
, flags
);
1249 t_now
= ktime_to_us(ktime_get());
1251 /* We have not started to fill the FIFO yet, delay is 0 */
1257 * Either the timestamps are messed or equal. Report
1264 time_delta
= t_now
- t0
;
1265 if (time_delta
<= dac33
->mode7_us_to_lthr
) {
1268 * After burst (draining phase)
1270 samples_out
= US_TO_SAMPLES(
1271 substream
->runtime
->rate
,
1274 if (likely(uthr
> samples_out
))
1275 delay
= uthr
- samples_out
;
1281 * During burst operation
1283 time_delta
= time_delta
- dac33
->mode7_us_to_lthr
;
1285 samples_out
= US_TO_SAMPLES(
1286 substream
->runtime
->rate
,
1288 samples_in
= US_TO_SAMPLES(
1291 delay
= DAC33_MODE7_MARGIN
+ samples_in
- samples_out
;
1293 if (unlikely(delay
> uthr
))
1298 dev_warn(codec
->dev
, "Unhandled FIFO mode: %d\n",
1306 static int dac33_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1307 int clk_id
, unsigned int freq
, int dir
)
1309 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1310 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1311 u8 ioc_reg
, asrcb_reg
;
1313 ioc_reg
= dac33_read_reg_cache(codec
, DAC33_INT_OSC_CTRL
);
1314 asrcb_reg
= dac33_read_reg_cache(codec
, DAC33_ASRC_CTRL_B
);
1316 case TLV320DAC33_MCLK
:
1317 ioc_reg
|= DAC33_REFSEL
;
1318 asrcb_reg
|= DAC33_SRCREFSEL
;
1320 case TLV320DAC33_SLEEPCLK
:
1321 ioc_reg
&= ~DAC33_REFSEL
;
1322 asrcb_reg
&= ~DAC33_SRCREFSEL
;
1325 dev_err(codec
->dev
, "Invalid clock ID (%d)\n", clk_id
);
1328 dac33
->refclk
= freq
;
1330 dac33_write_reg_cache(codec
, DAC33_INT_OSC_CTRL
, ioc_reg
);
1331 dac33_write_reg_cache(codec
, DAC33_ASRC_CTRL_B
, asrcb_reg
);
1336 static int dac33_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1339 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1340 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1341 u8 aictrl_a
, aictrl_b
;
1343 aictrl_a
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
);
1344 aictrl_b
= dac33_read_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
);
1345 /* set master/slave audio interface */
1346 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1347 case SND_SOC_DAIFMT_CBM_CFM
:
1349 aictrl_a
|= (DAC33_MSBCLK
| DAC33_MSWCLK
);
1351 case SND_SOC_DAIFMT_CBS_CFS
:
1353 if (dac33
->fifo_mode
) {
1354 dev_err(codec
->dev
, "FIFO mode requires master mode\n");
1357 aictrl_a
&= ~(DAC33_MSBCLK
| DAC33_MSWCLK
);
1363 aictrl_a
&= ~DAC33_AFMT_MASK
;
1364 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1365 case SND_SOC_DAIFMT_I2S
:
1366 aictrl_a
|= DAC33_AFMT_I2S
;
1368 case SND_SOC_DAIFMT_DSP_A
:
1369 aictrl_a
|= DAC33_AFMT_DSP
;
1370 aictrl_b
&= ~DAC33_DATA_DELAY_MASK
;
1371 aictrl_b
|= DAC33_DATA_DELAY(0);
1373 case SND_SOC_DAIFMT_RIGHT_J
:
1374 aictrl_a
|= DAC33_AFMT_RIGHT_J
;
1376 case SND_SOC_DAIFMT_LEFT_J
:
1377 aictrl_a
|= DAC33_AFMT_LEFT_J
;
1380 dev_err(codec
->dev
, "Unsupported format (%u)\n",
1381 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1385 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_A
, aictrl_a
);
1386 dac33_write_reg_cache(codec
, DAC33_SER_AUDIOIF_CTRL_B
, aictrl_b
);
1391 static int dac33_soc_probe(struct snd_soc_codec
*codec
)
1393 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1396 codec
->control_data
= dac33
->control_data
;
1397 codec
->hw_write
= (hw_write_t
) i2c_master_send
;
1398 codec
->dapm
.idle_bias_off
= 1;
1399 dac33
->codec
= codec
;
1401 /* Read the tlv320dac33 ID registers */
1402 ret
= dac33_hard_power(codec
, 1);
1404 dev_err(codec
->dev
, "Failed to power up codec: %d\n", ret
);
1407 ret
= dac33_read_id(codec
);
1408 dac33_hard_power(codec
, 0);
1411 dev_err(codec
->dev
, "Failed to read chip ID: %d\n", ret
);
1416 /* Check if the IRQ number is valid and request it */
1417 if (dac33
->irq
>= 0) {
1418 ret
= request_irq(dac33
->irq
, dac33_interrupt_handler
,
1419 IRQF_TRIGGER_RISING
,
1420 codec
->name
, codec
);
1422 dev_err(codec
->dev
, "Could not request IRQ%d (%d)\n",
1426 if (dac33
->irq
!= -1) {
1427 /* Setup work queue */
1429 create_singlethread_workqueue("tlv320dac33");
1430 if (dac33
->dac33_wq
== NULL
) {
1431 free_irq(dac33
->irq
, codec
);
1435 INIT_WORK(&dac33
->work
, dac33_work
);
1439 /* Only add the FIFO controls, if we have valid IRQ number */
1440 if (dac33
->irq
>= 0)
1441 snd_soc_add_controls(codec
, dac33_mode_snd_controls
,
1442 ARRAY_SIZE(dac33_mode_snd_controls
));
1448 static int dac33_soc_remove(struct snd_soc_codec
*codec
)
1450 struct tlv320dac33_priv
*dac33
= snd_soc_codec_get_drvdata(codec
);
1452 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1454 if (dac33
->irq
>= 0) {
1455 free_irq(dac33
->irq
, dac33
->codec
);
1456 destroy_workqueue(dac33
->dac33_wq
);
1461 static int dac33_soc_suspend(struct snd_soc_codec
*codec
)
1463 dac33_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1468 static int dac33_soc_resume(struct snd_soc_codec
*codec
)
1470 dac33_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1475 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33
= {
1476 .read
= dac33_read_reg_cache
,
1477 .write
= dac33_write_locked
,
1478 .set_bias_level
= dac33_set_bias_level
,
1479 .reg_cache_size
= ARRAY_SIZE(dac33_reg
),
1480 .reg_word_size
= sizeof(u8
),
1481 .reg_cache_default
= dac33_reg
,
1482 .probe
= dac33_soc_probe
,
1483 .remove
= dac33_soc_remove
,
1484 .suspend
= dac33_soc_suspend
,
1485 .resume
= dac33_soc_resume
,
1487 .controls
= dac33_snd_controls
,
1488 .num_controls
= ARRAY_SIZE(dac33_snd_controls
),
1489 .dapm_widgets
= dac33_dapm_widgets
,
1490 .num_dapm_widgets
= ARRAY_SIZE(dac33_dapm_widgets
),
1491 .dapm_routes
= audio_map
,
1492 .num_dapm_routes
= ARRAY_SIZE(audio_map
),
1495 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1496 SNDRV_PCM_RATE_48000)
1497 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1499 static const struct snd_soc_dai_ops dac33_dai_ops
= {
1500 .startup
= dac33_startup
,
1501 .shutdown
= dac33_shutdown
,
1502 .hw_params
= dac33_hw_params
,
1503 .trigger
= dac33_pcm_trigger
,
1504 .delay
= dac33_dai_delay
,
1505 .set_sysclk
= dac33_set_dai_sysclk
,
1506 .set_fmt
= dac33_set_dai_fmt
,
1509 static struct snd_soc_dai_driver dac33_dai
= {
1510 .name
= "tlv320dac33-hifi",
1512 .stream_name
= "Playback",
1515 .rates
= DAC33_RATES
,
1516 .formats
= DAC33_FORMATS
,
1519 .ops
= &dac33_dai_ops
,
1522 static int __devinit
dac33_i2c_probe(struct i2c_client
*client
,
1523 const struct i2c_device_id
*id
)
1525 struct tlv320dac33_platform_data
*pdata
;
1526 struct tlv320dac33_priv
*dac33
;
1529 if (client
->dev
.platform_data
== NULL
) {
1530 dev_err(&client
->dev
, "Platform data not set\n");
1533 pdata
= client
->dev
.platform_data
;
1535 dac33
= devm_kzalloc(&client
->dev
, sizeof(struct tlv320dac33_priv
),
1540 dac33
->control_data
= client
;
1541 mutex_init(&dac33
->mutex
);
1542 spin_lock_init(&dac33
->lock
);
1544 i2c_set_clientdata(client
, dac33
);
1546 dac33
->power_gpio
= pdata
->power_gpio
;
1547 dac33
->burst_bclkdiv
= pdata
->burst_bclkdiv
;
1548 dac33
->keep_bclk
= pdata
->keep_bclk
;
1549 dac33
->mode1_latency
= pdata
->mode1_latency
;
1550 if (!dac33
->mode1_latency
)
1551 dac33
->mode1_latency
= 10000; /* 10ms */
1552 dac33
->irq
= client
->irq
;
1553 /* Disable FIFO use by default */
1554 dac33
->fifo_mode
= DAC33_FIFO_BYPASS
;
1556 /* Check if the reset GPIO number is valid and request it */
1557 if (dac33
->power_gpio
>= 0) {
1558 ret
= gpio_request(dac33
->power_gpio
, "tlv320dac33 reset");
1560 dev_err(&client
->dev
,
1561 "Failed to request reset GPIO (%d)\n",
1565 gpio_direction_output(dac33
->power_gpio
, 0);
1568 for (i
= 0; i
< ARRAY_SIZE(dac33
->supplies
); i
++)
1569 dac33
->supplies
[i
].supply
= dac33_supply_names
[i
];
1571 ret
= regulator_bulk_get(&client
->dev
, ARRAY_SIZE(dac33
->supplies
),
1575 dev_err(&client
->dev
, "Failed to request supplies: %d\n", ret
);
1579 ret
= snd_soc_register_codec(&client
->dev
,
1580 &soc_codec_dev_tlv320dac33
, &dac33_dai
, 1);
1586 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1588 if (dac33
->power_gpio
>= 0)
1589 gpio_free(dac33
->power_gpio
);
1594 static int __devexit
dac33_i2c_remove(struct i2c_client
*client
)
1596 struct tlv320dac33_priv
*dac33
= i2c_get_clientdata(client
);
1598 if (unlikely(dac33
->chip_power
))
1599 dac33_hard_power(dac33
->codec
, 0);
1601 if (dac33
->power_gpio
>= 0)
1602 gpio_free(dac33
->power_gpio
);
1604 regulator_bulk_free(ARRAY_SIZE(dac33
->supplies
), dac33
->supplies
);
1606 snd_soc_unregister_codec(&client
->dev
);
1610 static const struct i2c_device_id tlv320dac33_i2c_id
[] = {
1612 .name
= "tlv320dac33",
1617 MODULE_DEVICE_TABLE(i2c
, tlv320dac33_i2c_id
);
1619 static struct i2c_driver tlv320dac33_i2c_driver
= {
1621 .name
= "tlv320dac33-codec",
1622 .owner
= THIS_MODULE
,
1624 .probe
= dac33_i2c_probe
,
1625 .remove
= __devexit_p(dac33_i2c_remove
),
1626 .id_table
= tlv320dac33_i2c_id
,
1629 static int __init
dac33_module_init(void)
1632 r
= i2c_add_driver(&tlv320dac33_i2c_driver
);
1634 printk(KERN_ERR
"DAC33: driver registration failed\n");
1639 module_init(dac33_module_init
);
1641 static void __exit
dac33_module_exit(void)
1643 i2c_del_driver(&tlv320dac33_i2c_driver
);
1645 module_exit(dac33_module_exit
);
1648 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1649 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1650 MODULE_LICENSE("GPL");