sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/slab.h>
  29 #include <linux/of_device.h>
  30
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/soc.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <asm/div64.h>
  38
  39 #include "wm8580.h"
  40
  41 /* WM8580 register space */
  42 #define WM8580_PLLA1                         0x00
  43 #define WM8580_PLLA2                         0x01
  44 #define WM8580_PLLA3                         0x02
  45 #define WM8580_PLLA4                         0x03
  46 #define WM8580_PLLB1                         0x04
  47 #define WM8580_PLLB2                         0x05
  48 #define WM8580_PLLB3                         0x06
  49 #define WM8580_PLLB4                         0x07
  50 #define WM8580_CLKSEL                        0x08
  51 #define WM8580_PAIF1                         0x09
  52 #define WM8580_PAIF2                         0x0A
  53 #define WM8580_SAIF1                         0x0B
  54 #define WM8580_PAIF3                         0x0C
  55 #define WM8580_PAIF4                         0x0D
  56 #define WM8580_SAIF2                         0x0E
  57 #define WM8580_DAC_CONTROL1                  0x0F
  58 #define WM8580_DAC_CONTROL2                  0x10
  59 #define WM8580_DAC_CONTROL3                  0x11
  60 #define WM8580_DAC_CONTROL4                  0x12
  61 #define WM8580_DAC_CONTROL5                  0x13
  62 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  63 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  64 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  65 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  66 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  67 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  68 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  69 #define WM8580_ADC_CONTROL1                  0x1D
  70 #define WM8580_SPDTXCHAN0                    0x1E
  71 #define WM8580_SPDTXCHAN1                    0x1F
  72 #define WM8580_SPDTXCHAN2                    0x20
  73 #define WM8580_SPDTXCHAN3                    0x21
  74 #define WM8580_SPDTXCHAN4                    0x22
  75 #define WM8580_SPDTXCHAN5                    0x23
  76 #define WM8580_SPDMODE                       0x24
  77 #define WM8580_INTMASK                       0x25
  78 #define WM8580_GPO1                          0x26
  79 #define WM8580_GPO2                          0x27
  80 #define WM8580_GPO3                          0x28
  81 #define WM8580_GPO4                          0x29
  82 #define WM8580_GPO5                          0x2A
  83 #define WM8580_INTSTAT                       0x2B
  84 #define WM8580_SPDRXCHAN1                    0x2C
  85 #define WM8580_SPDRXCHAN2                    0x2D
  86 #define WM8580_SPDRXCHAN3                    0x2E
  87 #define WM8580_SPDRXCHAN4                    0x2F
  88 #define WM8580_SPDRXCHAN5                    0x30
  89 #define WM8580_SPDSTAT                       0x31
  90 #define WM8580_PWRDN1                        0x32
  91 #define WM8580_PWRDN2                        0x33
  92 #define WM8580_READBACK                      0x34
  93 #define WM8580_RESET                         0x35
  94
  95 #define WM8580_MAX_REGISTER                  0x35
  96
  97 #define WM8580_DACOSR 0x40
  98
  99 /* PLLB4 (register 7h) */
 100 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 103 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 104
 105 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 109
 110 /* CLKSEL (register 8h) */
 111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 114
 115 /* AIF control 1 (registers 9h-bh) */
 116 #define WM8580_AIF_RATE_MASK       0x7
 117 #define WM8580_AIF_BCLKSEL_MASK   0x18
 118
 119 #define WM8580_AIF_MS             0x20
 120
 121 #define WM8580_AIF_CLKSRC_MASK    0xc0
 122 #define WM8580_AIF_CLKSRC_PLLA    0x40
 123 #define WM8580_AIF_CLKSRC_PLLB    0x40
 124 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 125
 126 /* AIF control 2 (registers ch-eh) */
 127 #define WM8580_AIF_FMT_MASK    0x03
 128 #define WM8580_AIF_FMT_RIGHTJ  0x00
 129 #define WM8580_AIF_FMT_LEFTJ   0x01
 130 #define WM8580_AIF_FMT_I2S     0x02
 131 #define WM8580_AIF_FMT_DSP     0x03
 132
 133 #define WM8580_AIF_LENGTH_MASK   0x0c
 134 #define WM8580_AIF_LENGTH_16     0x00
 135 #define WM8580_AIF_LENGTH_20     0x04
 136 #define WM8580_AIF_LENGTH_24     0x08
 137 #define WM8580_AIF_LENGTH_32     0x0c
 138
 139 #define WM8580_AIF_LRP         0x10
 140 #define WM8580_AIF_BCP         0x20
 141
 142 /* Powerdown Register 1 (register 32h) */
 143 #define WM8580_PWRDN1_PWDN     0x001
 144 #define WM8580_PWRDN1_ALLDACPD 0x040
 145
 146 /* Powerdown Register 2 (register 33h) */
 147 #define WM8580_PWRDN2_OSSCPD   0x001
 148 #define WM8580_PWRDN2_PLLAPD   0x002
 149 #define WM8580_PWRDN2_PLLBPD   0x004
 150 #define WM8580_PWRDN2_SPDIFPD  0x008
 151 #define WM8580_PWRDN2_SPDIFTXD 0x010
 152 #define WM8580_PWRDN2_SPDIFRXD 0x020
 153
 154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 155
 156 /*
 157  * wm8580 register cache
 158  * We can't read the WM8580 register space when we
 159  * are using 2 wire for device control, so we cache them instead.
 160  */
 161 static const u16 wm8580_reg[] = {
 162         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 163         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 164         0x0010, 0x0002, 0x0002, 0x00c2, /*R11*/
 165         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 166         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 167         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 168         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 169         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 170         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 171         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 172         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 173         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 174         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 175         0x0000, 0x0000 /*R53*/
 176 };
 177
 178 struct pll_state {
 179         unsigned int in;
 180         unsigned int out;
 181 };
 182
 183 #define WM8580_NUM_SUPPLIES 3
 184 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 185         "AVDD",
 186         "DVDD",
 187         "PVDD",
 188 };
 189
 190 /* codec private data */
 191 struct wm8580_priv {
 192         enum snd_soc_control_type control_type;
 193         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 194         struct pll_state a;
 195         struct pll_state b;
 196         int sysclk[2];
 197 };
 198
 199 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 200
 201 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 202                          struct snd_ctl_elem_value *ucontrol)
 203 {
 204         struct soc_mixer_control *mc =
 205                 (struct soc_mixer_control *)kcontrol->private_value;
 206         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 207         u16 *reg_cache = codec->reg_cache;
 208         unsigned int reg = mc->reg;
 209         unsigned int reg2 = mc->rreg;
 210         int ret;
 211
 212         /* Clear the register cache so we write without VU set */
 213         reg_cache[reg] = 0;
 214         reg_cache[reg2] = 0;
 215
 216         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 217         if (ret < 0)
 218                 return ret;
 219
 220         /* Now write again with the volume update bit set */
 221         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 222         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 223
 224         return 0;
 225 }
 226
 227 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 228 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
 229                      WM8580_DIGITAL_ATTENUATION_DACL1,
 230                      WM8580_DIGITAL_ATTENUATION_DACR1,
 231                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 232 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
 233                      WM8580_DIGITAL_ATTENUATION_DACL2,
 234                      WM8580_DIGITAL_ATTENUATION_DACR2,
 235                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 236 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
 237                      WM8580_DIGITAL_ATTENUATION_DACL3,
 238                      WM8580_DIGITAL_ATTENUATION_DACR3,
 239                      0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
 240
 241 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 242 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 243 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 244
 245 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 246 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 247 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 248
 249 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 250 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
 251 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
 252 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
 253
 254 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
 255 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 256 };
 257
 258 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 259 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 260 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 261 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 262
 263 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 264 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 265 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 266 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 267 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 268 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 269
 270 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 271
 272 SND_SOC_DAPM_INPUT("AINL"),
 273 SND_SOC_DAPM_INPUT("AINR"),
 274 };
 275
 276 static const struct snd_soc_dapm_route audio_map[] = {
 277         { "VOUT1L", NULL, "DAC1" },
 278         { "VOUT1R", NULL, "DAC1" },
 279
 280         { "VOUT2L", NULL, "DAC2" },
 281         { "VOUT2R", NULL, "DAC2" },
 282
 283         { "VOUT3L", NULL, "DAC3" },
 284         { "VOUT3R", NULL, "DAC3" },
 285
 286         { "ADC", NULL, "AINL" },
 287         { "ADC", NULL, "AINR" },
 288 };
 289
 290 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 291 {
 292         struct snd_soc_dapm_context *dapm = &codec->dapm;
 293
 294         snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets,
 295                                   ARRAY_SIZE(wm8580_dapm_widgets));
 296         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 297
 298         return 0;
 299 }
 300
 301 /* PLL divisors */
 302 struct _pll_div {
 303         u32 prescale:1;
 304         u32 postscale:1;
 305         u32 freqmode:2;
 306         u32 n:4;
 307         u32 k:24;
 308 };
 309
 310 /* The size in bits of the pll divide */
 311 #define FIXED_PLL_SIZE (1 << 22)
 312
 313 /* PLL rate to output rate divisions */
 314 static struct {
 315         unsigned int div;
 316         unsigned int freqmode;
 317         unsigned int postscale;
 318 } post_table[] = {
 319         {  2,  0, 0 },
 320         {  4,  0, 1 },
 321         {  4,  1, 0 },
 322         {  8,  1, 1 },
 323         {  8,  2, 0 },
 324         { 16,  2, 1 },
 325         { 12,  3, 0 },
 326         { 24,  3, 1 }
 327 };
 328
 329 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 330                        unsigned int source)
 331 {
 332         u64 Kpart;
 333         unsigned int K, Ndiv, Nmod;
 334         int i;
 335
 336         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 337
 338         /* Scale the output frequency up; the PLL should run in the
 339          * region of 90-100MHz.
 340          */
 341         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 342                 if (target * post_table[i].div >=  90000000 &&
 343                     target * post_table[i].div <= 100000000) {
 344                         pll_div->freqmode = post_table[i].freqmode;
 345                         pll_div->postscale = post_table[i].postscale;
 346                         target *= post_table[i].div;
 347                         break;
 348                 }
 349         }
 350
 351         if (i == ARRAY_SIZE(post_table)) {
 352                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 353                        "%u\n", target);
 354                 return -EINVAL;
 355         }
 356
 357         Ndiv = target / source;
 358
 359         if (Ndiv < 5) {
 360                 source /= 2;
 361                 pll_div->prescale = 1;
 362                 Ndiv = target / source;
 363         } else
 364                 pll_div->prescale = 0;
 365
 366         if ((Ndiv < 5) || (Ndiv > 13)) {
 367                 printk(KERN_ERR
 368                         "WM8580 N=%u outside supported range\n", Ndiv);
 369                 return -EINVAL;
 370         }
 371
 372         pll_div->n = Ndiv;
 373         Nmod = target % source;
 374         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 375
 376         do_div(Kpart, source);
 377
 378         K = Kpart & 0xFFFFFFFF;
 379
 380         pll_div->k = K;
 381
 382         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 383                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 384                  pll_div->postscale);
 385
 386         return 0;
 387 }
 388
 389 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 390                 int source, unsigned int freq_in, unsigned int freq_out)
 391 {
 392         int offset;
 393         struct snd_soc_codec *codec = codec_dai->codec;
 394         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 395         struct pll_state *state;
 396         struct _pll_div pll_div;
 397         unsigned int reg;
 398         unsigned int pwr_mask;
 399         int ret;
 400
 401         /* GCC isn't able to work out the ifs below for initialising/using
 402          * pll_div so suppress warnings.
 403          */
 404         memset(&pll_div, 0, sizeof(pll_div));
 405
 406         switch (pll_id) {
 407         case WM8580_PLLA:
 408                 state = &wm8580->a;
 409                 offset = 0;
 410                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 411                 break;
 412         case WM8580_PLLB:
 413                 state = &wm8580->b;
 414                 offset = 4;
 415                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 416                 break;
 417         default:
 418                 return -ENODEV;
 419         }
 420
 421         if (freq_in && freq_out) {
 422                 ret = pll_factors(&pll_div, freq_out, freq_in);
 423                 if (ret != 0)
 424                         return ret;
 425         }
 426
 427         state->in = freq_in;
 428         state->out = freq_out;
 429
 430         /* Always disable the PLL - it is not safe to leave it running
 431          * while reprogramming it.
 432          */
 433         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
 434
 435         if (!freq_in || !freq_out)
 436                 return 0;
 437
 438         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 439         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 440         snd_soc_write(codec, WM8580_PLLA3 + offset,
 441                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 442
 443         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 444         reg &= ~0x1b;
 445         reg |= pll_div.prescale | pll_div.postscale << 1 |
 446                 pll_div.freqmode << 3;
 447
 448         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 449
 450         /* All done, turn it on */
 451         snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
 452
 453         return 0;
 454 }
 455
 456 static const int wm8580_sysclk_ratios[] = {
 457         128, 192, 256, 384, 512, 768, 1152,
 458 };
 459
 460 /*
 461  * Set PCM DAI bit size and sample rate.
 462  */
 463 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 464                                  struct snd_pcm_hw_params *params,
 465                                  struct snd_soc_dai *dai)
 466 {
 467         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 468         struct snd_soc_codec *codec = rtd->codec;
 469         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 470         u16 paifa = 0;
 471         u16 paifb = 0;
 472         int i, ratio, osr;
 473
 474         /* bit size */
 475         switch (params_format(params)) {
 476         case SNDRV_PCM_FORMAT_S16_LE:
 477                 paifa |= 0x8;
 478                 break;
 479         case SNDRV_PCM_FORMAT_S20_3LE:
 480                 paifa |= 0x0;
 481                 paifb |= WM8580_AIF_LENGTH_20;
 482                 break;
 483         case SNDRV_PCM_FORMAT_S24_LE:
 484                 paifa |= 0x0;
 485                 paifb |= WM8580_AIF_LENGTH_24;
 486                 break;
 487         case SNDRV_PCM_FORMAT_S32_LE:
 488                 paifa |= 0x0;
 489                 paifb |= WM8580_AIF_LENGTH_32;
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         /* Look up the SYSCLK ratio; accept only exact matches */
 496         ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
 497         for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
 498                 if (ratio == wm8580_sysclk_ratios[i])
 499                         break;
 500         if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
 501                 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
 502                         wm8580->sysclk[dai->driver->id], params_rate(params));
 503                 return -EINVAL;
 504         }
 505         paifa |= i;
 506         dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
 507                 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
 508
 509         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 510                 switch (ratio) {
 511                 case 128:
 512                 case 192:
 513                         osr = WM8580_DACOSR;
 514                         dev_dbg(codec->dev, "Selecting 64x OSR\n");
 515                         break;
 516                 default:
 517                         osr = 0;
 518                         dev_dbg(codec->dev, "Selecting 128x OSR\n");
 519                         break;
 520                 }
 521
 522                 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
 523         }
 524
 525         snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
 526                             WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
 527                             paifa);
 528         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 529                             WM8580_AIF_LENGTH_MASK, paifb);
 530         return 0;
 531 }
 532
 533 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 534                                       unsigned int fmt)
 535 {
 536         struct snd_soc_codec *codec = codec_dai->codec;
 537         unsigned int aifa;
 538         unsigned int aifb;
 539         int can_invert_lrclk;
 540
 541         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 542         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 543
 544         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 545
 546         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 547         case SND_SOC_DAIFMT_CBS_CFS:
 548                 aifa &= ~WM8580_AIF_MS;
 549                 break;
 550         case SND_SOC_DAIFMT_CBM_CFM:
 551                 aifa |= WM8580_AIF_MS;
 552                 break;
 553         default:
 554                 return -EINVAL;
 555         }
 556
 557         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 558         case SND_SOC_DAIFMT_I2S:
 559                 can_invert_lrclk = 1;
 560                 aifb |= WM8580_AIF_FMT_I2S;
 561                 break;
 562         case SND_SOC_DAIFMT_RIGHT_J:
 563                 can_invert_lrclk = 1;
 564                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 565                 break;
 566         case SND_SOC_DAIFMT_LEFT_J:
 567                 can_invert_lrclk = 1;
 568                 aifb |= WM8580_AIF_FMT_LEFTJ;
 569                 break;
 570         case SND_SOC_DAIFMT_DSP_A:
 571                 can_invert_lrclk = 0;
 572                 aifb |= WM8580_AIF_FMT_DSP;
 573                 break;
 574         case SND_SOC_DAIFMT_DSP_B:
 575                 can_invert_lrclk = 0;
 576                 aifb |= WM8580_AIF_FMT_DSP;
 577                 aifb |= WM8580_AIF_LRP;
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582
 583         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 584         case SND_SOC_DAIFMT_NB_NF:
 585                 break;
 586
 587         case SND_SOC_DAIFMT_IB_IF:
 588                 if (!can_invert_lrclk)
 589                         return -EINVAL;
 590                 aifb |= WM8580_AIF_BCP;
 591                 aifb |= WM8580_AIF_LRP;
 592                 break;
 593
 594         case SND_SOC_DAIFMT_IB_NF:
 595                 aifb |= WM8580_AIF_BCP;
 596                 break;
 597
 598         case SND_SOC_DAIFMT_NB_IF:
 599                 if (!can_invert_lrclk)
 600                         return -EINVAL;
 601                 aifb |= WM8580_AIF_LRP;
 602                 break;
 603
 604         default:
 605                 return -EINVAL;
 606         }
 607
 608         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 609         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 610
 611         return 0;
 612 }
 613
 614 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 615                                  int div_id, int div)
 616 {
 617         struct snd_soc_codec *codec = codec_dai->codec;
 618         unsigned int reg;
 619
 620         switch (div_id) {
 621         case WM8580_MCLK:
 622                 reg = snd_soc_read(codec, WM8580_PLLB4);
 623                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 624
 625                 switch (div) {
 626                 case WM8580_CLKSRC_MCLK:
 627                         /* Input */
 628                         break;
 629
 630                 case WM8580_CLKSRC_PLLA:
 631                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 632                         break;
 633                 case WM8580_CLKSRC_PLLB:
 634                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 635                         break;
 636
 637                 case WM8580_CLKSRC_OSC:
 638                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 639                         break;
 640
 641                 default:
 642                         return -EINVAL;
 643                 }
 644                 snd_soc_write(codec, WM8580_PLLB4, reg);
 645                 break;
 646
 647         case WM8580_CLKOUTSRC:
 648                 reg = snd_soc_read(codec, WM8580_PLLB4);
 649                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 650
 651                 switch (div) {
 652                 case WM8580_CLKSRC_NONE:
 653                         break;
 654
 655                 case WM8580_CLKSRC_PLLA:
 656                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 657                         break;
 658
 659                 case WM8580_CLKSRC_PLLB:
 660                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 661                         break;
 662
 663                 case WM8580_CLKSRC_OSC:
 664                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 665                         break;
 666
 667                 default:
 668                         return -EINVAL;
 669                 }
 670                 snd_soc_write(codec, WM8580_PLLB4, reg);
 671                 break;
 672
 673         default:
 674                 return -EINVAL;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 681                              unsigned int freq, int dir)
 682 {
 683         struct snd_soc_codec *codec = dai->codec;
 684         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 685         int sel, sel_mask, sel_shift;
 686
 687         switch (dai->driver->id) {
 688         case WM8580_DAI_PAIFRX:
 689                 sel_mask = 0x3;
 690                 sel_shift = 0;
 691                 break;
 692
 693         case WM8580_DAI_PAIFTX:
 694                 sel_mask = 0xc;
 695                 sel_shift = 2;
 696                 break;
 697
 698         default:
 699                 BUG_ON("Unknown DAI driver ID\n");
 700                 return -EINVAL;
 701         }
 702
 703         switch (clk_id) {
 704         case WM8580_CLKSRC_ADCMCLK:
 705                 if (dai->driver->id != WM8580_DAI_PAIFTX)
 706                         return -EINVAL;
 707                 sel = 0 << sel_shift;
 708                 break;
 709         case WM8580_CLKSRC_PLLA:
 710                 sel = 1 << sel_shift;
 711                 break;
 712         case WM8580_CLKSRC_PLLB:
 713                 sel = 2 << sel_shift;
 714                 break;
 715         case WM8580_CLKSRC_MCLK:
 716                 sel = 3 << sel_shift;
 717                 break;
 718         default:
 719                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
 720                 return -EINVAL;
 721         }
 722
 723         /* We really should validate PLL settings but not yet */
 724         wm8580->sysclk[dai->driver->id] = freq;
 725
 726         return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
 727 }
 728
 729 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 730 {
 731         struct snd_soc_codec *codec = codec_dai->codec;
 732         unsigned int reg;
 733
 734         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 735
 736         if (mute)
 737                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 738         else
 739                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 740
 741         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 742
 743         return 0;
 744 }
 745
 746 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 747         enum snd_soc_bias_level level)
 748 {
 749         switch (level) {
 750         case SND_SOC_BIAS_ON:
 751         case SND_SOC_BIAS_PREPARE:
 752                 break;
 753
 754         case SND_SOC_BIAS_STANDBY:
 755                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 756                         /* Power up and get individual control of the DACs */
 757                         snd_soc_update_bits(codec, WM8580_PWRDN1,
 758                                             WM8580_PWRDN1_PWDN |
 759                                             WM8580_PWRDN1_ALLDACPD, 0);
 760
 761                         /* Make VMID high impedance */
 762                         snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
 763                                             0x100, 0);
 764                 }
 765                 break;
 766
 767         case SND_SOC_BIAS_OFF:
 768                 snd_soc_update_bits(codec, WM8580_PWRDN1,
 769                                     WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
 770                 break;
 771         }
 772         codec->dapm.bias_level = level;
 773         return 0;
 774 }
 775
 776 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 777                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 778
 779 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 780         .set_sysclk     = wm8580_set_sysclk,
 781         .hw_params      = wm8580_paif_hw_params,
 782         .set_fmt        = wm8580_set_paif_dai_fmt,
 783         .set_clkdiv     = wm8580_set_dai_clkdiv,
 784         .set_pll        = wm8580_set_dai_pll,
 785         .digital_mute   = wm8580_digital_mute,
 786 };
 787
 788 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 789         .set_sysclk     = wm8580_set_sysclk,
 790         .hw_params      = wm8580_paif_hw_params,
 791         .set_fmt        = wm8580_set_paif_dai_fmt,
 792         .set_clkdiv     = wm8580_set_dai_clkdiv,
 793         .set_pll        = wm8580_set_dai_pll,
 794 };
 795
 796 static struct snd_soc_dai_driver wm8580_dai[] = {
 797         {
 798                 .name = "wm8580-hifi-playback",
 799                 .id     = WM8580_DAI_PAIFRX,
 800                 .playback = {
 801                         .stream_name = "Playback",
 802                         .channels_min = 1,
 803                         .channels_max = 6,
 804                         .rates = SNDRV_PCM_RATE_8000_192000,
 805                         .formats = WM8580_FORMATS,
 806                 },
 807                 .ops = &wm8580_dai_ops_playback,
 808         },
 809         {
 810                 .name = "wm8580-hifi-capture",
 811                 .id     =       WM8580_DAI_PAIFTX,
 812                 .capture = {
 813                         .stream_name = "Capture",
 814                         .channels_min = 2,
 815                         .channels_max = 2,
 816                         .rates = SNDRV_PCM_RATE_8000_192000,
 817                         .formats = WM8580_FORMATS,
 818                 },
 819                 .ops = &wm8580_dai_ops_capture,
 820         },
 821 };
 822
 823 static int wm8580_probe(struct snd_soc_codec *codec)
 824 {
 825         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 826         int ret = 0,i;
 827
 828         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
 829         if (ret < 0) {
 830                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 831                 return ret;
 832         }
 833
 834         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 835                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 836
 837         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 838                                  wm8580->supplies);
 839         if (ret != 0) {
 840                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 841                 return ret;
 842         }
 843
 844         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 845                                     wm8580->supplies);
 846         if (ret != 0) {
 847                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 848                 goto err_regulator_get;
 849         }
 850
 851         /* Get the codec into a known state */
 852         ret = snd_soc_write(codec, WM8580_RESET, 0);
 853         if (ret != 0) {
 854                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 855                 goto err_regulator_enable;
 856         }
 857
 858         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 859
 860         snd_soc_add_controls(codec, wm8580_snd_controls,
 861                              ARRAY_SIZE(wm8580_snd_controls));
 862         wm8580_add_widgets(codec);
 863
 864         return 0;
 865
 866 err_regulator_enable:
 867         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 868 err_regulator_get:
 869         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 870         return ret;
 871 }
 872
 873 /* power down chip */
 874 static int wm8580_remove(struct snd_soc_codec *codec)
 875 {
 876         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 877
 878         wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
 879
 880         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 881         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 882
 883         return 0;
 884 }
 885
 886 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 887         .probe =        wm8580_probe,
 888         .remove =       wm8580_remove,
 889         .set_bias_level = wm8580_set_bias_level,
 890         .reg_cache_size = ARRAY_SIZE(wm8580_reg),
 891         .reg_word_size = sizeof(u16),
 892         .reg_cache_default = wm8580_reg,
 893 };
 894
 895 static const struct of_device_id wm8580_of_match[] = {
 896         { .compatible = "wlf,wm8580" },
 897         { },
 898 };
 899
 900 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 901 static int wm8580_i2c_probe(struct i2c_client *i2c,
 902                             const struct i2c_device_id *id)
 903 {
 904         struct wm8580_priv *wm8580;
 905         int ret;
 906
 907         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 908         if (wm8580 == NULL)
 909                 return -ENOMEM;
 910
 911         i2c_set_clientdata(i2c, wm8580);
 912         wm8580->control_type = SND_SOC_I2C;
 913
 914         ret =  snd_soc_register_codec(&i2c->dev,
 915                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 916         if (ret < 0)
 917                 kfree(wm8580);
 918         return ret;
 919 }
 920
 921 static int wm8580_i2c_remove(struct i2c_client *client)
 922 {
 923         snd_soc_unregister_codec(&client->dev);
 924         kfree(i2c_get_clientdata(client));
 925         return 0;
 926 }
 927
 928 static const struct i2c_device_id wm8580_i2c_id[] = {
 929         { "wm8580", 0 },
 930         { }
 931 };
 932 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 933
 934 static struct i2c_driver wm8580_i2c_driver = {
 935         .driver = {
 936                 .name = "wm8580",
 937                 .owner = THIS_MODULE,
 938                 .of_match_table = wm8580_of_match,
 939         },
 940         .probe =    wm8580_i2c_probe,
 941         .remove =   wm8580_i2c_remove,
 942         .id_table = wm8580_i2c_id,
 943 };
 944 #endif
 945
 946 static int __init wm8580_modinit(void)
 947 {
 948         int ret = 0;
 949
 950 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 951         ret = i2c_add_driver(&wm8580_i2c_driver);
 952         if (ret != 0) {
 953                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 954         }
 955 #endif
 956
 957         return ret;
 958 }
 959 module_init(wm8580_modinit);
 960
 961 static void __exit wm8580_exit(void)
 962 {
 963 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 964         i2c_del_driver(&wm8580_i2c_driver);
 965 #endif
 966 }
 967 module_exit(wm8580_exit);
 968
 969 MODULE_DESCRIPTION("ASoC WM8580 driver");
 970 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 971 MODULE_LICENSE("GPL");