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5ebe2c04e5cfe3084c14d1125b53a25916d21f5e
[deliverable/linux.git] / sound / soc / codecs / wm8961.c
1 /*
2 * wm8961.c -- WM8961 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Currently unimplemented features:
11 * - ALC
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include "wm8961.h"
31
32 #define WM8961_MAX_REGISTER 0xFC
33
34 static u16 wm8961_reg_defaults[] = {
35 0x009F, /* R0 - Left Input volume */
36 0x009F, /* R1 - Right Input volume */
37 0x0000, /* R2 - LOUT1 volume */
38 0x0000, /* R3 - ROUT1 volume */
39 0x0020, /* R4 - Clocking1 */
40 0x0008, /* R5 - ADC & DAC Control 1 */
41 0x0000, /* R6 - ADC & DAC Control 2 */
42 0x000A, /* R7 - Audio Interface 0 */
43 0x01F4, /* R8 - Clocking2 */
44 0x0000, /* R9 - Audio Interface 1 */
45 0x00FF, /* R10 - Left DAC volume */
46 0x00FF, /* R11 - Right DAC volume */
47 0x0000, /* R12 */
48 0x0000, /* R13 */
49 0x0040, /* R14 - Audio Interface 2 */
50 0x0000, /* R15 - Software Reset */
51 0x0000, /* R16 */
52 0x007B, /* R17 - ALC1 */
53 0x0000, /* R18 - ALC2 */
54 0x0032, /* R19 - ALC3 */
55 0x0000, /* R20 - Noise Gate */
56 0x00C0, /* R21 - Left ADC volume */
57 0x00C0, /* R22 - Right ADC volume */
58 0x0120, /* R23 - Additional control(1) */
59 0x0000, /* R24 - Additional control(2) */
60 0x0000, /* R25 - Pwr Mgmt (1) */
61 0x0000, /* R26 - Pwr Mgmt (2) */
62 0x0000, /* R27 - Additional Control (3) */
63 0x0000, /* R28 - Anti-pop */
64 0x0000, /* R29 */
65 0x005F, /* R30 - Clocking 3 */
66 0x0000, /* R31 */
67 0x0000, /* R32 - ADCL signal path */
68 0x0000, /* R33 - ADCR signal path */
69 0x0000, /* R34 */
70 0x0000, /* R35 */
71 0x0000, /* R36 */
72 0x0000, /* R37 */
73 0x0000, /* R38 */
74 0x0000, /* R39 */
75 0x0000, /* R40 - LOUT2 volume */
76 0x0000, /* R41 - ROUT2 volume */
77 0x0000, /* R42 */
78 0x0000, /* R43 */
79 0x0000, /* R44 */
80 0x0000, /* R45 */
81 0x0000, /* R46 */
82 0x0000, /* R47 - Pwr Mgmt (3) */
83 0x0023, /* R48 - Additional Control (4) */
84 0x0000, /* R49 - Class D Control 1 */
85 0x0000, /* R50 */
86 0x0003, /* R51 - Class D Control 2 */
87 0x0000, /* R52 */
88 0x0000, /* R53 */
89 0x0000, /* R54 */
90 0x0000, /* R55 */
91 0x0106, /* R56 - Clocking 4 */
92 0x0000, /* R57 - DSP Sidetone 0 */
93 0x0000, /* R58 - DSP Sidetone 1 */
94 0x0000, /* R59 */
95 0x0000, /* R60 - DC Servo 0 */
96 0x0000, /* R61 - DC Servo 1 */
97 0x0000, /* R62 */
98 0x015E, /* R63 - DC Servo 3 */
99 0x0010, /* R64 */
100 0x0010, /* R65 - DC Servo 5 */
101 0x0000, /* R66 */
102 0x0001, /* R67 */
103 0x0003, /* R68 - Analogue PGA Bias */
104 0x0000, /* R69 - Analogue HP 0 */
105 0x0060, /* R70 */
106 0x01FB, /* R71 - Analogue HP 2 */
107 0x0000, /* R72 - Charge Pump 1 */
108 0x0065, /* R73 */
109 0x005F, /* R74 */
110 0x0059, /* R75 */
111 0x006B, /* R76 */
112 0x0038, /* R77 */
113 0x000C, /* R78 */
114 0x000A, /* R79 */
115 0x006B, /* R80 */
116 0x0000, /* R81 */
117 0x0000, /* R82 - Charge Pump B */
118 0x0087, /* R83 */
119 0x0000, /* R84 */
120 0x005C, /* R85 */
121 0x0000, /* R86 */
122 0x0000, /* R87 - Write Sequencer 1 */
123 0x0000, /* R88 - Write Sequencer 2 */
124 0x0000, /* R89 - Write Sequencer 3 */
125 0x0000, /* R90 - Write Sequencer 4 */
126 0x0000, /* R91 - Write Sequencer 5 */
127 0x0000, /* R92 - Write Sequencer 6 */
128 0x0000, /* R93 - Write Sequencer 7 */
129 0x0000, /* R94 */
130 0x0000, /* R95 */
131 0x0000, /* R96 */
132 0x0000, /* R97 */
133 0x0000, /* R98 */
134 0x0000, /* R99 */
135 0x0000, /* R100 */
136 0x0000, /* R101 */
137 0x0000, /* R102 */
138 0x0000, /* R103 */
139 0x0000, /* R104 */
140 0x0000, /* R105 */
141 0x0000, /* R106 */
142 0x0000, /* R107 */
143 0x0000, /* R108 */
144 0x0000, /* R109 */
145 0x0000, /* R110 */
146 0x0000, /* R111 */
147 0x0000, /* R112 */
148 0x0000, /* R113 */
149 0x0000, /* R114 */
150 0x0000, /* R115 */
151 0x0000, /* R116 */
152 0x0000, /* R117 */
153 0x0000, /* R118 */
154 0x0000, /* R119 */
155 0x0000, /* R120 */
156 0x0000, /* R121 */
157 0x0000, /* R122 */
158 0x0000, /* R123 */
159 0x0000, /* R124 */
160 0x0000, /* R125 */
161 0x0000, /* R126 */
162 0x0000, /* R127 */
163 0x0000, /* R128 */
164 0x0000, /* R129 */
165 0x0000, /* R130 */
166 0x0000, /* R131 */
167 0x0000, /* R132 */
168 0x0000, /* R133 */
169 0x0000, /* R134 */
170 0x0000, /* R135 */
171 0x0000, /* R136 */
172 0x0000, /* R137 */
173 0x0000, /* R138 */
174 0x0000, /* R139 */
175 0x0000, /* R140 */
176 0x0000, /* R141 */
177 0x0000, /* R142 */
178 0x0000, /* R143 */
179 0x0000, /* R144 */
180 0x0000, /* R145 */
181 0x0000, /* R146 */
182 0x0000, /* R147 */
183 0x0000, /* R148 */
184 0x0000, /* R149 */
185 0x0000, /* R150 */
186 0x0000, /* R151 */
187 0x0000, /* R152 */
188 0x0000, /* R153 */
189 0x0000, /* R154 */
190 0x0000, /* R155 */
191 0x0000, /* R156 */
192 0x0000, /* R157 */
193 0x0000, /* R158 */
194 0x0000, /* R159 */
195 0x0000, /* R160 */
196 0x0000, /* R161 */
197 0x0000, /* R162 */
198 0x0000, /* R163 */
199 0x0000, /* R164 */
200 0x0000, /* R165 */
201 0x0000, /* R166 */
202 0x0000, /* R167 */
203 0x0000, /* R168 */
204 0x0000, /* R169 */
205 0x0000, /* R170 */
206 0x0000, /* R171 */
207 0x0000, /* R172 */
208 0x0000, /* R173 */
209 0x0000, /* R174 */
210 0x0000, /* R175 */
211 0x0000, /* R176 */
212 0x0000, /* R177 */
213 0x0000, /* R178 */
214 0x0000, /* R179 */
215 0x0000, /* R180 */
216 0x0000, /* R181 */
217 0x0000, /* R182 */
218 0x0000, /* R183 */
219 0x0000, /* R184 */
220 0x0000, /* R185 */
221 0x0000, /* R186 */
222 0x0000, /* R187 */
223 0x0000, /* R188 */
224 0x0000, /* R189 */
225 0x0000, /* R190 */
226 0x0000, /* R191 */
227 0x0000, /* R192 */
228 0x0000, /* R193 */
229 0x0000, /* R194 */
230 0x0000, /* R195 */
231 0x0030, /* R196 */
232 0x0006, /* R197 */
233 0x0000, /* R198 */
234 0x0060, /* R199 */
235 0x0000, /* R200 */
236 0x003F, /* R201 */
237 0x0000, /* R202 */
238 0x0000, /* R203 */
239 0x0000, /* R204 */
240 0x0001, /* R205 */
241 0x0000, /* R206 */
242 0x0181, /* R207 */
243 0x0005, /* R208 */
244 0x0008, /* R209 */
245 0x0008, /* R210 */
246 0x0000, /* R211 */
247 0x013B, /* R212 */
248 0x0000, /* R213 */
249 0x0000, /* R214 */
250 0x0000, /* R215 */
251 0x0000, /* R216 */
252 0x0070, /* R217 */
253 0x0000, /* R218 */
254 0x0000, /* R219 */
255 0x0000, /* R220 */
256 0x0000, /* R221 */
257 0x0000, /* R222 */
258 0x0003, /* R223 */
259 0x0000, /* R224 */
260 0x0000, /* R225 */
261 0x0001, /* R226 */
262 0x0008, /* R227 */
263 0x0000, /* R228 */
264 0x0000, /* R229 */
265 0x0000, /* R230 */
266 0x0000, /* R231 */
267 0x0004, /* R232 */
268 0x0000, /* R233 */
269 0x0000, /* R234 */
270 0x0000, /* R235 */
271 0x0000, /* R236 */
272 0x0000, /* R237 */
273 0x0080, /* R238 */
274 0x0000, /* R239 */
275 0x0000, /* R240 */
276 0x0000, /* R241 */
277 0x0000, /* R242 */
278 0x0000, /* R243 */
279 0x0000, /* R244 */
280 0x0052, /* R245 */
281 0x0110, /* R246 */
282 0x0040, /* R247 */
283 0x0000, /* R248 */
284 0x0030, /* R249 */
285 0x0000, /* R250 */
286 0x0000, /* R251 */
287 0x0001, /* R252 - General test 1 */
288 };
289
290 struct wm8961_priv {
291 enum snd_soc_control_type control_type;
292 void *control_data;
293 int sysclk;
294 u16 reg_cache[WM8961_MAX_REGISTER];
295 };
296
297 static int wm8961_volatile_register(unsigned int reg)
298 {
299 switch (reg) {
300 case WM8961_SOFTWARE_RESET:
301 case WM8961_WRITE_SEQUENCER_7:
302 case WM8961_DC_SERVO_1:
303 return 1;
304
305 default:
306 return 0;
307 }
308 }
309
310 static int wm8961_reset(struct snd_soc_codec *codec)
311 {
312 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
313 }
314
315 /*
316 * The headphone output supports special anti-pop sequences giving
317 * silent power up and power down.
318 */
319 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
320 struct snd_kcontrol *kcontrol, int event)
321 {
322 struct snd_soc_codec *codec = w->codec;
323 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
324 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
325 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
326 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
327 int timeout = 500;
328
329 if (event & SND_SOC_DAPM_POST_PMU) {
330 /* Make sure the output is shorted */
331 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
332 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
333
334 /* Enable the charge pump */
335 cp_reg |= WM8961_CP_ENA;
336 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
337 mdelay(5);
338
339 /* Enable the PGA */
340 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
341 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
342
343 /* Enable the amplifier */
344 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
345 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
346
347 /* Second stage enable */
348 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
349 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
350
351 /* Enable the DC servo & trigger startup */
352 dcs_reg |=
353 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
354 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
355 dev_dbg(codec->dev, "Enabling DC servo\n");
356
357 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
358 do {
359 msleep(1);
360 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
361 } while (--timeout &&
362 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
363 WM8961_DCS_TRIG_STARTUP_HPL));
364 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
365 WM8961_DCS_TRIG_STARTUP_HPL))
366 dev_err(codec->dev, "DC servo timed out\n");
367 else
368 dev_dbg(codec->dev, "DC servo startup complete\n");
369
370 /* Enable the output stage */
371 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
372 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
373
374 /* Remove the short on the output stage */
375 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
376 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
377 }
378
379 if (event & SND_SOC_DAPM_PRE_PMD) {
380 /* Short the output */
381 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
382 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
383
384 /* Disable the output stage */
385 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
386 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
387
388 /* Disable DC offset cancellation */
389 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
390 WM8961_DCS_ENA_CHAN_HPL);
391 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
392
393 /* Finish up */
394 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
395 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
396 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
397
398 /* Disable the PGA */
399 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
400 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
401
402 /* Disable the charge pump */
403 dev_dbg(codec->dev, "Disabling charge pump\n");
404 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
405 cp_reg & ~WM8961_CP_ENA);
406 }
407
408 return 0;
409 }
410
411 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
412 struct snd_kcontrol *kcontrol, int event)
413 {
414 struct snd_soc_codec *codec = w->codec;
415 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
416 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
417
418 if (event & SND_SOC_DAPM_POST_PMU) {
419 /* Enable the PGA */
420 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
421 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
422
423 /* Enable the amplifier */
424 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
425 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
426 }
427
428 if (event & SND_SOC_DAPM_PRE_PMD) {
429 /* Enable the amplifier */
430 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
431 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
432
433 /* Enable the PGA */
434 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
435 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
436 }
437
438 return 0;
439 }
440
441 static const char *adc_hpf_text[] = {
442 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
443 };
444
445 static const struct soc_enum adc_hpf =
446 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
447
448 static const char *dac_deemph_text[] = {
449 "None", "32kHz", "44.1kHz", "48kHz",
450 };
451
452 static const struct soc_enum dac_deemph =
453 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
454
455 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
456 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
457 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
458 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
459 static unsigned int boost_tlv[] = {
460 TLV_DB_RANGE_HEAD(4),
461 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
462 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
463 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
464 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
465 };
466 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
467
468 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
469 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
470 0, 127, 0, out_tlv),
471 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
472 6, 3, 7, 0, hp_sec_tlv),
473 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
474 7, 1, 0),
475
476 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
477 0, 127, 0, out_tlv),
478 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
479 7, 1, 0),
480 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
481
482 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
483 SOC_ENUM("DAC Deemphasis", dac_deemph),
484 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
485
486 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
487 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
488
489 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
490 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
491
492 SOC_DOUBLE_R_TLV("Capture Volume",
493 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
494 1, 119, 0, adc_tlv),
495 SOC_DOUBLE_R_TLV("Capture Boost Volume",
496 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
497 4, 3, 0, boost_tlv),
498 SOC_DOUBLE_R_TLV("Capture PGA Volume",
499 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
500 0, 62, 0, pga_tlv),
501 SOC_DOUBLE_R("Capture PGA ZC Switch",
502 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
503 6, 1, 1),
504 SOC_DOUBLE_R("Capture PGA Switch",
505 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
506 7, 1, 1),
507 };
508
509 static const char *sidetone_text[] = {
510 "None", "Left", "Right"
511 };
512
513 static const struct soc_enum dacl_sidetone =
514 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
515
516 static const struct soc_enum dacr_sidetone =
517 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
518
519 static const struct snd_kcontrol_new dacl_mux =
520 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
521
522 static const struct snd_kcontrol_new dacr_mux =
523 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
524
525 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
526 SND_SOC_DAPM_INPUT("LINPUT"),
527 SND_SOC_DAPM_INPUT("RINPUT"),
528
529 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
530
531 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
532 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
533
534 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
535 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
536
537 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
538
539 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
540 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
541
542 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
543 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
544
545 /* Handle as a mono path for DCS */
546 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
547 4, 0, NULL, 0, wm8961_hp_event,
548 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
549 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
550 4, 0, NULL, 0, wm8961_spk_event,
551 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
552
553 SND_SOC_DAPM_OUTPUT("HP_L"),
554 SND_SOC_DAPM_OUTPUT("HP_R"),
555 SND_SOC_DAPM_OUTPUT("SPK_LN"),
556 SND_SOC_DAPM_OUTPUT("SPK_LP"),
557 SND_SOC_DAPM_OUTPUT("SPK_RN"),
558 SND_SOC_DAPM_OUTPUT("SPK_RP"),
559 };
560
561
562 static const struct snd_soc_dapm_route audio_paths[] = {
563 { "DACL", NULL, "CLK_DSP" },
564 { "DACL", NULL, "DACL Sidetone" },
565 { "DACR", NULL, "CLK_DSP" },
566 { "DACR", NULL, "DACR Sidetone" },
567
568 { "DACL Sidetone", "Left", "ADCL" },
569 { "DACL Sidetone", "Right", "ADCR" },
570
571 { "DACR Sidetone", "Left", "ADCL" },
572 { "DACR Sidetone", "Right", "ADCR" },
573
574 { "HP_L", NULL, "Headphone Output" },
575 { "HP_R", NULL, "Headphone Output" },
576 { "Headphone Output", NULL, "DACL" },
577 { "Headphone Output", NULL, "DACR" },
578
579 { "SPK_LN", NULL, "Speaker Output" },
580 { "SPK_LP", NULL, "Speaker Output" },
581 { "SPK_RN", NULL, "Speaker Output" },
582 { "SPK_RP", NULL, "Speaker Output" },
583
584 { "Speaker Output", NULL, "DACL" },
585 { "Speaker Output", NULL, "DACR" },
586
587 { "ADCL", NULL, "Left Input" },
588 { "ADCL", NULL, "CLK_DSP" },
589 { "ADCR", NULL, "Right Input" },
590 { "ADCR", NULL, "CLK_DSP" },
591
592 { "Left Input", NULL, "LINPUT" },
593 { "Right Input", NULL, "RINPUT" },
594
595 };
596
597 /* Values for CLK_SYS_RATE */
598 static struct {
599 int ratio;
600 u16 val;
601 } wm8961_clk_sys_ratio[] = {
602 { 64, 0 },
603 { 128, 1 },
604 { 192, 2 },
605 { 256, 3 },
606 { 384, 4 },
607 { 512, 5 },
608 { 768, 6 },
609 { 1024, 7 },
610 { 1408, 8 },
611 { 1536, 9 },
612 };
613
614 /* Values for SAMPLE_RATE */
615 static struct {
616 int rate;
617 u16 val;
618 } wm8961_srate[] = {
619 { 48000, 0 },
620 { 44100, 0 },
621 { 32000, 1 },
622 { 22050, 2 },
623 { 24000, 2 },
624 { 16000, 3 },
625 { 11250, 4 },
626 { 12000, 4 },
627 { 8000, 5 },
628 };
629
630 static int wm8961_hw_params(struct snd_pcm_substream *substream,
631 struct snd_pcm_hw_params *params,
632 struct snd_soc_dai *dai)
633 {
634 struct snd_soc_codec *codec = dai->codec;
635 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
636 int i, best, target, fs;
637 u16 reg;
638
639 fs = params_rate(params);
640
641 if (!wm8961->sysclk) {
642 dev_err(codec->dev, "MCLK has not been specified\n");
643 return -EINVAL;
644 }
645
646 /* Find the closest sample rate for the filters */
647 best = 0;
648 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
649 if (abs(wm8961_srate[i].rate - fs) <
650 abs(wm8961_srate[best].rate - fs))
651 best = i;
652 }
653 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
654 reg &= ~WM8961_SAMPLE_RATE_MASK;
655 reg |= wm8961_srate[best].val;
656 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
657 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
658 wm8961_srate[best].rate, fs);
659
660 /* Select a CLK_SYS/fs ratio equal to or higher than required */
661 target = wm8961->sysclk / fs;
662
663 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
664 dev_err(codec->dev,
665 "SYSCLK must be at least 64*fs for DAC\n");
666 return -EINVAL;
667 }
668 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
669 dev_err(codec->dev,
670 "SYSCLK must be at least 256*fs for ADC\n");
671 return -EINVAL;
672 }
673
674 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
675 if (wm8961_clk_sys_ratio[i].ratio >= target)
676 break;
677 }
678 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
679 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
680 return -EINVAL;
681 }
682 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
683 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
684 wm8961->sysclk / fs);
685
686 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
687 reg &= ~WM8961_CLK_SYS_RATE_MASK;
688 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
689 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
690
691 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
692 reg &= ~WM8961_WL_MASK;
693 switch (params_format(params)) {
694 case SNDRV_PCM_FORMAT_S16_LE:
695 break;
696 case SNDRV_PCM_FORMAT_S20_3LE:
697 reg |= 1 << WM8961_WL_SHIFT;
698 break;
699 case SNDRV_PCM_FORMAT_S24_LE:
700 reg |= 2 << WM8961_WL_SHIFT;
701 break;
702 case SNDRV_PCM_FORMAT_S32_LE:
703 reg |= 3 << WM8961_WL_SHIFT;
704 break;
705 default:
706 return -EINVAL;
707 }
708 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
709
710 /* Sloping stop-band filter is recommended for <= 24kHz */
711 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
712 if (fs <= 24000)
713 reg |= WM8961_DACSLOPE;
714 else
715 reg &= WM8961_DACSLOPE;
716 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
717
718 return 0;
719 }
720
721 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
722 unsigned int freq,
723 int dir)
724 {
725 struct snd_soc_codec *codec = dai->codec;
726 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
727 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
728
729 if (freq > 33000000) {
730 dev_err(codec->dev, "MCLK must be <33MHz\n");
731 return -EINVAL;
732 }
733
734 if (freq > 16500000) {
735 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
736 reg |= WM8961_MCLKDIV;
737 freq /= 2;
738 } else {
739 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
740 reg &= WM8961_MCLKDIV;
741 }
742
743 snd_soc_write(codec, WM8961_CLOCKING1, reg);
744
745 wm8961->sysclk = freq;
746
747 return 0;
748 }
749
750 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
751 {
752 struct snd_soc_codec *codec = dai->codec;
753 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
754
755 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
756 WM8961_MS | WM8961_FORMAT_MASK);
757
758 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
759 case SND_SOC_DAIFMT_CBM_CFM:
760 aif |= WM8961_MS;
761 break;
762 case SND_SOC_DAIFMT_CBS_CFS:
763 break;
764 default:
765 return -EINVAL;
766 }
767
768 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
769 case SND_SOC_DAIFMT_RIGHT_J:
770 break;
771
772 case SND_SOC_DAIFMT_LEFT_J:
773 aif |= 1;
774 break;
775
776 case SND_SOC_DAIFMT_I2S:
777 aif |= 2;
778 break;
779
780 case SND_SOC_DAIFMT_DSP_B:
781 aif |= WM8961_LRP;
782 case SND_SOC_DAIFMT_DSP_A:
783 aif |= 3;
784 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
785 case SND_SOC_DAIFMT_NB_NF:
786 case SND_SOC_DAIFMT_IB_NF:
787 break;
788 default:
789 return -EINVAL;
790 }
791 break;
792
793 default:
794 return -EINVAL;
795 }
796
797 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
798 case SND_SOC_DAIFMT_NB_NF:
799 break;
800 case SND_SOC_DAIFMT_NB_IF:
801 aif |= WM8961_LRP;
802 break;
803 case SND_SOC_DAIFMT_IB_NF:
804 aif |= WM8961_BCLKINV;
805 break;
806 case SND_SOC_DAIFMT_IB_IF:
807 aif |= WM8961_BCLKINV | WM8961_LRP;
808 break;
809 default:
810 return -EINVAL;
811 }
812
813 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
814 }
815
816 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
817 {
818 struct snd_soc_codec *codec = dai->codec;
819 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
820
821 if (tristate)
822 reg |= WM8961_TRIS;
823 else
824 reg &= ~WM8961_TRIS;
825
826 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
827 }
828
829 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
830 {
831 struct snd_soc_codec *codec = dai->codec;
832 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
833
834 if (mute)
835 reg |= WM8961_DACMU;
836 else
837 reg &= ~WM8961_DACMU;
838
839 msleep(17);
840
841 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
842 }
843
844 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
845 {
846 struct snd_soc_codec *codec = dai->codec;
847 u16 reg;
848
849 switch (div_id) {
850 case WM8961_BCLK:
851 reg = snd_soc_read(codec, WM8961_CLOCKING2);
852 reg &= ~WM8961_BCLKDIV_MASK;
853 reg |= div;
854 snd_soc_write(codec, WM8961_CLOCKING2, reg);
855 break;
856
857 case WM8961_LRCLK:
858 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
859 reg &= ~WM8961_LRCLK_RATE_MASK;
860 reg |= div;
861 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
862 break;
863
864 default:
865 return -EINVAL;
866 }
867
868 return 0;
869 }
870
871 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
872 enum snd_soc_bias_level level)
873 {
874 u16 reg;
875
876 /* This is all slightly unusual since we have no bypass paths
877 * and the output amplifier structure means we can just slam
878 * the biases straight up rather than having to ramp them
879 * slowly.
880 */
881 switch (level) {
882 case SND_SOC_BIAS_ON:
883 break;
884
885 case SND_SOC_BIAS_PREPARE:
886 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
887 /* Enable bias generation */
888 reg = snd_soc_read(codec, WM8961_ANTI_POP);
889 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
890 snd_soc_write(codec, WM8961_ANTI_POP, reg);
891
892 /* VMID=2*50k, VREF */
893 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
894 reg &= ~WM8961_VMIDSEL_MASK;
895 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
896 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
897 }
898 break;
899
900 case SND_SOC_BIAS_STANDBY:
901 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
902 /* VREF off */
903 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
904 reg &= ~WM8961_VREF;
905 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
906
907 /* Bias generation off */
908 reg = snd_soc_read(codec, WM8961_ANTI_POP);
909 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
910 snd_soc_write(codec, WM8961_ANTI_POP, reg);
911
912 /* VMID off */
913 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
914 reg &= ~WM8961_VMIDSEL_MASK;
915 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
916 }
917 break;
918
919 case SND_SOC_BIAS_OFF:
920 break;
921 }
922
923 codec->bias_level = level;
924
925 return 0;
926 }
927
928
929 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
930
931 #define WM8961_FORMATS \
932 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
933 SNDRV_PCM_FMTBIT_S24_LE)
934
935 static struct snd_soc_dai_ops wm8961_dai_ops = {
936 .hw_params = wm8961_hw_params,
937 .set_sysclk = wm8961_set_sysclk,
938 .set_fmt = wm8961_set_fmt,
939 .digital_mute = wm8961_digital_mute,
940 .set_tristate = wm8961_set_tristate,
941 .set_clkdiv = wm8961_set_clkdiv,
942 };
943
944 static struct snd_soc_dai_driver wm8961_dai = {
945 .name = "wm8961-hifi",
946 .playback = {
947 .stream_name = "HiFi Playback",
948 .channels_min = 1,
949 .channels_max = 2,
950 .rates = WM8961_RATES,
951 .formats = WM8961_FORMATS,},
952 .capture = {
953 .stream_name = "HiFi Capture",
954 .channels_min = 1,
955 .channels_max = 2,
956 .rates = WM8961_RATES,
957 .formats = WM8961_FORMATS,},
958 .ops = &wm8961_dai_ops,
959 };
960
961 static int wm8961_probe(struct snd_soc_codec *codec)
962 {
963 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
964 int ret = 0;
965 u16 reg;
966
967 codec->control_data = wm8961->control_data;
968 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
969 if (ret != 0) {
970 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
971 return ret;
972 }
973
974 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
975 if (reg != 0x1801) {
976 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
977 return -EINVAL;
978 }
979
980 /* This isn't volatile - readback doesn't correspond to write */
981 reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
982 dev_info(codec->dev, "WM8961 family %d revision %c\n",
983 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
984 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
985 + 'A');
986
987 ret = wm8961_reset(codec);
988 if (ret < 0) {
989 dev_err(codec->dev, "Failed to issue reset\n");
990 return ret;
991 }
992
993 /* Enable class W */
994 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
995 reg |= WM8961_CP_DYN_PWR_MASK;
996 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
997
998 /* Latch volume update bits (right channel only, we always
999 * write both out) and default ZC on. */
1000 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1001 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1002 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1003 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1004 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1005 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1006 reg | WM8961_SPKRZC | WM8961_SPKVU);
1007 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1008
1009 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1010 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1011 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1012 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1013
1014 /* Use soft mute by default */
1015 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1016 reg |= WM8961_DACSMM;
1017 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1018
1019 /* Use automatic clocking mode by default; for now this is all
1020 * we support.
1021 */
1022 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1023 reg &= ~WM8961_MANUAL_MODE;
1024 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1025
1026 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1027
1028 snd_soc_add_controls(codec, wm8961_snd_controls,
1029 ARRAY_SIZE(wm8961_snd_controls));
1030 snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets,
1031 ARRAY_SIZE(wm8961_dapm_widgets));
1032 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1033
1034 return 0;
1035 }
1036
1037 static int wm8961_remove(struct snd_soc_codec *codec)
1038 {
1039 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1040 return 0;
1041 }
1042
1043 #ifdef CONFIG_PM
1044 static int wm8961_suspend(struct snd_soc_codec *codec, pm_message_t state)
1045 {
1046 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1047
1048 return 0;
1049 }
1050
1051 static int wm8961_resume(struct snd_soc_codec *codec)
1052 {
1053 u16 *reg_cache = codec->reg_cache;
1054 int i;
1055
1056 for (i = 0; i < codec->driver->reg_cache_size; i++) {
1057 if (reg_cache[i] == wm8961_reg_defaults[i])
1058 continue;
1059
1060 if (i == WM8961_SOFTWARE_RESET)
1061 continue;
1062
1063 snd_soc_write(codec, i, reg_cache[i]);
1064 }
1065
1066 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1067
1068 return 0;
1069 }
1070 #else
1071 #define wm8961_suspend NULL
1072 #define wm8961_resume NULL
1073 #endif
1074
1075 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1076 .probe = wm8961_probe,
1077 .remove = wm8961_remove,
1078 .suspend = wm8961_suspend,
1079 .resume = wm8961_resume,
1080 .set_bias_level = wm8961_set_bias_level,
1081 .reg_cache_size = sizeof(wm8961_reg_defaults),
1082 .reg_word_size = sizeof(u16),
1083 .reg_cache_default = wm8961_reg_defaults,
1084 .volatile_register = wm8961_volatile_register,
1085 };
1086
1087 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1088 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1089 const struct i2c_device_id *id)
1090 {
1091 struct wm8961_priv *wm8961;
1092 int ret;
1093
1094 wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1095 if (wm8961 == NULL)
1096 return -ENOMEM;
1097
1098 i2c_set_clientdata(i2c, wm8961);
1099 wm8961->control_data = i2c;
1100
1101 ret = snd_soc_register_codec(&i2c->dev,
1102 &soc_codec_dev_wm8961, &wm8961_dai, 1);
1103 if (ret < 0)
1104 kfree(wm8961);
1105 return ret;
1106 }
1107
1108 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1109 {
1110 snd_soc_unregister_codec(&client->dev);
1111 kfree(i2c_get_clientdata(client));
1112 return 0;
1113 }
1114
1115 static const struct i2c_device_id wm8961_i2c_id[] = {
1116 { "wm8961", 0 },
1117 { }
1118 };
1119 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1120
1121 static struct i2c_driver wm8961_i2c_driver = {
1122 .driver = {
1123 .name = "wm8961-codec",
1124 .owner = THIS_MODULE,
1125 },
1126 .probe = wm8961_i2c_probe,
1127 .remove = __devexit_p(wm8961_i2c_remove),
1128 .id_table = wm8961_i2c_id,
1129 };
1130 #endif
1131
1132 static int __init wm8961_modinit(void)
1133 {
1134 int ret = 0;
1135 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1136 ret = i2c_add_driver(&wm8961_i2c_driver);
1137 if (ret != 0) {
1138 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
1139 ret);
1140 }
1141 #endif
1142 return ret;
1143 }
1144 module_init(wm8961_modinit);
1145
1146 static void __exit wm8961_exit(void)
1147 {
1148 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1149 i2c_del_driver(&wm8961_i2c_driver);
1150 #endif
1151 }
1152 module_exit(wm8961_exit);
1153
1154 MODULE_DESCRIPTION("ASoC WM8961 driver");
1155 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1156 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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