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ASoC: Rename WM8994 detecting flag to mic_detecting
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
1 /*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
32
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
37
38 #include "wm8994.h"
39 #include "wm_hubs.h"
40
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
43
44 static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48 };
49
50 static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54 };
55
56 static void wm8958_default_micdet(u16 status, void *data);
57
58 static const struct {
59 int sysclk;
60 bool idle;
61 int start;
62 int rate;
63 } wm8958_micd_rates[] = {
64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
68 };
69
70 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
71 {
72 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
73 int best, i, sysclk, val;
74 bool idle;
75
76 if (wm8994->jack_cb != wm8958_default_micdet)
77 return;
78
79 idle = !wm8994->jack_mic;
80
81 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
82 if (sysclk & WM8994_SYSCLK_SRC)
83 sysclk = wm8994->aifclk[1];
84 else
85 sysclk = wm8994->aifclk[0];
86
87 best = 0;
88 for (i = 0; i < ARRAY_SIZE(wm8958_micd_rates); i++) {
89 if (wm8958_micd_rates[i].idle != idle)
90 continue;
91 if (abs(wm8958_micd_rates[i].sysclk - sysclk) <
92 abs(wm8958_micd_rates[best].sysclk - sysclk))
93 best = i;
94 else if (wm8958_micd_rates[best].idle != idle)
95 best = i;
96 }
97
98 val = wm8958_micd_rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
99 | wm8958_micd_rates[best].rate << WM8958_MICD_RATE_SHIFT;
100
101 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
102 WM8958_MICD_BIAS_STARTTIME_MASK |
103 WM8958_MICD_RATE_MASK, val);
104 }
105
106 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
107 {
108 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
109 struct wm8994 *control = wm8994->wm8994;
110
111 switch (reg) {
112 case WM8994_GPIO_1:
113 case WM8994_GPIO_2:
114 case WM8994_GPIO_3:
115 case WM8994_GPIO_4:
116 case WM8994_GPIO_5:
117 case WM8994_GPIO_6:
118 case WM8994_GPIO_7:
119 case WM8994_GPIO_8:
120 case WM8994_GPIO_9:
121 case WM8994_GPIO_10:
122 case WM8994_GPIO_11:
123 case WM8994_INTERRUPT_STATUS_1:
124 case WM8994_INTERRUPT_STATUS_2:
125 case WM8994_INTERRUPT_RAW_STATUS_2:
126 return 1;
127
128 case WM8958_DSP2_PROGRAM:
129 case WM8958_DSP2_CONFIG:
130 case WM8958_DSP2_EXECCONTROL:
131 if (control->type == WM8958)
132 return 1;
133 else
134 return 0;
135
136 default:
137 break;
138 }
139
140 if (reg >= WM8994_CACHE_SIZE)
141 return 0;
142 return wm8994_access_masks[reg].readable != 0;
143 }
144
145 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
146 {
147 if (reg >= WM8994_CACHE_SIZE)
148 return 1;
149
150 switch (reg) {
151 case WM8994_SOFTWARE_RESET:
152 case WM8994_CHIP_REVISION:
153 case WM8994_DC_SERVO_1:
154 case WM8994_DC_SERVO_READBACK:
155 case WM8994_RATE_STATUS:
156 case WM8994_LDO_1:
157 case WM8994_LDO_2:
158 case WM8958_DSP2_EXECCONTROL:
159 case WM8958_MIC_DETECT_3:
160 case WM8994_DC_SERVO_4E:
161 return 1;
162 default:
163 return 0;
164 }
165 }
166
167 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
168 unsigned int value)
169 {
170 int ret;
171
172 BUG_ON(reg > WM8994_MAX_REGISTER);
173
174 if (!wm8994_volatile(codec, reg)) {
175 ret = snd_soc_cache_write(codec, reg, value);
176 if (ret != 0)
177 dev_err(codec->dev, "Cache write to %x failed: %d\n",
178 reg, ret);
179 }
180
181 return wm8994_reg_write(codec->control_data, reg, value);
182 }
183
184 static unsigned int wm8994_read(struct snd_soc_codec *codec,
185 unsigned int reg)
186 {
187 unsigned int val;
188 int ret;
189
190 BUG_ON(reg > WM8994_MAX_REGISTER);
191
192 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
193 reg < codec->driver->reg_cache_size) {
194 ret = snd_soc_cache_read(codec, reg, &val);
195 if (ret >= 0)
196 return val;
197 else
198 dev_err(codec->dev, "Cache read from %x failed: %d\n",
199 reg, ret);
200 }
201
202 return wm8994_reg_read(codec->control_data, reg);
203 }
204
205 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
206 {
207 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
208 int rate;
209 int reg1 = 0;
210 int offset;
211
212 if (aif)
213 offset = 4;
214 else
215 offset = 0;
216
217 switch (wm8994->sysclk[aif]) {
218 case WM8994_SYSCLK_MCLK1:
219 rate = wm8994->mclk[0];
220 break;
221
222 case WM8994_SYSCLK_MCLK2:
223 reg1 |= 0x8;
224 rate = wm8994->mclk[1];
225 break;
226
227 case WM8994_SYSCLK_FLL1:
228 reg1 |= 0x10;
229 rate = wm8994->fll[0].out;
230 break;
231
232 case WM8994_SYSCLK_FLL2:
233 reg1 |= 0x18;
234 rate = wm8994->fll[1].out;
235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 if (rate >= 13500000) {
242 rate /= 2;
243 reg1 |= WM8994_AIF1CLK_DIV;
244
245 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
246 aif + 1, rate);
247 }
248
249 wm8994->aifclk[aif] = rate;
250
251 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
252 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
253 reg1);
254
255 return 0;
256 }
257
258 static int configure_clock(struct snd_soc_codec *codec)
259 {
260 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
261 int change, new;
262
263 /* Bring up the AIF clocks first */
264 configure_aif_clock(codec, 0);
265 configure_aif_clock(codec, 1);
266
267 /* Then switch CLK_SYS over to the higher of them; a change
268 * can only happen as a result of a clocking change which can
269 * only be made outside of DAPM so we can safely redo the
270 * clocking.
271 */
272
273 /* If they're equal it doesn't matter which is used */
274 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
275 wm8958_micd_set_rate(codec);
276 return 0;
277 }
278
279 if (wm8994->aifclk[0] < wm8994->aifclk[1])
280 new = WM8994_SYSCLK_SRC;
281 else
282 new = 0;
283
284 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
285 WM8994_SYSCLK_SRC, new);
286 if (!change)
287 return 0;
288
289 snd_soc_dapm_sync(&codec->dapm);
290
291 wm8958_micd_set_rate(codec);
292
293 return 0;
294 }
295
296 static int check_clk_sys(struct snd_soc_dapm_widget *source,
297 struct snd_soc_dapm_widget *sink)
298 {
299 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
300 const char *clk;
301
302 /* Check what we're currently using for CLK_SYS */
303 if (reg & WM8994_SYSCLK_SRC)
304 clk = "AIF2CLK";
305 else
306 clk = "AIF1CLK";
307
308 return strcmp(source->name, clk) == 0;
309 }
310
311 static const char *sidetone_hpf_text[] = {
312 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
313 };
314
315 static const struct soc_enum sidetone_hpf =
316 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
317
318 static const char *adc_hpf_text[] = {
319 "HiFi", "Voice 1", "Voice 2", "Voice 3"
320 };
321
322 static const struct soc_enum aif1adc1_hpf =
323 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
324
325 static const struct soc_enum aif1adc2_hpf =
326 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
327
328 static const struct soc_enum aif2adc_hpf =
329 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
330
331 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
332 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
333 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
334 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
335 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
336 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
337 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
338
339 #define WM8994_DRC_SWITCH(xname, reg, shift) \
340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
341 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
342 .put = wm8994_put_drc_sw, \
343 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
344
345 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
346 struct snd_ctl_elem_value *ucontrol)
347 {
348 struct soc_mixer_control *mc =
349 (struct soc_mixer_control *)kcontrol->private_value;
350 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
351 int mask, ret;
352
353 /* Can't enable both ADC and DAC paths simultaneously */
354 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
355 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
356 WM8994_AIF1ADC1R_DRC_ENA_MASK;
357 else
358 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
359
360 ret = snd_soc_read(codec, mc->reg);
361 if (ret < 0)
362 return ret;
363 if (ret & mask)
364 return -EINVAL;
365
366 return snd_soc_put_volsw(kcontrol, ucontrol);
367 }
368
369 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
370 {
371 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
372 struct wm8994_pdata *pdata = wm8994->pdata;
373 int base = wm8994_drc_base[drc];
374 int cfg = wm8994->drc_cfg[drc];
375 int save, i;
376
377 /* Save any enables; the configuration should clear them. */
378 save = snd_soc_read(codec, base);
379 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
380 WM8994_AIF1ADC1R_DRC_ENA;
381
382 for (i = 0; i < WM8994_DRC_REGS; i++)
383 snd_soc_update_bits(codec, base + i, 0xffff,
384 pdata->drc_cfgs[cfg].regs[i]);
385
386 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
387 WM8994_AIF1ADC1L_DRC_ENA |
388 WM8994_AIF1ADC1R_DRC_ENA, save);
389 }
390
391 /* Icky as hell but saves code duplication */
392 static int wm8994_get_drc(const char *name)
393 {
394 if (strcmp(name, "AIF1DRC1 Mode") == 0)
395 return 0;
396 if (strcmp(name, "AIF1DRC2 Mode") == 0)
397 return 1;
398 if (strcmp(name, "AIF2DRC Mode") == 0)
399 return 2;
400 return -EINVAL;
401 }
402
403 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
404 struct snd_ctl_elem_value *ucontrol)
405 {
406 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
407 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
408 struct wm8994_pdata *pdata = wm8994->pdata;
409 int drc = wm8994_get_drc(kcontrol->id.name);
410 int value = ucontrol->value.integer.value[0];
411
412 if (drc < 0)
413 return drc;
414
415 if (value >= pdata->num_drc_cfgs)
416 return -EINVAL;
417
418 wm8994->drc_cfg[drc] = value;
419
420 wm8994_set_drc(codec, drc);
421
422 return 0;
423 }
424
425 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427 {
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
430 int drc = wm8994_get_drc(kcontrol->id.name);
431
432 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
433
434 return 0;
435 }
436
437 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
438 {
439 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
440 struct wm8994_pdata *pdata = wm8994->pdata;
441 int base = wm8994_retune_mobile_base[block];
442 int iface, best, best_val, save, i, cfg;
443
444 if (!pdata || !wm8994->num_retune_mobile_texts)
445 return;
446
447 switch (block) {
448 case 0:
449 case 1:
450 iface = 0;
451 break;
452 case 2:
453 iface = 1;
454 break;
455 default:
456 return;
457 }
458
459 /* Find the version of the currently selected configuration
460 * with the nearest sample rate. */
461 cfg = wm8994->retune_mobile_cfg[block];
462 best = 0;
463 best_val = INT_MAX;
464 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
465 if (strcmp(pdata->retune_mobile_cfgs[i].name,
466 wm8994->retune_mobile_texts[cfg]) == 0 &&
467 abs(pdata->retune_mobile_cfgs[i].rate
468 - wm8994->dac_rates[iface]) < best_val) {
469 best = i;
470 best_val = abs(pdata->retune_mobile_cfgs[i].rate
471 - wm8994->dac_rates[iface]);
472 }
473 }
474
475 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
476 block,
477 pdata->retune_mobile_cfgs[best].name,
478 pdata->retune_mobile_cfgs[best].rate,
479 wm8994->dac_rates[iface]);
480
481 /* The EQ will be disabled while reconfiguring it, remember the
482 * current configuration.
483 */
484 save = snd_soc_read(codec, base);
485 save &= WM8994_AIF1DAC1_EQ_ENA;
486
487 for (i = 0; i < WM8994_EQ_REGS; i++)
488 snd_soc_update_bits(codec, base + i, 0xffff,
489 pdata->retune_mobile_cfgs[best].regs[i]);
490
491 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
492 }
493
494 /* Icky as hell but saves code duplication */
495 static int wm8994_get_retune_mobile_block(const char *name)
496 {
497 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
498 return 0;
499 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
500 return 1;
501 if (strcmp(name, "AIF2 EQ Mode") == 0)
502 return 2;
503 return -EINVAL;
504 }
505
506 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
507 struct snd_ctl_elem_value *ucontrol)
508 {
509 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
511 struct wm8994_pdata *pdata = wm8994->pdata;
512 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
513 int value = ucontrol->value.integer.value[0];
514
515 if (block < 0)
516 return block;
517
518 if (value >= pdata->num_retune_mobile_cfgs)
519 return -EINVAL;
520
521 wm8994->retune_mobile_cfg[block] = value;
522
523 wm8994_set_retune_mobile(codec, block);
524
525 return 0;
526 }
527
528 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
529 struct snd_ctl_elem_value *ucontrol)
530 {
531 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
532 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
533 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
534
535 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
536
537 return 0;
538 }
539
540 static const char *aif_chan_src_text[] = {
541 "Left", "Right"
542 };
543
544 static const struct soc_enum aif1adcl_src =
545 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
546
547 static const struct soc_enum aif1adcr_src =
548 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
549
550 static const struct soc_enum aif2adcl_src =
551 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
552
553 static const struct soc_enum aif2adcr_src =
554 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
555
556 static const struct soc_enum aif1dacl_src =
557 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
558
559 static const struct soc_enum aif1dacr_src =
560 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
561
562 static const struct soc_enum aif2dacl_src =
563 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
564
565 static const struct soc_enum aif2dacr_src =
566 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
567
568 static const char *osr_text[] = {
569 "Low Power", "High Performance",
570 };
571
572 static const struct soc_enum dac_osr =
573 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
574
575 static const struct soc_enum adc_osr =
576 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
577
578 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
579 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
580 WM8994_AIF1_ADC1_RIGHT_VOLUME,
581 1, 119, 0, digital_tlv),
582 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
583 WM8994_AIF1_ADC2_RIGHT_VOLUME,
584 1, 119, 0, digital_tlv),
585 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
586 WM8994_AIF2_ADC_RIGHT_VOLUME,
587 1, 119, 0, digital_tlv),
588
589 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
590 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
591 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
592 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
593
594 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
595 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
596 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
597 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
598
599 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
600 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
601 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
602 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
603 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
604 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
605
606 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
607 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
608
609 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
610 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
611 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
612
613 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
614 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
615 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
616
617 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
618 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
619 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
620
621 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
622 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
623 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
624
625 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
626 5, 12, 0, st_tlv),
627 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
628 0, 12, 0, st_tlv),
629 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
630 5, 12, 0, st_tlv),
631 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
632 0, 12, 0, st_tlv),
633 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
634 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
635
636 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
637 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
638
639 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
640 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
641
642 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
643 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
644
645 SOC_ENUM("ADC OSR", adc_osr),
646 SOC_ENUM("DAC OSR", dac_osr),
647
648 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
649 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
650 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
651 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
652
653 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
654 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
655 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
656 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
657
658 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
659 6, 1, 1, wm_hubs_spkmix_tlv),
660 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
661 2, 1, 1, wm_hubs_spkmix_tlv),
662
663 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
664 6, 1, 1, wm_hubs_spkmix_tlv),
665 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
666 2, 1, 1, wm_hubs_spkmix_tlv),
667
668 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
669 10, 15, 0, wm8994_3d_tlv),
670 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
671 8, 1, 0),
672 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
673 10, 15, 0, wm8994_3d_tlv),
674 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
675 8, 1, 0),
676 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
677 10, 15, 0, wm8994_3d_tlv),
678 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
679 8, 1, 0),
680 };
681
682 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
683 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
684 eq_tlv),
685 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
686 eq_tlv),
687 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
688 eq_tlv),
689 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
690 eq_tlv),
691 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
692 eq_tlv),
693
694 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
695 eq_tlv),
696 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
697 eq_tlv),
698 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
699 eq_tlv),
700 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
701 eq_tlv),
702 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
703 eq_tlv),
704
705 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
706 eq_tlv),
707 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
708 eq_tlv),
709 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
710 eq_tlv),
711 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
712 eq_tlv),
713 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
714 eq_tlv),
715 };
716
717 static const char *wm8958_ng_text[] = {
718 "30ms", "125ms", "250ms", "500ms",
719 };
720
721 static const struct soc_enum wm8958_aif1dac1_ng_hold =
722 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
723 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
724
725 static const struct soc_enum wm8958_aif1dac2_ng_hold =
726 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
727 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
728
729 static const struct soc_enum wm8958_aif2dac_ng_hold =
730 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
731 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
732
733 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
734 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
735
736 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
737 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
738 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
739 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
740 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
741 7, 1, ng_tlv),
742
743 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
744 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
745 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
746 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
747 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
748 7, 1, ng_tlv),
749
750 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
751 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
752 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
753 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
754 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
755 7, 1, ng_tlv),
756 };
757
758 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
759 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
760 mixin_boost_tlv),
761 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
762 mixin_boost_tlv),
763 };
764
765 static int clk_sys_event(struct snd_soc_dapm_widget *w,
766 struct snd_kcontrol *kcontrol, int event)
767 {
768 struct snd_soc_codec *codec = w->codec;
769
770 switch (event) {
771 case SND_SOC_DAPM_PRE_PMU:
772 return configure_clock(codec);
773
774 case SND_SOC_DAPM_POST_PMD:
775 configure_clock(codec);
776 break;
777 }
778
779 return 0;
780 }
781
782 static void vmid_reference(struct snd_soc_codec *codec)
783 {
784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785
786 wm8994->vmid_refcount++;
787
788 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
789 wm8994->vmid_refcount);
790
791 if (wm8994->vmid_refcount == 1) {
792 /* Startup bias, VMID ramp & buffer */
793 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
794 WM8994_STARTUP_BIAS_ENA |
795 WM8994_VMID_BUF_ENA |
796 WM8994_VMID_RAMP_MASK,
797 WM8994_STARTUP_BIAS_ENA |
798 WM8994_VMID_BUF_ENA |
799 (0x11 << WM8994_VMID_RAMP_SHIFT));
800
801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803 WM8994_BIAS_ENA |
804 WM8994_VMID_SEL_MASK,
805 WM8994_BIAS_ENA | 0x2);
806
807 msleep(20);
808 }
809 }
810
811 static void vmid_dereference(struct snd_soc_codec *codec)
812 {
813 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
814
815 wm8994->vmid_refcount--;
816
817 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
818 wm8994->vmid_refcount);
819
820 if (wm8994->vmid_refcount == 0) {
821 /* Switch over to startup biases */
822 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
823 WM8994_BIAS_SRC |
824 WM8994_STARTUP_BIAS_ENA |
825 WM8994_VMID_BUF_ENA |
826 WM8994_VMID_RAMP_MASK,
827 WM8994_BIAS_SRC |
828 WM8994_STARTUP_BIAS_ENA |
829 WM8994_VMID_BUF_ENA |
830 (1 << WM8994_VMID_RAMP_SHIFT));
831
832 /* Disable main biases */
833 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
834 WM8994_BIAS_ENA |
835 WM8994_VMID_SEL_MASK, 0);
836
837 /* Discharge line */
838 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
839 WM8994_LINEOUT1_DISCH |
840 WM8994_LINEOUT2_DISCH,
841 WM8994_LINEOUT1_DISCH |
842 WM8994_LINEOUT2_DISCH);
843
844 msleep(5);
845
846 /* Switch off startup biases */
847 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
848 WM8994_BIAS_SRC |
849 WM8994_STARTUP_BIAS_ENA |
850 WM8994_VMID_BUF_ENA |
851 WM8994_VMID_RAMP_MASK, 0);
852 }
853 }
854
855 static int vmid_event(struct snd_soc_dapm_widget *w,
856 struct snd_kcontrol *kcontrol, int event)
857 {
858 struct snd_soc_codec *codec = w->codec;
859
860 switch (event) {
861 case SND_SOC_DAPM_PRE_PMU:
862 vmid_reference(codec);
863 break;
864
865 case SND_SOC_DAPM_POST_PMD:
866 vmid_dereference(codec);
867 break;
868 }
869
870 return 0;
871 }
872
873 static void wm8994_update_class_w(struct snd_soc_codec *codec)
874 {
875 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
876 int enable = 1;
877 int source = 0; /* GCC flow analysis can't track enable */
878 int reg, reg_r;
879
880 /* Only support direct DAC->headphone paths */
881 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
882 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
883 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
884 enable = 0;
885 }
886
887 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
888 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
889 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
890 enable = 0;
891 }
892
893 /* We also need the same setting for L/R and only one path */
894 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
895 switch (reg) {
896 case WM8994_AIF2DACL_TO_DAC1L:
897 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
898 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
899 break;
900 case WM8994_AIF1DAC2L_TO_DAC1L:
901 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
902 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
903 break;
904 case WM8994_AIF1DAC1L_TO_DAC1L:
905 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
906 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
907 break;
908 default:
909 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
910 enable = 0;
911 break;
912 }
913
914 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
915 if (reg_r != reg) {
916 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
917 enable = 0;
918 }
919
920 if (enable) {
921 dev_dbg(codec->dev, "Class W enabled\n");
922 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
923 WM8994_CP_DYN_PWR |
924 WM8994_CP_DYN_SRC_SEL_MASK,
925 source | WM8994_CP_DYN_PWR);
926 wm8994->hubs.class_w = true;
927
928 } else {
929 dev_dbg(codec->dev, "Class W disabled\n");
930 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
931 WM8994_CP_DYN_PWR, 0);
932 wm8994->hubs.class_w = false;
933 }
934 }
935
936 static int late_enable_ev(struct snd_soc_dapm_widget *w,
937 struct snd_kcontrol *kcontrol, int event)
938 {
939 struct snd_soc_codec *codec = w->codec;
940 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
941
942 switch (event) {
943 case SND_SOC_DAPM_PRE_PMU:
944 if (wm8994->aif1clk_enable) {
945 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
946 WM8994_AIF1CLK_ENA_MASK,
947 WM8994_AIF1CLK_ENA);
948 wm8994->aif1clk_enable = 0;
949 }
950 if (wm8994->aif2clk_enable) {
951 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
952 WM8994_AIF2CLK_ENA_MASK,
953 WM8994_AIF2CLK_ENA);
954 wm8994->aif2clk_enable = 0;
955 }
956 break;
957 }
958
959 /* We may also have postponed startup of DSP, handle that. */
960 wm8958_aif_ev(w, kcontrol, event);
961
962 return 0;
963 }
964
965 static int late_disable_ev(struct snd_soc_dapm_widget *w,
966 struct snd_kcontrol *kcontrol, int event)
967 {
968 struct snd_soc_codec *codec = w->codec;
969 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
970
971 switch (event) {
972 case SND_SOC_DAPM_POST_PMD:
973 if (wm8994->aif1clk_disable) {
974 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
975 WM8994_AIF1CLK_ENA_MASK, 0);
976 wm8994->aif1clk_disable = 0;
977 }
978 if (wm8994->aif2clk_disable) {
979 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
980 WM8994_AIF2CLK_ENA_MASK, 0);
981 wm8994->aif2clk_disable = 0;
982 }
983 break;
984 }
985
986 return 0;
987 }
988
989 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
990 struct snd_kcontrol *kcontrol, int event)
991 {
992 struct snd_soc_codec *codec = w->codec;
993 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
994
995 switch (event) {
996 case SND_SOC_DAPM_PRE_PMU:
997 wm8994->aif1clk_enable = 1;
998 break;
999 case SND_SOC_DAPM_POST_PMD:
1000 wm8994->aif1clk_disable = 1;
1001 break;
1002 }
1003
1004 return 0;
1005 }
1006
1007 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1008 struct snd_kcontrol *kcontrol, int event)
1009 {
1010 struct snd_soc_codec *codec = w->codec;
1011 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1012
1013 switch (event) {
1014 case SND_SOC_DAPM_PRE_PMU:
1015 wm8994->aif2clk_enable = 1;
1016 break;
1017 case SND_SOC_DAPM_POST_PMD:
1018 wm8994->aif2clk_disable = 1;
1019 break;
1020 }
1021
1022 return 0;
1023 }
1024
1025 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1026 struct snd_kcontrol *kcontrol, int event)
1027 {
1028 late_enable_ev(w, kcontrol, event);
1029 return 0;
1030 }
1031
1032 static int micbias_ev(struct snd_soc_dapm_widget *w,
1033 struct snd_kcontrol *kcontrol, int event)
1034 {
1035 late_enable_ev(w, kcontrol, event);
1036 return 0;
1037 }
1038
1039 static int dac_ev(struct snd_soc_dapm_widget *w,
1040 struct snd_kcontrol *kcontrol, int event)
1041 {
1042 struct snd_soc_codec *codec = w->codec;
1043 unsigned int mask = 1 << w->shift;
1044
1045 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1046 mask, mask);
1047 return 0;
1048 }
1049
1050 static const char *hp_mux_text[] = {
1051 "Mixer",
1052 "DAC",
1053 };
1054
1055 #define WM8994_HP_ENUM(xname, xenum) \
1056 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1057 .info = snd_soc_info_enum_double, \
1058 .get = snd_soc_dapm_get_enum_double, \
1059 .put = wm8994_put_hp_enum, \
1060 .private_value = (unsigned long)&xenum }
1061
1062 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1063 struct snd_ctl_elem_value *ucontrol)
1064 {
1065 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1066 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1067 struct snd_soc_codec *codec = w->codec;
1068 int ret;
1069
1070 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1071
1072 wm8994_update_class_w(codec);
1073
1074 return ret;
1075 }
1076
1077 static const struct soc_enum hpl_enum =
1078 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1079
1080 static const struct snd_kcontrol_new hpl_mux =
1081 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1082
1083 static const struct soc_enum hpr_enum =
1084 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1085
1086 static const struct snd_kcontrol_new hpr_mux =
1087 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1088
1089 static const char *adc_mux_text[] = {
1090 "ADC",
1091 "DMIC",
1092 };
1093
1094 static const struct soc_enum adc_enum =
1095 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1096
1097 static const struct snd_kcontrol_new adcl_mux =
1098 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1099
1100 static const struct snd_kcontrol_new adcr_mux =
1101 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1102
1103 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1104 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1105 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1106 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1107 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1108 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1109 };
1110
1111 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1112 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1113 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1114 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1115 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1116 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1117 };
1118
1119 /* Debugging; dump chip status after DAPM transitions */
1120 static int post_ev(struct snd_soc_dapm_widget *w,
1121 struct snd_kcontrol *kcontrol, int event)
1122 {
1123 struct snd_soc_codec *codec = w->codec;
1124 dev_dbg(codec->dev, "SRC status: %x\n",
1125 snd_soc_read(codec,
1126 WM8994_RATE_STATUS));
1127 return 0;
1128 }
1129
1130 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1131 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1132 1, 1, 0),
1133 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1134 0, 1, 0),
1135 };
1136
1137 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1138 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1139 1, 1, 0),
1140 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1141 0, 1, 0),
1142 };
1143
1144 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1145 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1146 1, 1, 0),
1147 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1148 0, 1, 0),
1149 };
1150
1151 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1152 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1153 1, 1, 0),
1154 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1155 0, 1, 0),
1156 };
1157
1158 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1159 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1160 5, 1, 0),
1161 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1162 4, 1, 0),
1163 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1164 2, 1, 0),
1165 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1166 1, 1, 0),
1167 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1168 0, 1, 0),
1169 };
1170
1171 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1172 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1173 5, 1, 0),
1174 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1175 4, 1, 0),
1176 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1177 2, 1, 0),
1178 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1179 1, 1, 0),
1180 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1181 0, 1, 0),
1182 };
1183
1184 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1185 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1186 .info = snd_soc_info_volsw, \
1187 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1188 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1189
1190 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1191 struct snd_ctl_elem_value *ucontrol)
1192 {
1193 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1194 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1195 struct snd_soc_codec *codec = w->codec;
1196 int ret;
1197
1198 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1199
1200 wm8994_update_class_w(codec);
1201
1202 return ret;
1203 }
1204
1205 static const struct snd_kcontrol_new dac1l_mix[] = {
1206 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1207 5, 1, 0),
1208 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1209 4, 1, 0),
1210 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1211 2, 1, 0),
1212 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1213 1, 1, 0),
1214 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1215 0, 1, 0),
1216 };
1217
1218 static const struct snd_kcontrol_new dac1r_mix[] = {
1219 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1220 5, 1, 0),
1221 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1222 4, 1, 0),
1223 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1224 2, 1, 0),
1225 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1226 1, 1, 0),
1227 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1228 0, 1, 0),
1229 };
1230
1231 static const char *sidetone_text[] = {
1232 "ADC/DMIC1", "DMIC2",
1233 };
1234
1235 static const struct soc_enum sidetone1_enum =
1236 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1237
1238 static const struct snd_kcontrol_new sidetone1_mux =
1239 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1240
1241 static const struct soc_enum sidetone2_enum =
1242 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1243
1244 static const struct snd_kcontrol_new sidetone2_mux =
1245 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1246
1247 static const char *aif1dac_text[] = {
1248 "AIF1DACDAT", "AIF3DACDAT",
1249 };
1250
1251 static const struct soc_enum aif1dac_enum =
1252 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1253
1254 static const struct snd_kcontrol_new aif1dac_mux =
1255 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1256
1257 static const char *aif2dac_text[] = {
1258 "AIF2DACDAT", "AIF3DACDAT",
1259 };
1260
1261 static const struct soc_enum aif2dac_enum =
1262 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1263
1264 static const struct snd_kcontrol_new aif2dac_mux =
1265 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1266
1267 static const char *aif2adc_text[] = {
1268 "AIF2ADCDAT", "AIF3DACDAT",
1269 };
1270
1271 static const struct soc_enum aif2adc_enum =
1272 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1273
1274 static const struct snd_kcontrol_new aif2adc_mux =
1275 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1276
1277 static const char *aif3adc_text[] = {
1278 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1279 };
1280
1281 static const struct soc_enum wm8994_aif3adc_enum =
1282 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1283
1284 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1285 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1286
1287 static const struct soc_enum wm8958_aif3adc_enum =
1288 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1289
1290 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1291 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1292
1293 static const char *mono_pcm_out_text[] = {
1294 "None", "AIF2ADCL", "AIF2ADCR",
1295 };
1296
1297 static const struct soc_enum mono_pcm_out_enum =
1298 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1299
1300 static const struct snd_kcontrol_new mono_pcm_out_mux =
1301 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1302
1303 static const char *aif2dac_src_text[] = {
1304 "AIF2", "AIF3",
1305 };
1306
1307 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1308 static const struct soc_enum aif2dacl_src_enum =
1309 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1310
1311 static const struct snd_kcontrol_new aif2dacl_src_mux =
1312 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1313
1314 static const struct soc_enum aif2dacr_src_enum =
1315 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1316
1317 static const struct snd_kcontrol_new aif2dacr_src_mux =
1318 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1319
1320 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1321 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1322 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1323 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1324 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1325
1326 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1327 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1328 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1329 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1330 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1331 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1332 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1333 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1334 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1335 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1336
1337 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1338 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1339 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1340 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1341 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1342 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1343 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1344 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1345 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1346 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1347
1348 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1349 };
1350
1351 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1352 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1353 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1354 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1355 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1356 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1357 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1358 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1359 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1360 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1361 };
1362
1363 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1364 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1365 dac_ev, SND_SOC_DAPM_PRE_PMU),
1366 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1367 dac_ev, SND_SOC_DAPM_PRE_PMU),
1368 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1369 dac_ev, SND_SOC_DAPM_PRE_PMU),
1370 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1371 dac_ev, SND_SOC_DAPM_PRE_PMU),
1372 };
1373
1374 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1375 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1376 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1377 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1378 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1379 };
1380
1381 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1382 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1383 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1384 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1385 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1386 };
1387
1388 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1389 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1390 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1391 };
1392
1393 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1394 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1395 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1396 SND_SOC_DAPM_INPUT("Clock"),
1397
1398 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1399 SND_SOC_DAPM_PRE_PMU),
1400 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1401 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1402
1403 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1404 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1405
1406 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1407 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1408 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1409
1410 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1411 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1412 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1413 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1414 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1415 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1416 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1417 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1418 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1419 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1420
1421 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1422 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1423 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1424 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1425 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1426 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1427 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1428 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1429 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1430 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1431
1432 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1433 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1434 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1435 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1436
1437 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1438 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1439 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1440 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1441
1442 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1443 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1444 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1445 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1446
1447 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1448 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1449
1450 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1451 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1452 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1453 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1454
1455 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1456 WM8994_POWER_MANAGEMENT_4, 13, 0),
1457 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1458 WM8994_POWER_MANAGEMENT_4, 12, 0),
1459 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1460 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1461 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1462 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1463 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1464 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1465
1466 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1467 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1468 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1469 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1470
1471 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1472 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1473 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1474
1475 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1476 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1477
1478 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1479
1480 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1481 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1482 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1483 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1484
1485 /* Power is done with the muxes since the ADC power also controls the
1486 * downsampling chain, the chip will automatically manage the analogue
1487 * specific portions.
1488 */
1489 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1490 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1491
1492 SND_SOC_DAPM_POST("Debug log", post_ev),
1493 };
1494
1495 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1496 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1497 };
1498
1499 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1500 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1501 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1502 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1503 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1504 };
1505
1506 static const struct snd_soc_dapm_route intercon[] = {
1507 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1508 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1509
1510 { "DSP1CLK", NULL, "CLK_SYS" },
1511 { "DSP2CLK", NULL, "CLK_SYS" },
1512 { "DSPINTCLK", NULL, "CLK_SYS" },
1513
1514 { "AIF1ADC1L", NULL, "AIF1CLK" },
1515 { "AIF1ADC1L", NULL, "DSP1CLK" },
1516 { "AIF1ADC1R", NULL, "AIF1CLK" },
1517 { "AIF1ADC1R", NULL, "DSP1CLK" },
1518 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1519
1520 { "AIF1DAC1L", NULL, "AIF1CLK" },
1521 { "AIF1DAC1L", NULL, "DSP1CLK" },
1522 { "AIF1DAC1R", NULL, "AIF1CLK" },
1523 { "AIF1DAC1R", NULL, "DSP1CLK" },
1524 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1525
1526 { "AIF1ADC2L", NULL, "AIF1CLK" },
1527 { "AIF1ADC2L", NULL, "DSP1CLK" },
1528 { "AIF1ADC2R", NULL, "AIF1CLK" },
1529 { "AIF1ADC2R", NULL, "DSP1CLK" },
1530 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1531
1532 { "AIF1DAC2L", NULL, "AIF1CLK" },
1533 { "AIF1DAC2L", NULL, "DSP1CLK" },
1534 { "AIF1DAC2R", NULL, "AIF1CLK" },
1535 { "AIF1DAC2R", NULL, "DSP1CLK" },
1536 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1537
1538 { "AIF2ADCL", NULL, "AIF2CLK" },
1539 { "AIF2ADCL", NULL, "DSP2CLK" },
1540 { "AIF2ADCR", NULL, "AIF2CLK" },
1541 { "AIF2ADCR", NULL, "DSP2CLK" },
1542 { "AIF2ADCR", NULL, "DSPINTCLK" },
1543
1544 { "AIF2DACL", NULL, "AIF2CLK" },
1545 { "AIF2DACL", NULL, "DSP2CLK" },
1546 { "AIF2DACR", NULL, "AIF2CLK" },
1547 { "AIF2DACR", NULL, "DSP2CLK" },
1548 { "AIF2DACR", NULL, "DSPINTCLK" },
1549
1550 { "DMIC1L", NULL, "DMIC1DAT" },
1551 { "DMIC1L", NULL, "CLK_SYS" },
1552 { "DMIC1R", NULL, "DMIC1DAT" },
1553 { "DMIC1R", NULL, "CLK_SYS" },
1554 { "DMIC2L", NULL, "DMIC2DAT" },
1555 { "DMIC2L", NULL, "CLK_SYS" },
1556 { "DMIC2R", NULL, "DMIC2DAT" },
1557 { "DMIC2R", NULL, "CLK_SYS" },
1558
1559 { "ADCL", NULL, "AIF1CLK" },
1560 { "ADCL", NULL, "DSP1CLK" },
1561 { "ADCL", NULL, "DSPINTCLK" },
1562
1563 { "ADCR", NULL, "AIF1CLK" },
1564 { "ADCR", NULL, "DSP1CLK" },
1565 { "ADCR", NULL, "DSPINTCLK" },
1566
1567 { "ADCL Mux", "ADC", "ADCL" },
1568 { "ADCL Mux", "DMIC", "DMIC1L" },
1569 { "ADCR Mux", "ADC", "ADCR" },
1570 { "ADCR Mux", "DMIC", "DMIC1R" },
1571
1572 { "DAC1L", NULL, "AIF1CLK" },
1573 { "DAC1L", NULL, "DSP1CLK" },
1574 { "DAC1L", NULL, "DSPINTCLK" },
1575
1576 { "DAC1R", NULL, "AIF1CLK" },
1577 { "DAC1R", NULL, "DSP1CLK" },
1578 { "DAC1R", NULL, "DSPINTCLK" },
1579
1580 { "DAC2L", NULL, "AIF2CLK" },
1581 { "DAC2L", NULL, "DSP2CLK" },
1582 { "DAC2L", NULL, "DSPINTCLK" },
1583
1584 { "DAC2R", NULL, "AIF2DACR" },
1585 { "DAC2R", NULL, "AIF2CLK" },
1586 { "DAC2R", NULL, "DSP2CLK" },
1587 { "DAC2R", NULL, "DSPINTCLK" },
1588
1589 { "TOCLK", NULL, "CLK_SYS" },
1590
1591 /* AIF1 outputs */
1592 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1593 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1594 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1595
1596 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1597 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1598 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1599
1600 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1601 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1602 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1603
1604 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1605 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1606 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1607
1608 /* Pin level routing for AIF3 */
1609 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1610 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1611 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1612 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1613
1614 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1615 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1616 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1617 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1618 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1619 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1620 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1621
1622 /* DAC1 inputs */
1623 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1624 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1625 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1626 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1627 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1628
1629 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1630 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1631 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1632 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1633 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1634
1635 /* DAC2/AIF2 outputs */
1636 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1637 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1638 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1639 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1640 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1641 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1642
1643 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1644 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1645 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1646 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1647 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1648 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1649
1650 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1651 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1652 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1653 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1654
1655 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1656
1657 /* AIF3 output */
1658 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1659 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1660 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1661 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1662 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1663 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1664 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1665 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1666
1667 /* Sidetone */
1668 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1669 { "Left Sidetone", "DMIC2", "DMIC2L" },
1670 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1671 { "Right Sidetone", "DMIC2", "DMIC2R" },
1672
1673 /* Output stages */
1674 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1675 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1676
1677 { "SPKL", "DAC1 Switch", "DAC1L" },
1678 { "SPKL", "DAC2 Switch", "DAC2L" },
1679
1680 { "SPKR", "DAC1 Switch", "DAC1R" },
1681 { "SPKR", "DAC2 Switch", "DAC2R" },
1682
1683 { "Left Headphone Mux", "DAC", "DAC1L" },
1684 { "Right Headphone Mux", "DAC", "DAC1R" },
1685 };
1686
1687 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1688 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1689 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1690 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1691 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1692 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1693 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1694 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1695 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1696 };
1697
1698 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1699 { "DAC1L", NULL, "DAC1L Mixer" },
1700 { "DAC1R", NULL, "DAC1R Mixer" },
1701 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1702 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1703 };
1704
1705 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1706 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1707 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1708 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1709 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1710 { "MICBIAS1", NULL, "CLK_SYS" },
1711 { "MICBIAS1", NULL, "MICBIAS Supply" },
1712 { "MICBIAS2", NULL, "CLK_SYS" },
1713 { "MICBIAS2", NULL, "MICBIAS Supply" },
1714 };
1715
1716 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1717 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1718 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1719 { "MICBIAS1", NULL, "VMID" },
1720 { "MICBIAS2", NULL, "VMID" },
1721 };
1722
1723 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1724 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1725 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1726
1727 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1728 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1729 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1730 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1731
1732 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1733 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1734
1735 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1736 };
1737
1738 /* The size in bits of the FLL divide multiplied by 10
1739 * to allow rounding later */
1740 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1741
1742 struct fll_div {
1743 u16 outdiv;
1744 u16 n;
1745 u16 k;
1746 u16 clk_ref_div;
1747 u16 fll_fratio;
1748 };
1749
1750 static int wm8994_get_fll_config(struct fll_div *fll,
1751 int freq_in, int freq_out)
1752 {
1753 u64 Kpart;
1754 unsigned int K, Ndiv, Nmod;
1755
1756 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1757
1758 /* Scale the input frequency down to <= 13.5MHz */
1759 fll->clk_ref_div = 0;
1760 while (freq_in > 13500000) {
1761 fll->clk_ref_div++;
1762 freq_in /= 2;
1763
1764 if (fll->clk_ref_div > 3)
1765 return -EINVAL;
1766 }
1767 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1768
1769 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1770 fll->outdiv = 3;
1771 while (freq_out * (fll->outdiv + 1) < 90000000) {
1772 fll->outdiv++;
1773 if (fll->outdiv > 63)
1774 return -EINVAL;
1775 }
1776 freq_out *= fll->outdiv + 1;
1777 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1778
1779 if (freq_in > 1000000) {
1780 fll->fll_fratio = 0;
1781 } else if (freq_in > 256000) {
1782 fll->fll_fratio = 1;
1783 freq_in *= 2;
1784 } else if (freq_in > 128000) {
1785 fll->fll_fratio = 2;
1786 freq_in *= 4;
1787 } else if (freq_in > 64000) {
1788 fll->fll_fratio = 3;
1789 freq_in *= 8;
1790 } else {
1791 fll->fll_fratio = 4;
1792 freq_in *= 16;
1793 }
1794 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1795
1796 /* Now, calculate N.K */
1797 Ndiv = freq_out / freq_in;
1798
1799 fll->n = Ndiv;
1800 Nmod = freq_out % freq_in;
1801 pr_debug("Nmod=%d\n", Nmod);
1802
1803 /* Calculate fractional part - scale up so we can round. */
1804 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1805
1806 do_div(Kpart, freq_in);
1807
1808 K = Kpart & 0xFFFFFFFF;
1809
1810 if ((K % 10) >= 5)
1811 K += 5;
1812
1813 /* Move down to proper range now rounding is done */
1814 fll->k = K / 10;
1815
1816 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1817
1818 return 0;
1819 }
1820
1821 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1822 unsigned int freq_in, unsigned int freq_out)
1823 {
1824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1825 struct wm8994 *control = wm8994->wm8994;
1826 int reg_offset, ret;
1827 struct fll_div fll;
1828 u16 reg, aif1, aif2;
1829 unsigned long timeout;
1830 bool was_enabled;
1831
1832 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1833 & WM8994_AIF1CLK_ENA;
1834
1835 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1836 & WM8994_AIF2CLK_ENA;
1837
1838 switch (id) {
1839 case WM8994_FLL1:
1840 reg_offset = 0;
1841 id = 0;
1842 break;
1843 case WM8994_FLL2:
1844 reg_offset = 0x20;
1845 id = 1;
1846 break;
1847 default:
1848 return -EINVAL;
1849 }
1850
1851 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1852 was_enabled = reg & WM8994_FLL1_ENA;
1853
1854 switch (src) {
1855 case 0:
1856 /* Allow no source specification when stopping */
1857 if (freq_out)
1858 return -EINVAL;
1859 src = wm8994->fll[id].src;
1860 break;
1861 case WM8994_FLL_SRC_MCLK1:
1862 case WM8994_FLL_SRC_MCLK2:
1863 case WM8994_FLL_SRC_LRCLK:
1864 case WM8994_FLL_SRC_BCLK:
1865 break;
1866 default:
1867 return -EINVAL;
1868 }
1869
1870 /* Are we changing anything? */
1871 if (wm8994->fll[id].src == src &&
1872 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1873 return 0;
1874
1875 /* If we're stopping the FLL redo the old config - no
1876 * registers will actually be written but we avoid GCC flow
1877 * analysis bugs spewing warnings.
1878 */
1879 if (freq_out)
1880 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1881 else
1882 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1883 wm8994->fll[id].out);
1884 if (ret < 0)
1885 return ret;
1886
1887 /* Gate the AIF clocks while we reclock */
1888 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1889 WM8994_AIF1CLK_ENA, 0);
1890 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1891 WM8994_AIF2CLK_ENA, 0);
1892
1893 /* We always need to disable the FLL while reconfiguring */
1894 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1895 WM8994_FLL1_ENA, 0);
1896
1897 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1898 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1899 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1900 WM8994_FLL1_OUTDIV_MASK |
1901 WM8994_FLL1_FRATIO_MASK, reg);
1902
1903 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1904
1905 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1906 WM8994_FLL1_N_MASK,
1907 fll.n << WM8994_FLL1_N_SHIFT);
1908
1909 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1910 WM8994_FLL1_REFCLK_DIV_MASK |
1911 WM8994_FLL1_REFCLK_SRC_MASK,
1912 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1913 (src - 1));
1914
1915 /* Clear any pending completion from a previous failure */
1916 try_wait_for_completion(&wm8994->fll_locked[id]);
1917
1918 /* Enable (with fractional mode if required) */
1919 if (freq_out) {
1920 /* Enable VMID if we need it */
1921 if (!was_enabled) {
1922 switch (control->type) {
1923 case WM8994:
1924 vmid_reference(codec);
1925 break;
1926 case WM8958:
1927 if (wm8994->revision < 1)
1928 vmid_reference(codec);
1929 break;
1930 default:
1931 break;
1932 }
1933 }
1934
1935 if (fll.k)
1936 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1937 else
1938 reg = WM8994_FLL1_ENA;
1939 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1940 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1941 reg);
1942
1943 if (wm8994->fll_locked_irq) {
1944 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1945 msecs_to_jiffies(10));
1946 if (timeout == 0)
1947 dev_warn(codec->dev,
1948 "Timed out waiting for FLL lock\n");
1949 } else {
1950 msleep(5);
1951 }
1952 } else {
1953 if (was_enabled) {
1954 switch (control->type) {
1955 case WM8994:
1956 vmid_dereference(codec);
1957 break;
1958 case WM8958:
1959 if (wm8994->revision < 1)
1960 vmid_dereference(codec);
1961 break;
1962 default:
1963 break;
1964 }
1965 }
1966 }
1967
1968 wm8994->fll[id].in = freq_in;
1969 wm8994->fll[id].out = freq_out;
1970 wm8994->fll[id].src = src;
1971
1972 /* Enable any gated AIF clocks */
1973 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1974 WM8994_AIF1CLK_ENA, aif1);
1975 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1976 WM8994_AIF2CLK_ENA, aif2);
1977
1978 configure_clock(codec);
1979
1980 return 0;
1981 }
1982
1983 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1984 {
1985 struct completion *completion = data;
1986
1987 complete(completion);
1988
1989 return IRQ_HANDLED;
1990 }
1991
1992 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1993
1994 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1995 unsigned int freq_in, unsigned int freq_out)
1996 {
1997 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1998 }
1999
2000 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2001 int clk_id, unsigned int freq, int dir)
2002 {
2003 struct snd_soc_codec *codec = dai->codec;
2004 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2005 int i;
2006
2007 switch (dai->id) {
2008 case 1:
2009 case 2:
2010 break;
2011
2012 default:
2013 /* AIF3 shares clocking with AIF1/2 */
2014 return -EINVAL;
2015 }
2016
2017 switch (clk_id) {
2018 case WM8994_SYSCLK_MCLK1:
2019 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2020 wm8994->mclk[0] = freq;
2021 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2022 dai->id, freq);
2023 break;
2024
2025 case WM8994_SYSCLK_MCLK2:
2026 /* TODO: Set GPIO AF */
2027 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2028 wm8994->mclk[1] = freq;
2029 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2030 dai->id, freq);
2031 break;
2032
2033 case WM8994_SYSCLK_FLL1:
2034 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2035 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2036 break;
2037
2038 case WM8994_SYSCLK_FLL2:
2039 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2040 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2041 break;
2042
2043 case WM8994_SYSCLK_OPCLK:
2044 /* Special case - a division (times 10) is given and
2045 * no effect on main clocking.
2046 */
2047 if (freq) {
2048 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2049 if (opclk_divs[i] == freq)
2050 break;
2051 if (i == ARRAY_SIZE(opclk_divs))
2052 return -EINVAL;
2053 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2054 WM8994_OPCLK_DIV_MASK, i);
2055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2056 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2057 } else {
2058 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2059 WM8994_OPCLK_ENA, 0);
2060 }
2061
2062 default:
2063 return -EINVAL;
2064 }
2065
2066 configure_clock(codec);
2067
2068 return 0;
2069 }
2070
2071 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2072 enum snd_soc_bias_level level)
2073 {
2074 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2075 struct wm8994 *control = wm8994->wm8994;
2076
2077 switch (level) {
2078 case SND_SOC_BIAS_ON:
2079 break;
2080
2081 case SND_SOC_BIAS_PREPARE:
2082 /* MICBIAS into regulating mode */
2083 switch (control->type) {
2084 case WM8958:
2085 case WM1811:
2086 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2087 WM8958_MICB1_MODE, 0);
2088 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2089 WM8958_MICB2_MODE, 0);
2090 break;
2091 default:
2092 break;
2093 }
2094 break;
2095
2096 case SND_SOC_BIAS_STANDBY:
2097 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2098 pm_runtime_get_sync(codec->dev);
2099
2100 switch (control->type) {
2101 case WM8994:
2102 if (wm8994->revision < 4) {
2103 /* Tweak DC servo and DSP
2104 * configuration for improved
2105 * performance. */
2106 snd_soc_write(codec, 0x102, 0x3);
2107 snd_soc_write(codec, 0x56, 0x3);
2108 snd_soc_write(codec, 0x817, 0);
2109 snd_soc_write(codec, 0x102, 0);
2110 }
2111 break;
2112
2113 case WM8958:
2114 if (wm8994->revision == 0) {
2115 /* Optimise performance for rev A */
2116 snd_soc_write(codec, 0x102, 0x3);
2117 snd_soc_write(codec, 0xcb, 0x81);
2118 snd_soc_write(codec, 0x817, 0);
2119 snd_soc_write(codec, 0x102, 0);
2120
2121 snd_soc_update_bits(codec,
2122 WM8958_CHARGE_PUMP_2,
2123 WM8958_CP_DISCH,
2124 WM8958_CP_DISCH);
2125 }
2126 break;
2127
2128 case WM1811:
2129 if (wm8994->revision < 2) {
2130 snd_soc_write(codec, 0x102, 0x3);
2131 snd_soc_write(codec, 0x5d, 0x7e);
2132 snd_soc_write(codec, 0x5e, 0x0);
2133 snd_soc_write(codec, 0x102, 0x0);
2134 }
2135 break;
2136 }
2137
2138 /* Discharge LINEOUT1 & 2 */
2139 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2140 WM8994_LINEOUT1_DISCH |
2141 WM8994_LINEOUT2_DISCH,
2142 WM8994_LINEOUT1_DISCH |
2143 WM8994_LINEOUT2_DISCH);
2144 }
2145
2146 /* MICBIAS into bypass mode on newer devices */
2147 switch (control->type) {
2148 case WM8958:
2149 case WM1811:
2150 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2151 WM8958_MICB1_MODE,
2152 WM8958_MICB1_MODE);
2153 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2154 WM8958_MICB2_MODE,
2155 WM8958_MICB2_MODE);
2156 break;
2157 default:
2158 break;
2159 }
2160 break;
2161
2162 case SND_SOC_BIAS_OFF:
2163 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
2164 wm8994->cur_fw = NULL;
2165
2166 pm_runtime_put(codec->dev);
2167 }
2168 break;
2169 }
2170 codec->dapm.bias_level = level;
2171 return 0;
2172 }
2173
2174 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2175 {
2176 struct snd_soc_codec *codec = dai->codec;
2177 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2178 struct wm8994 *control = wm8994->wm8994;
2179 int ms_reg;
2180 int aif1_reg;
2181 int ms = 0;
2182 int aif1 = 0;
2183
2184 switch (dai->id) {
2185 case 1:
2186 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2187 aif1_reg = WM8994_AIF1_CONTROL_1;
2188 break;
2189 case 2:
2190 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2191 aif1_reg = WM8994_AIF2_CONTROL_1;
2192 break;
2193 default:
2194 return -EINVAL;
2195 }
2196
2197 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2198 case SND_SOC_DAIFMT_CBS_CFS:
2199 break;
2200 case SND_SOC_DAIFMT_CBM_CFM:
2201 ms = WM8994_AIF1_MSTR;
2202 break;
2203 default:
2204 return -EINVAL;
2205 }
2206
2207 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2208 case SND_SOC_DAIFMT_DSP_B:
2209 aif1 |= WM8994_AIF1_LRCLK_INV;
2210 case SND_SOC_DAIFMT_DSP_A:
2211 aif1 |= 0x18;
2212 break;
2213 case SND_SOC_DAIFMT_I2S:
2214 aif1 |= 0x10;
2215 break;
2216 case SND_SOC_DAIFMT_RIGHT_J:
2217 break;
2218 case SND_SOC_DAIFMT_LEFT_J:
2219 aif1 |= 0x8;
2220 break;
2221 default:
2222 return -EINVAL;
2223 }
2224
2225 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2226 case SND_SOC_DAIFMT_DSP_A:
2227 case SND_SOC_DAIFMT_DSP_B:
2228 /* frame inversion not valid for DSP modes */
2229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2230 case SND_SOC_DAIFMT_NB_NF:
2231 break;
2232 case SND_SOC_DAIFMT_IB_NF:
2233 aif1 |= WM8994_AIF1_BCLK_INV;
2234 break;
2235 default:
2236 return -EINVAL;
2237 }
2238 break;
2239
2240 case SND_SOC_DAIFMT_I2S:
2241 case SND_SOC_DAIFMT_RIGHT_J:
2242 case SND_SOC_DAIFMT_LEFT_J:
2243 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2244 case SND_SOC_DAIFMT_NB_NF:
2245 break;
2246 case SND_SOC_DAIFMT_IB_IF:
2247 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2248 break;
2249 case SND_SOC_DAIFMT_IB_NF:
2250 aif1 |= WM8994_AIF1_BCLK_INV;
2251 break;
2252 case SND_SOC_DAIFMT_NB_IF:
2253 aif1 |= WM8994_AIF1_LRCLK_INV;
2254 break;
2255 default:
2256 return -EINVAL;
2257 }
2258 break;
2259 default:
2260 return -EINVAL;
2261 }
2262
2263 /* The AIF2 format configuration needs to be mirrored to AIF3
2264 * on WM8958 if it's in use so just do it all the time. */
2265 switch (control->type) {
2266 case WM1811:
2267 case WM8958:
2268 if (dai->id == 2)
2269 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2270 WM8994_AIF1_LRCLK_INV |
2271 WM8958_AIF3_FMT_MASK, aif1);
2272 break;
2273
2274 default:
2275 break;
2276 }
2277
2278 snd_soc_update_bits(codec, aif1_reg,
2279 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2280 WM8994_AIF1_FMT_MASK,
2281 aif1);
2282 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2283 ms);
2284
2285 return 0;
2286 }
2287
2288 static struct {
2289 int val, rate;
2290 } srs[] = {
2291 { 0, 8000 },
2292 { 1, 11025 },
2293 { 2, 12000 },
2294 { 3, 16000 },
2295 { 4, 22050 },
2296 { 5, 24000 },
2297 { 6, 32000 },
2298 { 7, 44100 },
2299 { 8, 48000 },
2300 { 9, 88200 },
2301 { 10, 96000 },
2302 };
2303
2304 static int fs_ratios[] = {
2305 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2306 };
2307
2308 static int bclk_divs[] = {
2309 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2310 640, 880, 960, 1280, 1760, 1920
2311 };
2312
2313 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2314 struct snd_pcm_hw_params *params,
2315 struct snd_soc_dai *dai)
2316 {
2317 struct snd_soc_codec *codec = dai->codec;
2318 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2319 int aif1_reg;
2320 int aif2_reg;
2321 int bclk_reg;
2322 int lrclk_reg;
2323 int rate_reg;
2324 int aif1 = 0;
2325 int aif2 = 0;
2326 int bclk = 0;
2327 int lrclk = 0;
2328 int rate_val = 0;
2329 int id = dai->id - 1;
2330
2331 int i, cur_val, best_val, bclk_rate, best;
2332
2333 switch (dai->id) {
2334 case 1:
2335 aif1_reg = WM8994_AIF1_CONTROL_1;
2336 aif2_reg = WM8994_AIF1_CONTROL_2;
2337 bclk_reg = WM8994_AIF1_BCLK;
2338 rate_reg = WM8994_AIF1_RATE;
2339 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2340 wm8994->lrclk_shared[0]) {
2341 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2342 } else {
2343 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2344 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2345 }
2346 break;
2347 case 2:
2348 aif1_reg = WM8994_AIF2_CONTROL_1;
2349 aif2_reg = WM8994_AIF2_CONTROL_2;
2350 bclk_reg = WM8994_AIF2_BCLK;
2351 rate_reg = WM8994_AIF2_RATE;
2352 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2353 wm8994->lrclk_shared[1]) {
2354 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2355 } else {
2356 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2357 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2358 }
2359 break;
2360 default:
2361 return -EINVAL;
2362 }
2363
2364 bclk_rate = params_rate(params) * 2;
2365 switch (params_format(params)) {
2366 case SNDRV_PCM_FORMAT_S16_LE:
2367 bclk_rate *= 16;
2368 break;
2369 case SNDRV_PCM_FORMAT_S20_3LE:
2370 bclk_rate *= 20;
2371 aif1 |= 0x20;
2372 break;
2373 case SNDRV_PCM_FORMAT_S24_LE:
2374 bclk_rate *= 24;
2375 aif1 |= 0x40;
2376 break;
2377 case SNDRV_PCM_FORMAT_S32_LE:
2378 bclk_rate *= 32;
2379 aif1 |= 0x60;
2380 break;
2381 default:
2382 return -EINVAL;
2383 }
2384
2385 /* Try to find an appropriate sample rate; look for an exact match. */
2386 for (i = 0; i < ARRAY_SIZE(srs); i++)
2387 if (srs[i].rate == params_rate(params))
2388 break;
2389 if (i == ARRAY_SIZE(srs))
2390 return -EINVAL;
2391 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2392
2393 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2394 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2395 dai->id, wm8994->aifclk[id], bclk_rate);
2396
2397 if (params_channels(params) == 1 &&
2398 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2399 aif2 |= WM8994_AIF1_MONO;
2400
2401 if (wm8994->aifclk[id] == 0) {
2402 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2403 return -EINVAL;
2404 }
2405
2406 /* AIFCLK/fs ratio; look for a close match in either direction */
2407 best = 0;
2408 best_val = abs((fs_ratios[0] * params_rate(params))
2409 - wm8994->aifclk[id]);
2410 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2411 cur_val = abs((fs_ratios[i] * params_rate(params))
2412 - wm8994->aifclk[id]);
2413 if (cur_val >= best_val)
2414 continue;
2415 best = i;
2416 best_val = cur_val;
2417 }
2418 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2419 dai->id, fs_ratios[best]);
2420 rate_val |= best;
2421
2422 /* We may not get quite the right frequency if using
2423 * approximate clocks so look for the closest match that is
2424 * higher than the target (we need to ensure that there enough
2425 * BCLKs to clock out the samples).
2426 */
2427 best = 0;
2428 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2429 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2430 if (cur_val < 0) /* BCLK table is sorted */
2431 break;
2432 best = i;
2433 }
2434 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2435 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2436 bclk_divs[best], bclk_rate);
2437 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2438
2439 lrclk = bclk_rate / params_rate(params);
2440 if (!lrclk) {
2441 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2442 bclk_rate);
2443 return -EINVAL;
2444 }
2445 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2446 lrclk, bclk_rate / lrclk);
2447
2448 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2449 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2450 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2451 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2452 lrclk);
2453 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2454 WM8994_AIF1CLK_RATE_MASK, rate_val);
2455
2456 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2457 switch (dai->id) {
2458 case 1:
2459 wm8994->dac_rates[0] = params_rate(params);
2460 wm8994_set_retune_mobile(codec, 0);
2461 wm8994_set_retune_mobile(codec, 1);
2462 break;
2463 case 2:
2464 wm8994->dac_rates[1] = params_rate(params);
2465 wm8994_set_retune_mobile(codec, 2);
2466 break;
2467 }
2468 }
2469
2470 return 0;
2471 }
2472
2473 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2474 struct snd_pcm_hw_params *params,
2475 struct snd_soc_dai *dai)
2476 {
2477 struct snd_soc_codec *codec = dai->codec;
2478 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2479 struct wm8994 *control = wm8994->wm8994;
2480 int aif1_reg;
2481 int aif1 = 0;
2482
2483 switch (dai->id) {
2484 case 3:
2485 switch (control->type) {
2486 case WM1811:
2487 case WM8958:
2488 aif1_reg = WM8958_AIF3_CONTROL_1;
2489 break;
2490 default:
2491 return 0;
2492 }
2493 default:
2494 return 0;
2495 }
2496
2497 switch (params_format(params)) {
2498 case SNDRV_PCM_FORMAT_S16_LE:
2499 break;
2500 case SNDRV_PCM_FORMAT_S20_3LE:
2501 aif1 |= 0x20;
2502 break;
2503 case SNDRV_PCM_FORMAT_S24_LE:
2504 aif1 |= 0x40;
2505 break;
2506 case SNDRV_PCM_FORMAT_S32_LE:
2507 aif1 |= 0x60;
2508 break;
2509 default:
2510 return -EINVAL;
2511 }
2512
2513 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2514 }
2515
2516 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2517 struct snd_soc_dai *dai)
2518 {
2519 struct snd_soc_codec *codec = dai->codec;
2520 int rate_reg = 0;
2521
2522 switch (dai->id) {
2523 case 1:
2524 rate_reg = WM8994_AIF1_RATE;
2525 break;
2526 case 2:
2527 rate_reg = WM8994_AIF2_RATE;
2528 break;
2529 default:
2530 break;
2531 }
2532
2533 /* If the DAI is idle then configure the divider tree for the
2534 * lowest output rate to save a little power if the clock is
2535 * still active (eg, because it is system clock).
2536 */
2537 if (rate_reg && !dai->playback_active && !dai->capture_active)
2538 snd_soc_update_bits(codec, rate_reg,
2539 WM8994_AIF1_SR_MASK |
2540 WM8994_AIF1CLK_RATE_MASK, 0x9);
2541 }
2542
2543 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2544 {
2545 struct snd_soc_codec *codec = codec_dai->codec;
2546 int mute_reg;
2547 int reg;
2548
2549 switch (codec_dai->id) {
2550 case 1:
2551 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2552 break;
2553 case 2:
2554 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2555 break;
2556 default:
2557 return -EINVAL;
2558 }
2559
2560 if (mute)
2561 reg = WM8994_AIF1DAC1_MUTE;
2562 else
2563 reg = 0;
2564
2565 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2566
2567 return 0;
2568 }
2569
2570 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2571 {
2572 struct snd_soc_codec *codec = codec_dai->codec;
2573 int reg, val, mask;
2574
2575 switch (codec_dai->id) {
2576 case 1:
2577 reg = WM8994_AIF1_MASTER_SLAVE;
2578 mask = WM8994_AIF1_TRI;
2579 break;
2580 case 2:
2581 reg = WM8994_AIF2_MASTER_SLAVE;
2582 mask = WM8994_AIF2_TRI;
2583 break;
2584 case 3:
2585 reg = WM8994_POWER_MANAGEMENT_6;
2586 mask = WM8994_AIF3_TRI;
2587 break;
2588 default:
2589 return -EINVAL;
2590 }
2591
2592 if (tristate)
2593 val = mask;
2594 else
2595 val = 0;
2596
2597 return snd_soc_update_bits(codec, reg, mask, val);
2598 }
2599
2600 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2601 {
2602 struct snd_soc_codec *codec = dai->codec;
2603
2604 /* Disable the pulls on the AIF if we're using it to save power. */
2605 snd_soc_update_bits(codec, WM8994_GPIO_3,
2606 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2607 snd_soc_update_bits(codec, WM8994_GPIO_4,
2608 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2609 snd_soc_update_bits(codec, WM8994_GPIO_5,
2610 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2611
2612 return 0;
2613 }
2614
2615 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2616
2617 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2618 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2619
2620 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2621 .set_sysclk = wm8994_set_dai_sysclk,
2622 .set_fmt = wm8994_set_dai_fmt,
2623 .hw_params = wm8994_hw_params,
2624 .shutdown = wm8994_aif_shutdown,
2625 .digital_mute = wm8994_aif_mute,
2626 .set_pll = wm8994_set_fll,
2627 .set_tristate = wm8994_set_tristate,
2628 };
2629
2630 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2631 .set_sysclk = wm8994_set_dai_sysclk,
2632 .set_fmt = wm8994_set_dai_fmt,
2633 .hw_params = wm8994_hw_params,
2634 .shutdown = wm8994_aif_shutdown,
2635 .digital_mute = wm8994_aif_mute,
2636 .set_pll = wm8994_set_fll,
2637 .set_tristate = wm8994_set_tristate,
2638 };
2639
2640 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2641 .hw_params = wm8994_aif3_hw_params,
2642 .set_tristate = wm8994_set_tristate,
2643 };
2644
2645 static struct snd_soc_dai_driver wm8994_dai[] = {
2646 {
2647 .name = "wm8994-aif1",
2648 .id = 1,
2649 .playback = {
2650 .stream_name = "AIF1 Playback",
2651 .channels_min = 1,
2652 .channels_max = 2,
2653 .rates = WM8994_RATES,
2654 .formats = WM8994_FORMATS,
2655 },
2656 .capture = {
2657 .stream_name = "AIF1 Capture",
2658 .channels_min = 1,
2659 .channels_max = 2,
2660 .rates = WM8994_RATES,
2661 .formats = WM8994_FORMATS,
2662 },
2663 .ops = &wm8994_aif1_dai_ops,
2664 },
2665 {
2666 .name = "wm8994-aif2",
2667 .id = 2,
2668 .playback = {
2669 .stream_name = "AIF2 Playback",
2670 .channels_min = 1,
2671 .channels_max = 2,
2672 .rates = WM8994_RATES,
2673 .formats = WM8994_FORMATS,
2674 },
2675 .capture = {
2676 .stream_name = "AIF2 Capture",
2677 .channels_min = 1,
2678 .channels_max = 2,
2679 .rates = WM8994_RATES,
2680 .formats = WM8994_FORMATS,
2681 },
2682 .probe = wm8994_aif2_probe,
2683 .ops = &wm8994_aif2_dai_ops,
2684 },
2685 {
2686 .name = "wm8994-aif3",
2687 .id = 3,
2688 .playback = {
2689 .stream_name = "AIF3 Playback",
2690 .channels_min = 1,
2691 .channels_max = 2,
2692 .rates = WM8994_RATES,
2693 .formats = WM8994_FORMATS,
2694 },
2695 .capture = {
2696 .stream_name = "AIF3 Capture",
2697 .channels_min = 1,
2698 .channels_max = 2,
2699 .rates = WM8994_RATES,
2700 .formats = WM8994_FORMATS,
2701 },
2702 .ops = &wm8994_aif3_dai_ops,
2703 }
2704 };
2705
2706 #ifdef CONFIG_PM
2707 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2708 {
2709 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2710 struct wm8994 *control = wm8994->wm8994;
2711 int i, ret;
2712
2713 switch (control->type) {
2714 case WM8994:
2715 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2716 break;
2717 case WM1811:
2718 case WM8958:
2719 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2720 WM8958_MICD_ENA, 0);
2721 break;
2722 }
2723
2724 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2725 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2726 sizeof(struct wm8994_fll_config));
2727 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2728 if (ret < 0)
2729 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2730 i + 1, ret);
2731 }
2732
2733 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2734
2735 return 0;
2736 }
2737
2738 static int wm8994_resume(struct snd_soc_codec *codec)
2739 {
2740 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2741 struct wm8994 *control = wm8994->wm8994;
2742 int i, ret;
2743 unsigned int val, mask;
2744
2745 if (wm8994->revision < 4) {
2746 /* force a HW read */
2747 val = wm8994_reg_read(codec->control_data,
2748 WM8994_POWER_MANAGEMENT_5);
2749
2750 /* modify the cache only */
2751 codec->cache_only = 1;
2752 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2753 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2754 val &= mask;
2755 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2756 mask, val);
2757 codec->cache_only = 0;
2758 }
2759
2760 /* Restore the registers */
2761 ret = snd_soc_cache_sync(codec);
2762 if (ret != 0)
2763 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2764
2765 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2766
2767 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2768 if (!wm8994->fll_suspend[i].out)
2769 continue;
2770
2771 ret = _wm8994_set_fll(codec, i + 1,
2772 wm8994->fll_suspend[i].src,
2773 wm8994->fll_suspend[i].in,
2774 wm8994->fll_suspend[i].out);
2775 if (ret < 0)
2776 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2777 i + 1, ret);
2778 }
2779
2780 switch (control->type) {
2781 case WM8994:
2782 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2783 snd_soc_update_bits(codec, WM8994_MICBIAS,
2784 WM8994_MICD_ENA, WM8994_MICD_ENA);
2785 break;
2786 case WM1811:
2787 case WM8958:
2788 if (wm8994->jack_cb)
2789 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2790 WM8958_MICD_ENA, WM8958_MICD_ENA);
2791 break;
2792 }
2793
2794 return 0;
2795 }
2796 #else
2797 #define wm8994_suspend NULL
2798 #define wm8994_resume NULL
2799 #endif
2800
2801 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2802 {
2803 struct snd_soc_codec *codec = wm8994->codec;
2804 struct wm8994_pdata *pdata = wm8994->pdata;
2805 struct snd_kcontrol_new controls[] = {
2806 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2807 wm8994->retune_mobile_enum,
2808 wm8994_get_retune_mobile_enum,
2809 wm8994_put_retune_mobile_enum),
2810 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2811 wm8994->retune_mobile_enum,
2812 wm8994_get_retune_mobile_enum,
2813 wm8994_put_retune_mobile_enum),
2814 SOC_ENUM_EXT("AIF2 EQ Mode",
2815 wm8994->retune_mobile_enum,
2816 wm8994_get_retune_mobile_enum,
2817 wm8994_put_retune_mobile_enum),
2818 };
2819 int ret, i, j;
2820 const char **t;
2821
2822 /* We need an array of texts for the enum API but the number
2823 * of texts is likely to be less than the number of
2824 * configurations due to the sample rate dependency of the
2825 * configurations. */
2826 wm8994->num_retune_mobile_texts = 0;
2827 wm8994->retune_mobile_texts = NULL;
2828 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2829 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2830 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2831 wm8994->retune_mobile_texts[j]) == 0)
2832 break;
2833 }
2834
2835 if (j != wm8994->num_retune_mobile_texts)
2836 continue;
2837
2838 /* Expand the array... */
2839 t = krealloc(wm8994->retune_mobile_texts,
2840 sizeof(char *) *
2841 (wm8994->num_retune_mobile_texts + 1),
2842 GFP_KERNEL);
2843 if (t == NULL)
2844 continue;
2845
2846 /* ...store the new entry... */
2847 t[wm8994->num_retune_mobile_texts] =
2848 pdata->retune_mobile_cfgs[i].name;
2849
2850 /* ...and remember the new version. */
2851 wm8994->num_retune_mobile_texts++;
2852 wm8994->retune_mobile_texts = t;
2853 }
2854
2855 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2856 wm8994->num_retune_mobile_texts);
2857
2858 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2859 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2860
2861 ret = snd_soc_add_controls(wm8994->codec, controls,
2862 ARRAY_SIZE(controls));
2863 if (ret != 0)
2864 dev_err(wm8994->codec->dev,
2865 "Failed to add ReTune Mobile controls: %d\n", ret);
2866 }
2867
2868 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2869 {
2870 struct snd_soc_codec *codec = wm8994->codec;
2871 struct wm8994_pdata *pdata = wm8994->pdata;
2872 int ret, i;
2873
2874 if (!pdata)
2875 return;
2876
2877 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2878 pdata->lineout2_diff,
2879 pdata->lineout1fb,
2880 pdata->lineout2fb,
2881 pdata->jd_scthr,
2882 pdata->jd_thr,
2883 pdata->micbias1_lvl,
2884 pdata->micbias2_lvl);
2885
2886 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2887
2888 if (pdata->num_drc_cfgs) {
2889 struct snd_kcontrol_new controls[] = {
2890 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2891 wm8994_get_drc_enum, wm8994_put_drc_enum),
2892 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2893 wm8994_get_drc_enum, wm8994_put_drc_enum),
2894 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2895 wm8994_get_drc_enum, wm8994_put_drc_enum),
2896 };
2897
2898 /* We need an array of texts for the enum API */
2899 wm8994->drc_texts = kmalloc(sizeof(char *)
2900 * pdata->num_drc_cfgs, GFP_KERNEL);
2901 if (!wm8994->drc_texts) {
2902 dev_err(wm8994->codec->dev,
2903 "Failed to allocate %d DRC config texts\n",
2904 pdata->num_drc_cfgs);
2905 return;
2906 }
2907
2908 for (i = 0; i < pdata->num_drc_cfgs; i++)
2909 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2910
2911 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2912 wm8994->drc_enum.texts = wm8994->drc_texts;
2913
2914 ret = snd_soc_add_controls(wm8994->codec, controls,
2915 ARRAY_SIZE(controls));
2916 if (ret != 0)
2917 dev_err(wm8994->codec->dev,
2918 "Failed to add DRC mode controls: %d\n", ret);
2919
2920 for (i = 0; i < WM8994_NUM_DRC; i++)
2921 wm8994_set_drc(codec, i);
2922 }
2923
2924 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2925 pdata->num_retune_mobile_cfgs);
2926
2927 if (pdata->num_retune_mobile_cfgs)
2928 wm8994_handle_retune_mobile_pdata(wm8994);
2929 else
2930 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2931 ARRAY_SIZE(wm8994_eq_controls));
2932
2933 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2934 if (pdata->micbias[i]) {
2935 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2936 pdata->micbias[i] & 0xffff);
2937 }
2938 }
2939 }
2940
2941 /**
2942 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2943 *
2944 * @codec: WM8994 codec
2945 * @jack: jack to report detection events on
2946 * @micbias: microphone bias to detect on
2947 * @det: value to report for presence detection
2948 * @shrt: value to report for short detection
2949 *
2950 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2951 * being used to bring out signals to the processor then only platform
2952 * data configuration is needed for WM8994 and processor GPIOs should
2953 * be configured using snd_soc_jack_add_gpios() instead.
2954 *
2955 * Configuration of detection levels is available via the micbias1_lvl
2956 * and micbias2_lvl platform data members.
2957 */
2958 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2959 int micbias, int det, int shrt)
2960 {
2961 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2962 struct wm8994_micdet *micdet;
2963 struct wm8994 *control = wm8994->wm8994;
2964 int reg;
2965
2966 if (control->type != WM8994)
2967 return -EINVAL;
2968
2969 switch (micbias) {
2970 case 1:
2971 micdet = &wm8994->micdet[0];
2972 break;
2973 case 2:
2974 micdet = &wm8994->micdet[1];
2975 break;
2976 default:
2977 return -EINVAL;
2978 }
2979
2980 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2981 micbias, det, shrt);
2982
2983 /* Store the configuration */
2984 micdet->jack = jack;
2985 micdet->det = det;
2986 micdet->shrt = shrt;
2987
2988 /* If either of the jacks is set up then enable detection */
2989 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2990 reg = WM8994_MICD_ENA;
2991 else
2992 reg = 0;
2993
2994 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2995
2996 return 0;
2997 }
2998 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2999
3000 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3001 {
3002 struct wm8994_priv *priv = data;
3003 struct snd_soc_codec *codec = priv->codec;
3004 int reg;
3005 int report;
3006
3007 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3008 trace_snd_soc_jack_irq(dev_name(codec->dev));
3009 #endif
3010
3011 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3012 if (reg < 0) {
3013 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3014 reg);
3015 return IRQ_HANDLED;
3016 }
3017
3018 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3019
3020 report = 0;
3021 if (reg & WM8994_MIC1_DET_STS)
3022 report |= priv->micdet[0].det;
3023 if (reg & WM8994_MIC1_SHRT_STS)
3024 report |= priv->micdet[0].shrt;
3025 snd_soc_jack_report(priv->micdet[0].jack, report,
3026 priv->micdet[0].det | priv->micdet[0].shrt);
3027
3028 report = 0;
3029 if (reg & WM8994_MIC2_DET_STS)
3030 report |= priv->micdet[1].det;
3031 if (reg & WM8994_MIC2_SHRT_STS)
3032 report |= priv->micdet[1].shrt;
3033 snd_soc_jack_report(priv->micdet[1].jack, report,
3034 priv->micdet[1].det | priv->micdet[1].shrt);
3035
3036 return IRQ_HANDLED;
3037 }
3038
3039 /* Default microphone detection handler for WM8958 - the user can
3040 * override this if they wish.
3041 */
3042 static void wm8958_default_micdet(u16 status, void *data)
3043 {
3044 struct snd_soc_codec *codec = data;
3045 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3046 int report;
3047
3048 dev_dbg(codec->dev, "MICDET %x\n", status);
3049
3050 /* If nothing present then clear our statuses */
3051 if (!(status & WM8958_MICD_STS)) {
3052 dev_dbg(codec->dev, "Detected open circuit\n");
3053 wm8994->jack_mic = false;
3054 wm8994->mic_detecting = true;
3055
3056 wm8958_micd_set_rate(codec);
3057
3058 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3059 wm8994->btn_mask | SND_JACK_HEADSET);
3060
3061 return;
3062 }
3063
3064 /* If the measurement is showing a high impedence we've got a
3065 * microphone.
3066 */
3067 if (wm8994->mic_detecting && (status & 0x600)) {
3068 dev_dbg(codec->dev, "Detected microphone\n");
3069
3070 wm8994->mic_detecting = false;
3071 wm8994->jack_mic = true;
3072
3073 wm8958_micd_set_rate(codec);
3074
3075 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3076 SND_JACK_HEADSET);
3077 }
3078
3079
3080 if (wm8994->mic_detecting && status & 0x4) {
3081 dev_dbg(codec->dev, "Detected headphone\n");
3082 wm8994->mic_detecting = false;
3083
3084 wm8958_micd_set_rate(codec);
3085
3086 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3087 SND_JACK_HEADSET);
3088 }
3089
3090 /* Report short circuit as a button */
3091 if (wm8994->jack_mic) {
3092 report = 0;
3093 if (status & 0x4)
3094 report |= SND_JACK_BTN_0;
3095
3096 if (status & 0x8)
3097 report |= SND_JACK_BTN_1;
3098
3099 if (status & 0x10)
3100 report |= SND_JACK_BTN_2;
3101
3102 if (status & 0x20)
3103 report |= SND_JACK_BTN_3;
3104
3105 if (status & 0x40)
3106 report |= SND_JACK_BTN_4;
3107
3108 if (status & 0x80)
3109 report |= SND_JACK_BTN_5;
3110
3111 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3112 wm8994->btn_mask);
3113 }
3114 }
3115
3116 /**
3117 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3118 *
3119 * @codec: WM8958 codec
3120 * @jack: jack to report detection events on
3121 *
3122 * Enable microphone detection functionality for the WM8958. By
3123 * default simple detection which supports the detection of up to 6
3124 * buttons plus video and microphone functionality is supported.
3125 *
3126 * The WM8958 has an advanced jack detection facility which is able to
3127 * support complex accessory detection, especially when used in
3128 * conjunction with external circuitry. In order to provide maximum
3129 * flexiblity a callback is provided which allows a completely custom
3130 * detection algorithm.
3131 */
3132 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3133 wm8958_micdet_cb cb, void *cb_data)
3134 {
3135 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3136 struct wm8994 *control = wm8994->wm8994;
3137 u16 micd_lvl_sel;
3138
3139 switch (control->type) {
3140 case WM1811:
3141 case WM8958:
3142 break;
3143 default:
3144 return -EINVAL;
3145 }
3146
3147 if (jack) {
3148 if (!cb) {
3149 dev_dbg(codec->dev, "Using default micdet callback\n");
3150 cb = wm8958_default_micdet;
3151 cb_data = codec;
3152 }
3153
3154 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3155
3156 wm8994->micdet[0].jack = jack;
3157 wm8994->jack_cb = cb;
3158 wm8994->jack_cb_data = cb_data;
3159
3160 wm8994->mic_detecting = true;
3161 wm8994->jack_mic = false;
3162
3163 wm8958_micd_set_rate(codec);
3164
3165 /* Detect microphones and short circuits by default */
3166 if (wm8994->pdata->micd_lvl_sel)
3167 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3168 else
3169 micd_lvl_sel = 0x41;
3170
3171 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3172 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3173 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3174
3175 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3176 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3177
3178 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3179 WM8958_MICD_ENA, WM8958_MICD_ENA);
3180 } else {
3181 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3182 WM8958_MICD_ENA, 0);
3183 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3184 }
3185
3186 return 0;
3187 }
3188 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3189
3190 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3191 {
3192 struct wm8994_priv *wm8994 = data;
3193 struct snd_soc_codec *codec = wm8994->codec;
3194 int reg, count;
3195
3196 /* We may occasionally read a detection without an impedence
3197 * range being provided - if that happens loop again.
3198 */
3199 count = 10;
3200 do {
3201 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3202 if (reg < 0) {
3203 dev_err(codec->dev,
3204 "Failed to read mic detect status: %d\n",
3205 reg);
3206 return IRQ_NONE;
3207 }
3208
3209 if (!(reg & WM8958_MICD_VALID)) {
3210 dev_dbg(codec->dev, "Mic detect data not valid\n");
3211 goto out;
3212 }
3213
3214 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3215 break;
3216
3217 msleep(1);
3218 } while (count--);
3219
3220 if (count == 0)
3221 dev_warn(codec->dev, "No impedence range reported for jack\n");
3222
3223 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3224 trace_snd_soc_jack_irq(dev_name(codec->dev));
3225 #endif
3226
3227 if (wm8994->jack_cb)
3228 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3229 else
3230 dev_warn(codec->dev, "Accessory detection with no callback\n");
3231
3232 out:
3233 return IRQ_HANDLED;
3234 }
3235
3236 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3237 {
3238 struct snd_soc_codec *codec = data;
3239
3240 dev_err(codec->dev, "FIFO error\n");
3241
3242 return IRQ_HANDLED;
3243 }
3244
3245 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3246 {
3247 struct snd_soc_codec *codec = data;
3248
3249 dev_err(codec->dev, "Thermal warning\n");
3250
3251 return IRQ_HANDLED;
3252 }
3253
3254 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3255 {
3256 struct snd_soc_codec *codec = data;
3257
3258 dev_crit(codec->dev, "Thermal shutdown\n");
3259
3260 return IRQ_HANDLED;
3261 }
3262
3263 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3264 {
3265 struct wm8994 *control;
3266 struct wm8994_priv *wm8994;
3267 struct snd_soc_dapm_context *dapm = &codec->dapm;
3268 int ret, i;
3269
3270 codec->control_data = dev_get_drvdata(codec->dev->parent);
3271 control = codec->control_data;
3272
3273 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3274 if (wm8994 == NULL)
3275 return -ENOMEM;
3276 snd_soc_codec_set_drvdata(codec, wm8994);
3277
3278
3279 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3280 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3281 wm8994->codec = codec;
3282
3283 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3284 init_completion(&wm8994->fll_locked[i]);
3285
3286 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3287 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3288 else if (wm8994->pdata && wm8994->pdata->irq_base)
3289 wm8994->micdet_irq = wm8994->pdata->irq_base +
3290 WM8994_IRQ_MIC1_DET;
3291
3292 pm_runtime_enable(codec->dev);
3293 pm_runtime_resume(codec->dev);
3294
3295 /* Read our current status back from the chip - we don't want to
3296 * reset as this may interfere with the GPIO or LDO operation. */
3297 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3298 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
3299 continue;
3300
3301 ret = wm8994_reg_read(codec->control_data, i);
3302 if (ret <= 0)
3303 continue;
3304
3305 ret = snd_soc_cache_write(codec, i, ret);
3306 if (ret != 0) {
3307 dev_err(codec->dev,
3308 "Failed to initialise cache for 0x%x: %d\n",
3309 i, ret);
3310 goto err;
3311 }
3312 }
3313
3314 /* Set revision-specific configuration */
3315 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3316 switch (control->type) {
3317 case WM8994:
3318 switch (wm8994->revision) {
3319 case 2:
3320 case 3:
3321 wm8994->hubs.dcs_codes_l = -5;
3322 wm8994->hubs.dcs_codes_r = -5;
3323 wm8994->hubs.hp_startup_mode = 1;
3324 wm8994->hubs.dcs_readback_mode = 1;
3325 wm8994->hubs.series_startup = 1;
3326 break;
3327 default:
3328 wm8994->hubs.dcs_readback_mode = 2;
3329 break;
3330 }
3331 break;
3332
3333 case WM8958:
3334 wm8994->hubs.dcs_readback_mode = 1;
3335 break;
3336
3337 case WM1811:
3338 wm8994->hubs.dcs_readback_mode = 2;
3339 wm8994->hubs.no_series_update = 1;
3340
3341 switch (wm8994->revision) {
3342 case 0:
3343 case 1:
3344 case 2:
3345 case 3:
3346 wm8994->hubs.dcs_codes_l = -9;
3347 wm8994->hubs.dcs_codes_r = -5;
3348 break;
3349 default:
3350 break;
3351 }
3352
3353 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3354 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3355 break;
3356
3357 default:
3358 break;
3359 }
3360
3361 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3362 wm8994_fifo_error, "FIFO error", codec);
3363 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3364 wm8994_temp_warn, "Thermal warning", codec);
3365 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3366 wm8994_temp_shut, "Thermal shutdown", codec);
3367
3368 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3369 wm_hubs_dcs_done, "DC servo done",
3370 &wm8994->hubs);
3371 if (ret == 0)
3372 wm8994->hubs.dcs_done_irq = true;
3373
3374 switch (control->type) {
3375 case WM8994:
3376 if (wm8994->micdet_irq) {
3377 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3378 wm8994_mic_irq,
3379 IRQF_TRIGGER_RISING,
3380 "Mic1 detect",
3381 wm8994);
3382 if (ret != 0)
3383 dev_warn(codec->dev,
3384 "Failed to request Mic1 detect IRQ: %d\n",
3385 ret);
3386 }
3387
3388 ret = wm8994_request_irq(wm8994->wm8994,
3389 WM8994_IRQ_MIC1_SHRT,
3390 wm8994_mic_irq, "Mic 1 short",
3391 wm8994);
3392 if (ret != 0)
3393 dev_warn(codec->dev,
3394 "Failed to request Mic1 short IRQ: %d\n",
3395 ret);
3396
3397 ret = wm8994_request_irq(wm8994->wm8994,
3398 WM8994_IRQ_MIC2_DET,
3399 wm8994_mic_irq, "Mic 2 detect",
3400 wm8994);
3401 if (ret != 0)
3402 dev_warn(codec->dev,
3403 "Failed to request Mic2 detect IRQ: %d\n",
3404 ret);
3405
3406 ret = wm8994_request_irq(wm8994->wm8994,
3407 WM8994_IRQ_MIC2_SHRT,
3408 wm8994_mic_irq, "Mic 2 short",
3409 wm8994);
3410 if (ret != 0)
3411 dev_warn(codec->dev,
3412 "Failed to request Mic2 short IRQ: %d\n",
3413 ret);
3414 break;
3415
3416 case WM8958:
3417 case WM1811:
3418 if (wm8994->micdet_irq) {
3419 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3420 wm8958_mic_irq,
3421 IRQF_TRIGGER_RISING,
3422 "Mic detect",
3423 wm8994);
3424 if (ret != 0)
3425 dev_warn(codec->dev,
3426 "Failed to request Mic detect IRQ: %d\n",
3427 ret);
3428 }
3429 }
3430
3431 wm8994->fll_locked_irq = true;
3432 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3433 ret = wm8994_request_irq(wm8994->wm8994,
3434 WM8994_IRQ_FLL1_LOCK + i,
3435 wm8994_fll_locked_irq, "FLL lock",
3436 &wm8994->fll_locked[i]);
3437 if (ret != 0)
3438 wm8994->fll_locked_irq = false;
3439 }
3440
3441 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3442 * configured on init - if a system wants to do this dynamically
3443 * at runtime we can deal with that then.
3444 */
3445 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3446 if (ret < 0) {
3447 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3448 goto err_irq;
3449 }
3450 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3451 wm8994->lrclk_shared[0] = 1;
3452 wm8994_dai[0].symmetric_rates = 1;
3453 } else {
3454 wm8994->lrclk_shared[0] = 0;
3455 }
3456
3457 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3458 if (ret < 0) {
3459 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3460 goto err_irq;
3461 }
3462 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3463 wm8994->lrclk_shared[1] = 1;
3464 wm8994_dai[1].symmetric_rates = 1;
3465 } else {
3466 wm8994->lrclk_shared[1] = 0;
3467 }
3468
3469 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3470
3471 /* Latch volume updates (right only; we always do left then right). */
3472 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3473 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3474 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3475 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3476 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3477 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3478 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3479 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3480 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3481 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3482 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3483 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3484 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3485 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3486 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3487 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3488 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3489 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3490 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3491 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3492 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3493 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3494 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3495 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3496 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3497 WM8994_DAC1_VU, WM8994_DAC1_VU);
3498 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3499 WM8994_DAC1_VU, WM8994_DAC1_VU);
3500 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3501 WM8994_DAC2_VU, WM8994_DAC2_VU);
3502 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3503 WM8994_DAC2_VU, WM8994_DAC2_VU);
3504
3505 /* Set the low bit of the 3D stereo depth so TLV matches */
3506 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3507 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3508 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3509 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3510 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3511 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3512 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3513 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3514 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3515
3516 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3517 * use this; it only affects behaviour on idle TDM clock
3518 * cycles. */
3519 switch (control->type) {
3520 case WM8994:
3521 case WM8958:
3522 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3523 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3524 break;
3525 default:
3526 break;
3527 }
3528
3529 /* Put MICBIAS into bypass mode by default on newer devices */
3530 switch (control->type) {
3531 case WM8958:
3532 case WM1811:
3533 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3534 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3535 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3536 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3537 break;
3538 default:
3539 break;
3540 }
3541
3542 wm8994_update_class_w(codec);
3543
3544 wm8994_handle_pdata(wm8994);
3545
3546 wm_hubs_add_analogue_controls(codec);
3547 snd_soc_add_controls(codec, wm8994_snd_controls,
3548 ARRAY_SIZE(wm8994_snd_controls));
3549 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3550 ARRAY_SIZE(wm8994_dapm_widgets));
3551
3552 switch (control->type) {
3553 case WM8994:
3554 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3555 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3556 if (wm8994->revision < 4) {
3557 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3558 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3559 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3560 ARRAY_SIZE(wm8994_adc_revd_widgets));
3561 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3562 ARRAY_SIZE(wm8994_dac_revd_widgets));
3563 } else {
3564 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3565 ARRAY_SIZE(wm8994_lateclk_widgets));
3566 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3567 ARRAY_SIZE(wm8994_adc_widgets));
3568 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3569 ARRAY_SIZE(wm8994_dac_widgets));
3570 }
3571 break;
3572 case WM8958:
3573 snd_soc_add_controls(codec, wm8958_snd_controls,
3574 ARRAY_SIZE(wm8958_snd_controls));
3575 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3576 ARRAY_SIZE(wm8958_dapm_widgets));
3577 if (wm8994->revision < 1) {
3578 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3579 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3580 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3581 ARRAY_SIZE(wm8994_adc_revd_widgets));
3582 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3583 ARRAY_SIZE(wm8994_dac_revd_widgets));
3584 } else {
3585 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3586 ARRAY_SIZE(wm8994_lateclk_widgets));
3587 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3588 ARRAY_SIZE(wm8994_adc_widgets));
3589 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3590 ARRAY_SIZE(wm8994_dac_widgets));
3591 }
3592 break;
3593
3594 case WM1811:
3595 snd_soc_add_controls(codec, wm8958_snd_controls,
3596 ARRAY_SIZE(wm8958_snd_controls));
3597 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3598 ARRAY_SIZE(wm8958_dapm_widgets));
3599 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3600 ARRAY_SIZE(wm8994_lateclk_widgets));
3601 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3602 ARRAY_SIZE(wm8994_adc_widgets));
3603 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3604 ARRAY_SIZE(wm8994_dac_widgets));
3605 break;
3606 }
3607
3608
3609 wm_hubs_add_analogue_routes(codec, 0, 0);
3610 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3611
3612 switch (control->type) {
3613 case WM8994:
3614 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3615 ARRAY_SIZE(wm8994_intercon));
3616
3617 if (wm8994->revision < 4) {
3618 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3619 ARRAY_SIZE(wm8994_revd_intercon));
3620 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3621 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3622 } else {
3623 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3624 ARRAY_SIZE(wm8994_lateclk_intercon));
3625 }
3626 break;
3627 case WM8958:
3628 if (wm8994->revision < 1) {
3629 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3630 ARRAY_SIZE(wm8994_revd_intercon));
3631 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3632 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3633 } else {
3634 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3635 ARRAY_SIZE(wm8994_lateclk_intercon));
3636 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3637 ARRAY_SIZE(wm8958_intercon));
3638 }
3639
3640 wm8958_dsp2_init(codec);
3641 break;
3642 case WM1811:
3643 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3644 ARRAY_SIZE(wm8994_lateclk_intercon));
3645 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3646 ARRAY_SIZE(wm8958_intercon));
3647 break;
3648 }
3649
3650 return 0;
3651
3652 err_irq:
3653 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3654 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3655 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3656 if (wm8994->micdet_irq)
3657 free_irq(wm8994->micdet_irq, wm8994);
3658 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3659 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3660 &wm8994->fll_locked[i]);
3661 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3662 &wm8994->hubs);
3663 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3664 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3665 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3666 err:
3667 kfree(wm8994);
3668 return ret;
3669 }
3670
3671 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3672 {
3673 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3674 struct wm8994 *control = wm8994->wm8994;
3675 int i;
3676
3677 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3678
3679 pm_runtime_disable(codec->dev);
3680
3681 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3682 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3683 &wm8994->fll_locked[i]);
3684
3685 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3686 &wm8994->hubs);
3687 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3688 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3689 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3690
3691 switch (control->type) {
3692 case WM8994:
3693 if (wm8994->micdet_irq)
3694 free_irq(wm8994->micdet_irq, wm8994);
3695 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3696 wm8994);
3697 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3698 wm8994);
3699 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3700 wm8994);
3701 break;
3702
3703 case WM1811:
3704 case WM8958:
3705 if (wm8994->micdet_irq)
3706 free_irq(wm8994->micdet_irq, wm8994);
3707 break;
3708 }
3709 if (wm8994->mbc)
3710 release_firmware(wm8994->mbc);
3711 if (wm8994->mbc_vss)
3712 release_firmware(wm8994->mbc_vss);
3713 if (wm8994->enh_eq)
3714 release_firmware(wm8994->enh_eq);
3715 kfree(wm8994->retune_mobile_texts);
3716 kfree(wm8994->drc_texts);
3717 kfree(wm8994);
3718
3719 return 0;
3720 }
3721
3722 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3723 .probe = wm8994_codec_probe,
3724 .remove = wm8994_codec_remove,
3725 .suspend = wm8994_suspend,
3726 .resume = wm8994_resume,
3727 .read = wm8994_read,
3728 .write = wm8994_write,
3729 .readable_register = wm8994_readable,
3730 .volatile_register = wm8994_volatile,
3731 .set_bias_level = wm8994_set_bias_level,
3732
3733 .reg_cache_size = WM8994_CACHE_SIZE,
3734 .reg_cache_default = wm8994_reg_defaults,
3735 .reg_word_size = 2,
3736 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3737 };
3738
3739 static int __devinit wm8994_probe(struct platform_device *pdev)
3740 {
3741 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3742 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3743 }
3744
3745 static int __devexit wm8994_remove(struct platform_device *pdev)
3746 {
3747 snd_soc_unregister_codec(&pdev->dev);
3748 return 0;
3749 }
3750
3751 static struct platform_driver wm8994_codec_driver = {
3752 .driver = {
3753 .name = "wm8994-codec",
3754 .owner = THIS_MODULE,
3755 },
3756 .probe = wm8994_probe,
3757 .remove = __devexit_p(wm8994_remove),
3758 };
3759
3760 module_platform_driver(wm8994_codec_driver);
3761
3762 MODULE_DESCRIPTION("ASoC WM8994 driver");
3763 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3764 MODULE_LICENSE("GPL");
3765 MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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