sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/initval.h>
  23 #include <sound/soc.h>
  24
  25 #include "davinci-pcm.h"
  26
  27
  28 /*
  29  * NOTE:  terminology here is confusing.
  30  *
  31  *  - This driver supports the "Audio Serial Port" (ASP),
  32  *    found on dm6446, dm355, and other DaVinci chips.
  33  *
  34  *  - But it labels it a "Multi-channel Buffered Serial Port"
  35  *    (McBSP) as on older chips like the dm642 ... which was
  36  *    backward-compatible, possibly explaining that confusion.
  37  *
  38  *  - OMAP chips have a controller called McBSP, which is
  39  *    incompatible with the DaVinci flavor of McBSP.
  40  *
  41  *  - Newer DaVinci chips have a controller called McASP,
  42  *    incompatible with ASP and with either McBSP.
  43  *
  44  * In short:  this uses ASP to implement I2S, not McBSP.
  45  * And it won't be the only DaVinci implemention of I2S.
  46  */
  47 #define DAVINCI_MCBSP_DRR_REG   0x00
  48 #define DAVINCI_MCBSP_DXR_REG   0x04
  49 #define DAVINCI_MCBSP_SPCR_REG  0x08
  50 #define DAVINCI_MCBSP_RCR_REG   0x0c
  51 #define DAVINCI_MCBSP_XCR_REG   0x10
  52 #define DAVINCI_MCBSP_SRGR_REG  0x14
  53 #define DAVINCI_MCBSP_PCR_REG   0x24
  54
  55 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  56 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  57 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  58 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  59 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  60 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  61 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  62
  63 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  64 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  65 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  66 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  67
  68 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  69 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  70 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  71 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  72 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  73
  74 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  75 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  76 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  77
  78 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  79 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  80 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  81 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  82 #define DAVINCI_MCBSP_PCR_SCLKME        (1 << 7)
  83 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  84 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  85 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  86 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  87
  88 enum {
  89         DAVINCI_MCBSP_WORD_8 = 0,
  90         DAVINCI_MCBSP_WORD_12,
  91         DAVINCI_MCBSP_WORD_16,
  92         DAVINCI_MCBSP_WORD_20,
  93         DAVINCI_MCBSP_WORD_24,
  94         DAVINCI_MCBSP_WORD_32,
  95 };
  96
  97 static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
  98         .name = "I2S PCM Stereo out",
  99 };
 100
 101 static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
 102         .name = "I2S PCM Stereo in",
 103 };
 104
 105 struct davinci_mcbsp_dev {
 106         void __iomem                    *base;
 107         u32                             pcr;
 108         struct clk                      *clk;
 109         struct davinci_pcm_dma_params   *dma_params[2];
 110 };
 111
 112 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 113                                            int reg, u32 val)
 114 {
 115         __raw_writel(val, dev->base + reg);
 116 }
 117
 118 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 119 {
 120         return __raw_readl(dev->base + reg);
 121 }
 122
 123 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
 124 {
 125         u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
 126         /* The clock needs to toggle to complete reset.
 127          * So, fake it by toggling the clk polarity.
 128          */
 129         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
 130         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
 131 }
 132
 133 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
 134                 struct snd_pcm_substream *substream)
 135 {
 136         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 137         struct snd_soc_device *socdev = rtd->socdev;
 138         struct snd_soc_platform *platform = socdev->card->platform;
 139         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 140         u32 spcr;
 141         u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
 142         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 143         if (spcr & mask) {
 144                 /* start off disabled */
 145                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 146                                 spcr & ~mask);
 147                 toggle_clock(dev, playback);
 148         }
 149         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
 150                         DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
 151                 /* Start the sample generator */
 152                 spcr |= DAVINCI_MCBSP_SPCR_GRST;
 153                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 154         }
 155
 156         if (playback) {
 157                 /* Stop the DMA to avoid data loss */
 158                 /* while the transmitter is out of reset to handle XSYNCERR */
 159                 if (platform->pcm_ops->trigger) {
 160                         int ret = platform->pcm_ops->trigger(substream,
 161                                 SNDRV_PCM_TRIGGER_STOP);
 162                         if (ret < 0)
 163                                 printk(KERN_DEBUG "Playback DMA stop failed\n");
 164                 }
 165
 166                 /* Enable the transmitter */
 167                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 168                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 169                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 170
 171                 /* wait for any unexpected frame sync error to occur */
 172                 udelay(100);
 173
 174                 /* Disable the transmitter to clear any outstanding XSYNCERR */
 175                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 176                 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
 177                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 178                 toggle_clock(dev, playback);
 179
 180                 /* Restart the DMA */
 181                 if (platform->pcm_ops->trigger) {
 182                         int ret = platform->pcm_ops->trigger(substream,
 183                                 SNDRV_PCM_TRIGGER_START);
 184                         if (ret < 0)
 185                                 printk(KERN_DEBUG "Playback DMA start failed\n");
 186                 }
 187         }
 188
 189         /* Enable transmitter or receiver */
 190         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 191         spcr |= mask;
 192
 193         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
 194                 /* Start frame sync */
 195                 spcr |= DAVINCI_MCBSP_SPCR_FRST;
 196         }
 197         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 198 }
 199
 200 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 201 {
 202         u32 spcr;
 203
 204         /* Reset transmitter/receiver and sample rate/frame sync generators */
 205         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 206         spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
 207         spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
 208         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 209         toggle_clock(dev, playback);
 210 }
 211
 212 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
 213                                struct snd_soc_dai *cpu_dai)
 214 {
 215         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 216         cpu_dai->dma_data = dev->dma_params[substream->stream];
 217         return 0;
 218 }
 219
 220 #define DEFAULT_BITPERSAMPLE    16
 221
 222 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 223                                    unsigned int fmt)
 224 {
 225         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 226         unsigned int pcr;
 227         unsigned int srgr;
 228         unsigned int rcr;
 229         unsigned int xcr;
 230         srgr = DAVINCI_MCBSP_SRGR_FSGM |
 231                 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 232                 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 233
 234         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 235         case SND_SOC_DAIFMT_CBS_CFS:
 236                 /* cpu is master */
 237                 pcr = DAVINCI_MCBSP_PCR_FSXM |
 238                         DAVINCI_MCBSP_PCR_FSRM |
 239                         DAVINCI_MCBSP_PCR_CLKXM |
 240                         DAVINCI_MCBSP_PCR_CLKRM;
 241                 break;
 242         case SND_SOC_DAIFMT_CBM_CFS:
 243                 /* McBSP CLKR pin is the input for the Sample Rate Generator.
 244                  * McBSP FSR and FSX are driven by the Sample Rate Generator. */
 245                 pcr = DAVINCI_MCBSP_PCR_SCLKME |
 246                         DAVINCI_MCBSP_PCR_FSXM |
 247                         DAVINCI_MCBSP_PCR_FSRM;
 248                 break;
 249         case SND_SOC_DAIFMT_CBM_CFM:
 250                 /* codec is master */
 251                 pcr = 0;
 252                 break;
 253         default:
 254                 printk(KERN_ERR "%s:bad master\n", __func__);
 255                 return -EINVAL;
 256         }
 257
 258         rcr = DAVINCI_MCBSP_RCR_RFRLEN1(1);
 259         xcr = DAVINCI_MCBSP_XCR_XFIG | DAVINCI_MCBSP_XCR_XFRLEN1(1);
 260         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 261         case SND_SOC_DAIFMT_DSP_B:
 262                 break;
 263         case SND_SOC_DAIFMT_I2S:
 264                 /* Davinci doesn't support TRUE I2S, but some codecs will have
 265                  * the left and right channels contiguous. This allows
 266                  * dsp_a mode to be used with an inverted normal frame clk.
 267                  * If your codec is master and does not have contiguous
 268                  * channels, then you will have sound on only one channel.
 269                  * Try using a different mode, or codec as slave.
 270                  *
 271                  * The TLV320AIC33 is an example of a codec where this works.
 272                  * It has a variable bit clock frequency allowing it to have
 273                  * valid data on every bit clock.
 274                  *
 275                  * The TLV320AIC23 is an example of a codec where this does not
 276                  * work. It has a fixed bit clock frequency with progressively
 277                  * more empty bit clock slots between channels as the sample
 278                  * rate is lowered.
 279                  */
 280                 fmt ^= SND_SOC_DAIFMT_NB_IF;
 281         case SND_SOC_DAIFMT_DSP_A:
 282                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
 283                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
 284                 break;
 285         default:
 286                 printk(KERN_ERR "%s:bad format\n", __func__);
 287                 return -EINVAL;
 288         }
 289
 290         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 291         case SND_SOC_DAIFMT_NB_NF:
 292                 /* CLKRP Receive clock polarity,
 293                  *      1 - sampled on rising edge of CLKR
 294                  *      valid on rising edge
 295                  * CLKXP Transmit clock polarity,
 296                  *      1 - clocked on falling edge of CLKX
 297                  *      valid on rising edge
 298                  * FSRP  Receive frame sync pol, 0 - active high
 299                  * FSXP  Transmit frame sync pol, 0 - active high
 300                  */
 301                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
 302                 break;
 303         case SND_SOC_DAIFMT_IB_IF:
 304                 /* CLKRP Receive clock polarity,
 305                  *      0 - sampled on falling edge of CLKR
 306                  *      valid on falling edge
 307                  * CLKXP Transmit clock polarity,
 308                  *      0 - clocked on rising edge of CLKX
 309                  *      valid on falling edge
 310                  * FSRP  Receive frame sync pol, 1 - active low
 311                  * FSXP  Transmit frame sync pol, 1 - active low
 312                  */
 313                 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 314                 break;
 315         case SND_SOC_DAIFMT_NB_IF:
 316                 /* CLKRP Receive clock polarity,
 317                  *      1 - sampled on rising edge of CLKR
 318                  *      valid on rising edge
 319                  * CLKXP Transmit clock polarity,
 320                  *      1 - clocked on falling edge of CLKX
 321                  *      valid on rising edge
 322                  * FSRP  Receive frame sync pol, 1 - active low
 323                  * FSXP  Transmit frame sync pol, 1 - active low
 324                  */
 325                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
 326                         DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 327                 break;
 328         case SND_SOC_DAIFMT_IB_NF:
 329                 /* CLKRP Receive clock polarity,
 330                  *      0 - sampled on falling edge of CLKR
 331                  *      valid on falling edge
 332                  * CLKXP Transmit clock polarity,
 333                  *      0 - clocked on rising edge of CLKX
 334                  *      valid on falling edge
 335                  * FSRP  Receive frame sync pol, 0 - active high
 336                  * FSXP  Transmit frame sync pol, 0 - active high
 337                  */
 338                 break;
 339         default:
 340                 return -EINVAL;
 341         }
 342         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 343         dev->pcr = pcr;
 344         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
 345         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 346         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 347         return 0;
 348 }
 349
 350 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 351                                  struct snd_pcm_hw_params *params,
 352                                  struct snd_soc_dai *dai)
 353 {
 354         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 355         struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
 356         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 357         struct snd_interval *i = NULL;
 358         int mcbsp_word_length;
 359         unsigned int rcr, xcr, srgr;
 360         u32 spcr;
 361
 362         /* general line settings */
 363         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 364         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 365                 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 366                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 367         } else {
 368                 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 369                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 370         }
 371
 372         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 373         srgr = DAVINCI_MCBSP_SRGR_FSGM;
 374         srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 375
 376         i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 377         srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
 378         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 379
 380         /* Determine xfer data type */
 381         switch (params_format(params)) {
 382         case SNDRV_PCM_FORMAT_S8:
 383                 dma_params->data_type = 1;
 384                 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
 385                 break;
 386         case SNDRV_PCM_FORMAT_S16_LE:
 387                 dma_params->data_type = 2;
 388                 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
 389                 break;
 390         case SNDRV_PCM_FORMAT_S32_LE:
 391                 dma_params->data_type = 4;
 392                 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
 393                 break;
 394         default:
 395                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
 396                 return -EINVAL;
 397         }
 398
 399         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 400                 rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
 401                 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 402                                DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 403                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 404
 405         } else {
 406                 xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
 407                 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 408                                 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 409                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 410
 411         }
 412         return 0;
 413 }
 414
 415 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 416                                struct snd_soc_dai *dai)
 417 {
 418         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 419         struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
 420         int ret = 0;
 421         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 422
 423         switch (cmd) {
 424         case SNDRV_PCM_TRIGGER_START:
 425         case SNDRV_PCM_TRIGGER_RESUME:
 426         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 427                 davinci_mcbsp_start(dev, substream);
 428                 break;
 429         case SNDRV_PCM_TRIGGER_STOP:
 430         case SNDRV_PCM_TRIGGER_SUSPEND:
 431         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 432                 davinci_mcbsp_stop(dev, playback);
 433                 break;
 434         default:
 435                 ret = -EINVAL;
 436         }
 437
 438         return ret;
 439 }
 440
 441 static int davinci_i2s_probe(struct platform_device *pdev,
 442                              struct snd_soc_dai *dai)
 443 {
 444         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 445         struct snd_soc_card *card = socdev->card;
 446         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 447         struct davinci_mcbsp_dev *dev;
 448         struct resource *mem, *ioarea;
 449         struct evm_snd_platform_data *pdata;
 450         int ret;
 451
 452         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 453         if (!mem) {
 454                 dev_err(&pdev->dev, "no mem resource?\n");
 455                 return -ENODEV;
 456         }
 457
 458         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 459                                     pdev->name);
 460         if (!ioarea) {
 461                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 462                 return -EBUSY;
 463         }
 464
 465         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 466         if (!dev) {
 467                 ret = -ENOMEM;
 468                 goto err_release_region;
 469         }
 470
 471         cpu_dai->private_data = dev;
 472
 473         dev->clk = clk_get(&pdev->dev, NULL);
 474         if (IS_ERR(dev->clk)) {
 475                 ret = -ENODEV;
 476                 goto err_free_mem;
 477         }
 478         clk_enable(dev->clk);
 479
 480         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 481         pdata = pdev->dev.platform_data;
 482
 483         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
 484         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = pdata->tx_dma_ch;
 485         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
 486             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 487
 488         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
 489         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = pdata->rx_dma_ch;
 490         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
 491             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 492
 493         return 0;
 494
 495 err_free_mem:
 496         kfree(dev);
 497 err_release_region:
 498         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 499
 500         return ret;
 501 }
 502
 503 static void davinci_i2s_remove(struct platform_device *pdev,
 504                                struct snd_soc_dai *dai)
 505 {
 506         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 507         struct snd_soc_card *card = socdev->card;
 508         struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai;
 509         struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 510         struct resource *mem;
 511
 512         clk_disable(dev->clk);
 513         clk_put(dev->clk);
 514         dev->clk = NULL;
 515
 516         kfree(dev);
 517
 518         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 519         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 520 }
 521
 522 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 523
 524 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 525         .startup        = davinci_i2s_startup,
 526         .trigger        = davinci_i2s_trigger,
 527         .hw_params      = davinci_i2s_hw_params,
 528         .set_fmt        = davinci_i2s_set_dai_fmt,
 529 };
 530
 531 struct snd_soc_dai davinci_i2s_dai = {
 532         .name = "davinci-i2s",
 533         .id = 0,
 534         .probe = davinci_i2s_probe,
 535         .remove = davinci_i2s_remove,
 536         .playback = {
 537                 .channels_min = 2,
 538                 .channels_max = 2,
 539                 .rates = DAVINCI_I2S_RATES,
 540                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 541         .capture = {
 542                 .channels_min = 2,
 543                 .channels_max = 2,
 544                 .rates = DAVINCI_I2S_RATES,
 545                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 546         .ops = &davinci_i2s_dai_ops,
 547 };
 548 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
 549
 550 static int __init davinci_i2s_init(void)
 551 {
 552         return snd_soc_register_dai(&davinci_i2s_dai);
 553 }
 554 module_init(davinci_i2s_init);
 555
 556 static void __exit davinci_i2s_exit(void)
 557 {
 558         snd_soc_unregister_dai(&davinci_i2s_dai);
 559 }
 560 module_exit(davinci_i2s_exit);
 561
 562 MODULE_AUTHOR("Vladimir Barinov");
 563 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 564 MODULE_LICENSE("GPL");