sound/soc/intel/skylake/skl-sst-dsp.h

   1 /*
   2  * Skylake SST DSP Support
   3  *
   4  * Copyright (C) 2014-15, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  */
  15
  16 #ifndef __SKL_SST_DSP_H__
  17 #define __SKL_SST_DSP_H__
  18
  19 #include <linux/interrupt.h>
  20 #include <sound/memalloc.h>
  21 #include "skl-sst-cldma.h"
  22
  23 struct sst_dsp;
  24 struct skl_sst;
  25 struct sst_dsp_device;
  26
  27 /* Intel HD Audio General DSP Registers */
  28 #define SKL_ADSP_GEN_BASE               0x0
  29 #define SKL_ADSP_REG_ADSPCS             (SKL_ADSP_GEN_BASE + 0x04)
  30 #define SKL_ADSP_REG_ADSPIC             (SKL_ADSP_GEN_BASE + 0x08)
  31 #define SKL_ADSP_REG_ADSPIS             (SKL_ADSP_GEN_BASE + 0x0C)
  32 #define SKL_ADSP_REG_ADSPIC2            (SKL_ADSP_GEN_BASE + 0x10)
  33 #define SKL_ADSP_REG_ADSPIS2            (SKL_ADSP_GEN_BASE + 0x14)
  34
  35 /* Intel HD Audio Inter-Processor Communication Registers */
  36 #define SKL_ADSP_IPC_BASE               0x40
  37 #define SKL_ADSP_REG_HIPCT              (SKL_ADSP_IPC_BASE + 0x00)
  38 #define SKL_ADSP_REG_HIPCTE             (SKL_ADSP_IPC_BASE + 0x04)
  39 #define SKL_ADSP_REG_HIPCI              (SKL_ADSP_IPC_BASE + 0x08)
  40 #define SKL_ADSP_REG_HIPCIE             (SKL_ADSP_IPC_BASE + 0x0C)
  41 #define SKL_ADSP_REG_HIPCCTL            (SKL_ADSP_IPC_BASE + 0x10)
  42
  43 /*  HIPCI */
  44 #define SKL_ADSP_REG_HIPCI_BUSY         BIT(31)
  45
  46 /* HIPCIE */
  47 #define SKL_ADSP_REG_HIPCIE_DONE        BIT(30)
  48
  49 /* HIPCCTL */
  50 #define SKL_ADSP_REG_HIPCCTL_DONE       BIT(1)
  51 #define SKL_ADSP_REG_HIPCCTL_BUSY       BIT(0)
  52
  53 /* HIPCT */
  54 #define SKL_ADSP_REG_HIPCT_BUSY         BIT(31)
  55
  56 /* FW base IDs */
  57 #define SKL_INSTANCE_ID                 0
  58 #define SKL_BASE_FW_MODULE_ID           0
  59
  60 /* Intel HD Audio SRAM Window 1 */
  61 #define SKL_ADSP_SRAM1_BASE             0xA000
  62
  63 #define SKL_ADSP_MMIO_LEN               0x10000
  64
  65 #define SKL_ADSP_W0_STAT_SZ             0x1000
  66
  67 #define SKL_ADSP_W0_UP_SZ               0x1000
  68
  69 #define SKL_ADSP_W1_SZ                  0x1000
  70
  71 #define SKL_FW_STS_MASK                 0xf
  72
  73 #define SKL_FW_INIT                     0x1
  74 #define SKL_FW_RFW_START                0xf
  75
  76 #define SKL_ADSPIC_IPC                  1
  77 #define SKL_ADSPIS_IPC                  1
  78
  79 /* ADSPCS - Audio DSP Control & Status */
  80 #define SKL_DSP_CORES           1
  81 #define SKL_DSP_CORE0_MASK      1
  82 #define SKL_DSP_CORES_MASK      ((1 << SKL_DSP_CORES) - 1)
  83
  84 /* Core Reset - asserted high */
  85 #define SKL_ADSPCS_CRST_SHIFT   0
  86 #define SKL_ADSPCS_CRST_MASK    (SKL_DSP_CORES_MASK << SKL_ADSPCS_CRST_SHIFT)
  87 #define SKL_ADSPCS_CRST(x)      ((x << SKL_ADSPCS_CRST_SHIFT) & SKL_ADSPCS_CRST_MASK)
  88
  89 /* Core run/stall - when set to '1' core is stalled */
  90 #define SKL_ADSPCS_CSTALL_SHIFT 8
  91 #define SKL_ADSPCS_CSTALL_MASK  (SKL_DSP_CORES_MASK <<  \
  92                                         SKL_ADSPCS_CSTALL_SHIFT)
  93 #define SKL_ADSPCS_CSTALL(x)    ((x << SKL_ADSPCS_CSTALL_SHIFT) &       \
  94                                 SKL_ADSPCS_CSTALL_MASK)
  95
  96 /* Set Power Active - when set to '1' turn cores on */
  97 #define SKL_ADSPCS_SPA_SHIFT    16
  98 #define SKL_ADSPCS_SPA_MASK     (SKL_DSP_CORES_MASK << SKL_ADSPCS_SPA_SHIFT)
  99 #define SKL_ADSPCS_SPA(x)       ((x << SKL_ADSPCS_SPA_SHIFT) & SKL_ADSPCS_SPA_MASK)
 100
 101 /* Current Power Active - power status of cores, set by hardware */
 102 #define SKL_ADSPCS_CPA_SHIFT    24
 103 #define SKL_ADSPCS_CPA_MASK     (SKL_DSP_CORES_MASK << SKL_ADSPCS_CPA_SHIFT)
 104 #define SKL_ADSPCS_CPA(x)       ((x << SKL_ADSPCS_CPA_SHIFT) & SKL_ADSPCS_CPA_MASK)
 105
 106 #define SST_DSP_POWER_D0        0x0  /* full On */
 107 #define SST_DSP_POWER_D3        0x3  /* Off */
 108
 109 enum skl_dsp_states {
 110         SKL_DSP_RUNNING = 1,
 111         SKL_DSP_RESET,
 112 };
 113
 114 struct skl_dsp_fw_ops {
 115         int (*load_fw)(struct sst_dsp  *ctx);
 116         /* FW module parser/loader */
 117         int (*parse_fw)(struct sst_dsp *ctx);
 118         int (*set_state_D0)(struct sst_dsp *ctx);
 119         int (*set_state_D3)(struct sst_dsp *ctx);
 120         unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
 121         int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
 122         int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
 123
 124 };
 125
 126 struct skl_dsp_loader_ops {
 127         int stream_tag;
 128
 129         int (*alloc_dma_buf)(struct device *dev,
 130                 struct snd_dma_buffer *dmab, size_t size);
 131         int (*free_dma_buf)(struct device *dev,
 132                 struct snd_dma_buffer *dmab);
 133         int (*prepare)(struct device *dev, unsigned int format,
 134                                 unsigned int byte_size,
 135                                 struct snd_dma_buffer *bufp);
 136         int (*trigger)(struct device *dev, bool start, int stream_tag);
 137
 138         int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
 139                                  int stream_tag);
 140 };
 141
 142 struct skl_load_module_info {
 143         u16 mod_id;
 144         const struct firmware *fw;
 145 };
 146
 147 struct skl_module_table {
 148         struct skl_load_module_info *mod_info;
 149         unsigned int usage_cnt;
 150         struct list_head list;
 151 };
 152
 153 void skl_cldma_process_intr(struct sst_dsp *ctx);
 154 void skl_cldma_int_disable(struct sst_dsp *ctx);
 155 int skl_cldma_prepare(struct sst_dsp *ctx);
 156
 157 void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
 158 struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
 159                 struct sst_dsp_device *sst_dev, int irq);
 160 int skl_dsp_enable_core(struct sst_dsp *ctx);
 161 int skl_dsp_disable_core(struct sst_dsp *ctx);
 162 bool is_skl_dsp_running(struct sst_dsp *ctx);
 163 irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
 164 int skl_dsp_wake(struct sst_dsp *ctx);
 165 int skl_dsp_sleep(struct sst_dsp *ctx);
 166 void skl_dsp_free(struct sst_dsp *dsp);
 167
 168 int skl_dsp_boot(struct sst_dsp *ctx);
 169 int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 170                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 171                 struct skl_sst **dsp);
 172 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
 173                 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
 174                 struct skl_sst **dsp);
 175 void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 176 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
 177
 178 #endif /*__SKL_SST_DSP_H__*/