sound/soc/mxs/mxs-saif.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <mach/dma.h>
  31 #include <asm/mach-types.h>
  32 #include <mach/hardware.h>
  33 #include <mach/mxs.h>
  34
  35 #include "mxs-saif.h"
  36
  37 static struct mxs_saif *mxs_saif[2];
  38
  39 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  40                         int clk_id, unsigned int freq, int dir)
  41 {
  42         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
  43
  44         switch (clk_id) {
  45         case MXS_SAIF_MCLK:
  46                 saif->mclk = freq;
  47                 break;
  48         default:
  49                 return -EINVAL;
  50         }
  51         return 0;
  52 }
  53
  54 /*
  55  * Set SAIF clock and MCLK
  56  */
  57 static int mxs_saif_set_clk(struct mxs_saif *saif,
  58                                   unsigned int mclk,
  59                                   unsigned int rate)
  60 {
  61         u32 scr;
  62         int ret;
  63
  64         scr = __raw_readl(saif->base + SAIF_CTRL);
  65         scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
  66         scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  67
  68         /*
  69          * Set SAIF clock
  70          *
  71          * The SAIF clock should be either 384*fs or 512*fs.
  72          * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
  73          *  For 32x mclk, set saif clk as 512*fs.
  74          *  For 48x mclk, set saif clk as 384*fs.
  75          *
  76          * If MCLK is not used, we just set saif clk to 512*fs.
  77          */
  78         if (saif->mclk_in_use) {
  79                 if (mclk % 32 == 0) {
  80                         scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  81                         ret = clk_set_rate(saif->clk, 512 * rate);
  82                 } else if (mclk % 48 == 0) {
  83                         scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
  84                         ret = clk_set_rate(saif->clk, 384 * rate);
  85                 } else {
  86                         /* SAIF MCLK should be either 32x or 48x */
  87                         return -EINVAL;
  88                 }
  89         } else {
  90                 ret = clk_set_rate(saif->clk, 512 * rate);
  91                 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
  92         }
  93
  94         if (ret)
  95                 return ret;
  96
  97         if (!saif->mclk_in_use) {
  98                 __raw_writel(scr, saif->base + SAIF_CTRL);
  99                 return 0;
 100         }
 101
 102         /*
 103          * Program the over-sample rate for MCLK output
 104          *
 105          * The available MCLK range is 32x, 48x... 512x. The rate
 106          * could be from 8kHz to 192kH.
 107          */
 108         switch (mclk / rate) {
 109         case 32:
 110                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
 111                 break;
 112         case 64:
 113                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
 114                 break;
 115         case 128:
 116                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
 117                 break;
 118         case 256:
 119                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
 120                 break;
 121         case 512:
 122                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
 123                 break;
 124         case 48:
 125                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
 126                 break;
 127         case 96:
 128                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
 129                 break;
 130         case 192:
 131                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
 132                 break;
 133         case 384:
 134                 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139
 140         __raw_writel(scr, saif->base + SAIF_CTRL);
 141
 142         return 0;
 143 }
 144
 145 /*
 146  * Put and disable MCLK.
 147  */
 148 int mxs_saif_put_mclk(unsigned int saif_id)
 149 {
 150         struct mxs_saif *saif = mxs_saif[saif_id];
 151         u32 stat;
 152
 153         if (!saif)
 154                 return -EINVAL;
 155
 156         stat = __raw_readl(saif->base + SAIF_STAT);
 157         if (stat & BM_SAIF_STAT_BUSY) {
 158                 dev_err(saif->dev, "error: busy\n");
 159                 return -EBUSY;
 160         }
 161
 162         clk_disable(saif->clk);
 163
 164         /* disable MCLK output */
 165         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 166                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 167         __raw_writel(BM_SAIF_CTRL_RUN,
 168                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 169
 170         saif->mclk_in_use = 0;
 171         return 0;
 172 }
 173
 174 /*
 175  * Get MCLK and set clock rate, then enable it
 176  *
 177  * This interface is used for codecs who are using MCLK provided
 178  * by saif.
 179  */
 180 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
 181                                         unsigned int rate)
 182 {
 183         struct mxs_saif *saif = mxs_saif[saif_id];
 184         u32 stat;
 185         int ret;
 186
 187         if (!saif)
 188                 return -EINVAL;
 189
 190         stat = __raw_readl(saif->base + SAIF_STAT);
 191         if (stat & BM_SAIF_STAT_BUSY) {
 192                 dev_err(saif->dev, "error: busy\n");
 193                 return -EBUSY;
 194         }
 195
 196         /* Clear Reset */
 197         __raw_writel(BM_SAIF_CTRL_SFTRST,
 198                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 199
 200         saif->mclk_in_use = 1;
 201         ret = mxs_saif_set_clk(saif, mclk, rate);
 202         if (ret)
 203                 return ret;
 204
 205         ret = clk_enable(saif->clk);
 206         if (ret)
 207                 return ret;
 208
 209         /* enable MCLK output */
 210         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 211                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 212         __raw_writel(BM_SAIF_CTRL_RUN,
 213                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 214
 215         return 0;
 216 }
 217
 218 /*
 219  * SAIF DAI format configuration.
 220  * Should only be called when port is inactive.
 221  */
 222 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 223 {
 224         u32 scr, stat;
 225         u32 scr0;
 226         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 227
 228         stat = __raw_readl(saif->base + SAIF_STAT);
 229         if (stat & BM_SAIF_STAT_BUSY) {
 230                 dev_err(cpu_dai->dev, "error: busy\n");
 231                 return -EBUSY;
 232         }
 233
 234         scr0 = __raw_readl(saif->base + SAIF_CTRL);
 235         scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
 236                 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
 237         scr = 0;
 238
 239         /* DAI mode */
 240         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 241         case SND_SOC_DAIFMT_I2S:
 242                 /* data frame low 1clk before data */
 243                 scr |= BM_SAIF_CTRL_DELAY;
 244                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 245                 break;
 246         case SND_SOC_DAIFMT_LEFT_J:
 247                 /* data frame high with data */
 248                 scr &= ~BM_SAIF_CTRL_DELAY;
 249                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 250                 scr &= ~BM_SAIF_CTRL_JUSTIFY;
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         /* DAI clock inversion */
 257         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 258         case SND_SOC_DAIFMT_IB_IF:
 259                 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
 260                 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
 261                 break;
 262         case SND_SOC_DAIFMT_IB_NF:
 263                 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
 264                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 265                 break;
 266         case SND_SOC_DAIFMT_NB_IF:
 267                 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
 268                 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
 269                 break;
 270         case SND_SOC_DAIFMT_NB_NF:
 271                 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
 272                 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
 273                 break;
 274         }
 275
 276         /*
 277          * Note: We simply just support master mode since SAIF TX can only
 278          * work as master.
 279          */
 280         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 281         case SND_SOC_DAIFMT_CBS_CFS:
 282                 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
 283                 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
 284                 break;
 285         default:
 286                 return -EINVAL;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int mxs_saif_startup(struct snd_pcm_substream *substream,
 293                            struct snd_soc_dai *cpu_dai)
 294 {
 295         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 296         snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
 297
 298         /* clear error status to 0 for each re-open */
 299         saif->fifo_underrun = 0;
 300         saif->fifo_overrun = 0;
 301
 302         /* Clear Reset for normal operations */
 303         __raw_writel(BM_SAIF_CTRL_SFTRST,
 304                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Should only be called when port is inactive.
 311  * although can be called multiple times by upper layers.
 312  */
 313 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
 314                              struct snd_pcm_hw_params *params,
 315                              struct snd_soc_dai *cpu_dai)
 316 {
 317         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 318         u32 scr, stat;
 319         int ret;
 320
 321         /* mclk should already be set */
 322         if (!saif->mclk && saif->mclk_in_use) {
 323                 dev_err(cpu_dai->dev, "set mclk first\n");
 324                 return -EINVAL;
 325         }
 326
 327         stat = __raw_readl(saif->base + SAIF_STAT);
 328         if (stat & BM_SAIF_STAT_BUSY) {
 329                 dev_err(cpu_dai->dev, "error: busy\n");
 330                 return -EBUSY;
 331         }
 332
 333         /*
 334          * Set saif clk based on sample rate.
 335          * If mclk is used, we also set mclk, if not, saif->mclk is
 336          * default 0, means not used.
 337          */
 338         ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
 339         if (ret) {
 340                 dev_err(cpu_dai->dev, "unable to get proper clk\n");
 341                 return ret;
 342         }
 343
 344         scr = __raw_readl(saif->base + SAIF_CTRL);
 345
 346         scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
 347         scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 348         switch (params_format(params)) {
 349         case SNDRV_PCM_FORMAT_S16_LE:
 350                 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
 351                 break;
 352         case SNDRV_PCM_FORMAT_S20_3LE:
 353                 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
 354                 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 355                 break;
 356         case SNDRV_PCM_FORMAT_S24_LE:
 357                 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
 358                 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
 359                 break;
 360         default:
 361                 return -EINVAL;
 362         }
 363
 364         /* Tx/Rx config */
 365         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 366                 /* enable TX mode */
 367                 scr &= ~BM_SAIF_CTRL_READ_MODE;
 368         } else {
 369                 /* enable RX mode */
 370                 scr |= BM_SAIF_CTRL_READ_MODE;
 371         }
 372
 373         __raw_writel(scr, saif->base + SAIF_CTRL);
 374         return 0;
 375 }
 376
 377 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
 378                            struct snd_soc_dai *cpu_dai)
 379 {
 380         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 381
 382         /* clear clock gate */
 383         __raw_writel(BM_SAIF_CTRL_CLKGATE,
 384                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 385
 386         /* enable FIFO error irqs */
 387         __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
 388                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 389
 390         return 0;
 391 }
 392
 393 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
 394                                 struct snd_soc_dai *cpu_dai)
 395 {
 396         struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
 397
 398         switch (cmd) {
 399         case SNDRV_PCM_TRIGGER_START:
 400         case SNDRV_PCM_TRIGGER_RESUME:
 401         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 402                 dev_dbg(cpu_dai->dev, "start\n");
 403
 404                 clk_enable(saif->clk);
 405                 if (!saif->mclk_in_use)
 406                         __raw_writel(BM_SAIF_CTRL_RUN,
 407                                 saif->base + SAIF_CTRL + MXS_SET_ADDR);
 408
 409                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 410                         /*
 411                          * write a data to saif data register to trigger
 412                          * the transfer
 413                          */
 414                         __raw_writel(0, saif->base + SAIF_DATA);
 415                 } else {
 416                         /*
 417                          * read a data from saif data register to trigger
 418                          * the receive
 419                          */
 420                         __raw_readl(saif->base + SAIF_DATA);
 421                 }
 422
 423                 dev_dbg(cpu_dai->dev, "CTRL 0x%x STAT 0x%x\n",
 424                         __raw_readl(saif->base + SAIF_CTRL),
 425                         __raw_readl(saif->base + SAIF_STAT));
 426
 427                 break;
 428         case SNDRV_PCM_TRIGGER_SUSPEND:
 429         case SNDRV_PCM_TRIGGER_STOP:
 430         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 431                 dev_dbg(cpu_dai->dev, "stop\n");
 432
 433                 clk_disable(saif->clk);
 434                 if (!saif->mclk_in_use)
 435                         __raw_writel(BM_SAIF_CTRL_RUN,
 436                                 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
 437
 438                 break;
 439         default:
 440                 return -EINVAL;
 441         }
 442
 443         return 0;
 444 }
 445
 446 #define MXS_SAIF_RATES          SNDRV_PCM_RATE_8000_192000
 447 #define MXS_SAIF_FORMATS \
 448         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
 449         SNDRV_PCM_FMTBIT_S24_LE)
 450
 451 static struct snd_soc_dai_ops mxs_saif_dai_ops = {
 452         .startup = mxs_saif_startup,
 453         .trigger = mxs_saif_trigger,
 454         .prepare = mxs_saif_prepare,
 455         .hw_params = mxs_saif_hw_params,
 456         .set_sysclk = mxs_saif_set_dai_sysclk,
 457         .set_fmt = mxs_saif_set_dai_fmt,
 458 };
 459
 460 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
 461 {
 462         struct mxs_saif *saif = dev_get_drvdata(dai->dev);
 463
 464         snd_soc_dai_set_drvdata(dai, saif);
 465
 466         return 0;
 467 }
 468
 469 static struct snd_soc_dai_driver mxs_saif_dai = {
 470         .name = "mxs-saif",
 471         .probe = mxs_saif_dai_probe,
 472         .playback = {
 473                 .channels_min = 2,
 474                 .channels_max = 2,
 475                 .rates = MXS_SAIF_RATES,
 476                 .formats = MXS_SAIF_FORMATS,
 477         },
 478         .capture = {
 479                 .channels_min = 2,
 480                 .channels_max = 2,
 481                 .rates = MXS_SAIF_RATES,
 482                 .formats = MXS_SAIF_FORMATS,
 483         },
 484         .ops = &mxs_saif_dai_ops,
 485 };
 486
 487 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
 488 {
 489         struct mxs_saif *saif = dev_id;
 490         unsigned int stat;
 491
 492         stat = __raw_readl(saif->base + SAIF_STAT);
 493         if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
 494                         BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
 495                 return IRQ_NONE;
 496
 497         if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
 498                 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
 499                 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
 500                                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
 501         }
 502
 503         if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
 504                 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
 505                 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
 506                                 saif->base + SAIF_STAT + MXS_CLR_ADDR);
 507         }
 508
 509         dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
 510                __raw_readl(saif->base + SAIF_CTRL),
 511                __raw_readl(saif->base + SAIF_STAT));
 512
 513         return IRQ_HANDLED;
 514 }
 515
 516 static int mxs_saif_probe(struct platform_device *pdev)
 517 {
 518         struct resource *res;
 519         struct mxs_saif *saif;
 520         int ret = 0;
 521
 522         saif = kzalloc(sizeof(*saif), GFP_KERNEL);
 523         if (!saif)
 524                 return -ENOMEM;
 525
 526         if (pdev->id >= ARRAY_SIZE(mxs_saif))
 527                 return -EINVAL;
 528         mxs_saif[pdev->id] = saif;
 529
 530         saif->clk = clk_get(&pdev->dev, NULL);
 531         if (IS_ERR(saif->clk)) {
 532                 ret = PTR_ERR(saif->clk);
 533                 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
 534                         ret);
 535                 goto failed_clk;
 536         }
 537
 538         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 539         if (!res) {
 540                 ret = -ENODEV;
 541                 dev_err(&pdev->dev, "failed to get io resource: %d\n",
 542                         ret);
 543                 goto failed_get_resource;
 544         }
 545
 546         if (!request_mem_region(res->start, resource_size(res), "mxs-saif")) {
 547                 dev_err(&pdev->dev, "request_mem_region failed\n");
 548                 ret = -EBUSY;
 549                 goto failed_get_resource;
 550         }
 551
 552         saif->base = ioremap(res->start, resource_size(res));
 553         if (!saif->base) {
 554                 dev_err(&pdev->dev, "ioremap failed\n");
 555                 ret = -ENODEV;
 556                 goto failed_ioremap;
 557         }
 558
 559         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 560         if (!res) {
 561                 ret = -ENODEV;
 562                 dev_err(&pdev->dev, "failed to get dma resource: %d\n",
 563                         ret);
 564                 goto failed_ioremap;
 565         }
 566         saif->dma_param.chan_num = res->start;
 567
 568         saif->irq = platform_get_irq(pdev, 0);
 569         if (saif->irq < 0) {
 570                 ret = saif->irq;
 571                 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
 572                         ret);
 573                 goto failed_get_irq1;
 574         }
 575
 576         saif->dev = &pdev->dev;
 577         ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
 578         if (ret) {
 579                 dev_err(&pdev->dev, "failed to request irq\n");
 580                 goto failed_get_irq1;
 581         }
 582
 583         saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
 584         if (saif->dma_param.chan_irq < 0) {
 585                 ret = saif->dma_param.chan_irq;
 586                 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
 587                         ret);
 588                 goto failed_get_irq2;
 589         }
 590
 591         platform_set_drvdata(pdev, saif);
 592
 593         ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
 594         if (ret) {
 595                 dev_err(&pdev->dev, "register DAI failed\n");
 596                 goto failed_register;
 597         }
 598
 599         saif->soc_platform_pdev = platform_device_alloc(
 600                                         "mxs-pcm-audio", pdev->id);
 601         if (!saif->soc_platform_pdev) {
 602                 ret = -ENOMEM;
 603                 goto failed_pdev_alloc;
 604         }
 605
 606         platform_set_drvdata(saif->soc_platform_pdev, saif);
 607         ret = platform_device_add(saif->soc_platform_pdev);
 608         if (ret) {
 609                 dev_err(&pdev->dev, "failed to add soc platform device\n");
 610                 goto failed_pdev_add;
 611         }
 612
 613         return 0;
 614
 615 failed_pdev_add:
 616         platform_device_put(saif->soc_platform_pdev);
 617 failed_pdev_alloc:
 618         snd_soc_unregister_dai(&pdev->dev);
 619 failed_register:
 620 failed_get_irq2:
 621         free_irq(saif->irq, saif);
 622 failed_get_irq1:
 623         iounmap(saif->base);
 624 failed_ioremap:
 625         release_mem_region(res->start, resource_size(res));
 626 failed_get_resource:
 627         clk_put(saif->clk);
 628 failed_clk:
 629         kfree(saif);
 630
 631         return ret;
 632 }
 633
 634 static int __devexit mxs_saif_remove(struct platform_device *pdev)
 635 {
 636         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 637         struct mxs_saif *saif = platform_get_drvdata(pdev);
 638
 639         platform_device_unregister(saif->soc_platform_pdev);
 640
 641         snd_soc_unregister_dai(&pdev->dev);
 642
 643         iounmap(saif->base);
 644         release_mem_region(res->start, resource_size(res));
 645         free_irq(saif->irq, saif);
 646
 647         clk_put(saif->clk);
 648         kfree(saif);
 649
 650         return 0;
 651 }
 652
 653 static struct platform_driver mxs_saif_driver = {
 654         .probe = mxs_saif_probe,
 655         .remove = __devexit_p(mxs_saif_remove),
 656
 657         .driver = {
 658                 .name = "mxs-saif",
 659                 .owner = THIS_MODULE,
 660         },
 661 };
 662
 663 static int __init mxs_saif_init(void)
 664 {
 665         return platform_driver_register(&mxs_saif_driver);
 666 }
 667
 668 static void __exit mxs_saif_exit(void)
 669 {
 670         platform_driver_unregister(&mxs_saif_driver);
 671 }
 672
 673 module_init(mxs_saif_init);
 674 module_exit(mxs_saif_exit);
 675 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 676 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
 677 MODULE_LICENSE("GPL");