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ASoC: fsi: remove SH_FSI_xxx_INV flags
[deliverable/linux.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/io.h>
19 #include <linux/scatterlist.h>
20 #include <linux/sh_dma.h>
21 #include <linux/slab.h>
22 #include <linux/module.h>
23 #include <linux/workqueue.h>
24 #include <sound/soc.h>
25 #include <sound/pcm_params.h>
26 #include <sound/sh_fsi.h>
27
28 /* PortA/PortB register */
29 #define REG_DO_FMT 0x0000
30 #define REG_DOFF_CTL 0x0004
31 #define REG_DOFF_ST 0x0008
32 #define REG_DI_FMT 0x000C
33 #define REG_DIFF_CTL 0x0010
34 #define REG_DIFF_ST 0x0014
35 #define REG_CKG1 0x0018
36 #define REG_CKG2 0x001C
37 #define REG_DIDT 0x0020
38 #define REG_DODT 0x0024
39 #define REG_MUTE_ST 0x0028
40 #define REG_OUT_DMAC 0x002C
41 #define REG_OUT_SEL 0x0030
42 #define REG_IN_DMAC 0x0038
43
44 /* master register */
45 #define MST_CLK_RST 0x0210
46 #define MST_SOFT_RST 0x0214
47 #define MST_FIFO_SZ 0x0218
48
49 /* core register (depend on FSI version) */
50 #define A_MST_CTLR 0x0180
51 #define B_MST_CTLR 0x01A0
52 #define CPU_INT_ST 0x01F4
53 #define CPU_IEMSK 0x01F8
54 #define CPU_IMSK 0x01FC
55 #define INT_ST 0x0200
56 #define IEMSK 0x0204
57 #define IMSK 0x0208
58
59 /* DO_FMT */
60 /* DI_FMT */
61 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
62 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
63 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
64 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
65
66 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
67 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
68 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
69
70 #define CR_MONO (0x0 << 4)
71 #define CR_MONO_D (0x1 << 4)
72 #define CR_PCM (0x2 << 4)
73 #define CR_I2S (0x3 << 4)
74 #define CR_TDM (0x4 << 4)
75 #define CR_TDM_D (0x5 << 4)
76
77 /* OUT_DMAC */
78 /* IN_DMAC */
79 #define VDMD_MASK (0x3 << 4)
80 #define VDMD_FRONT (0x0 << 4) /* Package in front */
81 #define VDMD_BACK (0x1 << 4) /* Package in back */
82 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
83
84 #define DMA_ON (0x1 << 0)
85
86 /* DOFF_CTL */
87 /* DIFF_CTL */
88 #define IRQ_HALF 0x00100000
89 #define FIFO_CLR 0x00000001
90
91 /* DOFF_ST */
92 #define ERR_OVER 0x00000010
93 #define ERR_UNDER 0x00000001
94 #define ST_ERR (ERR_OVER | ERR_UNDER)
95
96 /* CKG1 */
97 #define ACKMD_MASK 0x00007000
98 #define BPFMD_MASK 0x00000700
99 #define DIMD (1 << 4)
100 #define DOMD (1 << 0)
101
102 /* A/B MST_CTLR */
103 #define BP (1 << 4) /* Fix the signal of Biphase output */
104 #define SE (1 << 0) /* Fix the master clock */
105
106 /* CLK_RST */
107 #define CRB (1 << 4)
108 #define CRA (1 << 0)
109
110 /* IO SHIFT / MACRO */
111 #define BI_SHIFT 12
112 #define BO_SHIFT 8
113 #define AI_SHIFT 4
114 #define AO_SHIFT 0
115 #define AB_IO(param, shift) (param << shift)
116
117 /* SOFT_RST */
118 #define PBSR (1 << 12) /* Port B Software Reset */
119 #define PASR (1 << 8) /* Port A Software Reset */
120 #define IR (1 << 4) /* Interrupt Reset */
121 #define FSISR (1 << 0) /* Software Reset */
122
123 /* OUT_SEL (FSI2) */
124 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
125 /* 1: Biphase and serial */
126
127 /* FIFO_SZ */
128 #define FIFO_SZ_MASK 0x7
129
130 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
131
132 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
133
134 /*
135 * bus options
136 *
137 * 0x000000BA
138 *
139 * A : sample widtht 16bit setting
140 * B : sample widtht 24bit setting
141 */
142
143 #define SHIFT_16DATA 0
144 #define SHIFT_24DATA 4
145
146 #define PACKAGE_24BITBUS_BACK 0
147 #define PACKAGE_24BITBUS_FRONT 1
148 #define PACKAGE_16BITBUS_STREAM 2
149
150 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
151 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
152
153 /*
154 * FSI driver use below type name for variable
155 *
156 * xxx_num : number of data
157 * xxx_pos : position of data
158 * xxx_capa : capacity of data
159 */
160
161 /*
162 * period/frame/sample image
163 *
164 * ex) PCM (2ch)
165 *
166 * period pos period pos
167 * [n] [n + 1]
168 * |<-------------------- period--------------------->|
169 * ==|============================================ ... =|==
170 * | |
171 * ||<----- frame ----->|<------ frame ----->| ... |
172 * |+--------------------+--------------------+- ... |
173 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
174 * |+--------------------+--------------------+- ... |
175 * ==|============================================ ... =|==
176 */
177
178 /*
179 * FSI FIFO image
180 *
181 * | |
182 * | |
183 * | [ sample ] |
184 * | [ sample ] |
185 * | [ sample ] |
186 * | [ sample ] |
187 * --> go to codecs
188 */
189
190 /*
191 * FSI clock
192 *
193 * FSIxCLK [CPG] (ick) -------> |
194 * |-> FSI_DIV (div)-> FSI2
195 * FSIxCK [external] (xck) ---> |
196 */
197
198 /*
199 * struct
200 */
201
202 struct fsi_stream_handler;
203 struct fsi_stream {
204
205 /*
206 * these are initialized by fsi_stream_init()
207 */
208 struct snd_pcm_substream *substream;
209 int fifo_sample_capa; /* sample capacity of FSI FIFO */
210 int buff_sample_capa; /* sample capacity of ALSA buffer */
211 int buff_sample_pos; /* sample position of ALSA buffer */
212 int period_samples; /* sample number / 1 period */
213 int period_pos; /* current period position */
214 int sample_width; /* sample width */
215 int uerr_num;
216 int oerr_num;
217
218 /*
219 * bus options
220 */
221 u32 bus_option;
222
223 /*
224 * thse are initialized by fsi_handler_init()
225 */
226 struct fsi_stream_handler *handler;
227 struct fsi_priv *priv;
228
229 /*
230 * these are for DMAEngine
231 */
232 struct dma_chan *chan;
233 struct sh_dmae_slave slave; /* see fsi_handler_init() */
234 struct work_struct work;
235 dma_addr_t dma;
236 };
237
238 struct fsi_clk {
239 /* see [FSI clock] */
240 struct clk *own;
241 struct clk *xck;
242 struct clk *ick;
243 struct clk *div;
244 int (*set_rate)(struct device *dev,
245 struct fsi_priv *fsi);
246
247 unsigned long rate;
248 unsigned int count;
249 };
250
251 struct fsi_priv {
252 void __iomem *base;
253 struct fsi_master *master;
254
255 struct fsi_stream playback;
256 struct fsi_stream capture;
257
258 struct fsi_clk clock;
259
260 u32 fmt;
261
262 int chan_num:16;
263 int clk_master:1;
264 int clk_cpg:1;
265 int spdif:1;
266 int enable_stream:1;
267 int bit_clk_inv:1;
268 int lr_clk_inv:1;
269 };
270
271 struct fsi_stream_handler {
272 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
273 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
274 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
275 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
276 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
277 void (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
278 int enable);
279 };
280 #define fsi_stream_handler_call(io, func, args...) \
281 (!(io) ? -ENODEV : \
282 !((io)->handler->func) ? 0 : \
283 (io)->handler->func(args))
284
285 struct fsi_core {
286 int ver;
287
288 u32 int_st;
289 u32 iemsk;
290 u32 imsk;
291 u32 a_mclk;
292 u32 b_mclk;
293 };
294
295 struct fsi_master {
296 void __iomem *base;
297 int irq;
298 struct fsi_priv fsia;
299 struct fsi_priv fsib;
300 struct fsi_core *core;
301 spinlock_t lock;
302 };
303
304 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
305
306 /*
307 * basic read write function
308 */
309
310 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
311 {
312 /* valid data area is 24bit */
313 data &= 0x00ffffff;
314
315 __raw_writel(data, reg);
316 }
317
318 static u32 __fsi_reg_read(u32 __iomem *reg)
319 {
320 return __raw_readl(reg);
321 }
322
323 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
324 {
325 u32 val = __fsi_reg_read(reg);
326
327 val &= ~mask;
328 val |= data & mask;
329
330 __fsi_reg_write(reg, val);
331 }
332
333 #define fsi_reg_write(p, r, d)\
334 __fsi_reg_write((p->base + REG_##r), d)
335
336 #define fsi_reg_read(p, r)\
337 __fsi_reg_read((p->base + REG_##r))
338
339 #define fsi_reg_mask_set(p, r, m, d)\
340 __fsi_reg_mask_set((p->base + REG_##r), m, d)
341
342 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
343 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
344 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
345 {
346 u32 ret;
347 unsigned long flags;
348
349 spin_lock_irqsave(&master->lock, flags);
350 ret = __fsi_reg_read(master->base + reg);
351 spin_unlock_irqrestore(&master->lock, flags);
352
353 return ret;
354 }
355
356 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
357 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
358 static void _fsi_master_mask_set(struct fsi_master *master,
359 u32 reg, u32 mask, u32 data)
360 {
361 unsigned long flags;
362
363 spin_lock_irqsave(&master->lock, flags);
364 __fsi_reg_mask_set(master->base + reg, mask, data);
365 spin_unlock_irqrestore(&master->lock, flags);
366 }
367
368 /*
369 * basic function
370 */
371 static int fsi_version(struct fsi_master *master)
372 {
373 return master->core->ver;
374 }
375
376 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
377 {
378 return fsi->master;
379 }
380
381 static int fsi_is_clk_master(struct fsi_priv *fsi)
382 {
383 return fsi->clk_master;
384 }
385
386 static int fsi_is_port_a(struct fsi_priv *fsi)
387 {
388 return fsi->master->base == fsi->base;
389 }
390
391 static int fsi_is_spdif(struct fsi_priv *fsi)
392 {
393 return fsi->spdif;
394 }
395
396 static int fsi_is_enable_stream(struct fsi_priv *fsi)
397 {
398 return fsi->enable_stream;
399 }
400
401 static int fsi_is_play(struct snd_pcm_substream *substream)
402 {
403 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
404 }
405
406 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
407 {
408 struct snd_soc_pcm_runtime *rtd = substream->private_data;
409
410 return rtd->cpu_dai;
411 }
412
413 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
414 {
415 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
416
417 if (dai->id == 0)
418 return &master->fsia;
419 else
420 return &master->fsib;
421 }
422
423 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
424 {
425 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
426 }
427
428 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
429 {
430 int is_play = fsi_stream_is_play(fsi, io);
431 int is_porta = fsi_is_port_a(fsi);
432 u32 shift;
433
434 if (is_porta)
435 shift = is_play ? AO_SHIFT : AI_SHIFT;
436 else
437 shift = is_play ? BO_SHIFT : BI_SHIFT;
438
439 return shift;
440 }
441
442 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
443 {
444 return frames * fsi->chan_num;
445 }
446
447 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
448 {
449 return samples / fsi->chan_num;
450 }
451
452 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
453 struct fsi_stream *io)
454 {
455 int is_play = fsi_stream_is_play(fsi, io);
456 u32 status;
457 int frames;
458
459 status = is_play ?
460 fsi_reg_read(fsi, DOFF_ST) :
461 fsi_reg_read(fsi, DIFF_ST);
462
463 frames = 0x1ff & (status >> 8);
464
465 return fsi_frame2sample(fsi, frames);
466 }
467
468 static void fsi_count_fifo_err(struct fsi_priv *fsi)
469 {
470 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
471 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
472
473 if (ostatus & ERR_OVER)
474 fsi->playback.oerr_num++;
475
476 if (ostatus & ERR_UNDER)
477 fsi->playback.uerr_num++;
478
479 if (istatus & ERR_OVER)
480 fsi->capture.oerr_num++;
481
482 if (istatus & ERR_UNDER)
483 fsi->capture.uerr_num++;
484
485 fsi_reg_write(fsi, DOFF_ST, 0);
486 fsi_reg_write(fsi, DIFF_ST, 0);
487 }
488
489 /*
490 * fsi_stream_xx() function
491 */
492 static inline int fsi_stream_is_play(struct fsi_priv *fsi,
493 struct fsi_stream *io)
494 {
495 return &fsi->playback == io;
496 }
497
498 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
499 struct snd_pcm_substream *substream)
500 {
501 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
502 }
503
504 static int fsi_stream_is_working(struct fsi_priv *fsi,
505 struct fsi_stream *io)
506 {
507 struct fsi_master *master = fsi_get_master(fsi);
508 unsigned long flags;
509 int ret;
510
511 spin_lock_irqsave(&master->lock, flags);
512 ret = !!(io->substream && io->substream->runtime);
513 spin_unlock_irqrestore(&master->lock, flags);
514
515 return ret;
516 }
517
518 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
519 {
520 return io->priv;
521 }
522
523 static void fsi_stream_init(struct fsi_priv *fsi,
524 struct fsi_stream *io,
525 struct snd_pcm_substream *substream)
526 {
527 struct snd_pcm_runtime *runtime = substream->runtime;
528 struct fsi_master *master = fsi_get_master(fsi);
529 unsigned long flags;
530
531 spin_lock_irqsave(&master->lock, flags);
532 io->substream = substream;
533 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
534 io->buff_sample_pos = 0;
535 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
536 io->period_pos = 0;
537 io->sample_width = samples_to_bytes(runtime, 1);
538 io->bus_option = 0;
539 io->oerr_num = -1; /* ignore 1st err */
540 io->uerr_num = -1; /* ignore 1st err */
541 fsi_stream_handler_call(io, init, fsi, io);
542 spin_unlock_irqrestore(&master->lock, flags);
543 }
544
545 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
546 {
547 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
548 struct fsi_master *master = fsi_get_master(fsi);
549 unsigned long flags;
550
551 spin_lock_irqsave(&master->lock, flags);
552
553 if (io->oerr_num > 0)
554 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
555
556 if (io->uerr_num > 0)
557 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
558
559 fsi_stream_handler_call(io, quit, fsi, io);
560 io->substream = NULL;
561 io->buff_sample_capa = 0;
562 io->buff_sample_pos = 0;
563 io->period_samples = 0;
564 io->period_pos = 0;
565 io->sample_width = 0;
566 io->bus_option = 0;
567 io->oerr_num = 0;
568 io->uerr_num = 0;
569 spin_unlock_irqrestore(&master->lock, flags);
570 }
571
572 static int fsi_stream_transfer(struct fsi_stream *io)
573 {
574 struct fsi_priv *fsi = fsi_stream_to_priv(io);
575 if (!fsi)
576 return -EIO;
577
578 return fsi_stream_handler_call(io, transfer, fsi, io);
579 }
580
581 #define fsi_stream_start(fsi, io)\
582 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
583
584 #define fsi_stream_stop(fsi, io)\
585 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
586
587 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
588 {
589 struct fsi_stream *io;
590 int ret1, ret2;
591
592 io = &fsi->playback;
593 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
594
595 io = &fsi->capture;
596 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
597
598 if (ret1 < 0)
599 return ret1;
600 if (ret2 < 0)
601 return ret2;
602
603 return 0;
604 }
605
606 static int fsi_stream_remove(struct fsi_priv *fsi)
607 {
608 struct fsi_stream *io;
609 int ret1, ret2;
610
611 io = &fsi->playback;
612 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
613
614 io = &fsi->capture;
615 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
616
617 if (ret1 < 0)
618 return ret1;
619 if (ret2 < 0)
620 return ret2;
621
622 return 0;
623 }
624
625 /*
626 * format/bus/dma setting
627 */
628 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
629 u32 bus, struct device *dev)
630 {
631 struct fsi_master *master = fsi_get_master(fsi);
632 int is_play = fsi_stream_is_play(fsi, io);
633 u32 fmt = fsi->fmt;
634
635 if (fsi_version(master) >= 2) {
636 u32 dma = 0;
637
638 /*
639 * FSI2 needs DMA/Bus setting
640 */
641 switch (bus) {
642 case PACKAGE_24BITBUS_FRONT:
643 fmt |= CR_BWS_24;
644 dma |= VDMD_FRONT;
645 dev_dbg(dev, "24bit bus / package in front\n");
646 break;
647 case PACKAGE_16BITBUS_STREAM:
648 fmt |= CR_BWS_16;
649 dma |= VDMD_STREAM;
650 dev_dbg(dev, "16bit bus / stream mode\n");
651 break;
652 case PACKAGE_24BITBUS_BACK:
653 default:
654 fmt |= CR_BWS_24;
655 dma |= VDMD_BACK;
656 dev_dbg(dev, "24bit bus / package in back\n");
657 break;
658 }
659
660 if (is_play)
661 fsi_reg_write(fsi, OUT_DMAC, dma);
662 else
663 fsi_reg_write(fsi, IN_DMAC, dma);
664 }
665
666 if (is_play)
667 fsi_reg_write(fsi, DO_FMT, fmt);
668 else
669 fsi_reg_write(fsi, DI_FMT, fmt);
670 }
671
672 /*
673 * irq function
674 */
675
676 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
677 {
678 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
679 struct fsi_master *master = fsi_get_master(fsi);
680
681 fsi_core_mask_set(master, imsk, data, data);
682 fsi_core_mask_set(master, iemsk, data, data);
683 }
684
685 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
686 {
687 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
688 struct fsi_master *master = fsi_get_master(fsi);
689
690 fsi_core_mask_set(master, imsk, data, 0);
691 fsi_core_mask_set(master, iemsk, data, 0);
692 }
693
694 static u32 fsi_irq_get_status(struct fsi_master *master)
695 {
696 return fsi_core_read(master, int_st);
697 }
698
699 static void fsi_irq_clear_status(struct fsi_priv *fsi)
700 {
701 u32 data = 0;
702 struct fsi_master *master = fsi_get_master(fsi);
703
704 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
705 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
706
707 /* clear interrupt factor */
708 fsi_core_mask_set(master, int_st, data, 0);
709 }
710
711 /*
712 * SPDIF master clock function
713 *
714 * These functions are used later FSI2
715 */
716 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
717 {
718 struct fsi_master *master = fsi_get_master(fsi);
719 u32 mask, val;
720
721 mask = BP | SE;
722 val = enable ? mask : 0;
723
724 fsi_is_port_a(fsi) ?
725 fsi_core_mask_set(master, a_mclk, mask, val) :
726 fsi_core_mask_set(master, b_mclk, mask, val);
727 }
728
729 /*
730 * clock function
731 */
732 static int fsi_clk_init(struct device *dev,
733 struct fsi_priv *fsi,
734 int xck,
735 int ick,
736 int div,
737 int (*set_rate)(struct device *dev,
738 struct fsi_priv *fsi))
739 {
740 struct fsi_clk *clock = &fsi->clock;
741 int is_porta = fsi_is_port_a(fsi);
742
743 clock->xck = NULL;
744 clock->ick = NULL;
745 clock->div = NULL;
746 clock->rate = 0;
747 clock->count = 0;
748 clock->set_rate = set_rate;
749
750 clock->own = devm_clk_get(dev, NULL);
751 if (IS_ERR(clock->own))
752 return -EINVAL;
753
754 /* external clock */
755 if (xck) {
756 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
757 if (IS_ERR(clock->xck)) {
758 dev_err(dev, "can't get xck clock\n");
759 return -EINVAL;
760 }
761 if (clock->xck == clock->own) {
762 dev_err(dev, "cpu doesn't support xck clock\n");
763 return -EINVAL;
764 }
765 }
766
767 /* FSIACLK/FSIBCLK */
768 if (ick) {
769 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
770 if (IS_ERR(clock->ick)) {
771 dev_err(dev, "can't get ick clock\n");
772 return -EINVAL;
773 }
774 if (clock->ick == clock->own) {
775 dev_err(dev, "cpu doesn't support ick clock\n");
776 return -EINVAL;
777 }
778 }
779
780 /* FSI-DIV */
781 if (div) {
782 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
783 if (IS_ERR(clock->div)) {
784 dev_err(dev, "can't get div clock\n");
785 return -EINVAL;
786 }
787 if (clock->div == clock->own) {
788 dev_err(dev, "cpu doens't support div clock\n");
789 return -EINVAL;
790 }
791 }
792
793 return 0;
794 }
795
796 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
797 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
798 {
799 fsi->clock.rate = rate;
800 }
801
802 static int fsi_clk_is_valid(struct fsi_priv *fsi)
803 {
804 return fsi->clock.set_rate &&
805 fsi->clock.rate;
806 }
807
808 static int fsi_clk_enable(struct device *dev,
809 struct fsi_priv *fsi)
810 {
811 struct fsi_clk *clock = &fsi->clock;
812 int ret = -EINVAL;
813
814 if (!fsi_clk_is_valid(fsi))
815 return ret;
816
817 if (0 == clock->count) {
818 ret = clock->set_rate(dev, fsi);
819 if (ret < 0) {
820 fsi_clk_invalid(fsi);
821 return ret;
822 }
823
824 if (clock->xck)
825 clk_enable(clock->xck);
826 if (clock->ick)
827 clk_enable(clock->ick);
828 if (clock->div)
829 clk_enable(clock->div);
830
831 clock->count++;
832 }
833
834 return ret;
835 }
836
837 static int fsi_clk_disable(struct device *dev,
838 struct fsi_priv *fsi)
839 {
840 struct fsi_clk *clock = &fsi->clock;
841
842 if (!fsi_clk_is_valid(fsi))
843 return -EINVAL;
844
845 if (1 == clock->count--) {
846 if (clock->xck)
847 clk_disable(clock->xck);
848 if (clock->ick)
849 clk_disable(clock->ick);
850 if (clock->div)
851 clk_disable(clock->div);
852 }
853
854 return 0;
855 }
856
857 static int fsi_clk_set_ackbpf(struct device *dev,
858 struct fsi_priv *fsi,
859 int ackmd, int bpfmd)
860 {
861 u32 data = 0;
862
863 /* check ackmd/bpfmd relationship */
864 if (bpfmd > ackmd) {
865 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
866 return -EINVAL;
867 }
868
869 /* ACKMD */
870 switch (ackmd) {
871 case 512:
872 data |= (0x0 << 12);
873 break;
874 case 256:
875 data |= (0x1 << 12);
876 break;
877 case 128:
878 data |= (0x2 << 12);
879 break;
880 case 64:
881 data |= (0x3 << 12);
882 break;
883 case 32:
884 data |= (0x4 << 12);
885 break;
886 default:
887 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
888 return -EINVAL;
889 }
890
891 /* BPFMD */
892 switch (bpfmd) {
893 case 32:
894 data |= (0x0 << 8);
895 break;
896 case 64:
897 data |= (0x1 << 8);
898 break;
899 case 128:
900 data |= (0x2 << 8);
901 break;
902 case 256:
903 data |= (0x3 << 8);
904 break;
905 case 512:
906 data |= (0x4 << 8);
907 break;
908 case 16:
909 data |= (0x7 << 8);
910 break;
911 default:
912 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
913 return -EINVAL;
914 }
915
916 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
917
918 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
919 udelay(10);
920
921 return 0;
922 }
923
924 static int fsi_clk_set_rate_external(struct device *dev,
925 struct fsi_priv *fsi)
926 {
927 struct clk *xck = fsi->clock.xck;
928 struct clk *ick = fsi->clock.ick;
929 unsigned long rate = fsi->clock.rate;
930 unsigned long xrate;
931 int ackmd, bpfmd;
932 int ret = 0;
933
934 /* check clock rate */
935 xrate = clk_get_rate(xck);
936 if (xrate % rate) {
937 dev_err(dev, "unsupported clock rate\n");
938 return -EINVAL;
939 }
940
941 clk_set_parent(ick, xck);
942 clk_set_rate(ick, xrate);
943
944 bpfmd = fsi->chan_num * 32;
945 ackmd = xrate / rate;
946
947 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
948
949 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
950 if (ret < 0)
951 dev_err(dev, "%s failed", __func__);
952
953 return ret;
954 }
955
956 static int fsi_clk_set_rate_cpg(struct device *dev,
957 struct fsi_priv *fsi)
958 {
959 struct clk *ick = fsi->clock.ick;
960 struct clk *div = fsi->clock.div;
961 unsigned long rate = fsi->clock.rate;
962 unsigned long target = 0; /* 12288000 or 11289600 */
963 unsigned long actual, cout;
964 unsigned long diff, min;
965 unsigned long best_cout, best_act;
966 int adj;
967 int ackmd, bpfmd;
968 int ret = -EINVAL;
969
970 if (!(12288000 % rate))
971 target = 12288000;
972 if (!(11289600 % rate))
973 target = 11289600;
974 if (!target) {
975 dev_err(dev, "unsupported rate\n");
976 return ret;
977 }
978
979 bpfmd = fsi->chan_num * 32;
980 ackmd = target / rate;
981 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
982 if (ret < 0) {
983 dev_err(dev, "%s failed", __func__);
984 return ret;
985 }
986
987 /*
988 * The clock flow is
989 *
990 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
991 *
992 * But, it needs to find best match of CPG and FSI_DIV
993 * combination, since it is difficult to generate correct
994 * frequency of audio clock from ick clock only.
995 * Because ick is created from its parent clock.
996 *
997 * target = rate x [512/256/128/64]fs
998 * cout = round(target x adjustment)
999 * actual = cout / adjustment (by FSI-DIV) ~= target
1000 * audio = actual
1001 */
1002 min = ~0;
1003 best_cout = 0;
1004 best_act = 0;
1005 for (adj = 1; adj < 0xffff; adj++) {
1006
1007 cout = target * adj;
1008 if (cout > 100000000) /* max clock = 100MHz */
1009 break;
1010
1011 /* cout/actual audio clock */
1012 cout = clk_round_rate(ick, cout);
1013 actual = cout / adj;
1014
1015 /* find best frequency */
1016 diff = abs(actual - target);
1017 if (diff < min) {
1018 min = diff;
1019 best_cout = cout;
1020 best_act = actual;
1021 }
1022 }
1023
1024 ret = clk_set_rate(ick, best_cout);
1025 if (ret < 0) {
1026 dev_err(dev, "ick clock failed\n");
1027 return -EIO;
1028 }
1029
1030 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1031 if (ret < 0) {
1032 dev_err(dev, "div clock failed\n");
1033 return -EIO;
1034 }
1035
1036 dev_dbg(dev, "ick/div = %ld/%ld\n",
1037 clk_get_rate(ick), clk_get_rate(div));
1038
1039 return ret;
1040 }
1041
1042 /*
1043 * pio data transfer handler
1044 */
1045 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1046 {
1047 int i;
1048
1049 if (fsi_is_enable_stream(fsi)) {
1050 /*
1051 * stream mode
1052 * see
1053 * fsi_pio_push_init()
1054 */
1055 u32 *buf = (u32 *)_buf;
1056
1057 for (i = 0; i < samples / 2; i++)
1058 fsi_reg_write(fsi, DODT, buf[i]);
1059 } else {
1060 /* normal mode */
1061 u16 *buf = (u16 *)_buf;
1062
1063 for (i = 0; i < samples; i++)
1064 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1065 }
1066 }
1067
1068 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1069 {
1070 u16 *buf = (u16 *)_buf;
1071 int i;
1072
1073 for (i = 0; i < samples; i++)
1074 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1075 }
1076
1077 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1078 {
1079 u32 *buf = (u32 *)_buf;
1080 int i;
1081
1082 for (i = 0; i < samples; i++)
1083 fsi_reg_write(fsi, DODT, *(buf + i));
1084 }
1085
1086 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1087 {
1088 u32 *buf = (u32 *)_buf;
1089 int i;
1090
1091 for (i = 0; i < samples; i++)
1092 *(buf + i) = fsi_reg_read(fsi, DIDT);
1093 }
1094
1095 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1096 {
1097 struct snd_pcm_runtime *runtime = io->substream->runtime;
1098
1099 return runtime->dma_area +
1100 samples_to_bytes(runtime, io->buff_sample_pos);
1101 }
1102
1103 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1104 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1105 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1106 int samples)
1107 {
1108 struct snd_pcm_runtime *runtime;
1109 struct snd_pcm_substream *substream;
1110 u8 *buf;
1111 int over_period;
1112
1113 if (!fsi_stream_is_working(fsi, io))
1114 return -EINVAL;
1115
1116 over_period = 0;
1117 substream = io->substream;
1118 runtime = substream->runtime;
1119
1120 /* FSI FIFO has limit.
1121 * So, this driver can not send periods data at a time
1122 */
1123 if (io->buff_sample_pos >=
1124 io->period_samples * (io->period_pos + 1)) {
1125
1126 over_period = 1;
1127 io->period_pos = (io->period_pos + 1) % runtime->periods;
1128
1129 if (0 == io->period_pos)
1130 io->buff_sample_pos = 0;
1131 }
1132
1133 buf = fsi_pio_get_area(fsi, io);
1134
1135 switch (io->sample_width) {
1136 case 2:
1137 run16(fsi, buf, samples);
1138 break;
1139 case 4:
1140 run32(fsi, buf, samples);
1141 break;
1142 default:
1143 return -EINVAL;
1144 }
1145
1146 /* update buff_sample_pos */
1147 io->buff_sample_pos += samples;
1148
1149 if (over_period)
1150 snd_pcm_period_elapsed(substream);
1151
1152 return 0;
1153 }
1154
1155 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1156 {
1157 int sample_residues; /* samples in FSI fifo */
1158 int sample_space; /* ALSA free samples space */
1159 int samples;
1160
1161 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1162 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1163
1164 samples = min(sample_residues, sample_space);
1165
1166 return fsi_pio_transfer(fsi, io,
1167 fsi_pio_pop16,
1168 fsi_pio_pop32,
1169 samples);
1170 }
1171
1172 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1173 {
1174 int sample_residues; /* ALSA residue samples */
1175 int sample_space; /* FSI fifo free samples space */
1176 int samples;
1177
1178 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1179 sample_space = io->fifo_sample_capa -
1180 fsi_get_current_fifo_samples(fsi, io);
1181
1182 samples = min(sample_residues, sample_space);
1183
1184 return fsi_pio_transfer(fsi, io,
1185 fsi_pio_push16,
1186 fsi_pio_push32,
1187 samples);
1188 }
1189
1190 static void fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1191 int enable)
1192 {
1193 struct fsi_master *master = fsi_get_master(fsi);
1194 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1195
1196 if (enable)
1197 fsi_irq_enable(fsi, io);
1198 else
1199 fsi_irq_disable(fsi, io);
1200
1201 if (fsi_is_clk_master(fsi))
1202 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1203 }
1204
1205 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1206 {
1207 /*
1208 * we can use 16bit stream mode
1209 * when "playback" and "16bit data"
1210 * and platform allows "stream mode"
1211 * see
1212 * fsi_pio_push16()
1213 */
1214 if (fsi_is_enable_stream(fsi))
1215 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1216 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1217 else
1218 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1219 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1220 return 0;
1221 }
1222
1223 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1224 {
1225 /*
1226 * always 24bit bus, package back when "capture"
1227 */
1228 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1229 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1230 return 0;
1231 }
1232
1233 static struct fsi_stream_handler fsi_pio_push_handler = {
1234 .init = fsi_pio_push_init,
1235 .transfer = fsi_pio_push,
1236 .start_stop = fsi_pio_start_stop,
1237 };
1238
1239 static struct fsi_stream_handler fsi_pio_pop_handler = {
1240 .init = fsi_pio_pop_init,
1241 .transfer = fsi_pio_pop,
1242 .start_stop = fsi_pio_start_stop,
1243 };
1244
1245 static irqreturn_t fsi_interrupt(int irq, void *data)
1246 {
1247 struct fsi_master *master = data;
1248 u32 int_st = fsi_irq_get_status(master);
1249
1250 /* clear irq status */
1251 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1252 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1253
1254 if (int_st & AB_IO(1, AO_SHIFT))
1255 fsi_stream_transfer(&master->fsia.playback);
1256 if (int_st & AB_IO(1, BO_SHIFT))
1257 fsi_stream_transfer(&master->fsib.playback);
1258 if (int_st & AB_IO(1, AI_SHIFT))
1259 fsi_stream_transfer(&master->fsia.capture);
1260 if (int_st & AB_IO(1, BI_SHIFT))
1261 fsi_stream_transfer(&master->fsib.capture);
1262
1263 fsi_count_fifo_err(&master->fsia);
1264 fsi_count_fifo_err(&master->fsib);
1265
1266 fsi_irq_clear_status(&master->fsia);
1267 fsi_irq_clear_status(&master->fsib);
1268
1269 return IRQ_HANDLED;
1270 }
1271
1272 /*
1273 * dma data transfer handler
1274 */
1275 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1276 {
1277 struct snd_pcm_runtime *runtime = io->substream->runtime;
1278 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1279 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
1280 DMA_TO_DEVICE : DMA_FROM_DEVICE;
1281
1282 /*
1283 * 24bit data : 24bit bus / package in back
1284 * 16bit data : 16bit bus / stream mode
1285 */
1286 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1287 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1288
1289 io->dma = dma_map_single(dai->dev, runtime->dma_area,
1290 snd_pcm_lib_buffer_bytes(io->substream), dir);
1291 return 0;
1292 }
1293
1294 static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io)
1295 {
1296 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1297 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
1298 DMA_TO_DEVICE : DMA_FROM_DEVICE;
1299
1300 dma_unmap_single(dai->dev, io->dma,
1301 snd_pcm_lib_buffer_bytes(io->substream), dir);
1302 return 0;
1303 }
1304
1305 static dma_addr_t fsi_dma_get_area(struct fsi_stream *io)
1306 {
1307 struct snd_pcm_runtime *runtime = io->substream->runtime;
1308
1309 return io->dma + samples_to_bytes(runtime, io->buff_sample_pos);
1310 }
1311
1312 static void fsi_dma_complete(void *data)
1313 {
1314 struct fsi_stream *io = (struct fsi_stream *)data;
1315 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1316 struct snd_pcm_runtime *runtime = io->substream->runtime;
1317 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1318 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
1319 DMA_TO_DEVICE : DMA_FROM_DEVICE;
1320
1321 dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io),
1322 samples_to_bytes(runtime, io->period_samples), dir);
1323
1324 io->buff_sample_pos += io->period_samples;
1325 io->period_pos++;
1326
1327 if (io->period_pos >= runtime->periods) {
1328 io->period_pos = 0;
1329 io->buff_sample_pos = 0;
1330 }
1331
1332 fsi_count_fifo_err(fsi);
1333 fsi_stream_transfer(io);
1334
1335 snd_pcm_period_elapsed(io->substream);
1336 }
1337
1338 static void fsi_dma_do_work(struct work_struct *work)
1339 {
1340 struct fsi_stream *io = container_of(work, struct fsi_stream, work);
1341 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1342 struct snd_soc_dai *dai;
1343 struct dma_async_tx_descriptor *desc;
1344 struct snd_pcm_runtime *runtime;
1345 enum dma_data_direction dir;
1346 int is_play = fsi_stream_is_play(fsi, io);
1347 int len;
1348 dma_addr_t buf;
1349
1350 if (!fsi_stream_is_working(fsi, io))
1351 return;
1352
1353 dai = fsi_get_dai(io->substream);
1354 runtime = io->substream->runtime;
1355 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1356 len = samples_to_bytes(runtime, io->period_samples);
1357 buf = fsi_dma_get_area(io);
1358
1359 dma_sync_single_for_device(dai->dev, buf, len, dir);
1360
1361 desc = dmaengine_prep_slave_single(io->chan, buf, len, dir,
1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1363 if (!desc) {
1364 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
1365 return;
1366 }
1367
1368 desc->callback = fsi_dma_complete;
1369 desc->callback_param = io;
1370
1371 if (dmaengine_submit(desc) < 0) {
1372 dev_err(dai->dev, "tx_submit() fail\n");
1373 return;
1374 }
1375
1376 dma_async_issue_pending(io->chan);
1377
1378 /*
1379 * FIXME
1380 *
1381 * In DMAEngine case, codec and FSI cannot be started simultaneously
1382 * since FSI is using the scheduler work queue.
1383 * Therefore, in capture case, probably FSI FIFO will have got
1384 * overflow error in this point.
1385 * in that case, DMA cannot start transfer until error was cleared.
1386 */
1387 if (!is_play) {
1388 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1389 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1390 fsi_reg_write(fsi, DIFF_ST, 0);
1391 }
1392 }
1393 }
1394
1395 static bool fsi_dma_filter(struct dma_chan *chan, void *param)
1396 {
1397 struct sh_dmae_slave *slave = param;
1398
1399 chan->private = slave;
1400
1401 return true;
1402 }
1403
1404 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1405 {
1406 schedule_work(&io->work);
1407
1408 return 0;
1409 }
1410
1411 static void fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1412 int start)
1413 {
1414 struct fsi_master *master = fsi_get_master(fsi);
1415 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1416 u32 enable = start ? DMA_ON : 0;
1417
1418 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1419
1420 dmaengine_terminate_all(io->chan);
1421
1422 if (fsi_is_clk_master(fsi))
1423 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1424 }
1425
1426 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1427 {
1428 dma_cap_mask_t mask;
1429
1430 dma_cap_zero(mask);
1431 dma_cap_set(DMA_SLAVE, mask);
1432
1433 io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave);
1434 if (!io->chan) {
1435
1436 /* switch to PIO handler */
1437 if (fsi_stream_is_play(fsi, io))
1438 fsi->playback.handler = &fsi_pio_push_handler;
1439 else
1440 fsi->capture.handler = &fsi_pio_pop_handler;
1441
1442 dev_info(dev, "switch handler (dma => pio)\n");
1443
1444 /* probe again */
1445 return fsi_stream_probe(fsi, dev);
1446 }
1447
1448 INIT_WORK(&io->work, fsi_dma_do_work);
1449
1450 return 0;
1451 }
1452
1453 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1454 {
1455 cancel_work_sync(&io->work);
1456
1457 fsi_stream_stop(fsi, io);
1458
1459 if (io->chan)
1460 dma_release_channel(io->chan);
1461
1462 io->chan = NULL;
1463 return 0;
1464 }
1465
1466 static struct fsi_stream_handler fsi_dma_push_handler = {
1467 .init = fsi_dma_init,
1468 .quit = fsi_dma_quit,
1469 .probe = fsi_dma_probe,
1470 .transfer = fsi_dma_transfer,
1471 .remove = fsi_dma_remove,
1472 .start_stop = fsi_dma_push_start_stop,
1473 };
1474
1475 /*
1476 * dai ops
1477 */
1478 static void fsi_fifo_init(struct fsi_priv *fsi,
1479 struct fsi_stream *io,
1480 struct device *dev)
1481 {
1482 struct fsi_master *master = fsi_get_master(fsi);
1483 int is_play = fsi_stream_is_play(fsi, io);
1484 u32 shift, i;
1485 int frame_capa;
1486
1487 /* get on-chip RAM capacity */
1488 shift = fsi_master_read(master, FIFO_SZ);
1489 shift >>= fsi_get_port_shift(fsi, io);
1490 shift &= FIFO_SZ_MASK;
1491 frame_capa = 256 << shift;
1492 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1493
1494 /*
1495 * The maximum number of sample data varies depending
1496 * on the number of channels selected for the format.
1497 *
1498 * FIFOs are used in 4-channel units in 3-channel mode
1499 * and in 8-channel units in 5- to 7-channel mode
1500 * meaning that more FIFOs than the required size of DPRAM
1501 * are used.
1502 *
1503 * ex) if 256 words of DP-RAM is connected
1504 * 1 channel: 256 (256 x 1 = 256)
1505 * 2 channels: 128 (128 x 2 = 256)
1506 * 3 channels: 64 ( 64 x 3 = 192)
1507 * 4 channels: 64 ( 64 x 4 = 256)
1508 * 5 channels: 32 ( 32 x 5 = 160)
1509 * 6 channels: 32 ( 32 x 6 = 192)
1510 * 7 channels: 32 ( 32 x 7 = 224)
1511 * 8 channels: 32 ( 32 x 8 = 256)
1512 */
1513 for (i = 1; i < fsi->chan_num; i <<= 1)
1514 frame_capa >>= 1;
1515 dev_dbg(dev, "%d channel %d store\n",
1516 fsi->chan_num, frame_capa);
1517
1518 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1519
1520 /*
1521 * set interrupt generation factor
1522 * clear FIFO
1523 */
1524 if (is_play) {
1525 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1526 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1527 } else {
1528 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1529 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1530 }
1531 }
1532
1533 static int fsi_hw_startup(struct fsi_priv *fsi,
1534 struct fsi_stream *io,
1535 struct device *dev)
1536 {
1537 u32 data = 0;
1538
1539 /* clock setting */
1540 if (fsi_is_clk_master(fsi))
1541 data = DIMD | DOMD;
1542
1543 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1544
1545 /* clock inversion (CKG2) */
1546 data = 0;
1547 if (fsi->bit_clk_inv)
1548 data |= (1 << 0);
1549 if (fsi->lr_clk_inv)
1550 data |= (1 << 4);
1551 if (fsi_is_clk_master(fsi))
1552 data <<= 8;
1553 fsi_reg_write(fsi, CKG2, data);
1554
1555 /* spdif ? */
1556 if (fsi_is_spdif(fsi)) {
1557 fsi_spdif_clk_ctrl(fsi, 1);
1558 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1559 }
1560
1561 /*
1562 * get bus settings
1563 */
1564 data = 0;
1565 switch (io->sample_width) {
1566 case 2:
1567 data = BUSOP_GET(16, io->bus_option);
1568 break;
1569 case 4:
1570 data = BUSOP_GET(24, io->bus_option);
1571 break;
1572 }
1573 fsi_format_bus_setup(fsi, io, data, dev);
1574
1575 /* irq clear */
1576 fsi_irq_disable(fsi, io);
1577 fsi_irq_clear_status(fsi);
1578
1579 /* fifo init */
1580 fsi_fifo_init(fsi, io, dev);
1581
1582 /* start master clock */
1583 if (fsi_is_clk_master(fsi))
1584 return fsi_clk_enable(dev, fsi);
1585
1586 return 0;
1587 }
1588
1589 static int fsi_hw_shutdown(struct fsi_priv *fsi,
1590 struct device *dev)
1591 {
1592 /* stop master clock */
1593 if (fsi_is_clk_master(fsi))
1594 return fsi_clk_disable(dev, fsi);
1595
1596 return 0;
1597 }
1598
1599 static int fsi_dai_startup(struct snd_pcm_substream *substream,
1600 struct snd_soc_dai *dai)
1601 {
1602 struct fsi_priv *fsi = fsi_get_priv(substream);
1603
1604 fsi_clk_invalid(fsi);
1605
1606 return 0;
1607 }
1608
1609 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1610 struct snd_soc_dai *dai)
1611 {
1612 struct fsi_priv *fsi = fsi_get_priv(substream);
1613
1614 fsi_clk_invalid(fsi);
1615 }
1616
1617 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1618 struct snd_soc_dai *dai)
1619 {
1620 struct fsi_priv *fsi = fsi_get_priv(substream);
1621 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1622 int ret = 0;
1623
1624 switch (cmd) {
1625 case SNDRV_PCM_TRIGGER_START:
1626 fsi_stream_init(fsi, io, substream);
1627 if (!ret)
1628 ret = fsi_hw_startup(fsi, io, dai->dev);
1629 if (!ret)
1630 ret = fsi_stream_transfer(io);
1631 if (!ret)
1632 fsi_stream_start(fsi, io);
1633 break;
1634 case SNDRV_PCM_TRIGGER_STOP:
1635 if (!ret)
1636 ret = fsi_hw_shutdown(fsi, dai->dev);
1637 fsi_stream_stop(fsi, io);
1638 fsi_stream_quit(fsi, io);
1639 break;
1640 }
1641
1642 return ret;
1643 }
1644
1645 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1646 {
1647 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1648 case SND_SOC_DAIFMT_I2S:
1649 fsi->fmt = CR_I2S;
1650 fsi->chan_num = 2;
1651 break;
1652 case SND_SOC_DAIFMT_LEFT_J:
1653 fsi->fmt = CR_PCM;
1654 fsi->chan_num = 2;
1655 break;
1656 default:
1657 return -EINVAL;
1658 }
1659
1660 return 0;
1661 }
1662
1663 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1664 {
1665 struct fsi_master *master = fsi_get_master(fsi);
1666
1667 if (fsi_version(master) < 2)
1668 return -EINVAL;
1669
1670 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1671 fsi->chan_num = 2;
1672
1673 return 0;
1674 }
1675
1676 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1677 {
1678 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1679 int ret;
1680
1681 /* set master/slave audio interface */
1682 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1683 case SND_SOC_DAIFMT_CBM_CFM:
1684 fsi->clk_master = 1;
1685 break;
1686 case SND_SOC_DAIFMT_CBS_CFS:
1687 break;
1688 default:
1689 return -EINVAL;
1690 }
1691
1692 /* set clock inversion */
1693 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1694 case SND_SOC_DAIFMT_NB_IF:
1695 fsi->bit_clk_inv = 0;
1696 fsi->lr_clk_inv = 1;
1697 break;
1698 case SND_SOC_DAIFMT_IB_NF:
1699 fsi->bit_clk_inv = 1;
1700 fsi->lr_clk_inv = 0;
1701 break;
1702 case SND_SOC_DAIFMT_IB_IF:
1703 fsi->bit_clk_inv = 1;
1704 fsi->lr_clk_inv = 1;
1705 break;
1706 case SND_SOC_DAIFMT_NB_NF:
1707 default:
1708 fsi->bit_clk_inv = 0;
1709 fsi->lr_clk_inv = 0;
1710 break;
1711 }
1712
1713 if (fsi_is_clk_master(fsi)) {
1714 if (fsi->clk_cpg)
1715 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1716 fsi_clk_set_rate_cpg);
1717 else
1718 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1719 fsi_clk_set_rate_external);
1720 }
1721
1722 /* set format */
1723 if (fsi_is_spdif(fsi))
1724 ret = fsi_set_fmt_spdif(fsi);
1725 else
1726 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1727
1728 return ret;
1729 }
1730
1731 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1732 struct snd_pcm_hw_params *params,
1733 struct snd_soc_dai *dai)
1734 {
1735 struct fsi_priv *fsi = fsi_get_priv(substream);
1736
1737 if (fsi_is_clk_master(fsi))
1738 fsi_clk_valid(fsi, params_rate(params));
1739
1740 return 0;
1741 }
1742
1743 static const struct snd_soc_dai_ops fsi_dai_ops = {
1744 .startup = fsi_dai_startup,
1745 .shutdown = fsi_dai_shutdown,
1746 .trigger = fsi_dai_trigger,
1747 .set_fmt = fsi_dai_set_fmt,
1748 .hw_params = fsi_dai_hw_params,
1749 };
1750
1751 /*
1752 * pcm ops
1753 */
1754
1755 static struct snd_pcm_hardware fsi_pcm_hardware = {
1756 .info = SNDRV_PCM_INFO_INTERLEAVED |
1757 SNDRV_PCM_INFO_MMAP |
1758 SNDRV_PCM_INFO_MMAP_VALID |
1759 SNDRV_PCM_INFO_PAUSE,
1760 .formats = FSI_FMTS,
1761 .rates = FSI_RATES,
1762 .rate_min = 8000,
1763 .rate_max = 192000,
1764 .channels_min = 2,
1765 .channels_max = 2,
1766 .buffer_bytes_max = 64 * 1024,
1767 .period_bytes_min = 32,
1768 .period_bytes_max = 8192,
1769 .periods_min = 1,
1770 .periods_max = 32,
1771 .fifo_size = 256,
1772 };
1773
1774 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1775 {
1776 struct snd_pcm_runtime *runtime = substream->runtime;
1777 int ret = 0;
1778
1779 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1780
1781 ret = snd_pcm_hw_constraint_integer(runtime,
1782 SNDRV_PCM_HW_PARAM_PERIODS);
1783
1784 return ret;
1785 }
1786
1787 static int fsi_hw_params(struct snd_pcm_substream *substream,
1788 struct snd_pcm_hw_params *hw_params)
1789 {
1790 return snd_pcm_lib_malloc_pages(substream,
1791 params_buffer_bytes(hw_params));
1792 }
1793
1794 static int fsi_hw_free(struct snd_pcm_substream *substream)
1795 {
1796 return snd_pcm_lib_free_pages(substream);
1797 }
1798
1799 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1800 {
1801 struct fsi_priv *fsi = fsi_get_priv(substream);
1802 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1803
1804 return fsi_sample2frame(fsi, io->buff_sample_pos);
1805 }
1806
1807 static struct snd_pcm_ops fsi_pcm_ops = {
1808 .open = fsi_pcm_open,
1809 .ioctl = snd_pcm_lib_ioctl,
1810 .hw_params = fsi_hw_params,
1811 .hw_free = fsi_hw_free,
1812 .pointer = fsi_pointer,
1813 };
1814
1815 /*
1816 * snd_soc_platform
1817 */
1818
1819 #define PREALLOC_BUFFER (32 * 1024)
1820 #define PREALLOC_BUFFER_MAX (32 * 1024)
1821
1822 static void fsi_pcm_free(struct snd_pcm *pcm)
1823 {
1824 snd_pcm_lib_preallocate_free_for_all(pcm);
1825 }
1826
1827 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1828 {
1829 struct snd_pcm *pcm = rtd->pcm;
1830
1831 /*
1832 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1833 * in MMAP mode (i.e. aplay -M)
1834 */
1835 return snd_pcm_lib_preallocate_pages_for_all(
1836 pcm,
1837 SNDRV_DMA_TYPE_CONTINUOUS,
1838 snd_dma_continuous_data(GFP_KERNEL),
1839 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1840 }
1841
1842 /*
1843 * alsa struct
1844 */
1845
1846 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1847 {
1848 .name = "fsia-dai",
1849 .playback = {
1850 .rates = FSI_RATES,
1851 .formats = FSI_FMTS,
1852 .channels_min = 2,
1853 .channels_max = 2,
1854 },
1855 .capture = {
1856 .rates = FSI_RATES,
1857 .formats = FSI_FMTS,
1858 .channels_min = 2,
1859 .channels_max = 2,
1860 },
1861 .ops = &fsi_dai_ops,
1862 },
1863 {
1864 .name = "fsib-dai",
1865 .playback = {
1866 .rates = FSI_RATES,
1867 .formats = FSI_FMTS,
1868 .channels_min = 2,
1869 .channels_max = 2,
1870 },
1871 .capture = {
1872 .rates = FSI_RATES,
1873 .formats = FSI_FMTS,
1874 .channels_min = 2,
1875 .channels_max = 2,
1876 },
1877 .ops = &fsi_dai_ops,
1878 },
1879 };
1880
1881 static struct snd_soc_platform_driver fsi_soc_platform = {
1882 .ops = &fsi_pcm_ops,
1883 .pcm_new = fsi_pcm_new,
1884 .pcm_free = fsi_pcm_free,
1885 };
1886
1887 /*
1888 * platform function
1889 */
1890 static void fsi_port_info_init(struct fsi_priv *fsi,
1891 struct sh_fsi_port_info *info)
1892 {
1893 if (info->flags & SH_FSI_FMT_SPDIF)
1894 fsi->spdif = 1;
1895
1896 if (info->flags & SH_FSI_CLK_CPG)
1897 fsi->clk_cpg = 1;
1898
1899 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1900 fsi->enable_stream = 1;
1901 }
1902
1903 static void fsi_handler_init(struct fsi_priv *fsi,
1904 struct sh_fsi_port_info *info)
1905 {
1906 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1907 fsi->playback.priv = fsi;
1908 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1909 fsi->capture.priv = fsi;
1910
1911 if (info->tx_id) {
1912 fsi->playback.slave.shdma_slave.slave_id = info->tx_id;
1913 fsi->playback.handler = &fsi_dma_push_handler;
1914 }
1915 }
1916
1917 static int fsi_probe(struct platform_device *pdev)
1918 {
1919 struct fsi_master *master;
1920 const struct platform_device_id *id_entry;
1921 struct sh_fsi_platform_info *info = pdev->dev.platform_data;
1922 struct sh_fsi_port_info nul_info, *pinfo;
1923 struct fsi_priv *fsi;
1924 struct resource *res;
1925 unsigned int irq;
1926 int ret;
1927
1928 nul_info.flags = 0;
1929 nul_info.tx_id = 0;
1930 nul_info.rx_id = 0;
1931
1932 id_entry = pdev->id_entry;
1933 if (!id_entry) {
1934 dev_err(&pdev->dev, "unknown fsi device\n");
1935 return -ENODEV;
1936 }
1937
1938 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1939 irq = platform_get_irq(pdev, 0);
1940 if (!res || (int)irq <= 0) {
1941 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1942 return -ENODEV;
1943 }
1944
1945 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1946 if (!master) {
1947 dev_err(&pdev->dev, "Could not allocate master\n");
1948 return -ENOMEM;
1949 }
1950
1951 master->base = devm_ioremap_nocache(&pdev->dev,
1952 res->start, resource_size(res));
1953 if (!master->base) {
1954 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1955 return -ENXIO;
1956 }
1957
1958 /* master setting */
1959 master->irq = irq;
1960 master->core = (struct fsi_core *)id_entry->driver_data;
1961 spin_lock_init(&master->lock);
1962
1963 /* FSI A setting */
1964 pinfo = (info) ? &info->port_a : &nul_info;
1965 fsi = &master->fsia;
1966 fsi->base = master->base;
1967 fsi->master = master;
1968 fsi_port_info_init(fsi, pinfo);
1969 fsi_handler_init(fsi, pinfo);
1970 ret = fsi_stream_probe(fsi, &pdev->dev);
1971 if (ret < 0) {
1972 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1973 return ret;
1974 }
1975
1976 /* FSI B setting */
1977 pinfo = (info) ? &info->port_b : &nul_info;
1978 fsi = &master->fsib;
1979 fsi->base = master->base + 0x40;
1980 fsi->master = master;
1981 fsi_port_info_init(fsi, pinfo);
1982 fsi_handler_init(fsi, pinfo);
1983 ret = fsi_stream_probe(fsi, &pdev->dev);
1984 if (ret < 0) {
1985 dev_err(&pdev->dev, "FSIB stream probe failed\n");
1986 goto exit_fsia;
1987 }
1988
1989 pm_runtime_enable(&pdev->dev);
1990 dev_set_drvdata(&pdev->dev, master);
1991
1992 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
1993 id_entry->name, master);
1994 if (ret) {
1995 dev_err(&pdev->dev, "irq request err\n");
1996 goto exit_fsib;
1997 }
1998
1999 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
2000 if (ret < 0) {
2001 dev_err(&pdev->dev, "cannot snd soc register\n");
2002 goto exit_fsib;
2003 }
2004
2005 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
2006 ARRAY_SIZE(fsi_soc_dai));
2007 if (ret < 0) {
2008 dev_err(&pdev->dev, "cannot snd dai register\n");
2009 goto exit_snd_soc;
2010 }
2011
2012 return ret;
2013
2014 exit_snd_soc:
2015 snd_soc_unregister_platform(&pdev->dev);
2016 exit_fsib:
2017 pm_runtime_disable(&pdev->dev);
2018 fsi_stream_remove(&master->fsib);
2019 exit_fsia:
2020 fsi_stream_remove(&master->fsia);
2021
2022 return ret;
2023 }
2024
2025 static int fsi_remove(struct platform_device *pdev)
2026 {
2027 struct fsi_master *master;
2028
2029 master = dev_get_drvdata(&pdev->dev);
2030
2031 pm_runtime_disable(&pdev->dev);
2032
2033 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
2034 snd_soc_unregister_platform(&pdev->dev);
2035
2036 fsi_stream_remove(&master->fsia);
2037 fsi_stream_remove(&master->fsib);
2038
2039 return 0;
2040 }
2041
2042 static void __fsi_suspend(struct fsi_priv *fsi,
2043 struct fsi_stream *io,
2044 struct device *dev)
2045 {
2046 if (!fsi_stream_is_working(fsi, io))
2047 return;
2048
2049 fsi_stream_stop(fsi, io);
2050 fsi_hw_shutdown(fsi, dev);
2051 }
2052
2053 static void __fsi_resume(struct fsi_priv *fsi,
2054 struct fsi_stream *io,
2055 struct device *dev)
2056 {
2057 if (!fsi_stream_is_working(fsi, io))
2058 return;
2059
2060 fsi_hw_startup(fsi, io, dev);
2061 fsi_stream_start(fsi, io);
2062 }
2063
2064 static int fsi_suspend(struct device *dev)
2065 {
2066 struct fsi_master *master = dev_get_drvdata(dev);
2067 struct fsi_priv *fsia = &master->fsia;
2068 struct fsi_priv *fsib = &master->fsib;
2069
2070 __fsi_suspend(fsia, &fsia->playback, dev);
2071 __fsi_suspend(fsia, &fsia->capture, dev);
2072
2073 __fsi_suspend(fsib, &fsib->playback, dev);
2074 __fsi_suspend(fsib, &fsib->capture, dev);
2075
2076 return 0;
2077 }
2078
2079 static int fsi_resume(struct device *dev)
2080 {
2081 struct fsi_master *master = dev_get_drvdata(dev);
2082 struct fsi_priv *fsia = &master->fsia;
2083 struct fsi_priv *fsib = &master->fsib;
2084
2085 __fsi_resume(fsia, &fsia->playback, dev);
2086 __fsi_resume(fsia, &fsia->capture, dev);
2087
2088 __fsi_resume(fsib, &fsib->playback, dev);
2089 __fsi_resume(fsib, &fsib->capture, dev);
2090
2091 return 0;
2092 }
2093
2094 static struct dev_pm_ops fsi_pm_ops = {
2095 .suspend = fsi_suspend,
2096 .resume = fsi_resume,
2097 };
2098
2099 static struct fsi_core fsi1_core = {
2100 .ver = 1,
2101
2102 /* Interrupt */
2103 .int_st = INT_ST,
2104 .iemsk = IEMSK,
2105 .imsk = IMSK,
2106 };
2107
2108 static struct fsi_core fsi2_core = {
2109 .ver = 2,
2110
2111 /* Interrupt */
2112 .int_st = CPU_INT_ST,
2113 .iemsk = CPU_IEMSK,
2114 .imsk = CPU_IMSK,
2115 .a_mclk = A_MST_CTLR,
2116 .b_mclk = B_MST_CTLR,
2117 };
2118
2119 static struct platform_device_id fsi_id_table[] = {
2120 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
2121 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
2122 {},
2123 };
2124 MODULE_DEVICE_TABLE(platform, fsi_id_table);
2125
2126 static struct platform_driver fsi_driver = {
2127 .driver = {
2128 .name = "fsi-pcm-audio",
2129 .pm = &fsi_pm_ops,
2130 },
2131 .probe = fsi_probe,
2132 .remove = fsi_remove,
2133 .id_table = fsi_id_table,
2134 };
2135
2136 module_platform_driver(fsi_driver);
2137
2138 MODULE_LICENSE("GPL");
2139 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2140 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2141 MODULE_ALIAS("platform:fsi-pcm-audio");
Linux kernel - Deliverables
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