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Merge branch 'master' of /pub/scm/linux/kernel/git/jejb/scsi-post-merge-2.6 into...
[deliverable/linux.git] / sound / soc / sh / fsi.c
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
35
36 /* master register */
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
40
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200
48 #define IEMSK 0x0204
49 #define IMSK 0x0208
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
81
82 /* A/B MST_CTLR */
83 #define BP (1 << 4) /* Fix the signal of Biphase output */
84 #define SE (1 << 0) /* Fix the master clock */
85
86 /* CLK_RST */
87 #define B_CLK 0x00000010
88 #define A_CLK 0x00000001
89
90 /* IO SHIFT / MACRO */
91 #define BI_SHIFT 12
92 #define BO_SHIFT 8
93 #define AI_SHIFT 4
94 #define AO_SHIFT 0
95 #define AB_IO(param, shift) (param << shift)
96
97 /* SOFT_RST */
98 #define PBSR (1 << 12) /* Port B Software Reset */
99 #define PASR (1 << 8) /* Port A Software Reset */
100 #define IR (1 << 4) /* Interrupt Reset */
101 #define FSISR (1 << 0) /* Software Reset */
102
103 /* OUT_SEL (FSI2) */
104 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
105 /* 1: Biphase and serial */
106
107 /* FIFO_SZ */
108 #define FIFO_SZ_MASK 0x7
109
110 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
111
112 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
113
114 /*
115 * FSI driver use below type name for variable
116 *
117 * xxx_len : data length
118 * xxx_width : data width
119 * xxx_offset : data offset
120 * xxx_num : number of data
121 */
122
123 /*
124 * struct
125 */
126
127 struct fsi_stream {
128 struct snd_pcm_substream *substream;
129
130 int fifo_max_num;
131 int chan_num;
132
133 int buff_offset;
134 int buff_len;
135 int period_len;
136 int period_num;
137
138 int uerr_num;
139 int oerr_num;
140 };
141
142 struct fsi_priv {
143 void __iomem *base;
144 struct fsi_master *master;
145
146 struct fsi_stream playback;
147 struct fsi_stream capture;
148
149 long rate;
150 };
151
152 struct fsi_core {
153 int ver;
154
155 u32 int_st;
156 u32 iemsk;
157 u32 imsk;
158 u32 a_mclk;
159 u32 b_mclk;
160 };
161
162 struct fsi_master {
163 void __iomem *base;
164 int irq;
165 struct fsi_priv fsia;
166 struct fsi_priv fsib;
167 struct fsi_core *core;
168 struct sh_fsi_platform_info *info;
169 spinlock_t lock;
170 };
171
172 /*
173 * basic read write function
174 */
175
176 static void __fsi_reg_write(u32 reg, u32 data)
177 {
178 /* valid data area is 24bit */
179 data &= 0x00ffffff;
180
181 __raw_writel(data, reg);
182 }
183
184 static u32 __fsi_reg_read(u32 reg)
185 {
186 return __raw_readl(reg);
187 }
188
189 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
190 {
191 u32 val = __fsi_reg_read(reg);
192
193 val &= ~mask;
194 val |= data & mask;
195
196 __fsi_reg_write(reg, val);
197 }
198
199 #define fsi_reg_write(p, r, d)\
200 __fsi_reg_write((u32)(p->base + REG_##r), d)
201
202 #define fsi_reg_read(p, r)\
203 __fsi_reg_read((u32)(p->base + REG_##r))
204
205 #define fsi_reg_mask_set(p, r, m, d)\
206 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
207
208 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
209 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
210 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
211 {
212 u32 ret;
213 unsigned long flags;
214
215 spin_lock_irqsave(&master->lock, flags);
216 ret = __fsi_reg_read((u32)(master->base + reg));
217 spin_unlock_irqrestore(&master->lock, flags);
218
219 return ret;
220 }
221
222 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
223 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
224 static void _fsi_master_mask_set(struct fsi_master *master,
225 u32 reg, u32 mask, u32 data)
226 {
227 unsigned long flags;
228
229 spin_lock_irqsave(&master->lock, flags);
230 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
231 spin_unlock_irqrestore(&master->lock, flags);
232 }
233
234 /*
235 * basic function
236 */
237
238 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
239 {
240 return fsi->master;
241 }
242
243 static int fsi_is_port_a(struct fsi_priv *fsi)
244 {
245 return fsi->master->base == fsi->base;
246 }
247
248 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
249 {
250 struct snd_soc_pcm_runtime *rtd = substream->private_data;
251
252 return rtd->cpu_dai;
253 }
254
255 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
256 {
257 struct snd_soc_dai *dai = fsi_get_dai(substream);
258 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
259
260 if (dai->id == 0)
261 return &master->fsia;
262 else
263 return &master->fsib;
264 }
265
266 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
267 {
268 int is_porta = fsi_is_port_a(fsi);
269 struct fsi_master *master = fsi_get_master(fsi);
270
271 return is_porta ? master->info->porta_flags :
272 master->info->portb_flags;
273 }
274
275 static inline int fsi_stream_is_play(int stream)
276 {
277 return stream == SNDRV_PCM_STREAM_PLAYBACK;
278 }
279
280 static inline int fsi_is_play(struct snd_pcm_substream *substream)
281 {
282 return fsi_stream_is_play(substream->stream);
283 }
284
285 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
286 int is_play)
287 {
288 return is_play ? &fsi->playback : &fsi->capture;
289 }
290
291 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
292 {
293 u32 mode;
294 u32 flags = fsi_get_info_flags(fsi);
295
296 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
297
298 /* return
299 * 1 : master mode
300 * 0 : slave mode
301 */
302
303 return (mode & flags) != mode;
304 }
305
306 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
307 {
308 int is_porta = fsi_is_port_a(fsi);
309 u32 shift;
310
311 if (is_porta)
312 shift = is_play ? AO_SHIFT : AI_SHIFT;
313 else
314 shift = is_play ? BO_SHIFT : BI_SHIFT;
315
316 return shift;
317 }
318
319 static void fsi_stream_push(struct fsi_priv *fsi,
320 int is_play,
321 struct snd_pcm_substream *substream,
322 u32 buffer_len,
323 u32 period_len)
324 {
325 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
326
327 io->substream = substream;
328 io->buff_len = buffer_len;
329 io->buff_offset = 0;
330 io->period_len = period_len;
331 io->period_num = 0;
332 io->oerr_num = -1; /* ignore 1st err */
333 io->uerr_num = -1; /* ignore 1st err */
334 }
335
336 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
337 {
338 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
339 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
340
341
342 if (io->oerr_num > 0)
343 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
344
345 if (io->uerr_num > 0)
346 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
347
348 io->substream = NULL;
349 io->buff_len = 0;
350 io->buff_offset = 0;
351 io->period_len = 0;
352 io->period_num = 0;
353 io->oerr_num = 0;
354 io->uerr_num = 0;
355 }
356
357 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
358 {
359 u32 status;
360 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
361 int data_num;
362
363 status = is_play ?
364 fsi_reg_read(fsi, DOFF_ST) :
365 fsi_reg_read(fsi, DIFF_ST);
366
367 data_num = 0x1ff & (status >> 8);
368 data_num *= io->chan_num;
369
370 return data_num;
371 }
372
373 static int fsi_len2num(int len, int width)
374 {
375 return len / width;
376 }
377
378 #define fsi_num2offset(a, b) fsi_num2len(a, b)
379 static int fsi_num2len(int num, int width)
380 {
381 return num * width;
382 }
383
384 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
385 {
386 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
387 struct snd_pcm_substream *substream = io->substream;
388 struct snd_pcm_runtime *runtime = substream->runtime;
389
390 return frames_to_bytes(runtime, 1) / io->chan_num;
391 }
392
393 static void fsi_count_fifo_err(struct fsi_priv *fsi)
394 {
395 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
396 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
397
398 if (ostatus & ERR_OVER)
399 fsi->playback.oerr_num++;
400
401 if (ostatus & ERR_UNDER)
402 fsi->playback.uerr_num++;
403
404 if (istatus & ERR_OVER)
405 fsi->capture.oerr_num++;
406
407 if (istatus & ERR_UNDER)
408 fsi->capture.uerr_num++;
409
410 fsi_reg_write(fsi, DOFF_ST, 0);
411 fsi_reg_write(fsi, DIFF_ST, 0);
412 }
413
414 /*
415 * dma function
416 */
417
418 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
419 {
420 int is_play = fsi_stream_is_play(stream);
421 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
422
423 return io->substream->runtime->dma_area + io->buff_offset;
424 }
425
426 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
427 {
428 u16 *start;
429 int i;
430
431 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
432
433 for (i = 0; i < num; i++)
434 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
435 }
436
437 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
438 {
439 u16 *start;
440 int i;
441
442 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
443
444
445 for (i = 0; i < num; i++)
446 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
447 }
448
449 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
450 {
451 u32 *start;
452 int i;
453
454 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
455
456
457 for (i = 0; i < num; i++)
458 fsi_reg_write(fsi, DODT, *(start + i));
459 }
460
461 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
462 {
463 u32 *start;
464 int i;
465
466 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
467
468 for (i = 0; i < num; i++)
469 *(start + i) = fsi_reg_read(fsi, DIDT);
470 }
471
472 /*
473 * irq function
474 */
475
476 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
477 {
478 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
479 struct fsi_master *master = fsi_get_master(fsi);
480
481 fsi_core_mask_set(master, imsk, data, data);
482 fsi_core_mask_set(master, iemsk, data, data);
483 }
484
485 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
486 {
487 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
488 struct fsi_master *master = fsi_get_master(fsi);
489
490 fsi_core_mask_set(master, imsk, data, 0);
491 fsi_core_mask_set(master, iemsk, data, 0);
492 }
493
494 static u32 fsi_irq_get_status(struct fsi_master *master)
495 {
496 return fsi_core_read(master, int_st);
497 }
498
499 static void fsi_irq_clear_status(struct fsi_priv *fsi)
500 {
501 u32 data = 0;
502 struct fsi_master *master = fsi_get_master(fsi);
503
504 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
505 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
506
507 /* clear interrupt factor */
508 fsi_core_mask_set(master, int_st, data, 0);
509 }
510
511 /*
512 * SPDIF master clock function
513 *
514 * These functions are used later FSI2
515 */
516 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
517 {
518 struct fsi_master *master = fsi_get_master(fsi);
519 u32 mask, val;
520
521 if (master->core->ver < 2) {
522 pr_err("fsi: register access err (%s)\n", __func__);
523 return;
524 }
525
526 mask = BP | SE;
527 val = enable ? mask : 0;
528
529 fsi_is_port_a(fsi) ?
530 fsi_core_mask_set(master, a_mclk, mask, val) :
531 fsi_core_mask_set(master, b_mclk, mask, val);
532 }
533
534 /*
535 * ctrl function
536 */
537
538 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
539 {
540 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
541 struct fsi_master *master = fsi_get_master(fsi);
542
543 if (enable)
544 fsi_master_mask_set(master, CLK_RST, val, val);
545 else
546 fsi_master_mask_set(master, CLK_RST, val, 0);
547 }
548
549 static void fsi_fifo_init(struct fsi_priv *fsi,
550 int is_play,
551 struct snd_soc_dai *dai)
552 {
553 struct fsi_master *master = fsi_get_master(fsi);
554 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
555 u32 shift, i;
556
557 /* get on-chip RAM capacity */
558 shift = fsi_master_read(master, FIFO_SZ);
559 shift >>= fsi_get_port_shift(fsi, is_play);
560 shift &= FIFO_SZ_MASK;
561 io->fifo_max_num = 256 << shift;
562 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
563
564 /*
565 * The maximum number of sample data varies depending
566 * on the number of channels selected for the format.
567 *
568 * FIFOs are used in 4-channel units in 3-channel mode
569 * and in 8-channel units in 5- to 7-channel mode
570 * meaning that more FIFOs than the required size of DPRAM
571 * are used.
572 *
573 * ex) if 256 words of DP-RAM is connected
574 * 1 channel: 256 (256 x 1 = 256)
575 * 2 channels: 128 (128 x 2 = 256)
576 * 3 channels: 64 ( 64 x 3 = 192)
577 * 4 channels: 64 ( 64 x 4 = 256)
578 * 5 channels: 32 ( 32 x 5 = 160)
579 * 6 channels: 32 ( 32 x 6 = 192)
580 * 7 channels: 32 ( 32 x 7 = 224)
581 * 8 channels: 32 ( 32 x 8 = 256)
582 */
583 for (i = 1; i < io->chan_num; i <<= 1)
584 io->fifo_max_num >>= 1;
585 dev_dbg(dai->dev, "%d channel %d store\n",
586 io->chan_num, io->fifo_max_num);
587
588 /*
589 * set interrupt generation factor
590 * clear FIFO
591 */
592 if (is_play) {
593 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
594 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
595 } else {
596 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
597 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
598 }
599 }
600
601 static void fsi_soft_all_reset(struct fsi_master *master)
602 {
603 /* port AB reset */
604 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
605 mdelay(10);
606
607 /* soft reset */
608 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
609 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
610 mdelay(10);
611 }
612
613 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
614 {
615 struct snd_pcm_runtime *runtime;
616 struct snd_pcm_substream *substream = NULL;
617 int is_play = fsi_stream_is_play(stream);
618 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
619 int data_residue_num;
620 int data_num;
621 int data_num_max;
622 int ch_width;
623 int over_period;
624 void (*fn)(struct fsi_priv *fsi, int size);
625
626 if (!fsi ||
627 !io->substream ||
628 !io->substream->runtime)
629 return -EINVAL;
630
631 over_period = 0;
632 substream = io->substream;
633 runtime = substream->runtime;
634
635 /* FSI FIFO has limit.
636 * So, this driver can not send periods data at a time
637 */
638 if (io->buff_offset >=
639 fsi_num2offset(io->period_num + 1, io->period_len)) {
640
641 over_period = 1;
642 io->period_num = (io->period_num + 1) % runtime->periods;
643
644 if (0 == io->period_num)
645 io->buff_offset = 0;
646 }
647
648 /* get 1 channel data width */
649 ch_width = fsi_get_frame_width(fsi, is_play);
650
651 /* get residue data number of alsa */
652 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
653 ch_width);
654
655 if (is_play) {
656 /*
657 * for play-back
658 *
659 * data_num_max : number of FSI fifo free space
660 * data_num : number of ALSA residue data
661 */
662 data_num_max = io->fifo_max_num * io->chan_num;
663 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
664
665 data_num = data_residue_num;
666
667 switch (ch_width) {
668 case 2:
669 fn = fsi_dma_soft_push16;
670 break;
671 case 4:
672 fn = fsi_dma_soft_push32;
673 break;
674 default:
675 return -EINVAL;
676 }
677 } else {
678 /*
679 * for capture
680 *
681 * data_num_max : number of ALSA free space
682 * data_num : number of data in FSI fifo
683 */
684 data_num_max = data_residue_num;
685 data_num = fsi_get_fifo_data_num(fsi, is_play);
686
687 switch (ch_width) {
688 case 2:
689 fn = fsi_dma_soft_pop16;
690 break;
691 case 4:
692 fn = fsi_dma_soft_pop32;
693 break;
694 default:
695 return -EINVAL;
696 }
697 }
698
699 data_num = min(data_num, data_num_max);
700
701 fn(fsi, data_num);
702
703 /* update buff_offset */
704 io->buff_offset += fsi_num2offset(data_num, ch_width);
705
706 if (over_period)
707 snd_pcm_period_elapsed(substream);
708
709 return 0;
710 }
711
712 static int fsi_data_pop(struct fsi_priv *fsi)
713 {
714 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
715 }
716
717 static int fsi_data_push(struct fsi_priv *fsi)
718 {
719 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
720 }
721
722 static irqreturn_t fsi_interrupt(int irq, void *data)
723 {
724 struct fsi_master *master = data;
725 u32 int_st = fsi_irq_get_status(master);
726
727 /* clear irq status */
728 fsi_master_mask_set(master, SOFT_RST, IR, 0);
729 fsi_master_mask_set(master, SOFT_RST, IR, IR);
730
731 if (int_st & AB_IO(1, AO_SHIFT))
732 fsi_data_push(&master->fsia);
733 if (int_st & AB_IO(1, BO_SHIFT))
734 fsi_data_push(&master->fsib);
735 if (int_st & AB_IO(1, AI_SHIFT))
736 fsi_data_pop(&master->fsia);
737 if (int_st & AB_IO(1, BI_SHIFT))
738 fsi_data_pop(&master->fsib);
739
740 fsi_count_fifo_err(&master->fsia);
741 fsi_count_fifo_err(&master->fsib);
742
743 fsi_irq_clear_status(&master->fsia);
744 fsi_irq_clear_status(&master->fsib);
745
746 return IRQ_HANDLED;
747 }
748
749 /*
750 * dai ops
751 */
752
753 static int fsi_dai_startup(struct snd_pcm_substream *substream,
754 struct snd_soc_dai *dai)
755 {
756 struct fsi_priv *fsi = fsi_get_priv(substream);
757 struct fsi_master *master = fsi_get_master(fsi);
758 struct fsi_stream *io;
759 u32 flags = fsi_get_info_flags(fsi);
760 u32 fmt;
761 u32 data;
762 int is_play = fsi_is_play(substream);
763 int is_master;
764
765 io = fsi_get_stream(fsi, is_play);
766
767 pm_runtime_get_sync(dai->dev);
768
769 /* CKG1 */
770 data = is_play ? (1 << 0) : (1 << 4);
771 is_master = fsi_is_master_mode(fsi, is_play);
772 if (is_master)
773 fsi_reg_mask_set(fsi, CKG1, data, data);
774 else
775 fsi_reg_mask_set(fsi, CKG1, data, 0);
776
777 /* clock inversion (CKG2) */
778 data = 0;
779 if (SH_FSI_LRM_INV & flags)
780 data |= 1 << 12;
781 if (SH_FSI_BRM_INV & flags)
782 data |= 1 << 8;
783 if (SH_FSI_LRS_INV & flags)
784 data |= 1 << 4;
785 if (SH_FSI_BRS_INV & flags)
786 data |= 1 << 0;
787
788 fsi_reg_write(fsi, CKG2, data);
789
790 /* do fmt, di fmt */
791 data = 0;
792 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
793 switch (fmt) {
794 case SH_FSI_FMT_MONO:
795 data = CR_MONO;
796 io->chan_num = 1;
797 break;
798 case SH_FSI_FMT_MONO_DELAY:
799 data = CR_MONO_D;
800 io->chan_num = 1;
801 break;
802 case SH_FSI_FMT_PCM:
803 data = CR_PCM;
804 io->chan_num = 2;
805 break;
806 case SH_FSI_FMT_I2S:
807 data = CR_I2S;
808 io->chan_num = 2;
809 break;
810 case SH_FSI_FMT_TDM:
811 io->chan_num = is_play ?
812 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
813 data = CR_TDM | (io->chan_num - 1);
814 break;
815 case SH_FSI_FMT_TDM_DELAY:
816 io->chan_num = is_play ?
817 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
818 data = CR_TDM_D | (io->chan_num - 1);
819 break;
820 case SH_FSI_FMT_SPDIF:
821 if (master->core->ver < 2) {
822 dev_err(dai->dev, "This FSI can not use SPDIF\n");
823 return -EINVAL;
824 }
825 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
826 io->chan_num = 2;
827 fsi_spdif_clk_ctrl(fsi, 1);
828 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
829 break;
830 default:
831 dev_err(dai->dev, "unknown format.\n");
832 return -EINVAL;
833 }
834 is_play ?
835 fsi_reg_write(fsi, DO_FMT, data) :
836 fsi_reg_write(fsi, DI_FMT, data);
837
838 /* irq clear */
839 fsi_irq_disable(fsi, is_play);
840 fsi_irq_clear_status(fsi);
841
842 /* fifo init */
843 fsi_fifo_init(fsi, is_play, dai);
844
845 return 0;
846 }
847
848 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
849 struct snd_soc_dai *dai)
850 {
851 struct fsi_priv *fsi = fsi_get_priv(substream);
852 int is_play = fsi_is_play(substream);
853 struct fsi_master *master = fsi_get_master(fsi);
854 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
855
856 fsi_irq_disable(fsi, is_play);
857 fsi_clk_ctrl(fsi, 0);
858
859 set_rate = master->info->set_rate;
860 if (set_rate && fsi->rate)
861 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
862 fsi->rate = 0;
863
864 pm_runtime_put_sync(dai->dev);
865 }
866
867 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
868 struct snd_soc_dai *dai)
869 {
870 struct fsi_priv *fsi = fsi_get_priv(substream);
871 struct snd_pcm_runtime *runtime = substream->runtime;
872 int is_play = fsi_is_play(substream);
873 int ret = 0;
874
875 switch (cmd) {
876 case SNDRV_PCM_TRIGGER_START:
877 fsi_stream_push(fsi, is_play, substream,
878 frames_to_bytes(runtime, runtime->buffer_size),
879 frames_to_bytes(runtime, runtime->period_size));
880 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
881 fsi_irq_enable(fsi, is_play);
882 break;
883 case SNDRV_PCM_TRIGGER_STOP:
884 fsi_irq_disable(fsi, is_play);
885 fsi_stream_pop(fsi, is_play);
886 break;
887 }
888
889 return ret;
890 }
891
892 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
893 struct snd_pcm_hw_params *params,
894 struct snd_soc_dai *dai)
895 {
896 struct fsi_priv *fsi = fsi_get_priv(substream);
897 struct fsi_master *master = fsi_get_master(fsi);
898 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
899 int fsi_ver = master->core->ver;
900 long rate = params_rate(params);
901 int ret;
902
903 set_rate = master->info->set_rate;
904 if (!set_rate)
905 return 0;
906
907 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
908 if (ret < 0) /* error */
909 return ret;
910
911 fsi->rate = rate;
912 if (ret > 0) {
913 u32 data = 0;
914
915 switch (ret & SH_FSI_ACKMD_MASK) {
916 default:
917 /* FALL THROUGH */
918 case SH_FSI_ACKMD_512:
919 data |= (0x0 << 12);
920 break;
921 case SH_FSI_ACKMD_256:
922 data |= (0x1 << 12);
923 break;
924 case SH_FSI_ACKMD_128:
925 data |= (0x2 << 12);
926 break;
927 case SH_FSI_ACKMD_64:
928 data |= (0x3 << 12);
929 break;
930 case SH_FSI_ACKMD_32:
931 if (fsi_ver < 2)
932 dev_err(dai->dev, "unsupported ACKMD\n");
933 else
934 data |= (0x4 << 12);
935 break;
936 }
937
938 switch (ret & SH_FSI_BPFMD_MASK) {
939 default:
940 /* FALL THROUGH */
941 case SH_FSI_BPFMD_32:
942 data |= (0x0 << 8);
943 break;
944 case SH_FSI_BPFMD_64:
945 data |= (0x1 << 8);
946 break;
947 case SH_FSI_BPFMD_128:
948 data |= (0x2 << 8);
949 break;
950 case SH_FSI_BPFMD_256:
951 data |= (0x3 << 8);
952 break;
953 case SH_FSI_BPFMD_512:
954 data |= (0x4 << 8);
955 break;
956 case SH_FSI_BPFMD_16:
957 if (fsi_ver < 2)
958 dev_err(dai->dev, "unsupported ACKMD\n");
959 else
960 data |= (0x7 << 8);
961 break;
962 }
963
964 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
965 udelay(10);
966 fsi_clk_ctrl(fsi, 1);
967 ret = 0;
968 }
969
970 return ret;
971
972 }
973
974 static struct snd_soc_dai_ops fsi_dai_ops = {
975 .startup = fsi_dai_startup,
976 .shutdown = fsi_dai_shutdown,
977 .trigger = fsi_dai_trigger,
978 .hw_params = fsi_dai_hw_params,
979 };
980
981 /*
982 * pcm ops
983 */
984
985 static struct snd_pcm_hardware fsi_pcm_hardware = {
986 .info = SNDRV_PCM_INFO_INTERLEAVED |
987 SNDRV_PCM_INFO_MMAP |
988 SNDRV_PCM_INFO_MMAP_VALID |
989 SNDRV_PCM_INFO_PAUSE,
990 .formats = FSI_FMTS,
991 .rates = FSI_RATES,
992 .rate_min = 8000,
993 .rate_max = 192000,
994 .channels_min = 1,
995 .channels_max = 2,
996 .buffer_bytes_max = 64 * 1024,
997 .period_bytes_min = 32,
998 .period_bytes_max = 8192,
999 .periods_min = 1,
1000 .periods_max = 32,
1001 .fifo_size = 256,
1002 };
1003
1004 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1005 {
1006 struct snd_pcm_runtime *runtime = substream->runtime;
1007 int ret = 0;
1008
1009 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1010
1011 ret = snd_pcm_hw_constraint_integer(runtime,
1012 SNDRV_PCM_HW_PARAM_PERIODS);
1013
1014 return ret;
1015 }
1016
1017 static int fsi_hw_params(struct snd_pcm_substream *substream,
1018 struct snd_pcm_hw_params *hw_params)
1019 {
1020 return snd_pcm_lib_malloc_pages(substream,
1021 params_buffer_bytes(hw_params));
1022 }
1023
1024 static int fsi_hw_free(struct snd_pcm_substream *substream)
1025 {
1026 return snd_pcm_lib_free_pages(substream);
1027 }
1028
1029 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1030 {
1031 struct snd_pcm_runtime *runtime = substream->runtime;
1032 struct fsi_priv *fsi = fsi_get_priv(substream);
1033 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1034 long location;
1035
1036 location = (io->buff_offset - 1);
1037 if (location < 0)
1038 location = 0;
1039
1040 return bytes_to_frames(runtime, location);
1041 }
1042
1043 static struct snd_pcm_ops fsi_pcm_ops = {
1044 .open = fsi_pcm_open,
1045 .ioctl = snd_pcm_lib_ioctl,
1046 .hw_params = fsi_hw_params,
1047 .hw_free = fsi_hw_free,
1048 .pointer = fsi_pointer,
1049 };
1050
1051 /*
1052 * snd_soc_platform
1053 */
1054
1055 #define PREALLOC_BUFFER (32 * 1024)
1056 #define PREALLOC_BUFFER_MAX (32 * 1024)
1057
1058 static void fsi_pcm_free(struct snd_pcm *pcm)
1059 {
1060 snd_pcm_lib_preallocate_free_for_all(pcm);
1061 }
1062
1063 static int fsi_pcm_new(struct snd_card *card,
1064 struct snd_soc_dai *dai,
1065 struct snd_pcm *pcm)
1066 {
1067 /*
1068 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1069 * in MMAP mode (i.e. aplay -M)
1070 */
1071 return snd_pcm_lib_preallocate_pages_for_all(
1072 pcm,
1073 SNDRV_DMA_TYPE_CONTINUOUS,
1074 snd_dma_continuous_data(GFP_KERNEL),
1075 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1076 }
1077
1078 /*
1079 * alsa struct
1080 */
1081
1082 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1083 {
1084 .name = "fsia-dai",
1085 .playback = {
1086 .rates = FSI_RATES,
1087 .formats = FSI_FMTS,
1088 .channels_min = 1,
1089 .channels_max = 8,
1090 },
1091 .capture = {
1092 .rates = FSI_RATES,
1093 .formats = FSI_FMTS,
1094 .channels_min = 1,
1095 .channels_max = 8,
1096 },
1097 .ops = &fsi_dai_ops,
1098 },
1099 {
1100 .name = "fsib-dai",
1101 .playback = {
1102 .rates = FSI_RATES,
1103 .formats = FSI_FMTS,
1104 .channels_min = 1,
1105 .channels_max = 8,
1106 },
1107 .capture = {
1108 .rates = FSI_RATES,
1109 .formats = FSI_FMTS,
1110 .channels_min = 1,
1111 .channels_max = 8,
1112 },
1113 .ops = &fsi_dai_ops,
1114 },
1115 };
1116
1117 static struct snd_soc_platform_driver fsi_soc_platform = {
1118 .ops = &fsi_pcm_ops,
1119 .pcm_new = fsi_pcm_new,
1120 .pcm_free = fsi_pcm_free,
1121 };
1122
1123 /*
1124 * platform function
1125 */
1126
1127 static int fsi_probe(struct platform_device *pdev)
1128 {
1129 struct fsi_master *master;
1130 const struct platform_device_id *id_entry;
1131 struct resource *res;
1132 unsigned int irq;
1133 int ret;
1134
1135 id_entry = pdev->id_entry;
1136 if (!id_entry) {
1137 dev_err(&pdev->dev, "unknown fsi device\n");
1138 return -ENODEV;
1139 }
1140
1141 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1142 irq = platform_get_irq(pdev, 0);
1143 if (!res || (int)irq <= 0) {
1144 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1145 ret = -ENODEV;
1146 goto exit;
1147 }
1148
1149 master = kzalloc(sizeof(*master), GFP_KERNEL);
1150 if (!master) {
1151 dev_err(&pdev->dev, "Could not allocate master\n");
1152 ret = -ENOMEM;
1153 goto exit;
1154 }
1155
1156 master->base = ioremap_nocache(res->start, resource_size(res));
1157 if (!master->base) {
1158 ret = -ENXIO;
1159 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1160 goto exit_kfree;
1161 }
1162
1163 /* master setting */
1164 master->irq = irq;
1165 master->info = pdev->dev.platform_data;
1166 master->core = (struct fsi_core *)id_entry->driver_data;
1167 spin_lock_init(&master->lock);
1168
1169 /* FSI A setting */
1170 master->fsia.base = master->base;
1171 master->fsia.master = master;
1172
1173 /* FSI B setting */
1174 master->fsib.base = master->base + 0x40;
1175 master->fsib.master = master;
1176
1177 pm_runtime_enable(&pdev->dev);
1178 pm_runtime_resume(&pdev->dev);
1179 dev_set_drvdata(&pdev->dev, master);
1180
1181 fsi_soft_all_reset(master);
1182
1183 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1184 id_entry->name, master);
1185 if (ret) {
1186 dev_err(&pdev->dev, "irq request err\n");
1187 goto exit_iounmap;
1188 }
1189
1190 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1191 if (ret < 0) {
1192 dev_err(&pdev->dev, "cannot snd soc register\n");
1193 goto exit_free_irq;
1194 }
1195
1196 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1197
1198 exit_free_irq:
1199 free_irq(irq, master);
1200 exit_iounmap:
1201 iounmap(master->base);
1202 pm_runtime_disable(&pdev->dev);
1203 exit_kfree:
1204 kfree(master);
1205 master = NULL;
1206 exit:
1207 return ret;
1208 }
1209
1210 static int fsi_remove(struct platform_device *pdev)
1211 {
1212 struct fsi_master *master;
1213
1214 master = dev_get_drvdata(&pdev->dev);
1215
1216 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1217 snd_soc_unregister_platform(&pdev->dev);
1218
1219 pm_runtime_disable(&pdev->dev);
1220
1221 free_irq(master->irq, master);
1222
1223 iounmap(master->base);
1224 kfree(master);
1225
1226 return 0;
1227 }
1228
1229 static int fsi_runtime_nop(struct device *dev)
1230 {
1231 /* Runtime PM callback shared between ->runtime_suspend()
1232 * and ->runtime_resume(). Simply returns success.
1233 *
1234 * This driver re-initializes all registers after
1235 * pm_runtime_get_sync() anyway so there is no need
1236 * to save and restore registers here.
1237 */
1238 return 0;
1239 }
1240
1241 static struct dev_pm_ops fsi_pm_ops = {
1242 .runtime_suspend = fsi_runtime_nop,
1243 .runtime_resume = fsi_runtime_nop,
1244 };
1245
1246 static struct fsi_core fsi1_core = {
1247 .ver = 1,
1248
1249 /* Interrupt */
1250 .int_st = INT_ST,
1251 .iemsk = IEMSK,
1252 .imsk = IMSK,
1253 };
1254
1255 static struct fsi_core fsi2_core = {
1256 .ver = 2,
1257
1258 /* Interrupt */
1259 .int_st = CPU_INT_ST,
1260 .iemsk = CPU_IEMSK,
1261 .imsk = CPU_IMSK,
1262 .a_mclk = A_MST_CTLR,
1263 .b_mclk = B_MST_CTLR,
1264 };
1265
1266 static struct platform_device_id fsi_id_table[] = {
1267 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1268 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1269 {},
1270 };
1271 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1272
1273 static struct platform_driver fsi_driver = {
1274 .driver = {
1275 .name = "fsi-pcm-audio",
1276 .pm = &fsi_pm_ops,
1277 },
1278 .probe = fsi_probe,
1279 .remove = fsi_remove,
1280 .id_table = fsi_id_table,
1281 };
1282
1283 static int __init fsi_mobile_init(void)
1284 {
1285 return platform_driver_register(&fsi_driver);
1286 }
1287
1288 static void __exit fsi_mobile_exit(void)
1289 {
1290 platform_driver_unregister(&fsi_driver);
1291 }
1292
1293 module_init(fsi_mobile_init);
1294 module_exit(fsi_mobile_exit);
1295
1296 MODULE_LICENSE("GPL");
1297 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1298 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
Linux kernel - Deliverables
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