sound/soc/sh/rcar/adg.c

   1 /*
   2  * Helper routines for R-Car sound ADG.
   3  *
   4  *  Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/sh_clk.h>
  11 #include "rsnd.h"
  12
  13 #define CLKA    0
  14 #define CLKB    1
  15 #define CLKC    2
  16 #define CLKI    3
  17 #define CLKMAX  4
  18
  19 struct rsnd_adg {
  20         struct clk *clk[CLKMAX];
  21
  22         int rbga_rate_for_441khz_div_6; /* RBGA */
  23         int rbgb_rate_for_48khz_div_6;  /* RBGB */
  24         u32 ckr;
  25 };
  26
  27 #define for_each_rsnd_clk(pos, adg, i)          \
  28         for (i = 0, (pos) = adg->clk[i];        \
  29              i < CLKMAX;                        \
  30              i++, (pos) = adg->clk[i])
  31 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  32
  33 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
  34                                   struct rsnd_mod *mod,
  35                                   unsigned int src_rate,
  36                                   unsigned int dst_rate)
  37 {
  38         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  39         struct device *dev = rsnd_priv_to_dev(priv);
  40         int idx, sel, div, shift;
  41         u32 mask, val;
  42         int id = rsnd_mod_id(mod);
  43         unsigned int sel_rate [] = {
  44                 clk_get_rate(adg->clk[CLKA]),   /* 000: CLKA */
  45                 clk_get_rate(adg->clk[CLKB]),   /* 001: CLKB */
  46                 clk_get_rate(adg->clk[CLKC]),   /* 010: CLKC */
  47                 0,                              /* 011: MLBCLK (not used) */
  48                 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
  49                 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
  50         };
  51
  52         /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
  53         for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
  54                 for (div  = 128,        idx = 0;
  55                      div <= 2048;
  56                      div *= 2,          idx++) {
  57                         if (src_rate == sel_rate[sel] / div) {
  58                                 val = (idx << 4) | sel;
  59                                 goto find_rate;
  60                         }
  61                 }
  62         }
  63         dev_err(dev, "can't find convert src clk\n");
  64         return -EINVAL;
  65
  66 find_rate:
  67         shift   = (id % 4) * 8;
  68         mask    = 0xFF << shift;
  69         val     = val << shift;
  70
  71         dev_dbg(dev, "adg convert src clk = %02x\n", val);
  72
  73         switch (id / 4) {
  74         case 0:
  75                 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
  76                 break;
  77         case 1:
  78                 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
  79                 break;
  80         case 2:
  81                 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
  82                 break;
  83         }
  84
  85         /*
  86          * Gen1 doesn't need dst_rate settings,
  87          * since it uses SSI WS pin.
  88          * see also rsnd_src_set_route_if_gen1()
  89          */
  90
  91         return 0;
  92 }
  93
  94 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
  95 {
  96         int id = rsnd_mod_id(mod);
  97         int shift = (id % 4) * 8;
  98         u32 mask = 0xFF << shift;
  99
 100         val = val << shift;
 101
 102         /*
 103          * SSI 8 is not connected to ADG.
 104          * it works with SSI 7
 105          */
 106         if (id == 8)
 107                 return;
 108
 109         switch (id / 4) {
 110         case 0:
 111                 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
 112                 break;
 113         case 1:
 114                 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
 115                 break;
 116         case 2:
 117                 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
 118                 break;
 119         }
 120 }
 121
 122 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
 123 {
 124         /*
 125          * "mod" = "ssi" here.
 126          * we can get "ssi id" from mod
 127          */
 128         rsnd_adg_set_ssi_clk(mod, 0);
 129
 130         return 0;
 131 }
 132
 133 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
 134 {
 135         struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
 136         struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
 137         struct device *dev = rsnd_priv_to_dev(priv);
 138         struct clk *clk;
 139         int i;
 140         u32 data;
 141         int sel_table[] = {
 142                 [CLKA] = 0x1,
 143                 [CLKB] = 0x2,
 144                 [CLKC] = 0x3,
 145                 [CLKI] = 0x0,
 146         };
 147
 148         dev_dbg(dev, "request clock = %d\n", rate);
 149
 150         /*
 151          * find suitable clock from
 152          * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
 153          */
 154         data = 0;
 155         for_each_rsnd_clk(clk, adg, i) {
 156                 if (rate == clk_get_rate(clk)) {
 157                         data = sel_table[i];
 158                         goto found_clock;
 159                 }
 160         }
 161
 162         /*
 163          * find 1/6 clock from BRGA/BRGB
 164          */
 165         if (rate == adg->rbga_rate_for_441khz_div_6) {
 166                 data = 0x10;
 167                 goto found_clock;
 168         }
 169
 170         if (rate == adg->rbgb_rate_for_48khz_div_6) {
 171                 data = 0x20;
 172                 goto found_clock;
 173         }
 174
 175         return -EIO;
 176
 177 found_clock:
 178
 179         /* see rsnd_adg_ssi_clk_init() */
 180         rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
 181         rsnd_mod_write(mod, BRRA,  0x00000002); /* 1/6 */
 182         rsnd_mod_write(mod, BRRB,  0x00000002); /* 1/6 */
 183
 184         /*
 185          * This "mod" = "ssi" here.
 186          * we can get "ssi id" from mod
 187          */
 188         rsnd_adg_set_ssi_clk(mod, data);
 189
 190         dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
 191                 rsnd_mod_id(mod), i, rate);
 192
 193         return 0;
 194 }
 195
 196 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
 197 {
 198         struct clk *clk;
 199         unsigned long rate;
 200         u32 ckr;
 201         int i;
 202         int brg_table[] = {
 203                 [CLKA] = 0x0,
 204                 [CLKB] = 0x1,
 205                 [CLKC] = 0x4,
 206                 [CLKI] = 0x2,
 207         };
 208
 209         /*
 210          * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
 211          * have 44.1kHz or 48kHz base clocks for now.
 212          *
 213          * SSI itself can divide parent clock by 1/1 - 1/16
 214          * So,  BRGA outputs 44.1kHz base parent clock 1/32,
 215          * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
 216          * see
 217          *      rsnd_adg_ssi_clk_try_start()
 218          */
 219         ckr = 0;
 220         adg->rbga_rate_for_441khz_div_6 = 0;
 221         adg->rbgb_rate_for_48khz_div_6  = 0;
 222         for_each_rsnd_clk(clk, adg, i) {
 223                 rate = clk_get_rate(clk);
 224
 225                 if (0 == rate) /* not used */
 226                         continue;
 227
 228                 /* RBGA */
 229                 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
 230                         adg->rbga_rate_for_441khz_div_6 = rate / 6;
 231                         ckr |= brg_table[i] << 20;
 232                 }
 233
 234                 /* RBGB */
 235                 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
 236                         adg->rbgb_rate_for_48khz_div_6 = rate / 6;
 237                         ckr |= brg_table[i] << 16;
 238                 }
 239         }
 240
 241         adg->ckr = ckr;
 242 }
 243
 244 int rsnd_adg_probe(struct platform_device *pdev,
 245                    struct rcar_snd_info *info,
 246                    struct rsnd_priv *priv)
 247 {
 248         struct rsnd_adg *adg;
 249         struct device *dev = rsnd_priv_to_dev(priv);
 250         struct clk *clk;
 251         int i;
 252
 253         adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
 254         if (!adg) {
 255                 dev_err(dev, "ADG allocate failed\n");
 256                 return -ENOMEM;
 257         }
 258
 259         adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
 260         adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
 261         adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
 262         adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
 263         for_each_rsnd_clk(clk, adg, i) {
 264                 if (IS_ERR(clk)) {
 265                         dev_err(dev, "Audio clock failed\n");
 266                         return -EIO;
 267                 }
 268         }
 269
 270         rsnd_adg_ssi_clk_init(priv, adg);
 271
 272         priv->adg = adg;
 273
 274         dev_dbg(dev, "adg probed\n");
 275
 276         return 0;
 277 }
 278
 279 void rsnd_adg_remove(struct platform_device *pdev,
 280                      struct rsnd_priv *priv)
 281 {
 282         struct rsnd_adg *adg = priv->adg;
 283         struct clk *clk;
 284         int i;
 285
 286         for_each_rsnd_clk(clk, adg, i)
 287                 clk_put(clk);
 288 }