tools/perf/Documentation/perf-list.txt

   1 perf-list(1)
   2 ============
   3
   4 NAME
   5 ----
   6 perf-list - List all symbolic event types
   7
   8 SYNOPSIS
   9 --------
  10 [verse]
  11 'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
  12
  13 DESCRIPTION
  14 -----------
  15 This command displays the symbolic event types which can be selected in the
  16 various perf commands with the -e option.
  17
  18 [[EVENT_MODIFIERS]]
  19 EVENT MODIFIERS
  20 ---------------
  21
  22 Events can optionally have a modifier by appending a colon and one or
  23 more modifiers. Modifiers allow the user to restrict the events to be
  24 counted. The following modifiers exist:
  25
  26  u - user-space counting
  27  k - kernel counting
  28  h - hypervisor counting
  29  I - non idle counting
  30  G - guest counting (in KVM guests)
  31  H - host counting (not in KVM guests)
  32  p - precise level
  33  P - use maximum detected precise level
  34  S - read sample value (PERF_SAMPLE_READ)
  35  D - pin the event to the PMU
  36
  37 The 'p' modifier can be used for specifying how precise the instruction
  38 address should be. The 'p' modifier can be specified multiple times:
  39
  40  0 - SAMPLE_IP can have arbitrary skid
  41  1 - SAMPLE_IP must have constant skid
  42  2 - SAMPLE_IP requested to have 0 skid
  43  3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
  44      sample shadowing effects.
  45
  46 For Intel systems precise event sampling is implemented with PEBS
  47 which supports up to precise-level 2, and precise level 3 for
  48 some special cases
  49
  50 On AMD systems it is implemented using IBS (up to precise-level 2).
  51 The precise modifier works with event types 0x76 (cpu-cycles, CPU
  52 clocks not halted) and 0xC1 (micro-ops retired). Both events map to
  53 IBS execution sampling (IBS op) with the IBS Op Counter Control bit
  54 (IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
  55 Manual Volume 2: System Programming, 13.3 Instruction-Based
  56 Sampling). Examples to use IBS:
  57
  58  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
  59  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
  60  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
  61
  62 RAW HARDWARE EVENT DESCRIPTOR
  63 -----------------------------
  64 Even when an event is not available in a symbolic form within perf right now,
  65 it can be encoded in a per processor specific way.
  66
  67 For instance For x86 CPUs NNN represents the raw register encoding with the
  68 layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
  69 of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
  70 Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
  71
  72 Note: Only the following bit fields can be set in x86 counter
  73 registers: event, umask, edge, inv, cmask. Esp. guest/host only and
  74 OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
  75 MODIFIERS>>.
  76
  77 Example:
  78
  79 If the Intel docs for a QM720 Core i7 describe an event as:
  80
  81   Event  Umask  Event Mask
  82   Num.   Value  Mnemonic    Description                        Comment
  83
  84   A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
  85                             delivered by loop stream detector  invert to count
  86                                                                cycles
  87
  88 raw encoding of 0x1A8 can be used:
  89
  90  perf stat -e r1a8 -a sleep 1
  91  perf record -e r1a8 ...
  92
  93 You should refer to the processor specific documentation for getting these
  94 details. Some of them are referenced in the SEE ALSO section below.
  95
  96 PARAMETERIZED EVENTS
  97 --------------------
  98
  99 Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
 100 example:
 101
 102   hv_gpci/dtbp_ptitc,phys_processor_idx=?/
 103
 104 This means that when provided as an event, a value for '?' must
 105 also be supplied. For example:
 106
 107   perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
 108
 109 OPTIONS
 110 -------
 111
 112 Without options all known events will be listed.
 113
 114 To limit the list use:
 115
 116 . 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
 117
 118 . 'sw' or 'software' to list software events such as context switches, etc.
 119
 120 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
 121
 122 . 'tracepoint' to list all tracepoint events, alternatively use
 123   'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
 124   block, etc.
 125
 126 . 'pmu' to print the kernel supplied PMU events.
 127
 128 . If none of the above is matched, it will apply the supplied glob to all
 129   events, printing the ones that match.
 130
 131 . As a last resort, it will do a substring search in all event names.
 132
 133 One or more types can be used at the same time, listing the events for the
 134 types specified.
 135
 136 Support raw format:
 137
 138 . '--raw-dump', shows the raw-dump of all the events.
 139 . '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
 140   a certain kind of events.
 141
 142 SEE ALSO
 143 --------
 144 linkperf:perf-stat[1], linkperf:perf-top[1],
 145 linkperf:perf-record[1],
 146 http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
 147 http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]