2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending
40 * - VGIC pending interrupts are stored on the vgic.irq_state vgic
41 * bitmap (this bitmap is updated by both user land ioctls and guest
42 * mmio ops, and other in-kernel peripherals such as the
43 * arch. timers) and indicate the 'wire' state.
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_state & dist->irq_enable
49 * - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ICFGR
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - The same is true when injecting an interrupt, except that we only
55 * consider a single interrupt at a time. The irq_spi_cpu array
56 * contains the target CPU for each SPI.
58 * The handling of level interrupts adds some extra complexity. We
59 * need to track when the interrupt has been EOIed, so we can sample
60 * the 'line' again. This is achieved as such:
62 * - When a level interrupt is moved onto a vcpu, the corresponding
63 * bit in irq_active is set. As long as this bit is set, the line
64 * will be ignored for further interrupts. The interrupt is injected
65 * into the vcpu with the GICH_LR_EOI bit set (generate a
66 * maintenance interrupt on EOI).
67 * - When the interrupt is EOIed, the maintenance interrupt fires,
68 * and clears the corresponding bit in irq_active. This allow the
69 * interrupt line to be sampled again.
72 #define VGIC_ADDR_UNDEF (-1)
73 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
75 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
76 #define IMPLEMENTER_ARM 0x43b
77 #define GICC_ARCH_VERSION_V2 0x2
79 #define ACCESS_READ_VALUE (1 << 0)
80 #define ACCESS_READ_RAZ (0 << 0)
81 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
82 #define ACCESS_WRITE_IGNORED (0 << 1)
83 #define ACCESS_WRITE_SETBIT (1 << 1)
84 #define ACCESS_WRITE_CLEARBIT (2 << 1)
85 #define ACCESS_WRITE_VALUE (3 << 1)
86 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
88 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
);
89 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
);
90 static void vgic_update_state(struct kvm
*kvm
);
91 static void vgic_kick_vcpus(struct kvm
*kvm
);
92 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
);
93 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
);
94 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
, struct vgic_lr lr_desc
);
95 static void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
);
96 static void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
);
98 static const struct vgic_ops
*vgic_ops
;
99 static const struct vgic_params
*vgic
;
101 static u32
*vgic_bitmap_get_reg(struct vgic_bitmap
*x
,
102 int cpuid
, u32 offset
)
106 return x
->percpu
[cpuid
].reg
;
108 return x
->shared
.reg
+ offset
- 1;
111 static int vgic_bitmap_get_irq_val(struct vgic_bitmap
*x
,
114 if (irq
< VGIC_NR_PRIVATE_IRQS
)
115 return test_bit(irq
, x
->percpu
[cpuid
].reg_ul
);
117 return test_bit(irq
- VGIC_NR_PRIVATE_IRQS
, x
->shared
.reg_ul
);
120 static void vgic_bitmap_set_irq_val(struct vgic_bitmap
*x
, int cpuid
,
125 if (irq
< VGIC_NR_PRIVATE_IRQS
) {
126 reg
= x
->percpu
[cpuid
].reg_ul
;
128 reg
= x
->shared
.reg_ul
;
129 irq
-= VGIC_NR_PRIVATE_IRQS
;
138 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap
*x
, int cpuid
)
140 if (unlikely(cpuid
>= VGIC_MAX_CPUS
))
142 return x
->percpu
[cpuid
].reg_ul
;
145 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap
*x
)
147 return x
->shared
.reg_ul
;
150 static u32
*vgic_bytemap_get_reg(struct vgic_bytemap
*x
, int cpuid
, u32 offset
)
153 BUG_ON(offset
> (VGIC_NR_IRQS
/ 4));
155 return x
->percpu
[cpuid
] + offset
;
157 return x
->shared
+ offset
- 8;
160 #define VGIC_CFG_LEVEL 0
161 #define VGIC_CFG_EDGE 1
163 static bool vgic_irq_is_edge(struct kvm_vcpu
*vcpu
, int irq
)
165 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
168 irq_val
= vgic_bitmap_get_irq_val(&dist
->irq_cfg
, vcpu
->vcpu_id
, irq
);
169 return irq_val
== VGIC_CFG_EDGE
;
172 static int vgic_irq_is_enabled(struct kvm_vcpu
*vcpu
, int irq
)
174 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
176 return vgic_bitmap_get_irq_val(&dist
->irq_enabled
, vcpu
->vcpu_id
, irq
);
179 static int vgic_irq_is_active(struct kvm_vcpu
*vcpu
, int irq
)
181 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
183 return vgic_bitmap_get_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
);
186 static void vgic_irq_set_active(struct kvm_vcpu
*vcpu
, int irq
)
188 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
190 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 1);
193 static void vgic_irq_clear_active(struct kvm_vcpu
*vcpu
, int irq
)
195 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
197 vgic_bitmap_set_irq_val(&dist
->irq_active
, vcpu
->vcpu_id
, irq
, 0);
200 static int vgic_dist_irq_is_pending(struct kvm_vcpu
*vcpu
, int irq
)
202 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
204 return vgic_bitmap_get_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
);
207 static void vgic_dist_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
209 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
211 vgic_bitmap_set_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
, 1);
214 static void vgic_dist_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
216 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
218 vgic_bitmap_set_irq_val(&dist
->irq_state
, vcpu
->vcpu_id
, irq
, 0);
221 static void vgic_cpu_irq_set(struct kvm_vcpu
*vcpu
, int irq
)
223 if (irq
< VGIC_NR_PRIVATE_IRQS
)
224 set_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
226 set_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
227 vcpu
->arch
.vgic_cpu
.pending_shared
);
230 static void vgic_cpu_irq_clear(struct kvm_vcpu
*vcpu
, int irq
)
232 if (irq
< VGIC_NR_PRIVATE_IRQS
)
233 clear_bit(irq
, vcpu
->arch
.vgic_cpu
.pending_percpu
);
235 clear_bit(irq
- VGIC_NR_PRIVATE_IRQS
,
236 vcpu
->arch
.vgic_cpu
.pending_shared
);
239 static u32
mmio_data_read(struct kvm_exit_mmio
*mmio
, u32 mask
)
241 return *((u32
*)mmio
->data
) & mask
;
244 static void mmio_data_write(struct kvm_exit_mmio
*mmio
, u32 mask
, u32 value
)
246 *((u32
*)mmio
->data
) = value
& mask
;
250 * vgic_reg_access - access vgic register
251 * @mmio: pointer to the data describing the mmio access
252 * @reg: pointer to the virtual backing of vgic distributor data
253 * @offset: least significant 2 bits used for word offset
254 * @mode: ACCESS_ mode (see defines above)
256 * Helper to make vgic register access easier using one of the access
257 * modes defined for vgic register access
258 * (read,raz,write-ignored,setbit,clearbit,write)
260 static void vgic_reg_access(struct kvm_exit_mmio
*mmio
, u32
*reg
,
261 phys_addr_t offset
, int mode
)
263 int word_offset
= (offset
& 3) * 8;
264 u32 mask
= (1UL << (mmio
->len
* 8)) - 1;
268 * Any alignment fault should have been delivered to the guest
269 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
275 BUG_ON(mode
!= (ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
));
279 if (mmio
->is_write
) {
280 u32 data
= mmio_data_read(mmio
, mask
) << word_offset
;
281 switch (ACCESS_WRITE_MASK(mode
)) {
282 case ACCESS_WRITE_IGNORED
:
285 case ACCESS_WRITE_SETBIT
:
289 case ACCESS_WRITE_CLEARBIT
:
293 case ACCESS_WRITE_VALUE
:
294 regval
= (regval
& ~(mask
<< word_offset
)) | data
;
299 switch (ACCESS_READ_MASK(mode
)) {
300 case ACCESS_READ_RAZ
:
304 case ACCESS_READ_VALUE
:
305 mmio_data_write(mmio
, mask
, regval
>> word_offset
);
310 static bool handle_mmio_misc(struct kvm_vcpu
*vcpu
,
311 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
314 u32 word_offset
= offset
& 3;
316 switch (offset
& ~3) {
317 case 0: /* GICD_CTLR */
318 reg
= vcpu
->kvm
->arch
.vgic
.enabled
;
319 vgic_reg_access(mmio
, ®
, word_offset
,
320 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
321 if (mmio
->is_write
) {
322 vcpu
->kvm
->arch
.vgic
.enabled
= reg
& 1;
323 vgic_update_state(vcpu
->kvm
);
328 case 4: /* GICD_TYPER */
329 reg
= (atomic_read(&vcpu
->kvm
->online_vcpus
) - 1) << 5;
330 reg
|= (VGIC_NR_IRQS
>> 5) - 1;
331 vgic_reg_access(mmio
, ®
, word_offset
,
332 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
335 case 8: /* GICD_IIDR */
336 reg
= (PRODUCT_ID_KVM
<< 24) | (IMPLEMENTER_ARM
<< 0);
337 vgic_reg_access(mmio
, ®
, word_offset
,
338 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
345 static bool handle_mmio_raz_wi(struct kvm_vcpu
*vcpu
,
346 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
348 vgic_reg_access(mmio
, NULL
, offset
,
349 ACCESS_READ_RAZ
| ACCESS_WRITE_IGNORED
);
353 static bool handle_mmio_set_enable_reg(struct kvm_vcpu
*vcpu
,
354 struct kvm_exit_mmio
*mmio
,
357 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
358 vcpu
->vcpu_id
, offset
);
359 vgic_reg_access(mmio
, reg
, offset
,
360 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
361 if (mmio
->is_write
) {
362 vgic_update_state(vcpu
->kvm
);
369 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu
*vcpu
,
370 struct kvm_exit_mmio
*mmio
,
373 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_enabled
,
374 vcpu
->vcpu_id
, offset
);
375 vgic_reg_access(mmio
, reg
, offset
,
376 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
377 if (mmio
->is_write
) {
378 if (offset
< 4) /* Force SGI enabled */
380 vgic_retire_disabled_irqs(vcpu
);
381 vgic_update_state(vcpu
->kvm
);
388 static bool handle_mmio_set_pending_reg(struct kvm_vcpu
*vcpu
,
389 struct kvm_exit_mmio
*mmio
,
392 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_state
,
393 vcpu
->vcpu_id
, offset
);
394 vgic_reg_access(mmio
, reg
, offset
,
395 ACCESS_READ_VALUE
| ACCESS_WRITE_SETBIT
);
396 if (mmio
->is_write
) {
397 vgic_update_state(vcpu
->kvm
);
404 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu
*vcpu
,
405 struct kvm_exit_mmio
*mmio
,
408 u32
*reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_state
,
409 vcpu
->vcpu_id
, offset
);
410 vgic_reg_access(mmio
, reg
, offset
,
411 ACCESS_READ_VALUE
| ACCESS_WRITE_CLEARBIT
);
412 if (mmio
->is_write
) {
413 vgic_update_state(vcpu
->kvm
);
420 static bool handle_mmio_priority_reg(struct kvm_vcpu
*vcpu
,
421 struct kvm_exit_mmio
*mmio
,
424 u32
*reg
= vgic_bytemap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_priority
,
425 vcpu
->vcpu_id
, offset
);
426 vgic_reg_access(mmio
, reg
, offset
,
427 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
431 #define GICD_ITARGETSR_SIZE 32
432 #define GICD_CPUTARGETS_BITS 8
433 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
434 static u32
vgic_get_target_reg(struct kvm
*kvm
, int irq
)
436 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
440 irq
-= VGIC_NR_PRIVATE_IRQS
;
442 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++)
443 val
|= 1 << (dist
->irq_spi_cpu
[irq
+ i
] + i
* 8);
448 static void vgic_set_target_reg(struct kvm
*kvm
, u32 val
, int irq
)
450 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
451 struct kvm_vcpu
*vcpu
;
456 irq
-= VGIC_NR_PRIVATE_IRQS
;
459 * Pick the LSB in each byte. This ensures we target exactly
460 * one vcpu per IRQ. If the byte is null, assume we target
463 for (i
= 0; i
< GICD_IRQS_PER_ITARGETSR
; i
++) {
464 int shift
= i
* GICD_CPUTARGETS_BITS
;
465 target
= ffs((val
>> shift
) & 0xffU
);
466 target
= target
? (target
- 1) : 0;
467 dist
->irq_spi_cpu
[irq
+ i
] = target
;
468 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
469 bmap
= vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[c
]);
471 set_bit(irq
+ i
, bmap
);
473 clear_bit(irq
+ i
, bmap
);
478 static bool handle_mmio_target_reg(struct kvm_vcpu
*vcpu
,
479 struct kvm_exit_mmio
*mmio
,
484 /* We treat the banked interrupts targets as read-only */
486 u32 roreg
= 1 << vcpu
->vcpu_id
;
488 roreg
|= roreg
<< 16;
490 vgic_reg_access(mmio
, &roreg
, offset
,
491 ACCESS_READ_VALUE
| ACCESS_WRITE_IGNORED
);
495 reg
= vgic_get_target_reg(vcpu
->kvm
, offset
& ~3U);
496 vgic_reg_access(mmio
, ®
, offset
,
497 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
498 if (mmio
->is_write
) {
499 vgic_set_target_reg(vcpu
->kvm
, reg
, offset
& ~3U);
500 vgic_update_state(vcpu
->kvm
);
507 static u32
vgic_cfg_expand(u16 val
)
513 * Turn a 16bit value like abcd...mnop into a 32bit word
514 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
516 for (i
= 0; i
< 16; i
++)
517 res
|= ((val
>> i
) & VGIC_CFG_EDGE
) << (2 * i
+ 1);
522 static u16
vgic_cfg_compress(u32 val
)
528 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
529 * abcd...mnop which is what we really care about.
531 for (i
= 0; i
< 16; i
++)
532 res
|= ((val
>> (i
* 2 + 1)) & VGIC_CFG_EDGE
) << i
;
538 * The distributor uses 2 bits per IRQ for the CFG register, but the
539 * LSB is always 0. As such, we only keep the upper bit, and use the
540 * two above functions to compress/expand the bits
542 static bool handle_mmio_cfg_reg(struct kvm_vcpu
*vcpu
,
543 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
548 reg
= vgic_bitmap_get_reg(&vcpu
->kvm
->arch
.vgic
.irq_cfg
,
549 vcpu
->vcpu_id
, offset
>> 1);
556 val
= vgic_cfg_expand(val
);
557 vgic_reg_access(mmio
, &val
, offset
,
558 ACCESS_READ_VALUE
| ACCESS_WRITE_VALUE
);
559 if (mmio
->is_write
) {
561 *reg
= ~0U; /* Force PPIs/SGIs to 1 */
565 val
= vgic_cfg_compress(val
);
570 *reg
&= 0xffff << 16;
578 static bool handle_mmio_sgi_reg(struct kvm_vcpu
*vcpu
,
579 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
582 vgic_reg_access(mmio
, ®
, offset
,
583 ACCESS_READ_RAZ
| ACCESS_WRITE_VALUE
);
584 if (mmio
->is_write
) {
585 vgic_dispatch_sgi(vcpu
, reg
);
586 vgic_update_state(vcpu
->kvm
);
594 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
595 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
597 * Move any pending IRQs that have already been assigned to LRs back to the
598 * emulated distributor state so that the complete emulated state can be read
599 * from the main emulation structures without investigating the LRs.
601 * Note that IRQs in the active state in the LRs get their pending state moved
602 * to the distributor but the active state stays in the LRs, because we don't
603 * track the active state on the distributor side.
605 static void vgic_unqueue_irqs(struct kvm_vcpu
*vcpu
)
607 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
608 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
609 int vcpu_id
= vcpu
->vcpu_id
;
612 for_each_set_bit(i
, vgic_cpu
->lr_used
, vgic_cpu
->nr_lr
) {
613 struct vgic_lr lr
= vgic_get_lr(vcpu
, i
);
616 * There are three options for the state bits:
620 * 11: pending and active
622 * If the LR holds only an active interrupt (not pending) then
623 * just leave it alone.
625 if ((lr
.state
& LR_STATE_MASK
) == LR_STATE_ACTIVE
)
629 * Reestablish the pending state on the distributor and the
630 * CPU interface. It may have already been pending, but that
631 * is fine, then we are only setting a few bits that were
634 vgic_dist_irq_set(vcpu
, lr
.irq
);
635 if (lr
.irq
< VGIC_NR_SGIS
)
636 dist
->irq_sgi_sources
[vcpu_id
][lr
.irq
] |= 1 << lr
.source
;
637 lr
.state
&= ~LR_STATE_PENDING
;
638 vgic_set_lr(vcpu
, i
, lr
);
641 * If there's no state left on the LR (it could still be
642 * active), then the LR does not hold any useful info and can
643 * be marked as free for other use.
645 if (!(lr
.state
& LR_STATE_MASK
))
646 vgic_retire_lr(i
, lr
.irq
, vcpu
);
648 /* Finally update the VGIC state. */
649 vgic_update_state(vcpu
->kvm
);
653 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
654 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
655 struct kvm_exit_mmio
*mmio
,
658 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
660 int min_sgi
= (offset
& ~0x3) * 4;
661 int max_sgi
= min_sgi
+ 3;
662 int vcpu_id
= vcpu
->vcpu_id
;
665 /* Copy source SGIs from distributor side */
666 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
667 int shift
= 8 * (sgi
- min_sgi
);
668 reg
|= (u32
)dist
->irq_sgi_sources
[vcpu_id
][sgi
] << shift
;
671 mmio_data_write(mmio
, ~0, reg
);
675 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu
*vcpu
,
676 struct kvm_exit_mmio
*mmio
,
677 phys_addr_t offset
, bool set
)
679 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
681 int min_sgi
= (offset
& ~0x3) * 4;
682 int max_sgi
= min_sgi
+ 3;
683 int vcpu_id
= vcpu
->vcpu_id
;
685 bool updated
= false;
687 reg
= mmio_data_read(mmio
, ~0);
689 /* Clear pending SGIs on the distributor */
690 for (sgi
= min_sgi
; sgi
<= max_sgi
; sgi
++) {
691 u8 mask
= reg
>> (8 * (sgi
- min_sgi
));
693 if ((dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
) != mask
)
695 dist
->irq_sgi_sources
[vcpu_id
][sgi
] |= mask
;
697 if (dist
->irq_sgi_sources
[vcpu_id
][sgi
] & mask
)
699 dist
->irq_sgi_sources
[vcpu_id
][sgi
] &= ~mask
;
704 vgic_update_state(vcpu
->kvm
);
709 static bool handle_mmio_sgi_set(struct kvm_vcpu
*vcpu
,
710 struct kvm_exit_mmio
*mmio
,
714 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
716 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, true);
719 static bool handle_mmio_sgi_clear(struct kvm_vcpu
*vcpu
,
720 struct kvm_exit_mmio
*mmio
,
724 return read_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
);
726 return write_set_clear_sgi_pend_reg(vcpu
, mmio
, offset
, false);
730 * I would have liked to use the kvm_bus_io_*() API instead, but it
731 * cannot cope with banked registers (only the VM pointer is passed
732 * around, and we need the vcpu). One of these days, someone please
738 bool (*handle_mmio
)(struct kvm_vcpu
*vcpu
, struct kvm_exit_mmio
*mmio
,
742 static const struct mmio_range vgic_dist_ranges
[] = {
744 .base
= GIC_DIST_CTRL
,
746 .handle_mmio
= handle_mmio_misc
,
749 .base
= GIC_DIST_IGROUP
,
750 .len
= VGIC_NR_IRQS
/ 8,
751 .handle_mmio
= handle_mmio_raz_wi
,
754 .base
= GIC_DIST_ENABLE_SET
,
755 .len
= VGIC_NR_IRQS
/ 8,
756 .handle_mmio
= handle_mmio_set_enable_reg
,
759 .base
= GIC_DIST_ENABLE_CLEAR
,
760 .len
= VGIC_NR_IRQS
/ 8,
761 .handle_mmio
= handle_mmio_clear_enable_reg
,
764 .base
= GIC_DIST_PENDING_SET
,
765 .len
= VGIC_NR_IRQS
/ 8,
766 .handle_mmio
= handle_mmio_set_pending_reg
,
769 .base
= GIC_DIST_PENDING_CLEAR
,
770 .len
= VGIC_NR_IRQS
/ 8,
771 .handle_mmio
= handle_mmio_clear_pending_reg
,
774 .base
= GIC_DIST_ACTIVE_SET
,
775 .len
= VGIC_NR_IRQS
/ 8,
776 .handle_mmio
= handle_mmio_raz_wi
,
779 .base
= GIC_DIST_ACTIVE_CLEAR
,
780 .len
= VGIC_NR_IRQS
/ 8,
781 .handle_mmio
= handle_mmio_raz_wi
,
784 .base
= GIC_DIST_PRI
,
786 .handle_mmio
= handle_mmio_priority_reg
,
789 .base
= GIC_DIST_TARGET
,
791 .handle_mmio
= handle_mmio_target_reg
,
794 .base
= GIC_DIST_CONFIG
,
795 .len
= VGIC_NR_IRQS
/ 4,
796 .handle_mmio
= handle_mmio_cfg_reg
,
799 .base
= GIC_DIST_SOFTINT
,
801 .handle_mmio
= handle_mmio_sgi_reg
,
804 .base
= GIC_DIST_SGI_PENDING_CLEAR
,
806 .handle_mmio
= handle_mmio_sgi_clear
,
809 .base
= GIC_DIST_SGI_PENDING_SET
,
811 .handle_mmio
= handle_mmio_sgi_set
,
817 struct mmio_range
*find_matching_range(const struct mmio_range
*ranges
,
818 struct kvm_exit_mmio
*mmio
,
821 const struct mmio_range
*r
= ranges
;
824 if (offset
>= r
->base
&&
825 (offset
+ mmio
->len
) <= (r
->base
+ r
->len
))
834 * vgic_handle_mmio - handle an in-kernel MMIO access
835 * @vcpu: pointer to the vcpu performing the access
836 * @run: pointer to the kvm_run structure
837 * @mmio: pointer to the data describing the access
839 * returns true if the MMIO access has been performed in kernel space,
840 * and false if it needs to be emulated in user space.
842 bool vgic_handle_mmio(struct kvm_vcpu
*vcpu
, struct kvm_run
*run
,
843 struct kvm_exit_mmio
*mmio
)
845 const struct mmio_range
*range
;
846 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
847 unsigned long base
= dist
->vgic_dist_base
;
849 unsigned long offset
;
851 if (!irqchip_in_kernel(vcpu
->kvm
) ||
852 mmio
->phys_addr
< base
||
853 (mmio
->phys_addr
+ mmio
->len
) > (base
+ KVM_VGIC_V2_DIST_SIZE
))
856 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
858 kvm_inject_dabt(vcpu
, mmio
->phys_addr
);
862 offset
= mmio
->phys_addr
- base
;
863 range
= find_matching_range(vgic_dist_ranges
, mmio
, offset
);
864 if (unlikely(!range
|| !range
->handle_mmio
)) {
865 pr_warn("Unhandled access %d %08llx %d\n",
866 mmio
->is_write
, mmio
->phys_addr
, mmio
->len
);
870 spin_lock(&vcpu
->kvm
->arch
.vgic
.lock
);
871 offset
= mmio
->phys_addr
- range
->base
- base
;
872 updated_state
= range
->handle_mmio(vcpu
, mmio
, offset
);
873 spin_unlock(&vcpu
->kvm
->arch
.vgic
.lock
);
874 kvm_prepare_mmio(run
, mmio
);
875 kvm_handle_mmio_return(vcpu
, run
);
878 vgic_kick_vcpus(vcpu
->kvm
);
883 static void vgic_dispatch_sgi(struct kvm_vcpu
*vcpu
, u32 reg
)
885 struct kvm
*kvm
= vcpu
->kvm
;
886 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
887 int nrcpus
= atomic_read(&kvm
->online_vcpus
);
889 int sgi
, mode
, c
, vcpu_id
;
891 vcpu_id
= vcpu
->vcpu_id
;
894 target_cpus
= (reg
>> 16) & 0xff;
895 mode
= (reg
>> 24) & 3;
904 target_cpus
= ((1 << nrcpus
) - 1) & ~(1 << vcpu_id
) & 0xff;
908 target_cpus
= 1 << vcpu_id
;
912 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
913 if (target_cpus
& 1) {
914 /* Flag the SGI as pending */
915 vgic_dist_irq_set(vcpu
, sgi
);
916 dist
->irq_sgi_sources
[c
][sgi
] |= 1 << vcpu_id
;
917 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi
, vcpu_id
, c
);
924 static int compute_pending_for_cpu(struct kvm_vcpu
*vcpu
)
926 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
927 unsigned long *pending
, *enabled
, *pend_percpu
, *pend_shared
;
928 unsigned long pending_private
, pending_shared
;
931 vcpu_id
= vcpu
->vcpu_id
;
932 pend_percpu
= vcpu
->arch
.vgic_cpu
.pending_percpu
;
933 pend_shared
= vcpu
->arch
.vgic_cpu
.pending_shared
;
935 pending
= vgic_bitmap_get_cpu_map(&dist
->irq_state
, vcpu_id
);
936 enabled
= vgic_bitmap_get_cpu_map(&dist
->irq_enabled
, vcpu_id
);
937 bitmap_and(pend_percpu
, pending
, enabled
, VGIC_NR_PRIVATE_IRQS
);
939 pending
= vgic_bitmap_get_shared_map(&dist
->irq_state
);
940 enabled
= vgic_bitmap_get_shared_map(&dist
->irq_enabled
);
941 bitmap_and(pend_shared
, pending
, enabled
, VGIC_NR_SHARED_IRQS
);
942 bitmap_and(pend_shared
, pend_shared
,
943 vgic_bitmap_get_shared_map(&dist
->irq_spi_target
[vcpu_id
]),
944 VGIC_NR_SHARED_IRQS
);
946 pending_private
= find_first_bit(pend_percpu
, VGIC_NR_PRIVATE_IRQS
);
947 pending_shared
= find_first_bit(pend_shared
, VGIC_NR_SHARED_IRQS
);
948 return (pending_private
< VGIC_NR_PRIVATE_IRQS
||
949 pending_shared
< VGIC_NR_SHARED_IRQS
);
953 * Update the interrupt state and determine which CPUs have pending
954 * interrupts. Must be called with distributor lock held.
956 static void vgic_update_state(struct kvm
*kvm
)
958 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
959 struct kvm_vcpu
*vcpu
;
962 if (!dist
->enabled
) {
963 set_bit(0, &dist
->irq_pending_on_cpu
);
967 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
968 if (compute_pending_for_cpu(vcpu
)) {
969 pr_debug("CPU%d has pending interrupts\n", c
);
970 set_bit(c
, &dist
->irq_pending_on_cpu
);
975 static struct vgic_lr
vgic_get_lr(const struct kvm_vcpu
*vcpu
, int lr
)
977 return vgic_ops
->get_lr(vcpu
, lr
);
980 static void vgic_set_lr(struct kvm_vcpu
*vcpu
, int lr
,
983 vgic_ops
->set_lr(vcpu
, lr
, vlr
);
986 static void vgic_sync_lr_elrsr(struct kvm_vcpu
*vcpu
, int lr
,
989 vgic_ops
->sync_lr_elrsr(vcpu
, lr
, vlr
);
992 static inline u64
vgic_get_elrsr(struct kvm_vcpu
*vcpu
)
994 return vgic_ops
->get_elrsr(vcpu
);
997 static inline u64
vgic_get_eisr(struct kvm_vcpu
*vcpu
)
999 return vgic_ops
->get_eisr(vcpu
);
1002 static inline u32
vgic_get_interrupt_status(struct kvm_vcpu
*vcpu
)
1004 return vgic_ops
->get_interrupt_status(vcpu
);
1007 static inline void vgic_enable_underflow(struct kvm_vcpu
*vcpu
)
1009 vgic_ops
->enable_underflow(vcpu
);
1012 static inline void vgic_disable_underflow(struct kvm_vcpu
*vcpu
)
1014 vgic_ops
->disable_underflow(vcpu
);
1017 static inline void vgic_get_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1019 vgic_ops
->get_vmcr(vcpu
, vmcr
);
1022 static void vgic_set_vmcr(struct kvm_vcpu
*vcpu
, struct vgic_vmcr
*vmcr
)
1024 vgic_ops
->set_vmcr(vcpu
, vmcr
);
1027 static inline void vgic_enable(struct kvm_vcpu
*vcpu
)
1029 vgic_ops
->enable(vcpu
);
1032 static void vgic_retire_lr(int lr_nr
, int irq
, struct kvm_vcpu
*vcpu
)
1034 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1035 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr_nr
);
1038 vgic_set_lr(vcpu
, lr_nr
, vlr
);
1039 clear_bit(lr_nr
, vgic_cpu
->lr_used
);
1040 vgic_cpu
->vgic_irq_lr_map
[irq
] = LR_EMPTY
;
1044 * An interrupt may have been disabled after being made pending on the
1045 * CPU interface (the classic case is a timer running while we're
1046 * rebooting the guest - the interrupt would kick as soon as the CPU
1047 * interface gets enabled, with deadly consequences).
1049 * The solution is to examine already active LRs, and check the
1050 * interrupt is still enabled. If not, just retire it.
1052 static void vgic_retire_disabled_irqs(struct kvm_vcpu
*vcpu
)
1054 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1057 for_each_set_bit(lr
, vgic_cpu
->lr_used
, vgic
->nr_lr
) {
1058 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1060 if (!vgic_irq_is_enabled(vcpu
, vlr
.irq
)) {
1061 vgic_retire_lr(lr
, vlr
.irq
, vcpu
);
1062 if (vgic_irq_is_active(vcpu
, vlr
.irq
))
1063 vgic_irq_clear_active(vcpu
, vlr
.irq
);
1069 * Queue an interrupt to a CPU virtual interface. Return true on success,
1070 * or false if it wasn't possible to queue it.
1072 static bool vgic_queue_irq(struct kvm_vcpu
*vcpu
, u8 sgi_source_id
, int irq
)
1074 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1078 /* Sanitize the input... */
1079 BUG_ON(sgi_source_id
& ~7);
1080 BUG_ON(sgi_source_id
&& irq
>= VGIC_NR_SGIS
);
1081 BUG_ON(irq
>= VGIC_NR_IRQS
);
1083 kvm_debug("Queue IRQ%d\n", irq
);
1085 lr
= vgic_cpu
->vgic_irq_lr_map
[irq
];
1087 /* Do we have an active interrupt for the same CPUID? */
1088 if (lr
!= LR_EMPTY
) {
1089 vlr
= vgic_get_lr(vcpu
, lr
);
1090 if (vlr
.source
== sgi_source_id
) {
1091 kvm_debug("LR%d piggyback for IRQ%d\n", lr
, vlr
.irq
);
1092 BUG_ON(!test_bit(lr
, vgic_cpu
->lr_used
));
1093 vlr
.state
|= LR_STATE_PENDING
;
1094 vgic_set_lr(vcpu
, lr
, vlr
);
1099 /* Try to use another LR for this interrupt */
1100 lr
= find_first_zero_bit((unsigned long *)vgic_cpu
->lr_used
,
1102 if (lr
>= vgic
->nr_lr
)
1105 kvm_debug("LR%d allocated for IRQ%d %x\n", lr
, irq
, sgi_source_id
);
1106 vgic_cpu
->vgic_irq_lr_map
[irq
] = lr
;
1107 set_bit(lr
, vgic_cpu
->lr_used
);
1110 vlr
.source
= sgi_source_id
;
1111 vlr
.state
= LR_STATE_PENDING
;
1112 if (!vgic_irq_is_edge(vcpu
, irq
))
1113 vlr
.state
|= LR_EOI_INT
;
1115 vgic_set_lr(vcpu
, lr
, vlr
);
1120 static bool vgic_queue_sgi(struct kvm_vcpu
*vcpu
, int irq
)
1122 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1123 unsigned long sources
;
1124 int vcpu_id
= vcpu
->vcpu_id
;
1127 sources
= dist
->irq_sgi_sources
[vcpu_id
][irq
];
1129 for_each_set_bit(c
, &sources
, VGIC_MAX_CPUS
) {
1130 if (vgic_queue_irq(vcpu
, c
, irq
))
1131 clear_bit(c
, &sources
);
1134 dist
->irq_sgi_sources
[vcpu_id
][irq
] = sources
;
1137 * If the sources bitmap has been cleared it means that we
1138 * could queue all the SGIs onto link registers (see the
1139 * clear_bit above), and therefore we are done with them in
1140 * our emulated gic and can get rid of them.
1143 vgic_dist_irq_clear(vcpu
, irq
);
1144 vgic_cpu_irq_clear(vcpu
, irq
);
1151 static bool vgic_queue_hwirq(struct kvm_vcpu
*vcpu
, int irq
)
1153 if (vgic_irq_is_active(vcpu
, irq
))
1154 return true; /* level interrupt, already queued */
1156 if (vgic_queue_irq(vcpu
, 0, irq
)) {
1157 if (vgic_irq_is_edge(vcpu
, irq
)) {
1158 vgic_dist_irq_clear(vcpu
, irq
);
1159 vgic_cpu_irq_clear(vcpu
, irq
);
1161 vgic_irq_set_active(vcpu
, irq
);
1171 * Fill the list registers with pending interrupts before running the
1174 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1176 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1177 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1181 vcpu_id
= vcpu
->vcpu_id
;
1184 * We may not have any pending interrupt, or the interrupts
1185 * may have been serviced from another vcpu. In all cases,
1188 if (!kvm_vgic_vcpu_pending_irq(vcpu
)) {
1189 pr_debug("CPU%d has no pending interrupt\n", vcpu_id
);
1194 for_each_set_bit(i
, vgic_cpu
->pending_percpu
, VGIC_NR_SGIS
) {
1195 if (!vgic_queue_sgi(vcpu
, i
))
1200 for_each_set_bit_from(i
, vgic_cpu
->pending_percpu
, VGIC_NR_PRIVATE_IRQS
) {
1201 if (!vgic_queue_hwirq(vcpu
, i
))
1206 for_each_set_bit(i
, vgic_cpu
->pending_shared
, VGIC_NR_SHARED_IRQS
) {
1207 if (!vgic_queue_hwirq(vcpu
, i
+ VGIC_NR_PRIVATE_IRQS
))
1213 vgic_enable_underflow(vcpu
);
1215 vgic_disable_underflow(vcpu
);
1217 * We're about to run this VCPU, and we've consumed
1218 * everything the distributor had in store for
1219 * us. Claim we don't have anything pending. We'll
1220 * adjust that if needed while exiting.
1222 clear_bit(vcpu_id
, &dist
->irq_pending_on_cpu
);
1226 static bool vgic_process_maintenance(struct kvm_vcpu
*vcpu
)
1228 u32 status
= vgic_get_interrupt_status(vcpu
);
1229 bool level_pending
= false;
1231 kvm_debug("STATUS = %08x\n", status
);
1233 if (status
& INT_STATUS_EOI
) {
1235 * Some level interrupts have been EOIed. Clear their
1238 u64 eisr
= vgic_get_eisr(vcpu
);
1239 unsigned long *eisr_ptr
= (unsigned long *)&eisr
;
1242 for_each_set_bit(lr
, eisr_ptr
, vgic
->nr_lr
) {
1243 struct vgic_lr vlr
= vgic_get_lr(vcpu
, lr
);
1245 vgic_irq_clear_active(vcpu
, vlr
.irq
);
1246 WARN_ON(vlr
.state
& LR_STATE_MASK
);
1248 vgic_set_lr(vcpu
, lr
, vlr
);
1250 /* Any additional pending interrupt? */
1251 if (vgic_dist_irq_is_pending(vcpu
, vlr
.irq
)) {
1252 vgic_cpu_irq_set(vcpu
, vlr
.irq
);
1253 level_pending
= true;
1255 vgic_cpu_irq_clear(vcpu
, vlr
.irq
);
1259 * Despite being EOIed, the LR may not have
1260 * been marked as empty.
1262 vgic_sync_lr_elrsr(vcpu
, lr
, vlr
);
1266 if (status
& INT_STATUS_UNDERFLOW
)
1267 vgic_disable_underflow(vcpu
);
1269 return level_pending
;
1273 * Sync back the VGIC state after a guest run. The distributor lock is
1274 * needed so we don't get preempted in the middle of the state processing.
1276 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1278 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1279 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1281 unsigned long *elrsr_ptr
;
1285 level_pending
= vgic_process_maintenance(vcpu
);
1286 elrsr
= vgic_get_elrsr(vcpu
);
1287 elrsr_ptr
= (unsigned long *)&elrsr
;
1289 /* Clear mappings for empty LRs */
1290 for_each_set_bit(lr
, elrsr_ptr
, vgic
->nr_lr
) {
1293 if (!test_and_clear_bit(lr
, vgic_cpu
->lr_used
))
1296 vlr
= vgic_get_lr(vcpu
, lr
);
1298 BUG_ON(vlr
.irq
>= VGIC_NR_IRQS
);
1299 vgic_cpu
->vgic_irq_lr_map
[vlr
.irq
] = LR_EMPTY
;
1302 /* Check if we still have something up our sleeve... */
1303 pending
= find_first_zero_bit(elrsr_ptr
, vgic
->nr_lr
);
1304 if (level_pending
|| pending
< vgic
->nr_lr
)
1305 set_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1308 void kvm_vgic_flush_hwstate(struct kvm_vcpu
*vcpu
)
1310 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1312 if (!irqchip_in_kernel(vcpu
->kvm
))
1315 spin_lock(&dist
->lock
);
1316 __kvm_vgic_flush_hwstate(vcpu
);
1317 spin_unlock(&dist
->lock
);
1320 void kvm_vgic_sync_hwstate(struct kvm_vcpu
*vcpu
)
1322 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1324 if (!irqchip_in_kernel(vcpu
->kvm
))
1327 spin_lock(&dist
->lock
);
1328 __kvm_vgic_sync_hwstate(vcpu
);
1329 spin_unlock(&dist
->lock
);
1332 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu
*vcpu
)
1334 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1336 if (!irqchip_in_kernel(vcpu
->kvm
))
1339 return test_bit(vcpu
->vcpu_id
, &dist
->irq_pending_on_cpu
);
1342 static void vgic_kick_vcpus(struct kvm
*kvm
)
1344 struct kvm_vcpu
*vcpu
;
1348 * We've injected an interrupt, time to find out who deserves
1351 kvm_for_each_vcpu(c
, vcpu
, kvm
) {
1352 if (kvm_vgic_vcpu_pending_irq(vcpu
))
1353 kvm_vcpu_kick(vcpu
);
1357 static int vgic_validate_injection(struct kvm_vcpu
*vcpu
, int irq
, int level
)
1359 int is_edge
= vgic_irq_is_edge(vcpu
, irq
);
1360 int state
= vgic_dist_irq_is_pending(vcpu
, irq
);
1363 * Only inject an interrupt if:
1364 * - edge triggered and we have a rising edge
1365 * - level triggered and we change level
1368 return level
> state
;
1370 return level
!= state
;
1373 static bool vgic_update_irq_state(struct kvm
*kvm
, int cpuid
,
1374 unsigned int irq_num
, bool level
)
1376 struct vgic_dist
*dist
= &kvm
->arch
.vgic
;
1377 struct kvm_vcpu
*vcpu
;
1378 int is_edge
, is_level
;
1382 spin_lock(&dist
->lock
);
1384 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1385 is_edge
= vgic_irq_is_edge(vcpu
, irq_num
);
1386 is_level
= !is_edge
;
1388 if (!vgic_validate_injection(vcpu
, irq_num
, level
)) {
1393 if (irq_num
>= VGIC_NR_PRIVATE_IRQS
) {
1394 cpuid
= dist
->irq_spi_cpu
[irq_num
- VGIC_NR_PRIVATE_IRQS
];
1395 vcpu
= kvm_get_vcpu(kvm
, cpuid
);
1398 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num
, level
, cpuid
);
1401 vgic_dist_irq_set(vcpu
, irq_num
);
1403 vgic_dist_irq_clear(vcpu
, irq_num
);
1405 enabled
= vgic_irq_is_enabled(vcpu
, irq_num
);
1412 if (is_level
&& vgic_irq_is_active(vcpu
, irq_num
)) {
1414 * Level interrupt in progress, will be picked up
1422 vgic_cpu_irq_set(vcpu
, irq_num
);
1423 set_bit(cpuid
, &dist
->irq_pending_on_cpu
);
1427 spin_unlock(&dist
->lock
);
1433 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1434 * @kvm: The VM structure pointer
1435 * @cpuid: The CPU for PPIs
1436 * @irq_num: The IRQ number that is assigned to the device
1437 * @level: Edge-triggered: true: to trigger the interrupt
1438 * false: to ignore the call
1439 * Level-sensitive true: activates an interrupt
1440 * false: deactivates an interrupt
1442 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1443 * level-sensitive interrupts. You can think of the level parameter as 1
1444 * being HIGH and 0 being LOW and all devices being active-HIGH.
1446 int kvm_vgic_inject_irq(struct kvm
*kvm
, int cpuid
, unsigned int irq_num
,
1449 if (vgic_update_irq_state(kvm
, cpuid
, irq_num
, level
))
1450 vgic_kick_vcpus(kvm
);
1455 static irqreturn_t
vgic_maintenance_handler(int irq
, void *data
)
1458 * We cannot rely on the vgic maintenance interrupt to be
1459 * delivered synchronously. This means we can only use it to
1460 * exit the VM, and we perform the handling of EOIed
1461 * interrupts on the exit path (see vgic_process_maintenance).
1467 * kvm_vgic_vcpu_init - Initialize per-vcpu VGIC state
1468 * @vcpu: pointer to the vcpu struct
1470 * Initialize the vgic_cpu struct and vgic_dist struct fields pertaining to
1471 * this vcpu and enable the VGIC for this VCPU
1473 int kvm_vgic_vcpu_init(struct kvm_vcpu
*vcpu
)
1475 struct vgic_cpu
*vgic_cpu
= &vcpu
->arch
.vgic_cpu
;
1476 struct vgic_dist
*dist
= &vcpu
->kvm
->arch
.vgic
;
1479 if (vcpu
->vcpu_id
>= VGIC_MAX_CPUS
)
1482 for (i
= 0; i
< VGIC_NR_IRQS
; i
++) {
1483 if (i
< VGIC_NR_PPIS
)
1484 vgic_bitmap_set_irq_val(&dist
->irq_enabled
,
1485 vcpu
->vcpu_id
, i
, 1);
1486 if (i
< VGIC_NR_PRIVATE_IRQS
)
1487 vgic_bitmap_set_irq_val(&dist
->irq_cfg
,
1488 vcpu
->vcpu_id
, i
, VGIC_CFG_EDGE
);
1490 vgic_cpu
->vgic_irq_lr_map
[i
] = LR_EMPTY
;
1494 * Store the number of LRs per vcpu, so we don't have to go
1495 * all the way to the distributor structure to find out. Only
1496 * assembly code should use this one.
1498 vgic_cpu
->nr_lr
= vgic
->nr_lr
;
1505 static void vgic_init_maintenance_interrupt(void *info
)
1507 enable_percpu_irq(vgic
->maint_irq
, 0);
1510 static int vgic_cpu_notify(struct notifier_block
*self
,
1511 unsigned long action
, void *cpu
)
1515 case CPU_STARTING_FROZEN
:
1516 vgic_init_maintenance_interrupt(NULL
);
1519 case CPU_DYING_FROZEN
:
1520 disable_percpu_irq(vgic
->maint_irq
);
1527 static struct notifier_block vgic_cpu_nb
= {
1528 .notifier_call
= vgic_cpu_notify
,
1531 static const struct of_device_id vgic_ids
[] = {
1532 { .compatible
= "arm,cortex-a15-gic", .data
= vgic_v2_probe
, },
1536 int kvm_vgic_hyp_init(void)
1538 const struct of_device_id
*matched_id
;
1539 int (*vgic_probe
)(struct device_node
*,const struct vgic_ops
**,
1540 const struct vgic_params
**);
1541 struct device_node
*vgic_node
;
1544 vgic_node
= of_find_matching_node_and_match(NULL
,
1545 vgic_ids
, &matched_id
);
1547 kvm_err("error: no compatible GIC node found\n");
1551 vgic_probe
= matched_id
->data
;
1552 ret
= vgic_probe(vgic_node
, &vgic_ops
, &vgic
);
1556 ret
= request_percpu_irq(vgic
->maint_irq
, vgic_maintenance_handler
,
1557 "vgic", kvm_get_running_vcpus());
1559 kvm_err("Cannot register interrupt %d\n", vgic
->maint_irq
);
1563 ret
= __register_cpu_notifier(&vgic_cpu_nb
);
1565 kvm_err("Cannot register vgic CPU notifier\n");
1569 on_each_cpu(vgic_init_maintenance_interrupt
, NULL
, 1);
1571 /* Callback into for arch code for setup */
1572 vgic_arch_setup(vgic
);
1577 free_percpu_irq(vgic
->maint_irq
, kvm_get_running_vcpus());
1582 * kvm_vgic_init - Initialize global VGIC state before running any VCPUs
1583 * @kvm: pointer to the kvm struct
1585 * Map the virtual CPU interface into the VM before running any VCPUs. We
1586 * can't do this at creation time, because user space must first set the
1587 * virtual CPU interface address in the guest physical address space. Also
1588 * initialize the ITARGETSRn regs to 0 on the emulated distributor.
1590 int kvm_vgic_init(struct kvm
*kvm
)
1594 if (!irqchip_in_kernel(kvm
))
1597 mutex_lock(&kvm
->lock
);
1599 if (vgic_initialized(kvm
))
1602 if (IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_dist_base
) ||
1603 IS_VGIC_ADDR_UNDEF(kvm
->arch
.vgic
.vgic_cpu_base
)) {
1604 kvm_err("Need to set vgic cpu and dist addresses first\n");
1609 ret
= kvm_phys_addr_ioremap(kvm
, kvm
->arch
.vgic
.vgic_cpu_base
,
1610 vgic
->vcpu_base
, KVM_VGIC_V2_CPU_SIZE
);
1612 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1616 for (i
= VGIC_NR_PRIVATE_IRQS
; i
< VGIC_NR_IRQS
; i
+= 4)
1617 vgic_set_target_reg(kvm
, 0, i
);
1619 kvm
->arch
.vgic
.ready
= true;
1621 mutex_unlock(&kvm
->lock
);
1625 int kvm_vgic_create(struct kvm
*kvm
)
1627 int i
, vcpu_lock_idx
= -1, ret
= 0;
1628 struct kvm_vcpu
*vcpu
;
1630 mutex_lock(&kvm
->lock
);
1632 if (kvm
->arch
.vgic
.vctrl_base
) {
1638 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1639 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1640 * that no other VCPUs are run while we create the vgic.
1642 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1643 if (!mutex_trylock(&vcpu
->mutex
))
1648 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1649 if (vcpu
->arch
.has_run_once
) {
1655 spin_lock_init(&kvm
->arch
.vgic
.lock
);
1656 kvm
->arch
.vgic
.in_kernel
= true;
1657 kvm
->arch
.vgic
.vctrl_base
= vgic
->vctrl_base
;
1658 kvm
->arch
.vgic
.vgic_dist_base
= VGIC_ADDR_UNDEF
;
1659 kvm
->arch
.vgic
.vgic_cpu_base
= VGIC_ADDR_UNDEF
;
1662 for (; vcpu_lock_idx
>= 0; vcpu_lock_idx
--) {
1663 vcpu
= kvm_get_vcpu(kvm
, vcpu_lock_idx
);
1664 mutex_unlock(&vcpu
->mutex
);
1668 mutex_unlock(&kvm
->lock
);
1672 static bool vgic_ioaddr_overlap(struct kvm
*kvm
)
1674 phys_addr_t dist
= kvm
->arch
.vgic
.vgic_dist_base
;
1675 phys_addr_t cpu
= kvm
->arch
.vgic
.vgic_cpu_base
;
1677 if (IS_VGIC_ADDR_UNDEF(dist
) || IS_VGIC_ADDR_UNDEF(cpu
))
1679 if ((dist
<= cpu
&& dist
+ KVM_VGIC_V2_DIST_SIZE
> cpu
) ||
1680 (cpu
<= dist
&& cpu
+ KVM_VGIC_V2_CPU_SIZE
> dist
))
1685 static int vgic_ioaddr_assign(struct kvm
*kvm
, phys_addr_t
*ioaddr
,
1686 phys_addr_t addr
, phys_addr_t size
)
1690 if (addr
& ~KVM_PHYS_MASK
)
1693 if (addr
& (SZ_4K
- 1))
1696 if (!IS_VGIC_ADDR_UNDEF(*ioaddr
))
1698 if (addr
+ size
< addr
)
1702 ret
= vgic_ioaddr_overlap(kvm
);
1704 *ioaddr
= VGIC_ADDR_UNDEF
;
1710 * kvm_vgic_addr - set or get vgic VM base addresses
1711 * @kvm: pointer to the vm struct
1712 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
1713 * @addr: pointer to address value
1714 * @write: if true set the address in the VM address space, if false read the
1717 * Set or get the vgic base addresses for the distributor and the virtual CPU
1718 * interface in the VM physical address space. These addresses are properties
1719 * of the emulated core/SoC and therefore user space initially knows this
1722 int kvm_vgic_addr(struct kvm
*kvm
, unsigned long type
, u64
*addr
, bool write
)
1725 struct vgic_dist
*vgic
= &kvm
->arch
.vgic
;
1727 mutex_lock(&kvm
->lock
);
1729 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
1731 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_dist_base
,
1732 *addr
, KVM_VGIC_V2_DIST_SIZE
);
1734 *addr
= vgic
->vgic_dist_base
;
1737 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
1739 r
= vgic_ioaddr_assign(kvm
, &vgic
->vgic_cpu_base
,
1740 *addr
, KVM_VGIC_V2_CPU_SIZE
);
1742 *addr
= vgic
->vgic_cpu_base
;
1749 mutex_unlock(&kvm
->lock
);
1753 static bool handle_cpu_mmio_misc(struct kvm_vcpu
*vcpu
,
1754 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1756 bool updated
= false;
1757 struct vgic_vmcr vmcr
;
1761 vgic_get_vmcr(vcpu
, &vmcr
);
1763 switch (offset
& ~0x3) {
1765 vmcr_field
= &vmcr
.ctlr
;
1767 case GIC_CPU_PRIMASK
:
1768 vmcr_field
= &vmcr
.pmr
;
1770 case GIC_CPU_BINPOINT
:
1771 vmcr_field
= &vmcr
.bpr
;
1773 case GIC_CPU_ALIAS_BINPOINT
:
1774 vmcr_field
= &vmcr
.abpr
;
1780 if (!mmio
->is_write
) {
1782 mmio_data_write(mmio
, ~0, reg
);
1784 reg
= mmio_data_read(mmio
, ~0);
1785 if (reg
!= *vmcr_field
) {
1787 vgic_set_vmcr(vcpu
, &vmcr
);
1794 static bool handle_mmio_abpr(struct kvm_vcpu
*vcpu
,
1795 struct kvm_exit_mmio
*mmio
, phys_addr_t offset
)
1797 return handle_cpu_mmio_misc(vcpu
, mmio
, GIC_CPU_ALIAS_BINPOINT
);
1800 static bool handle_cpu_mmio_ident(struct kvm_vcpu
*vcpu
,
1801 struct kvm_exit_mmio
*mmio
,
1810 reg
= (PRODUCT_ID_KVM
<< 20) |
1811 (GICC_ARCH_VERSION_V2
<< 16) |
1812 (IMPLEMENTER_ARM
<< 0);
1813 mmio_data_write(mmio
, ~0, reg
);
1818 * CPU Interface Register accesses - these are not accessed by the VM, but by
1819 * user space for saving and restoring VGIC state.
1821 static const struct mmio_range vgic_cpu_ranges
[] = {
1823 .base
= GIC_CPU_CTRL
,
1825 .handle_mmio
= handle_cpu_mmio_misc
,
1828 .base
= GIC_CPU_ALIAS_BINPOINT
,
1830 .handle_mmio
= handle_mmio_abpr
,
1833 .base
= GIC_CPU_ACTIVEPRIO
,
1835 .handle_mmio
= handle_mmio_raz_wi
,
1838 .base
= GIC_CPU_IDENT
,
1840 .handle_mmio
= handle_cpu_mmio_ident
,
1844 static int vgic_attr_regs_access(struct kvm_device
*dev
,
1845 struct kvm_device_attr
*attr
,
1846 u32
*reg
, bool is_write
)
1848 const struct mmio_range
*r
= NULL
, *ranges
;
1851 struct kvm_vcpu
*vcpu
, *tmp_vcpu
;
1852 struct vgic_dist
*vgic
;
1853 struct kvm_exit_mmio mmio
;
1855 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
1856 cpuid
= (attr
->attr
& KVM_DEV_ARM_VGIC_CPUID_MASK
) >>
1857 KVM_DEV_ARM_VGIC_CPUID_SHIFT
;
1859 mutex_lock(&dev
->kvm
->lock
);
1861 if (cpuid
>= atomic_read(&dev
->kvm
->online_vcpus
)) {
1866 vcpu
= kvm_get_vcpu(dev
->kvm
, cpuid
);
1867 vgic
= &dev
->kvm
->arch
.vgic
;
1870 mmio
.is_write
= is_write
;
1872 mmio_data_write(&mmio
, ~0, *reg
);
1873 switch (attr
->group
) {
1874 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1875 mmio
.phys_addr
= vgic
->vgic_dist_base
+ offset
;
1876 ranges
= vgic_dist_ranges
;
1878 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
1879 mmio
.phys_addr
= vgic
->vgic_cpu_base
+ offset
;
1880 ranges
= vgic_cpu_ranges
;
1885 r
= find_matching_range(ranges
, &mmio
, offset
);
1887 if (unlikely(!r
|| !r
->handle_mmio
)) {
1893 spin_lock(&vgic
->lock
);
1896 * Ensure that no other VCPU is running by checking the vcpu->cpu
1897 * field. If no other VPCUs are running we can safely access the VGIC
1898 * state, because even if another VPU is run after this point, that
1899 * VCPU will not touch the vgic state, because it will block on
1900 * getting the vgic->lock in kvm_vgic_sync_hwstate().
1902 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
) {
1903 if (unlikely(tmp_vcpu
->cpu
!= -1)) {
1905 goto out_vgic_unlock
;
1910 * Move all pending IRQs from the LRs on all VCPUs so the pending
1911 * state can be properly represented in the register state accessible
1914 kvm_for_each_vcpu(c
, tmp_vcpu
, dev
->kvm
)
1915 vgic_unqueue_irqs(tmp_vcpu
);
1918 r
->handle_mmio(vcpu
, &mmio
, offset
);
1921 *reg
= mmio_data_read(&mmio
, ~0);
1925 spin_unlock(&vgic
->lock
);
1927 mutex_unlock(&dev
->kvm
->lock
);
1931 static int vgic_set_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1935 switch (attr
->group
) {
1936 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1937 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1939 unsigned long type
= (unsigned long)attr
->attr
;
1941 if (copy_from_user(&addr
, uaddr
, sizeof(addr
)))
1944 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, true);
1945 return (r
== -ENODEV
) ? -ENXIO
: r
;
1948 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1949 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
1950 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
1953 if (get_user(reg
, uaddr
))
1956 return vgic_attr_regs_access(dev
, attr
, ®
, true);
1964 static int vgic_get_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
1968 switch (attr
->group
) {
1969 case KVM_DEV_ARM_VGIC_GRP_ADDR
: {
1970 u64 __user
*uaddr
= (u64 __user
*)(long)attr
->addr
;
1972 unsigned long type
= (unsigned long)attr
->attr
;
1974 r
= kvm_vgic_addr(dev
->kvm
, type
, &addr
, false);
1976 return (r
== -ENODEV
) ? -ENXIO
: r
;
1978 if (copy_to_user(uaddr
, &addr
, sizeof(addr
)))
1983 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
1984 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
: {
1985 u32 __user
*uaddr
= (u32 __user
*)(long)attr
->addr
;
1988 r
= vgic_attr_regs_access(dev
, attr
, ®
, false);
1991 r
= put_user(reg
, uaddr
);
2000 static int vgic_has_attr_regs(const struct mmio_range
*ranges
,
2003 struct kvm_exit_mmio dev_attr_mmio
;
2005 dev_attr_mmio
.len
= 4;
2006 if (find_matching_range(ranges
, &dev_attr_mmio
, offset
))
2012 static int vgic_has_attr(struct kvm_device
*dev
, struct kvm_device_attr
*attr
)
2016 switch (attr
->group
) {
2017 case KVM_DEV_ARM_VGIC_GRP_ADDR
:
2018 switch (attr
->attr
) {
2019 case KVM_VGIC_V2_ADDR_TYPE_DIST
:
2020 case KVM_VGIC_V2_ADDR_TYPE_CPU
:
2024 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS
:
2025 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2026 return vgic_has_attr_regs(vgic_dist_ranges
, offset
);
2027 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS
:
2028 offset
= attr
->attr
& KVM_DEV_ARM_VGIC_OFFSET_MASK
;
2029 return vgic_has_attr_regs(vgic_cpu_ranges
, offset
);
2034 static void vgic_destroy(struct kvm_device
*dev
)
2039 static int vgic_create(struct kvm_device
*dev
, u32 type
)
2041 return kvm_vgic_create(dev
->kvm
);
2044 struct kvm_device_ops kvm_arm_vgic_v2_ops
= {
2045 .name
= "kvm-arm-vgic",
2046 .create
= vgic_create
,
2047 .destroy
= vgic_destroy
,
2048 .set_attr
= vgic_set_attr
,
2049 .get_attr
= vgic_get_attr
,
2050 .has_attr
= vgic_has_attr
,