ARM Dependent Features
**********************

Options
=======

-marm [2|250|3|6|60|600|610|620|7|7M|7D|7DM|7DI|7DMI|70|700|700I|710|710C|7100|7500|7500FE|7TDMI|8|810|9|9TDMI|920|STRONGARM|STRONGARM110|STRONGARM1100]
     This option specifies the target processor.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.

-marmv [2|2A|3|3M|4|4T|5|5T]
     This option specifies the target architecture.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture.

-mthumb
     This option specifies that only Thumb instructions should be assembled.

-mall
     This option specifies that any Arm or Thumb instruction should be assembled.

-mfpa [10|11]
     This option specifies the floating point architecture in use on the target processor.

-mfpe-old
     Do not allow the assemble of floating point multiple instructions.

-mno-fpu
     Do not allow the assembly of any floating point instructions.

-mthumb-interwork
     This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mapcs [26|32]
     This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-mapcs-float
     This indicates the the floating point variant of the APCS should be used.  In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant
     This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-EB
     This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL
     This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k
     This option enables the generation of PIC (position independent code).

-moabi
     This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

Syntax
======

Special Characters
------------------

The presence of a @ on a line indicates the start of a comment that extends to the end of the current line.  If a # appears as the first character of a line, the whole line is treated as a comment.

On ARM systems running the GNU/Linux operating system, ; can be used instead of a newline to separate statements.

Either # or $ can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

Register Names
--------------

*TODO* Explain about ARM register naming, and the predefined names.

Floating Point
==============

The ARM family uses IEEE floating-point numbers.

ARM Machine Directives
======================

NAME .req REGISTER NAME
     This creates an alias for REGISTER NAME called NAME.  For example:

                  foo .req r0

.code [16|32]
     This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.thumb
     This performs the same action as .CODE 16.

.arm
     This performs the same action as .CODE 32.

.force_thumb
     This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.thumb_func
     This directive specifies that the following symbol is the name of a Thumb encoded function.  This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed.

.thumb_set
     This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined).  This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.ltorg
     This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary).

.pool
     This is a synonym for .ltorg.

Opcodes
=======

AS implements all the standard ARM opcodes.  It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

            nop

     This pseudo op will always evaluate to a legal ARM instruction that does nothing.  Currently it will evaluate to MOV r0, r0.

LDR

            ldr <register> , = <expression>

     If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions.  Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

            adr <register> <label>

     This instruction will load the address of LABEL into the indicated register.  The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located.  If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated.  This instruction will not make use of the literal pool.

ADRL

            adrl <register> <label>

     This instruction will load the address of LABEL into the indicated register.  The instruction will evaluate to one or two a PC relative ADD or SUB instructions depending upon where the label is located.  If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

     If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.