MIPS Dependent Features
***********************

GNU AS for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see ``Appendix D: Assembly Language Programming'' in the same work.

Assembler options
=================

The MIPS configurations of GNU AS support these special options:

-G NUM
     This option sets the largest size of an object that can be referenced implicitly with the gp register.  It is only accepted for targets that use ECOFF format.  The default value is 8.

-EB
-EL
     Any MIPS configuration of AS can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other).  Use -EB to select big-endian output, and -EL for little-endian.

-KPIC
     Generate SVR4-style PIC.  This option tells the assembler to generate SVR4-style position-independent macro expansions.  It also tells the assembler to mark the output file as PIC.

-mvxworks-pic
     Generate VxWorks PIC.  This option tells the assembler to generate VxWorks-style position-independent macro expansions.

-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips32r2
-mips64
-mips64r2
     Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, -mips3 to the R4000 processor, and -mips4 to the R8000 and R10000 processors.  -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 RELEASE 2 ISA processors, respectively.  You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mgp32
-mfp32
     Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times.  -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.

     The .set gp=32 and .set fp=32 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default.

     On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap.  Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64
-mfp64
     Assume that 64-bit registers are available.  This is provided in the interests of symmetry with -mgp32 and -mfp32.

     The .set gp=64 and .set fp=64 directives allow the size of registers to be changed for parts of an object. The default value is restored by .set gp=default and .set fp=default.

-mips16
-no-mips16
     Generate code for the MIPS 16 processor.  This is equivalent to putting .set mips16 at the start of the assembly file.  -no-mips16 turns off this option.

-msmartmips
-mno-smartmips
     Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications.  This is equivalent to putting .set smartmips at the start of the assembly file. -mno-smartmips turns off this option.

-mips3d
-no-mips3d
     Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option.

-mdmx
-no-mdmx
     Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option.

-mdsp
-mno-dsp
     Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.

-mdspr2
-mno-dspr2
     Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option.

-mmt
-mno-mt
     Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option.

-mfix7000
-mno-fix7000
     Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

-mfix-vr4120
-no-mfix-vr4120
     Insert nops to work around certain VR4120 errata.  This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.

-mfix-vr4130
-no-mfix-vr4130
     Insert nops to work around the VR4130 mflo/mfhi errata.

-mfix-24k
-no-mfix-24k
     Insert nops to work around the 24K eret/deret errata.

-m4010
-no-m4010
     Generate code for the LSI R4010 chip.  This tells the assembler to accept the R4010 specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4010 turns off this option.

-m4650
-no-m4650
     Generate code for the MIPS R4650 chip.  This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.

-m3900
-no-m3900
-m4100
-no-m4100
     For each option -mNNNN, generate code for the MIPS RNNNN chip.  This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

-march=CPU
     Generate code for a particular MIPS cpu.  It is exactly equivalent to -mCPU, except that there are more value of CPU understood.  Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f, octeon, xlr

     For compatibility reasons, Nx and Bfx are accepted as synonyms for Nf1_1.  These values are deprecated.

-mtune=CPU
     Schedule and tune for a particular MIPS cpu.  Valid CPU values are identical to -march=CPU.

-mabi=ABI
     Record which ABI the source code uses.  The recognized arguments are: 32, n32, o64, 64 and eabi.

-msym32
-mno-sym32
     Equivalent to adding .set sym32 or .set nosym32 to the beginning of the assembler input.  See MIPS symbol sizes.

-nocpp
     This option is ignored.  It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing.  With GNU AS, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.

-msoft-float
-mhard-float
     Disable or enable floating-point instructions.  Note that by default floating-point instructions are always allowed even with CPU targets that don't have support for these instructions.

-msingle-float
-mdouble-float
     Disable or enable double-precision floating-point operations.  Note that by default double-precision floating-point operations are always allowed even with CPU targets that don't have support for these operations.

--construct-floats
--no-construct-floats
     The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register.  This feature is useful if the processor support the FR bit in its status  register, and this bit is known (by the programmer) to be set.  This bit prevents the aliasing of the double width register by the single width registers.

     By default --construct-floats is selected, allowing construction of these floating point constants.

--trap
--no-break
     AS automatically macro expands certain division and multiplication instructions to check for overflow and division by zero.  This option causes AS to generate code to take a trap exception rather than a break exception when an error is detected.  The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break
--no-trap
     Generate code to take a break exception rather than a trap exception when an error is detected.  This is the default.

-mpdr
-mno-pdr
     Control generation of .pdr sections.  Off by default on IRIX, on elsewhere.

-mshared
-mno-shared
     When generating code using the Unix calling conventions (selected by -KPIC or -mcall_shared), gas will normally generate code which can go into a shared library.  The -mno-shared option tells gas to generate code which uses the calling convention, but can not go into a shared library.  The resulting code is slightly more efficient.  This option only affects the handling of the .cpload and .cpsetup pseudo-ops.

MIPS ECOFF object code
======================

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss.  The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a ``small object''.  Any object in the .sdata or .sbss sections is considered ``small'' in this sense. For external objects, or for objects in the .bss section, you can use the GCC -G option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp.  Passing -G 0 to AS prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case).  The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it.  The size of an external object may be set with the .extern directive.  For example, .extern sym,4 declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code).  MIPS ECOFF assembly code must not modify the $gp register.

Directives for debugging information
====================================

MIPS ECOFF AS supports several directives used for generating debugging information which are not support by traditional MIPS assemblers.  These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs.  The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging).  These directives are primarily used by compilers, not assembly language programmers!

Directives to override the size of symbols
==========================================

The n64 ABI allows symbols to have any 64-bit value.  Although this provides a great deal of flexibility, it means that some macros have much longer expansions than their 32-bit counterparts.  For example, the non-PIC expansion of dla $4,sym is usually:

     lui     $4,%highest(sym)
     lui     $1,%hi(sym)
     daddiu  $4,$4,%higher(sym)
     daddiu  $1,$1,%lo(sym)
     dsll32  $4,$4,0
     daddu   $4,$4,$1

whereas the 32-bit expansion is simply:

     lui     $4,%hi(sym)
     daddiu  $4,$4,%lo(sym)

n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion.

You can use the .set sym32 directive to tell the assembler that, from this point on, all expressions of the form SYMBOL or SYMBOL + OFFSET have 32-bit values.  For example:

     .set sym32
     dla     $4,sym
     lw      $4,sym+16
     sw      $4,sym+0x8000($4)

will cause the assembler to treat sym, sym+16 and sym+0x8000 as 32-bit values.  The handling of non-symbolic addresses is not affected.

The directive .set nosym32 ends a .set sym32 block and reverts to the normal behavior.  It is also possible to change the symbol size using the command-line options -msym32 and -mno-sym32.

These options and directives are always accepted, but at present, they have no effect for anything other than n64.

Directives to override the ISA level
====================================

GNU AS supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsN.  N should be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly.  .set mipsN affects not only which instructions are permitted, but also how certain macros are expanded.  .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration.  You can use this feature to permit specific MIPS3 instructions while assembling in 32 bit mode.  Use this directive with care!

The .set arch=CPU directive provides even finer control. It changes the effective CPU target and allows the assembler to use instructions specific to a particular CPU.  All CPUs supported by the -march command line option are also selectable by this directive. The original value is restored by .set arch=default.

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor.  Use .set nomips16 to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

Directives for extending MIPS 16 bit instructions
=================================================

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary.  The directive .set noautoextend will turn this off.  When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000).  The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode.  Traditional MIPS assemblers do not support this directive.

Directive to mark data as an instruction
========================================

The .insn directive tells AS that the following data is actually instructions.  This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, AS automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

Directives to save and restore options
======================================

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set.  The .set push directive saves the current settings on a stack.  The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

Directives to control generation of MIPS ASE instructions
=========================================================

The directive .set mips3d makes the assembler accept instructions from the MIPS-3D Application Specific Extension from that point on in the assembly.  The .set nomips3d directive prevents MIPS-3D instructions from being accepted.

The directive .set smartmips makes the assembler accept instructions from the SmartMIPS Application Specific Extension to the MIPS32 ISA from that point on in the assembly.  The .set nosmartmips directive prevents SmartMIPS instructions from being accepted.

The directive .set mdmx makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the assembly.  The .set nomdmx directive prevents MDMX instructions from being accepted.

The directive .set dsp makes the assembler accept instructions from the DSP Release 1 Application Specific Extension from that point on in the assembly.  The .set nodsp directive prevents DSP Release 1 instructions from being accepted.

The directive .set dspr2 makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point on in the assembly.  This dirctive implies .set dsp.  The .set nodspr2 directive prevents DSP Release 2 instructions from being accepted.

The directive .set mt makes the assembler accept instructions from the MT Application Specific Extension from that point on in the assembly.  The .set nomt directive prevents MT instructions from being accepted.

Traditional MIPS assemblers do not support these directives.

Directives to override floating-point options
=============================================

The directives .set softfloat and .set hardfloat provide finer control of disabling and enabling float-point instructions. These directives always override the default (that hard-float instructions are accepted) or the command-line options (-msoft-float and -mhard-float).

The directives .set singlefloat and .set doublefloat provide finer control of disabling and enabling double-precision float-point operations.  These directives always override the default (that double-precision operations are accepted) or the command-line options (-msingle-float and -mdouble-float).

Traditional MIPS assemblers do not support these directives.