[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Error: bad type in SIMD instruction -- `vbrsr.64 q0,q1,r2'
[^:]*:12: Error: ARM register expected -- `vbrsr.32 q0,q1,q2'
[^:]*:14: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:15: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:17: Error: syntax error -- `vbrsreq.32 q0,q1,r2'
[^:]*:19: Error: instruction missing MVE vector predication code -- `vbrsr.32 q0,q1,r2'
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vbrsrt.32 q0,q1,r2'