+static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_INSTPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
+ { { STATE_XTSYNC }, 'o' },
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_DATAPGSZID4 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_XTSYNC }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
+ { { STATE_PTBASE }, 'i' },
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
+ { { STATE_EXCVADDR }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
+ { { STATE_PSEXCM }, 'i' },
+ { { STATE_PSRING }, 'i' },
+ { { STATE_CPENABLE }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 58 /* tp7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 58 /* tp7 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
+ { { 6 /* art */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
+ { { 6 /* art */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
+ { { 6 /* art */ }, 'm' },
+ { { 4 /* ars */ }, 'i' },
+ { { 21 /* uimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' },
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
+ { { 6 /* art */ }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
+ { { STATE_SCOMPARE1 }, 'm' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_mul32_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_args[] = {
+ { { 3 /* arr */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
+ { { STATE_RoundMode }, 'i' },
+ { { STATE_InvalidEnable }, 'i' },
+ { { STATE_DivZeroEnable }, 'i' },
+ { { STATE_OverflowEnable }, 'i' },
+ { { STATE_UnderflowEnable }, 'i' },
+ { { STATE_InexactEnable }, 'i' },
+ { { STATE_FPreserved20 }, 'i' },
+ { { STATE_FPreserved5 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
+ { { STATE_RoundMode }, 'o' },
+ { { STATE_InvalidEnable }, 'o' },
+ { { STATE_DivZeroEnable }, 'o' },
+ { { STATE_OverflowEnable }, 'o' },
+ { { STATE_UnderflowEnable }, 'o' },
+ { { STATE_InexactEnable }, 'o' },
+ { { STATE_FPreserved20 }, 'o' },
+ { { STATE_FPreserved5 }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_args[] = {
+ { { 3 /* arr */ }, 'o' }
+};
+
+static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
+ { { STATE_InvalidFlag }, 'i' },
+ { { STATE_DivZeroFlag }, 'i' },
+ { { STATE_OverflowFlag }, 'i' },
+ { { STATE_UnderflowFlag }, 'i' },
+ { { STATE_InexactFlag }, 'i' },
+ { { STATE_FPreserved20a }, 'i' },
+ { { STATE_FPreserved7 }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_args[] = {
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
+ { { STATE_InvalidFlag }, 'o' },
+ { { STATE_DivZeroFlag }, 'o' },
+ { { STATE_OverflowFlag }, 'o' },
+ { { STATE_UnderflowFlag }, 'o' },
+ { { STATE_InexactFlag }, 'o' },
+ { { STATE_FPreserved20a }, 'o' },
+ { { STATE_FPreserved7 }, 'o' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 63 /* frs */ }, 'i' },
+ { { 64 /* frt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_stateArgs[] = {
+ { { STATE_RoundMode }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mac_args[] = {
+ { { 62 /* frr */ }, 'm' },
+ { { 63 /* frs */ }, 'i' },
+ { { 64 /* frt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
+ { { STATE_RoundMode }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_cmov_args[] = {
+ { { 62 /* frr */ }, 'm' },
+ { { 63 /* frs */ }, 'i' },
+ { { 42 /* bt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mov_args[] = {
+ { { 62 /* frr */ }, 'm' },
+ { { 63 /* frs */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mov2_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 63 /* frs */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_cmp_args[] = {
+ { { 44 /* br */ }, 'o' },
+ { { 63 /* frs */ }, 'i' },
+ { { 64 /* frt */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_float_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 65 /* t */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
+ { { STATE_RoundMode }, 'i' },
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_int_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 63 /* frs */ }, 'i' },
+ { { 65 /* t */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_rfr_args[] = {
+ { { 3 /* arr */ }, 'o' },
+ { { 63 /* frs */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_wfr_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsi_args[] = {
+ { { 64 /* frt */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 61 /* cimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
+ { { 64 /* frt */ }, 'o' },
+ { { 4 /* ars */ }, 'm' },
+ { { 61 /* cimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsx_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
+ { { 62 /* frr */ }, 'o' },
+ { { 4 /* ars */ }, 'm' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssi_args[] = {
+ { { 64 /* frt */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 61 /* cimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
+ { { 64 /* frt */ }, 'i' },
+ { { 4 /* ars */ }, 'm' },
+ { { 61 /* cimm8x4 */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssx_args[] = {
+ { { 62 /* frr */ }, 'i' },
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
+ { { 62 /* frr */ }, 'i' },
+ { { 4 /* ars */ }, 'm' },
+ { { 6 /* art */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
+ { { STATE_CPENABLE }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 60 /* xt_wbr18_label */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 17 /* b4const */ }, 'i' },
+ { { 60 /* xt_wbr18_label */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 18 /* b4constu */ }, 'i' },
+ { { 60 /* xt_wbr18_label */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 67 /* bbi */ }, 'i' },
+ { { 60 /* xt_wbr18_label */ }, 'i' }
+};
+
+static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
+ { { 4 /* ars */ }, 'i' },
+ { { 6 /* art */ }, 'i' },
+ { { 60 /* xt_wbr18_label */ }, 'i' }
+};
+
+static xtensa_iclass_internal iclasses[] = {
+ { 0, 0 /* xt_iclass_excw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_rfe */,
+ 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfde */,
+ 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_syscall */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_simcall */,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call12_args,
+ 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call8_args,
+ 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_call4_args,
+ 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx12_args,
+ 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx8_args,
+ 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_callx4_args,
+ 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_entry_args,
+ 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movsp_args,
+ 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rotw_args,
+ 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_retw_args,
+ 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfwou */,
+ 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l32e_args,
+ 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_s32e_args,
+ 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowbase_args,
+ 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowbase_args,
+ 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowbase_args,
+ 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_windowstart_args,
+ 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_windowstart_args,
+ 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_windowstart_args,
+ 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_add_n_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bz6_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill_n */,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_loadi4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_mov_n_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_n_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nopn */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_retn_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_storei4_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_threadptr_args,
+ 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_threadptr_args,
+ 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_addi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addmi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_addsub_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bit_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8b_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bsi8u_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bst8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bsz12_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_call0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_callx0_args,
+ 0, 0, 0, 0 },
+ { 4, Iclass_xt_iclass_exti_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_ill */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jump_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_jumpx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16ui_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l16si_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_l32r_args,
+ 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_l8i_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_loop_args,
+ 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_loopz_args,
+ 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_movi_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_movz_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_neg_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_nop */,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_return_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s16i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32i_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s8i_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_sar_args,
+ 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_sari_args,
+ 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shifts_args,
+ 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_shiftst_args,
+ 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_shiftt_args,
+ 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_slli_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_srli_args,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_memw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_extw */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_isync */,
+ 0, 0, 0, 0 },
+ { 0, 0 /* xt_iclass_sync */,
+ 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rsil_args,
+ 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lend_args,
+ 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lend_args,
+ 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lend_args,
+ 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lcount_args,
+ 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lcount_args,
+ 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lcount_args,
+ 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_lbeg_args,
+ 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_lbeg_args,
+ 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_lbeg_args,
+ 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_sar_args,
+ 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_sar_args,
+ 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_sar_args,
+ 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_litbase_args,
+ 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_litbase_args,
+ 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_litbase_args,
+ 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_176_args,
+ 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_208_args,
+ 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ps_args,
+ 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ps_args,
+ 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ps_args,
+ 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc1_args,
+ 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc1_args,
+ 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc1_args,
+ 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave1_args,
+ 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave1_args,
+ 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave1_args,
+ 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc2_args,
+ 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc2_args,
+ 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc2_args,
+ 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave2_args,
+ 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave2_args,
+ 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave2_args,
+ 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc3_args,
+ 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc3_args,
+ 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc3_args,
+ 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave3_args,
+ 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave3_args,
+ 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave3_args,
+ 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc4_args,
+ 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc4_args,
+ 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc4_args,
+ 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave4_args,
+ 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave4_args,
+ 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave4_args,
+ 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc5_args,
+ 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc5_args,
+ 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc5_args,
+ 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave5_args,
+ 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave5_args,
+ 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave5_args,
+ 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc6_args,
+ 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc6_args,
+ 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc6_args,
+ 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave6_args,
+ 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave6_args,
+ 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave6_args,
+ 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_epc7_args,
+ 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_epc7_args,
+ 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_epc7_args,
+ 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excsave7_args,
+ 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excsave7_args,
+ 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excsave7_args,
+ 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps2_args,
+ 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps2_args,
+ 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps2_args,
+ 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps3_args,
+ 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps3_args,
+ 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps3_args,
+ 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps4_args,
+ 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps4_args,
+ 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps4_args,
+ 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps5_args,
+ 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps5_args,
+ 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps5_args,
+ 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps6_args,
+ 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps6_args,
+ 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps6_args,
+ 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_eps7_args,
+ 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_eps7_args,
+ 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_eps7_args,
+ 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_excvaddr_args,
+ 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_excvaddr_args,
+ 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_excvaddr_args,
+ 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_depc_args,
+ 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_depc_args,
+ 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_depc_args,
+ 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_exccause_args,
+ 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_exccause_args,
+ 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_exccause_args,
+ 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc0_args,
+ 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc0_args,
+ 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc0_args,
+ 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc1_args,
+ 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc1_args,
+ 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc1_args,
+ 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc2_args,
+ 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc2_args,
+ 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc2_args,
+ 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_misc3_args,
+ 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_misc3_args,
+ 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_misc3_args,
+ 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_prid_args,
+ 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_vecbase_args,
+ 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_vecbase_args,
+ 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_vecbase_args,
+ 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_aa_args,
+ 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_ad_args,
+ 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_da_args,
+ 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_dd_args,
+ 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_aa_args,
+ 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_ad_args,
+ 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_da_args,
+ 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16a_dd_args,
+ 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_da_args,
+ 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
+ { 4, Iclass_xt_iclass_mac16al_dd_args,
+ 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_mac16_l_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_mul16_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m0_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m2_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_rsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_wsr_m3_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_xsr_m3_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acclo_args,
+ 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acclo_args,
+ 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acclo_args,
+ 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_acchi_args,
+ 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_acchi_args,
+ 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_acchi_args,
+ 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfi_args,
+ 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wait_args,
+ 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_interrupt_args,
+ 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intset_args,
+ 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intclear_args,
+ 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_intenable_args,
+ 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_intenable_args,
+ 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_intenable_args,
+ 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_break_args,
+ 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_break_n_args,
+ 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
+ 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
+ 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
+ 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
+ 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
+ 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
+ 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_debugcause_args,
+ 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_debugcause_args,
+ 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_debugcause_args,
+ 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icount_args,
+ 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icount_args,
+ 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icount_args,
+ 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_icountlevel_args,
+ 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_icountlevel_args,
+ 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_icountlevel_args,
+ 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ddr_args,
+ 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ddr_args,
+ 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ddr_args,
+ 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rfdo_args,
+ 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_rfdd */,
+ 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_mmid_args,
+ 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_bbool1_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool4_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbool8_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_bbranch_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_bmove_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_RSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_WSR_BR_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_XSR_BR_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccount_args,
+ 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccount_args,
+ 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccount_args,
+ 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare0_args,
+ 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare0_args,
+ 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare0_args,
+ 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare1_args,
+ 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare1_args,
+ 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare1_args,
+ 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ccompare2_args,
+ 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ccompare2_args,
+ 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ccompare2_args,
+ 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_lock_args,
+ 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_icache_inv_args,
+ 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_licx_args,
+ 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sicx_args,
+ 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_ind_args,
+ 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_inv_args,
+ 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_dpf_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_dcache_lock_args,
+ 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_sdct_args,
+ 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ldct_args,
+ 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
+ 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
+ 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_rasid_args,
+ 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_rasid_args,
+ 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_rasid_args,
+ 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
+ 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
+ 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_idtlb_args,
+ 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_rdtlb_args,
+ 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wdtlb_args,
+ 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_iitlb_args,
+ 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_ritlb_args,
+ 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_witlb_args,
+ 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_ldpte */,
+ 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwitlba */,
+ 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
+ { 0, 0 /* xt_iclass_hwwdtlba */,
+ 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_cpenable_args,
+ 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_cpenable_args,
+ 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_cpenable_args,
+ 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_clamp_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_minmax_args,
+ 0, 0, 0, 0 },
+ { 2, Iclass_xt_iclass_nsa_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_sx_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_l32ai_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32ri_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_s32c1i_args,
+ 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_rsr_scompare1_args,
+ 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_wsr_scompare1_args,
+ 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
+ { 1, Iclass_xt_iclass_xsr_scompare1_args,
+ 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
+ { 3, Iclass_xt_iclass_div_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_mul32_args,
+ 0, 0, 0, 0 },
+ { 1, Iclass_rur_fcr_args,
+ 9, Iclass_rur_fcr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_fcr_args,
+ 9, Iclass_wur_fcr_stateArgs, 0, 0 },
+ { 1, Iclass_rur_fsr_args,
+ 8, Iclass_rur_fsr_stateArgs, 0, 0 },
+ { 1, Iclass_wur_fsr_args,
+ 8, Iclass_wur_fsr_stateArgs, 0, 0 },
+ { 3, Iclass_fp_args,
+ 2, Iclass_fp_stateArgs, 0, 0 },
+ { 3, Iclass_fp_mac_args,
+ 2, Iclass_fp_mac_stateArgs, 0, 0 },
+ { 3, Iclass_fp_cmov_args,
+ 1, Iclass_fp_cmov_stateArgs, 0, 0 },
+ { 3, Iclass_fp_mov_args,
+ 1, Iclass_fp_mov_stateArgs, 0, 0 },
+ { 2, Iclass_fp_mov2_args,
+ 1, Iclass_fp_mov2_stateArgs, 0, 0 },
+ { 3, Iclass_fp_cmp_args,
+ 1, Iclass_fp_cmp_stateArgs, 0, 0 },
+ { 3, Iclass_fp_float_args,
+ 2, Iclass_fp_float_stateArgs, 0, 0 },
+ { 3, Iclass_fp_int_args,
+ 1, Iclass_fp_int_stateArgs, 0, 0 },
+ { 2, Iclass_fp_rfr_args,
+ 1, Iclass_fp_rfr_stateArgs, 0, 0 },
+ { 2, Iclass_fp_wfr_args,
+ 1, Iclass_fp_wfr_stateArgs, 0, 0 },
+ { 3, Iclass_fp_lsi_args,
+ 1, Iclass_fp_lsi_stateArgs, 0, 0 },
+ { 3, Iclass_fp_lsiu_args,
+ 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
+ { 3, Iclass_fp_lsx_args,
+ 1, Iclass_fp_lsx_stateArgs, 0, 0 },
+ { 3, Iclass_fp_lsxu_args,
+ 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
+ { 3, Iclass_fp_ssi_args,
+ 1, Iclass_fp_ssi_stateArgs, 0, 0 },
+ { 3, Iclass_fp_ssiu_args,
+ 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
+ { 3, Iclass_fp_ssx_args,
+ 1, Iclass_fp_ssx_stateArgs, 0, 0 },
+ { 3, Iclass_fp_ssxu_args,
+ 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
+ { 2, Iclass_xt_iclass_wb18_0_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_wb18_1_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_wb18_2_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_wb18_3_args,
+ 0, 0, 0, 0 },
+ { 3, Iclass_xt_iclass_wb18_4_args,
+ 0, 0, 0, 0 }
+};
+
+\f
+/* Opcode encodings. */
+
+static void
+Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2080;
+}
+
+static void
+Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3200;
+}
+
+static void
+Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5100;
+}
+
+static void
+Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35;
+}
+
+static void
+Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x25;
+}
+
+static void
+Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x15;
+}
+
+static void
+Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0;
+}
+
+static void
+Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0;
+}
+
+static void
+Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0;
+}
+
+static void
+Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36;
+}
+
+static void
+Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x408000;
+}
+
+static void
+Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90;
+}
+
+static void
+Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf01d;
+}
+
+static void
+Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3400;
+}
+
+static void
+Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3500;
+}
+
+static void
+Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490000;
+}
+
+static void
+Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34800;
+}
+
+static void
+Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134800;
+}
+
+static void
+Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614800;
+}
+
+static void
+Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x34900;
+}
+
+static void
+Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x134900;
+}
+
+static void
+Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x614900;
+}
+
+static void
+Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa;
+}
+
+static void
+Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb;
+}
+
+static void
+Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3000;
+}
+
+static void
+Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8c;
+}
+
+static void
+Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcc;
+}
+
+static void
+Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf06d;
+}
+
+static void
+Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8;
+}
+
+static void
+Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd;
+}
+
+static void
+Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa3000;
+}
+
+static void
+Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc080;
+}
+
+static void
+Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc;
+}
+
+static void
+Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc000;
+}
+
+static void
+Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf03d;
+}
+
+static void
+Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00d;
+}
+
+static void
+Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9;
+}
+
+static void
+Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e70;
+}
+
+static void
+Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e700;
+}
+
+static void
+Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc002;
+}
+
+static void
+Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200c00;
+}
+
+static void
+Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd002;
+}
+
+static void
+Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70000;
+}
+
+static void
+Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200d00;
+}
+
+static void
+Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800000;
+}
+
+static void
+Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x92000;
+}
+
+static void
+Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80000;
+}
+
+static void
+Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc00000;
+}
+
+static void
+Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa8000;
+}
+
+static void
+Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0000;
+}
+
+static void
+Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900000;
+}
+
+static void
+Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x94000;
+}
+
+static void
+Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa00000;
+}
+
+static void
+Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x98000;
+}
+
+static void
+Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5000;
+}
+
+static void
+Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb00000;
+}
+
+static void
+Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x93000;
+}
+
+static void
+Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0000;
+}
+
+static void
+Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd00000;
+}
+
+static void
+Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd0000;
+}
+
+static void
+Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe00000;
+}
+
+static void
+Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe0000;
+}
+
+static void
+Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf00000;
+}
+
+static void
+Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf0000;
+}
+
+static void
+Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x95000;
+}
+
+static void
+Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9e000;
+}
+
+static void
+Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x300000;
+}
+
+static void
+Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0000;
+}
+
+static void
+Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x26;
+}
+
+static void
+Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x66;
+}
+
+static void
+Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe6;
+}
+
+static void
+Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6;
+}
+
+static void
+Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6007;
+}
+
+static void
+Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe007;
+}
+
+static void
+Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf6;
+}
+
+static void
+Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb6;
+}
+
+static void
+Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1007;
+}
+
+static void
+Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9007;
+}
+
+static void
+Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa007;
+}
+
+static void
+Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2007;
+}
+
+static void
+Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb007;
+}
+
+static void
+Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3007;
+}
+
+static void
+Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8007;
+}
+
+static void
+Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7;
+}
+
+static void
+Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4007;
+}
+
+static void
+Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc007;
+}
+
+static void
+Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5007;
+}
+
+static void
+Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd007;
+}
+
+static void
+Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x16;
+}
+
+static void
+Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x56;
+}
+
+static void
+Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd6;
+}
+
+static void
+Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96;
+}
+
+static void
+Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5;
+}
+
+static void
+Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0;
+}
+
+static void
+Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0;
+}
+
+static void
+Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6;
+}
+
+static void
+Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0000;
+}
+
+static void
+Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0;
+}
+
+static void
+Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa3010;
+}
+
+static void
+Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1002;
+}
+
+static void
+Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200100;
+}
+
+static void
+Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9002;
+}
+
+static void
+Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200900;
+}
+
+static void
+Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2002;
+}
+
+static void
+Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200200;
+}
+
+static void
+Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1;
+}
+
+static void
+Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x100000;
+}
+
+static void
+Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2;
+}
+
+static void
+Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200000;
+}
+
+static void
+Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8076;
+}
+
+static void
+Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9076;
+}
+
+static void
+Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa076;
+}
+
+static void
+Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa002;
+}
+
+static void
+Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80000;
+}
+
+static void
+Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200a00;
+}
+
+static void
+Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x830000;
+}
+
+static void
+Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x96000;
+}
+
+static void
+Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x83000;
+}
+
+static void
+Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x930000;
+}
+
+static void
+Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9a000;
+}
+
+static void
+Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x93000;
+}
+
+static void
+Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa30000;
+}
+
+static void
+Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x99000;
+}
+
+static void
+Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa3000;
+}
+
+static void
+Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb30000;
+}
+
+static void
+Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x97000;
+}
+
+static void
+Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb3000;
+}
+
+static void
+Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600000;
+}
+
+static void
+Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa5000;
+}
+
+static void
+Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd100;
+}
+
+static void
+Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000;
+}
+
+static void
+Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x600100;
+}
+
+static void
+Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd000;
+}
+
+static void
+Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60010;
+}
+
+static void
+Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f0;
+}
+
+static void
+Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa3040;
+}
+
+static void
+Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc090;
+}
+
+static void
+Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc8000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20f;
+}
+
+static void
+Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80;
+}
+
+static void
+Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5002;
+}
+
+static void
+Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200500;
+}
+
+static void
+Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6002;
+}
+
+static void
+Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200600;
+}
+
+static void
+Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4002;
+}
+
+static void
+Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x200400;
+}
+
+static void
+Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x400000;
+}
+
+static void
+Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000;
+}
+
+static void
+Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x401000;
+}
+
+static void
+Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa3020;
+}
+
+static void
+Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40100;
+}
+
+static void
+Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x402000;
+}
+
+static void
+Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40200;
+}
+
+static void
+Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x403000;
+}
+
+static void
+Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40300;
+}
+
+static void
+Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x404000;
+}
+
+static void
+Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40400;
+}
+
+static void
+Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa10000;
+}
+
+static void
+Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa6000;
+}
+
+static void
+Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa1000;
+}
+
+static void
+Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x810000;
+}
+
+static void
+Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa2000;
+}
+
+static void
+Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x81000;
+}
+
+static void
+Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x910000;
+}
+
+static void
+Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa5200;
+}
+
+static void
+Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd400;
+}
+
+static void
+Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x91000;
+}
+
+static void
+Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb10000;
+}
+
+static void
+Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa5100;
+}
+
+static void
+Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd200;
+}
+
+static void
+Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb1000;
+}
+
+static void
+Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000;
+}
+
+static void
+Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000;
+}
+
+static void
+Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1000;
+}
+
+static void
+Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x210000;
+}
+
+static void
+Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe000;
+}
+
+static void
+Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x21000;
+}
+
+static void
+Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x410000;
+}
+
+static void
+Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa4000;
+}
+
+static void
+Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x41000;
+}
+
+static void
+Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20c0;
+}
+
+static void
+Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20d0;
+}
+
+static void
+Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2000;
+}
+
+static void
+Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2010;
+}
+
+static void
+Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2020;
+}
+
+static void
+Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2030;
+}
+
+static void
+Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6000;
+}
+
+static void
+Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30100;
+}
+
+static void
+Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130100;
+}
+
+static void
+Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610100;
+}
+
+static void
+Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30200;
+}
+
+static void
+Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130200;
+}
+
+static void
+Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610200;
+}
+
+static void
+Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000;
+}
+
+static void
+Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130000;
+}
+
+static void
+Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610000;
+}
+
+static void
+Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30300;
+}
+
+static void
+Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130300;
+}
+
+static void
+Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610300;
+}
+
+static void
+Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30500;
+}
+
+static void
+Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130500;
+}
+
+static void
+Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610500;
+}
+
+static void
+Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b000;
+}
+
+static void
+Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d000;
+}
+
+static void
+Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e600;
+}
+
+static void
+Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e600;
+}
+
+static void
+Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e600;
+}
+
+static void
+Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b100;
+}
+
+static void
+Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b100;
+}
+
+static void
+Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b100;
+}
+
+static void
+Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d100;
+}
+
+static void
+Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d100;
+}
+
+static void
+Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d100;
+}
+
+static void
+Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b200;
+}
+
+static void
+Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b200;
+}
+
+static void
+Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b200;
+}
+
+static void
+Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d200;
+}
+
+static void
+Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d200;
+}
+
+static void
+Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d200;
+}
+
+static void
+Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b300;
+}
+
+static void
+Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b300;
+}
+
+static void
+Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b300;
+}
+
+static void
+Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d300;
+}
+
+static void
+Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d300;
+}
+
+static void
+Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d300;
+}
+
+static void
+Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b400;
+}
+
+static void
+Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b400;
+}
+
+static void
+Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b400;
+}
+
+static void
+Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d400;
+}
+
+static void
+Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d400;
+}
+
+static void
+Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d400;
+}
+
+static void
+Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b500;
+}
+
+static void
+Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b500;
+}
+
+static void
+Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b500;
+}
+
+static void
+Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d500;
+}
+
+static void
+Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d500;
+}
+
+static void
+Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d500;
+}
+
+static void
+Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b600;
+}
+
+static void
+Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b600;
+}
+
+static void
+Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b600;
+}
+
+static void
+Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d600;
+}
+
+static void
+Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d600;
+}
+
+static void
+Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d600;
+}
+
+static void
+Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b700;
+}
+
+static void
+Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13b700;
+}
+
+static void
+Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61b700;
+}
+
+static void
+Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d700;
+}
+
+static void
+Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13d700;
+}
+
+static void
+Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61d700;
+}
+
+static void
+Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c200;
+}
+
+static void
+Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c200;
+}
+
+static void
+Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c200;
+}
+
+static void
+Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c300;
+}
+
+static void
+Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c300;
+}
+
+static void
+Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c300;
+}
+
+static void
+Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c400;
+}
+
+static void
+Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c400;
+}
+
+static void
+Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c400;
+}
+
+static void
+Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c500;
+}
+
+static void
+Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c500;
+}
+
+static void
+Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c500;
+}
+
+static void
+Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c600;
+}
+
+static void
+Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c600;
+}
+
+static void
+Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c600;
+}
+
+static void
+Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c700;
+}
+
+static void
+Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c700;
+}
+
+static void
+Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c700;
+}
+
+static void
+Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ee00;
+}
+
+static void
+Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ee00;
+}
+
+static void
+Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ee00;
+}
+
+static void
+Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c000;
+}
+
+static void
+Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13c000;
+}
+
+static void
+Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61c000;
+}
+
+static void
+Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e800;
+}
+
+static void
+Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e800;
+}
+
+static void
+Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e800;
+}
+
+static void
+Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f400;
+}
+
+static void
+Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f400;
+}
+
+static void
+Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f400;
+}
+
+static void
+Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f500;
+}
+
+static void
+Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f500;
+}
+
+static void
+Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f500;
+}
+
+static void
+Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f600;
+}
+
+static void
+Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f600;
+}
+
+static void
+Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f600;
+}
+
+static void
+Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f700;
+}
+
+static void
+Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f700;
+}
+
+static void
+Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f700;
+}
+
+static void
+Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3eb00;
+}
+
+static void
+Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e700;
+}
+
+static void
+Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e700;
+}
+
+static void
+Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e700;
+}
+
+static void
+Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x740004;
+}
+
+static void
+Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x750004;
+}
+
+static void
+Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x760004;
+}
+
+static void
+Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x770004;
+}
+
+static void
+Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x700004;
+}
+
+static void
+Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x710004;
+}
+
+static void
+Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x720004;
+}
+
+static void
+Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730004;
+}
+
+static void
+Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x340004;
+}
+
+static void
+Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x350004;
+}
+
+static void
+Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x360004;
+}
+
+static void
+Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370004;
+}
+
+static void
+Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x640004;
+}
+
+static void
+Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x650004;
+}
+
+static void
+Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x660004;
+}
+
+static void
+Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x670004;
+}
+
+static void
+Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x240004;
+}
+
+static void
+Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x250004;
+}
+
+static void
+Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x260004;
+}
+
+static void
+Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270004;
+}
+
+static void
+Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x780004;
+}
+
+static void
+Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x790004;
+}
+
+static void
+Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7a0004;
+}
+
+static void
+Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0004;
+}
+
+static void
+Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7c0004;
+}
+
+static void
+Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7d0004;
+}
+
+static void
+Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7e0004;
+}
+
+static void
+Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7f0004;
+}
+
+static void
+Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x380004;
+}
+
+static void
+Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x390004;
+}
+
+static void
+Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a0004;
+}
+
+static void
+Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0004;
+}
+
+static void
+Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3c0004;
+}
+
+static void
+Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3d0004;
+}
+
+static void
+Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e0004;
+}
+
+static void
+Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f0004;
+}
+
+static void
+Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x680004;
+}
+
+static void
+Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x690004;
+}
+
+static void
+Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6a0004;
+}
+
+static void
+Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0004;
+}
+
+static void
+Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6c0004;
+}
+
+static void
+Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6d0004;
+}
+
+static void
+Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6e0004;
+}
+
+static void
+Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6f0004;
+}
+
+static void
+Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x280004;
+}
+
+static void
+Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x290004;
+}
+
+static void
+Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0004;
+}
+
+static void
+Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0004;
+}
+
+static void
+Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2c0004;
+}
+
+static void
+Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2d0004;
+}
+
+static void
+Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2e0004;
+}
+
+static void
+Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2f0004;
+}
+
+static void
+Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580004;
+}
+
+static void
+Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480004;
+}
+
+static void
+Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x590004;
+}
+
+static void
+Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x490004;
+}
+
+static void
+Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0004;
+}
+
+static void
+Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0004;
+}
+
+static void
+Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0004;
+}
+
+static void
+Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0004;
+}
+
+static void
+Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180004;
+}
+
+static void
+Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80004;
+}
+
+static void
+Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x190004;
+}
+
+static void
+Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90004;
+}
+
+static void
+Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0004;
+}
+
+static void
+Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0004;
+}
+
+static void
+Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0004;
+}
+
+static void
+Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0004;
+}
+
+static void
+Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x900004;
+}
+
+static void
+Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x800004;
+}
+
+static void
+Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc10000;
+}
+
+static void
+Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9b000;
+}
+
+static void
+Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc1000;
+}
+
+static void
+Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd10000;
+}
+
+static void
+Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9c000;
+}
+
+static void
+Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd1000;
+}
+
+static void
+Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32000;
+}
+
+static void
+Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132000;
+}
+
+static void
+Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612000;
+}
+
+static void
+Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32100;
+}
+
+static void
+Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132100;
+}
+
+static void
+Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612100;
+}
+
+static void
+Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32200;
+}
+
+static void
+Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132200;
+}
+
+static void
+Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612200;
+}
+
+static void
+Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x32300;
+}
+
+static void
+Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x132300;
+}
+
+static void
+Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x612300;
+}
+
+static void
+Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31000;
+}
+
+static void
+Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131000;
+}
+
+static void
+Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611000;
+}
+
+static void
+Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x31100;
+}
+
+static void
+Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x131100;
+}
+
+static void
+Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x611100;
+}
+
+static void
+Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3010;
+}
+
+static void
+Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7000;
+}
+
+static void
+Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e200;
+}
+
+static void
+Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e200;
+}
+
+static void
+Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e300;
+}
+
+static void
+Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e400;
+}
+
+static void
+Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e400;
+}
+
+static void
+Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e400;
+}
+
+static void
+Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4000;
+}
+
+static void
+Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf02d;
+}
+
+static void
+Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39000;
+}
+
+static void
+Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139000;
+}
+
+static void
+Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619000;
+}
+
+static void
+Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a000;
+}
+
+static void
+Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a000;
+}
+
+static void
+Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a000;
+}
+
+static void
+Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x39100;
+}
+
+static void
+Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x139100;
+}
+
+static void
+Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x619100;
+}
+
+static void
+Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3a100;
+}
+
+static void
+Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13a100;
+}
+
+static void
+Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61a100;
+}
+
+static void
+Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000;
+}
+
+static void
+Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138000;
+}
+
+static void
+Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618000;
+}
+
+static void
+Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38100;
+}
+
+static void
+Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x138100;
+}
+
+static void
+Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x618100;
+}
+
+static void
+Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36000;
+}
+
+static void
+Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136000;
+}
+
+static void
+Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616000;
+}
+
+static void
+Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e900;
+}
+
+static void
+Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e900;
+}
+
+static void
+Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e900;
+}
+
+static void
+Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ec00;
+}
+
+static void
+Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ec00;
+}
+
+static void
+Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ec00;
+}
+
+static void
+Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ed00;
+}
+
+static void
+Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ed00;
+}
+
+static void
+Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ed00;
+}
+
+static void
+Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x36800;
+}
+
+static void
+Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x136800;
+}
+
+static void
+Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x616800;
+}
+
+static void
+Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e000;
+}
+
+static void
+Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1e010;
+}
+
+static void
+Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135900;
+}
+
+static void
+Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000;
+}
+
+static void
+Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x120000;
+}
+
+static void
+Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x220000;
+}
+
+static void
+Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x320000;
+}
+
+static void
+Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x420000;
+}
+
+static void
+Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9000;
+}
+
+static void
+Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa000;
+}
+
+static void
+Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb000;
+}
+
+static void
+Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x76;
+}
+
+static void
+Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1076;
+}
+
+static void
+Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc30000;
+}
+
+static void
+Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd30000;
+}
+
+static void
+Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30400;
+}
+
+static void
+Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130400;
+}
+
+static void
+Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610400;
+}
+
+static void
+Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3ea00;
+}
+
+static void
+Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13ea00;
+}
+
+static void
+Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61ea00;
+}
+
+static void
+Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f000;
+}
+
+static void
+Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f000;
+}
+
+static void
+Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f000;
+}
+
+static void
+Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f100;
+}
+
+static void
+Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f100;
+}
+
+static void
+Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f100;
+}
+
+static void
+Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3f200;
+}
+
+static void
+Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13f200;
+}
+
+static void
+Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61f200;
+}
+
+static void
+Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70c2;
+}
+
+static void
+Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70e2;
+}
+
+static void
+Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70d2;
+}
+
+static void
+Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x270d2;
+}
+
+static void
+Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x370d2;
+}
+
+static void
+Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70f2;
+}
+
+static void
+Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf10000;
+}
+
+static void
+Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf12000;
+}
+
+static void
+Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf11000;
+}
+
+static void
+Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf13000;
+}
+
+static void
+Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7042;
+}
+
+static void
+Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7052;
+}
+
+static void
+Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x47082;
+}
+
+static void
+Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x57082;
+}
+
+static void
+Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7062;
+}
+
+static void
+Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7072;
+}
+
+static void
+Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7002;
+}
+
+static void
+Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7012;
+}
+
+static void
+Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7022;
+}
+
+static void
+Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7032;
+}
+
+static void
+Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7082;
+}
+
+static void
+Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x27082;
+}
+
+static void
+Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x37082;
+}
+
+static void
+Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf19000;
+}
+
+static void
+Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf18000;
+}
+
+static void
+Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135300;
+}
+
+static void
+Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35300;
+}
+
+static void
+Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615300;
+}
+
+static void
+Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35a00;
+}
+
+static void
+Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135a00;
+}
+
+static void
+Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615a00;
+}
+
+static void
+Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35b00;
+}
+
+static void
+Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135b00;
+}
+
+static void
+Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615b00;
+}
+
+static void
+Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x35c00;
+}
+
+static void
+Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x135c00;
+}
+
+static void
+Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x615c00;
+}
+
+static void
+Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50c000;
+}
+
+static void
+Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50d000;
+}
+
+static void
+Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50b000;
+}
+
+static void
+Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50f000;
+}
+
+static void
+Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50e000;
+}
+
+static void
+Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x504000;
+}
+
+static void
+Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x505000;
+}
+
+static void
+Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x503000;
+}
+
+static void
+Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x507000;
+}
+
+static void
+Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x506000;
+}
+
+static void
+Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf1f000;
+}
+
+static void
+Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x501000;
+}
+
+static void
+Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x509000;
+}
+
+static void
+Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3e000;
+}
+
+static void
+Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x13e000;
+}
+
+static void
+Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x61e000;
+}
+
+static void
+Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x330000;
+}
+
+static void
+Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x33000;
+}
+
+static void
+Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x430000;
+}
+
+static void
+Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x43000;
+}
+
+static void
+Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x530000;
+}
+
+static void
+Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x53000;
+}
+
+static void
+Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x630000;
+}
+
+static void
+Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x63000;
+}
+
+static void
+Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x730000;
+}
+
+static void
+Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x73000;
+}
+
+static void
+Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e000;
+}
+
+static void
+Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40e00;
+}
+
+static void
+Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f000;
+}
+
+static void
+Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40f00;
+}
+
+static void
+Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x230000;
+}
+
+static void
+Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9f000;
+}
+
+static void
+Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000;
+}
+
+static void
+Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x23000;
+}
+
+static void
+Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb002;
+}
+
+static void
+Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf002;
+}
+
+static void
+Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe002;
+}
+
+static void
+Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30c00;
+}
+
+static void
+Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x130c00;
+}
+
+static void
+Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x610c00;
+}
+
+static void
+Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc20000;
+}
+
+static void
+Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xd20000;
+}
+
+static void
+Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe20000;
+}
+
+static void
+Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf20000;
+}
+
+static void
+Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x820000;
+}
+
+static void
+Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9d000;
+}
+
+static void
+Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x82000;
+}
+
+static void
+Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa20000;
+}
+
+static void
+Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb20000;
+}
+
+static void
+Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e80;
+}
+
+static void
+Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e800;
+}
+
+static void
+Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xe30e90;
+}
+
+static void
+Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xf3e900;
+}
+
+static void
+Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000;
+}
+
+static void
+Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1a0000;
+}
+
+static void
+Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2a0000;
+}
+
+static void
+Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4a0000;
+}
+
+static void
+Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5a0000;
+}
+
+static void
+Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xcb0000;
+}
+
+static void
+Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xdb0000;
+}
+
+static void
+Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8b0000;
+}
+
+static void
+Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9b0000;
+}
+
+static void
+Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xab0000;
+}
+
+static void
+Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xbb0000;
+}
+
+static void
+Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xfa0010;
+}
+
+static void
+Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xfa0000;
+}
+
+static void
+Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xfa0060;
+}
+
+static void
+Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x1b0000;
+}
+
+static void
+Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x2b0000;
+}
+
+static void
+Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3b0000;
+}
+
+static void
+Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4b0000;
+}
+
+static void
+Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x5b0000;
+}
+
+static void
+Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x6b0000;
+}
+
+static void
+Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x7b0000;
+}
+
+static void
+Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xca0000;
+}
+
+static void
+Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xda0000;
+}
+
+static void
+Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8a0000;
+}
+
+static void
+Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xba0000;
+}
+
+static void
+Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xaa0000;
+}
+
+static void
+Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x9a0000;
+}
+
+static void
+Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xea0000;
+}
+
+static void
+Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xfa0040;
+}
+
+static void
+Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xfa0050;
+}
+
+static void
+Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x3;
+}
+
+static void
+Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8003;
+}
+
+static void
+Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80000;
+}
+
+static void
+Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x180000;
+}
+
+static void
+Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x4003;
+}
+
+static void
+Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc003;
+}
+
+static void
+Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x480000;
+}
+
+static void
+Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x580000;
+}
+
+static void
+Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa8000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xc0000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb0000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xb8000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x40000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x98000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x50000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x70000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x60000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x80000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x8000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x10000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x38000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x90000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x48000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x68000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x58000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x78000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x20000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0xa0000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x18000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x88000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x28000000;
+ slotbuf[1] = 0;
+}
+
+static void
+Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
+{
+ slotbuf[0] = 0x30000000;
+ slotbuf[1] = 0;
+}
+
+xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
+ Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
+ Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
+ Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
+ Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+ Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
+ Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
+ Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
+ Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
+ Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
+ Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
+ Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
+ Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
+ Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
+ Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
+ Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
+ 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
+ Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
+ Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
+ Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
+ Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
+ Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
+ Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
+ Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
+ Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
+ Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
+ Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
+ 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
+ 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
+ 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
+ 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
+ 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
+ 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
+ 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
+ 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
+ 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
+ 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
+ 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
+ Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
+ Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
+ Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
+ Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
+ Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
+ Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
+ Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
+ Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
+ Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
+ Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
+ Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
+ Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
+ Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
+ Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
+ Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
+ Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
+ Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
+ Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
+ Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
+ Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
+ Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
+ Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
+ Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
+ Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
+ Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
+ Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
+ Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
+ Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
+ Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
+ Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
+ Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
+ Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
+ Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
+ Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
+ Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
+ Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
+ Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
+ Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
+ Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
+ Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
+ Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
+ Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
+ Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
+ Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
+ Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
+ Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
+ Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
+ Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
+ Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
+ Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
+ Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
+ Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
+ Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
+ Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
+ Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
+ Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
+ Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
+ Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
+ Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
+ Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
+ Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
+ Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
+ Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
+ Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
+ Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
+ Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
+ Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
+ Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
+ Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
+ Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
+ Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
+ Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
+ Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
+ Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
+ Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
+ Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
+ Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
+ Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
+ Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
+ Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
+ Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
+ Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
+ Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
+ Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
+ Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
+ Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
+ Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
+ Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
+ Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
+ Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
+ Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
+ Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
+ Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
+ Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
+ Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
+ Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
+ Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
+ Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
+ Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
+ Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
+ Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
+ Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
+ Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
+ Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
+ Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
+ Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
+ Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
+ Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
+ Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
+ Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
+ Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
+ Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
+ Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
+ Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
+ Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
+ Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
+ Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
+ Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
+ Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
+ Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
+ Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
+ Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
+ Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
+ Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
+ Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
+ Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
+ Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
+ Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
+ Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
+ Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
+ Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
+ Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
+ Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
+ Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
+ Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
+ Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
+ Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
+ Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
+ Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
+ Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
+ Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
+ Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
+ Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
+ Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
+ Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
+ Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
+ Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
+ Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
+ Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
+ Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
+ Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
+ Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
+ Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
+ Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
+ Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
+ Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
+ Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
+ Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
+ Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
+ Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
+ Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
+ Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
+ Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
+ Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
+ Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
+ Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
+ Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
+ Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
+ Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
+ Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
+ Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
+ Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
+ Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
+ Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
+ Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
+ Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
+ Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
+ Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
+ Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
+ Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
+ Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
+ Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
+ Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
+ Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
+ Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
+ Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
+ Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
+ Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
+ Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
+ Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
+ Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
+ Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
+ Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
+ Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
+ Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
+ Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
+ Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
+ Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
+ Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
+ Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
+ Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
+ Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
+ Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
+ Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
+ Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
+ Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
+ Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
+ Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
+ Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
+ Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
+ Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
+ Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
+ Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
+ Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
+ Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
+ Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
+ Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
+ Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
+ Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
+ Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
+ Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
+ Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
+ Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
+ Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
+ Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
+ Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
+ Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
+ Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
+ Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
+ Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
+ Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
+ Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
+ Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
+ Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
+ Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
+ Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
+ Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
+ Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
+ Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
+ Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
+ Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
+ Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
+ Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
+ Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
+ Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
+ Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
+ Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
+ Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
+ Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
+ Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
+ Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
+ Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
+ Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
+ Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
+ Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
+ Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
+ Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
+ Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
+ Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
+ Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
+ Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
+ Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
+ Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
+ Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
+ Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
+ Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
+ Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
+ Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
+ Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
+ Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
+ Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
+ Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
+ Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
+ Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
+ Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
+ Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
+ Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
+ Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
+ Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
+ Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
+ Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
+ Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
+ Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
+ Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
+ Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
+ Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
+ 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
+ Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
+ Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
+ Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
+ Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
+ Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
+ Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
+ Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
+ Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
+ Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
+ Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
+ Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
+ Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
+ Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
+ Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
+ Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
+ Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
+ Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
+ Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
+ Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
+ Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
+ Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
+ Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
+ Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
+ Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
+ Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
+ Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
+ Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
+ Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
+ Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
+ Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
+ Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
+ Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
+ Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
+ Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
+ Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
+ Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
+ Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
+ Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
+ Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
+ Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
+ Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
+ Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
+ Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
+ Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
+ Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
+ Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
+ Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
+ Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
+ Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
+ Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
+ Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
+ Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
+ Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
+ Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
+ Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
+ Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
+ Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
+ Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
+ Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
+ Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
+ Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
+ Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
+ Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
+ Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
+ Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
+ Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
+ Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
+ Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
+ Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
+ Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
+ Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
+ Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
+ Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
+ Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
+ Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
+ Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
+ Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
+ Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
+ Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
+ Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
+ Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
+ Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
+ Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
+ Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
+ Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
+ Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
+ Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
+ Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
+ Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
+ Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
+ Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
+ Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
+ Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
+ Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
+ Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
+ Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
+ Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
+ Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
+ Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
+ Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
+ Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
+ Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
+ Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
+ Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
+ Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
+ Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
+ Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
+ Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
+ Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
+ Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
+ Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
+ Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
+ Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
+ Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
+ Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
+ Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
+ Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
+ Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
+ Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
+ Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
+ Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
+ Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
+ Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
+ Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
+ Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
+};
+
+xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
+ Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
+ Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
+ Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
+ Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
+ Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
+ Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
+ Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
+ Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
+ Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
+ Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
+ Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
+ Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
+ Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
+ Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
+ Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
+ Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
+ Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
+ Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
+ Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
+ Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
+ Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
+ Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
+ Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
+ Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
+ Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
+ Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
+ Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
+ Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
+ Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
+ Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
+ Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
+ Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
+ Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
+ Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
+ Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
+ Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
+ Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
+ Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
+ Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
+ Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
+ Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
+ Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
+ Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
+ Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
+ Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
+ Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
+ Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
+ Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
+ Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
+ Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
+ Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
+ Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
+ Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
+ Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
+ Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
+};
+
+xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
+};
+
+xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
+ 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
+};
+
+\f
+/* Opcode table. */
+
+static xtensa_opcode_internal opcodes[] = {
+ { "excw", 0 /* xt_iclass_excw */,
+ 0,
+ Opcode_excw_encode_fns, 0, 0 },
+ { "rfe", 1 /* xt_iclass_rfe */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfe_encode_fns, 0, 0 },
+ { "rfde", 2 /* xt_iclass_rfde */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfde_encode_fns, 0, 0 },
+ { "syscall", 3 /* xt_iclass_syscall */,
+ 0,
+ Opcode_syscall_encode_fns, 0, 0 },
+ { "simcall", 4 /* xt_iclass_simcall */,
+ 0,
+ Opcode_simcall_encode_fns, 0, 0 },
+ { "call12", 5 /* xt_iclass_call12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call12_encode_fns, 0, 0 },
+ { "call8", 6 /* xt_iclass_call8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call8_encode_fns, 0, 0 },
+ { "call4", 7 /* xt_iclass_call4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_call4_encode_fns, 0, 0 },
+ { "callx12", 8 /* xt_iclass_callx12 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx12_encode_fns, 0, 0 },
+ { "callx8", 9 /* xt_iclass_callx8 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx8_encode_fns, 0, 0 },
+ { "callx4", 10 /* xt_iclass_callx4 */,
+ XTENSA_OPCODE_IS_CALL,
+ Opcode_callx4_encode_fns, 0, 0 },
+ { "entry", 11 /* xt_iclass_entry */,
+ 0,
+ Opcode_entry_encode_fns, 0, 0 },
+ { "movsp", 12 /* xt_iclass_movsp */,
+ 0,
+ Opcode_movsp_encode_fns, 0, 0 },
+ { "rotw", 13 /* xt_iclass_rotw */,
+ 0,
+ Opcode_rotw_encode_fns, 0, 0 },
+ { "retw", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_encode_fns, 0, 0 },
+ { "retw.n", 14 /* xt_iclass_retw */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_retw_n_encode_fns, 0, 0 },
+ { "rfwo", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwo_encode_fns, 0, 0 },
+ { "rfwu", 15 /* xt_iclass_rfwou */,
+ XTENSA_OPCODE_IS_JUMP,
+ Opcode_rfwu_encode_fns, 0, 0 },
+ { "l32e", 16 /* xt_iclass_l32e */,
+ 0,
+ Opcode_l32e_encode_fns, 0, 0 },
+ { "s32e", 17 /* xt_iclass_s32e */,
+ 0,
+ Opcode_s32e_encode_fns, 0, 0 },
+ { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
+ 0,
+ Opcode_rsr_windowbase_encode_fns, 0, 0 },
+ { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
+ 0,
+ Opcode_wsr_windowbase_encode_fns, 0, 0 },
+ { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
+ 0,
+ Opcode_xsr_windowbase_encode_fns, 0, 0 },
+ { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,