+;
+; Hardware: virtual registerts for FPU (single precision)
+; mapped to GPRs
+;
+(define-hardware
+ (name h-fsr)
+ (comment "floating point registers (single, virtual)")
+ (attrs VIRTUAL (MACH ORFPX32-MACHS))
+ (type register SF (32))
+ (indices keyword "" REG-INDICES)
+ (get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
+ (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
+ )
+
+;
+; Register pairs are offset by 2 for registers r16 and above. This is to
+; be able to allow registers to be call saved in GCC across function calls.
+;
+(define-pmacro (reg-pair-reg-lo index)
+ (and index (const #x1f))
+)
+
+(define-pmacro (reg-pair-reg-hi index)
+ (add (and index (const #x1f))
+ (if (eq (sra index (const 5))
+ (const 1))
+ (const 2)
+ (const 1)
+ )
+ )
+)
+
+;
+; Hardware: vrtual registers for double precision floating point
+; operands on 32-bit machines
+; mapped to GPRs
+;
+(define-hardware
+ (name h-fd32r)
+ (comment "or32 floating point registers (double, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DF (32))
+ (get (index) (join DF SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+
+;
+; Hardware: vrtual 64-bit integer registers for conversions
+; float64 <-> int64 on 32-bit machines
+; mapped to GPRs
+;
+(define-hardware
+ (name h-i64r)
+ (comment "or32 double word registers (int64, virtual)")
+ (attrs VIRTUAL (MACH ORFPX64A32-MACHS))
+ (type register DI (32))
+ (get (index) (join DI SI
+ (reg h-gpr (reg-pair-reg-lo index))
+ (reg h-gpr (reg-pair-reg-hi index))))
+ (set (index newval)
+ (sequence ()
+ (set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
+ (set (reg h-gpr (reg-pair-reg-hi index))
+ (subword SI newval 1))))
+)
+
+