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mtd: nand: drop unnecessary partition parser data
[deliverable/linux.git]
/
drivers
/
mtd
/
nand
/
lpc32xx_slc.c
diff --git
a/drivers/mtd/nand/lpc32xx_slc.c
b/drivers/mtd/nand/lpc32xx_slc.c
index abfec13868e5d8d3b95e3e9bd3e3e0e9759fd236..277626e46379ce408697a300b9d073e01ad2d54d 100644
(file)
--- a/
drivers/mtd/nand/lpc32xx_slc.c
+++ b/
drivers/mtd/nand/lpc32xx_slc.c
@@
-94,22
+94,25
@@
/**********************************************************************
* slc_tac register definitions
**********************************************************************/
/**********************************************************************
* slc_tac register definitions
**********************************************************************/
+/* Computation of clock cycles on basis of controller and device clock rates */
+#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
+
/* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
/* Write pulse width in clock cycles, 1 to 16 clocks */
/* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
/* Write pulse width in clock cycles, 1 to 16 clocks */
-#define SLCTAC_WWIDTH(
n) (((n) & 0xF) << 24
)
+#define SLCTAC_WWIDTH(
c, n) (SLCTAC_CLOCKS(c, n, 24)
)
/* Write hold time of control and data signals, 1 to 16 clocks */
/* Write hold time of control and data signals, 1 to 16 clocks */
-#define SLCTAC_WHOLD(
n) (((n) & 0xF) << 20
)
+#define SLCTAC_WHOLD(
c, n) (SLCTAC_CLOCKS(c, n, 20)
)
/* Write setup time of control and data signals, 1 to 16 clocks */
/* Write setup time of control and data signals, 1 to 16 clocks */
-#define SLCTAC_WSETUP(
n) (((n) & 0xF) << 16
)
+#define SLCTAC_WSETUP(
c, n) (SLCTAC_CLOCKS(c, n, 16)
)
/* Clock setting for RDY read sample wait time in 2*n clocks */
#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
/* Read pulse width in clock cycles, 1 to 16 clocks */
/* Clock setting for RDY read sample wait time in 2*n clocks */
#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
/* Read pulse width in clock cycles, 1 to 16 clocks */
-#define SLCTAC_RWIDTH(
n) (((n) & 0xF) << 8
)
+#define SLCTAC_RWIDTH(
c, n) (SLCTAC_CLOCKS(c, n, 8)
)
/* Read hold time of control and data signals, 1 to 16 clocks */
/* Read hold time of control and data signals, 1 to 16 clocks */
-#define SLCTAC_RHOLD(
n) (((n) & 0xF) << 4
)
+#define SLCTAC_RHOLD(
c, n) (SLCTAC_CLOCKS(c, n, 4)
)
/* Read setup time of control and data signals, 1 to 16 clocks */
/* Read setup time of control and data signals, 1 to 16 clocks */
-#define SLCTAC_RSETUP(
n) (((n) & 0xF) << 0
)
+#define SLCTAC_RSETUP(
c, n) (SLCTAC_CLOCKS(c, n, 0)
)
/**********************************************************************
* slc_ecc register definitions
/**********************************************************************
* slc_ecc register definitions
@@
-240,13
+243,13
@@
static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
/* Compute clock setup values */
tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
/* Compute clock setup values */
tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
- SLCTAC_WWIDTH(
1 + (clkrate / host->ncfg->wwidth)
) |
- SLCTAC_WHOLD(
1 + (clkrate / host->ncfg->whold)
) |
- SLCTAC_WSETUP(
1 + (clkrate / host->ncfg->wsetup)
) |
+ SLCTAC_WWIDTH(
clkrate, host->ncfg->wwidth
) |
+ SLCTAC_WHOLD(
clkrate, host->ncfg->whold
) |
+ SLCTAC_WSETUP(
clkrate, host->ncfg->wsetup
) |
SLCTAC_RDR(host->ncfg->rdr_clks) |
SLCTAC_RDR(host->ncfg->rdr_clks) |
- SLCTAC_RWIDTH(
1 + (clkrate / host->ncfg->rwidth)
) |
- SLCTAC_RHOLD(
1 + (clkrate / host->ncfg->rhold)
) |
- SLCTAC_RSETUP(
1 + (clkrate / host->ncfg->rsetup)
);
+ SLCTAC_RWIDTH(
clkrate, host->ncfg->rwidth
) |
+ SLCTAC_RHOLD(
clkrate, host->ncfg->rhold
) |
+ SLCTAC_RSETUP(
clkrate, host->ncfg->rsetup
);
writel(tmp, SLC_TAC(host->io_base));
}
writel(tmp, SLC_TAC(host->io_base));
}
@@
-660,7
+663,8
@@
static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
*/
static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
*/
static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
- const uint8_t *buf, int oob_required)
+ const uint8_t *buf,
+ int oob_required, int page)
{
struct lpc32xx_nand_host *host = chip->priv;
uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
{
struct lpc32xx_nand_host *host = chip->priv;
uint8_t *pb = chip->oob_poi + chip->ecc.layout->eccpos[0];
@@
-689,7
+693,7
@@
static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf,
static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
const uint8_t *buf,
- int oob_required)
+ int oob_required
, int page
)
{
/* Raw writes can just use the FIFO interface */
chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
{
/* Raw writes can just use the FIFO interface */
chip->write_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
@@
-759,7
+763,6
@@
static int lpc32xx_nand_probe(struct platform_device *pdev)
struct mtd_info *mtd;
struct nand_chip *chip;
struct resource *rc;
struct mtd_info *mtd;
struct nand_chip *chip;
struct resource *rc;
- struct mtd_part_parser_data ppdata = {};
int res;
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
int res;
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@
-799,6
+802,7
@@
static int lpc32xx_nand_probe(struct platform_device *pdev)
mtd = &host->mtd;
chip = &host->nand_chip;
chip->priv = host;
mtd = &host->mtd;
chip = &host->nand_chip;
chip->priv = host;
+ nand_set_flash_node(chip, pdev->dev.of_node);
mtd->priv = chip;
mtd->owner = THIS_MODULE;
mtd->dev.parent = &pdev->dev;
mtd->priv = chip;
mtd->owner = THIS_MODULE;
mtd->dev.parent = &pdev->dev;
@@
-810,7
+814,7
@@
static int lpc32xx_nand_probe(struct platform_device *pdev)
res = -ENOENT;
goto err_exit1;
}
res = -ENOENT;
goto err_exit1;
}
- clk_enable(host->clk);
+ clk_
prepare_
enable(host->clk);
/* Set NAND IO addresses and command/ready functions */
chip->IO_ADDR_R = SLC_DATA(host->io_base);
/* Set NAND IO addresses and command/ready functions */
chip->IO_ADDR_R = SLC_DATA(host->io_base);
@@
-904,9
+908,8
@@
static int lpc32xx_nand_probe(struct platform_device *pdev)
}
mtd->name = "nxp_lpc3220_slc";
}
mtd->name = "nxp_lpc3220_slc";
- ppdata.of_node = pdev->dev.of_node;
- res = mtd_device_parse_register(mtd, NULL, &ppdata, host->ncfg->parts,
- host->ncfg->num_parts);
+ res = mtd_device_register(mtd, host->ncfg->parts,
+ host->ncfg->num_parts);
if (!res)
return res;
if (!res)
return res;
@@
-915,7
+918,7
@@
static int lpc32xx_nand_probe(struct platform_device *pdev)
err_exit3:
dma_release_channel(host->dma_chan);
err_exit2:
err_exit3:
dma_release_channel(host->dma_chan);
err_exit2:
- clk_disable(host->clk);
+ clk_disable
_unprepare
(host->clk);
err_exit1:
lpc32xx_wp_enable(host);
err_exit1:
lpc32xx_wp_enable(host);
@@
-939,7
+942,7
@@
static int lpc32xx_nand_remove(struct platform_device *pdev)
tmp &= ~SLCCFG_CE_LOW;
writel(tmp, SLC_CTRL(host->io_base));
tmp &= ~SLCCFG_CE_LOW;
writel(tmp, SLC_CTRL(host->io_base));
- clk_disable(host->clk);
+ clk_disable
_unprepare
(host->clk);
lpc32xx_wp_enable(host);
return 0;
lpc32xx_wp_enable(host);
return 0;
@@
-951,7
+954,7
@@
static int lpc32xx_nand_resume(struct platform_device *pdev)
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
/* Re-enable NAND clock */
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
/* Re-enable NAND clock */
- clk_enable(host->clk);
+ clk_
prepare_
enable(host->clk);
/* Fresh init of NAND controller */
lpc32xx_nand_setup(host);
/* Fresh init of NAND controller */
lpc32xx_nand_setup(host);
@@
-976,7
+979,7
@@
static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
lpc32xx_wp_enable(host);
/* Disable clock */
lpc32xx_wp_enable(host);
/* Disable clock */
- clk_disable(host->clk);
+ clk_disable
_unprepare
(host->clk);
return 0;
}
return 0;
}
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