+
+ /* Upper and lower half of data and address registers. Order *must*
+ be DATAxL, ADDRxL, DATAxU, ADDRxU. */
+ DATA0L, /* lower half of data registers */
+ DATA1L,
+ DATA2L,
+ DATA3L,
+ DATA4L,
+ DATA5L,
+ DATA6L,
+ DATA7L,
+
+ ADDR0L, /* lower half of address registers */
+ ADDR1L,
+ ADDR2L,
+ ADDR3L,
+ ADDR4L,
+ ADDR5L,
+ ADDR6L,
+ ADDR7L,
+
+ DATA0U, /* upper half of data registers */
+ DATA1U,
+ DATA2U,
+ DATA3U,
+ DATA4U,
+ DATA5U,
+ DATA6U,
+ DATA7U,
+
+ ADDR0U, /* upper half of address registers */
+ ADDR1U,
+ ADDR2U,
+ ADDR3U,
+ ADDR4U,
+ ADDR5U,
+ ADDR6U,
+ ADDR7U,