[ARC] Improve parsing instruction operands.

[deliverable/binutils-gdb.git] / gas / config / tc-aarch64.c

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 969c18cfedaf53641e2162d5ef75f351c441f66b..8fa8657afcda44983dd21a7aea0b986904f62d6a 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1,6 +1,6 @@
 /* tc-aarch64.c -- Assemble for the AArch64 ISA
 
 /* tc-aarch64.c -- Assemble for the AArch64 ISA
 

-   Copyright (C) 2009-2017 Free Software Foundation, Inc.
+   Copyright (C) 2009-2020 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of GAS.
    Contributed by ARM Ltd.
 
    This file is part of GAS.


@@ -55,6 +55,9 @@ static const aarch64_feature_set *march_cpu_opt = NULL;
 /* Constants for known architecture features.  */
 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
 
 /* Constants for known architecture features.  */
 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
 

+/* Currently active instruction sequence.  */
+static aarch64_instr_sequence *insn_sequence = NULL;
+

 #ifdef OBJ_ELF
 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 static symbolS *GOT_symbol;
 #ifdef OBJ_ELF
 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 static symbolS *GOT_symbol;


@@ -62,12 +65,20 @@ static symbolS *GOT_symbol;
 /* Which ABI to use.  */
 enum aarch64_abi_type
 {
 /* Which ABI to use.  */
 enum aarch64_abi_type
 {

-  AARCH64_ABI_LP64 = 0,
-  AARCH64_ABI_ILP32 = 1
+  AARCH64_ABI_NONE = 0,
+  AARCH64_ABI_LP64 = 1,
+  AARCH64_ABI_ILP32 = 2

 };
 
 };
 

+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "aarch64"
+#endif
+
+/* DEFAULT_ARCH is initialized in gas/configure.tgt.  */
+static const char *default_arch = DEFAULT_ARCH;
+

 /* AArch64 ABI for the output file.  */
 /* AArch64 ABI for the output file.  */

-static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_LP64;
+static enum aarch64_abi_type aarch64_abi = AARCH64_ABI_NONE;

 
 /* When non-zero, program to a 32-bit model, in which the C data types
    int, long and all pointer types are 32-bit objects (ILP32); or to a
 
 /* When non-zero, program to a 32-bit model, in which the C data types
    int, long and all pointer types are 32-bit objects (ILP32); or to a


@@ -138,6 +149,13 @@ static aarch64_instruction inst;
 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
 
 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
 

+#ifdef OBJ_ELF
+#  define now_instr_sequence seg_info \
+               (now_seg)->tc_segment_info_data.insn_sequence
+#else
+static struct aarch64_instr_sequence now_instr_sequence;
+#endif
+

 /* Diagnostics inline function utilities.
 
    These are lightweight utilities which should only be called by parse_operands
 /* Diagnostics inline function utilities.
 
    These are lightweight utilities which should only be called by parse_operands


@@ -220,9 +238,6 @@ set_fatal_syntax_error (const char *error)
   set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
 }
 \f
   set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
 }
 \f

-/* Number of littlenums required to hold an extended precision number.  */
-#define MAX_LITTLENUMS 6
-

 /* Return value for certain parsers when the parsing fails; those parsers
    return the information of the parsed result, e.g. register number, on
    success.  */
 /* Return value for certain parsers when the parsing fails; those parsers
    return the information of the parsed result, e.g. register number, on
    success.  */


@@ -296,10 +311,11 @@ struct reloc_entry
                 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN)       \
                 | REG_TYPE(FP_B) | REG_TYPE(FP_H)                      \
                 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q))    \
                 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN)       \
                 | REG_TYPE(FP_B) | REG_TYPE(FP_H)                      \
                 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q))    \

-  /* Typecheck: as above, but also Zn and Pn.  This should only be     \
-     used for SVE instructions, since Zn and Pn are valid symbols      \
+  /* Typecheck: as above, but also Zn, Pn, and {W}SP.  This should only        \
+     be used for SVE instructions, since Zn and Pn are valid symbols   \

      in other contexts.  */                                            \
      in other contexts.  */                                            \

-  MULTI_REG_TYPE(R_Z_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64)                \
+  MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64)     \
+                | REG_TYPE(SP_32) | REG_TYPE(SP_64)                    \

                 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN)       \
                 | REG_TYPE(FP_B) | REG_TYPE(FP_H)                      \
                 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)     \
                 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN)       \
                 | REG_TYPE(FP_B) | REG_TYPE(FP_H)                      \
                 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)     \


@@ -407,7 +423,7 @@ get_reg_expected_msg (aarch64_reg_type reg_type)
               "register expected");
       break;
     case REG_TYPE_R_Z_BHSDQ_V:
               "register expected");
       break;
     case REG_TYPE_R_Z_BHSDQ_V:

-    case REG_TYPE_R_Z_BHSDQ_VZP:
+    case REG_TYPE_R_Z_SP_BHSDQ_VZP:

       msg = N_("register expected");
       break;
     case REG_TYPE_BHSDQ:       /* any [BHSDQ]P FP  */
       msg = N_("register expected");
       break;
     case REG_TYPE_BHSDQ:       /* any [BHSDQ]P FP  */


@@ -430,6 +446,7 @@ get_reg_expected_msg (aarch64_reg_type reg_type)
 
 /* Some well known registers that we refer to directly elsewhere.  */
 #define REG_SP 31
 
 /* Some well known registers that we refer to directly elsewhere.  */
 #define REG_SP 31

+#define REG_ZR 31

 
 /* Instructions take 4 bytes in the object file.  */
 #define INSN_SIZE      4
 
 /* Instructions take 4 bytes in the object file.  */
 #define INSN_SIZE      4


@@ -443,6 +460,7 @@ static struct hash_control *aarch64_sys_regs_ic_hsh;
 static struct hash_control *aarch64_sys_regs_dc_hsh;
 static struct hash_control *aarch64_sys_regs_at_hsh;
 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
 static struct hash_control *aarch64_sys_regs_dc_hsh;
 static struct hash_control *aarch64_sys_regs_at_hsh;
 static struct hash_control *aarch64_sys_regs_tlbi_hsh;

+static struct hash_control *aarch64_sys_regs_sr_hsh;

 static struct hash_control *aarch64_reg_hsh;
 static struct hash_control *aarch64_barrier_opt_hsh;
 static struct hash_control *aarch64_nzcv_hsh;
 static struct hash_control *aarch64_reg_hsh;
 static struct hash_control *aarch64_barrier_opt_hsh;
 static struct hash_control *aarch64_nzcv_hsh;


@@ -511,7 +529,7 @@ const char EXP_CHARS[] = "eE";
 /* As in 0f12.456  */
 /* or   0d1.2345e12  */
 
 /* As in 0f12.456  */
 /* or   0d1.2345e12  */
 

-const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+const char FLT_CHARS[] = "rRsSfFdDxXeEpPhH";

 
 /* Prefix character that indicates the start of an immediate value.  */
 #define is_immediate_prefix(C) ((C) == '#')
 
 /* Prefix character that indicates the start of an immediate value.  */
 #define is_immediate_prefix(C) ((C) == '#')


@@ -617,6 +635,54 @@ my_get_expression (expressionS * ep, char **str, int prefix_mode,
 const char *
 md_atof (int type, char *litP, int *sizeP)
 {
 const char *
 md_atof (int type, char *litP, int *sizeP)
 {

+  /* If this is a bfloat16 type, then parse it slightly differently -
+     as it does not follow the IEEE standard exactly.  */
+  if (type == 'b')
+    {
+      char * t;
+      LITTLENUM_TYPE words[MAX_LITTLENUMS];
+      FLONUM_TYPE generic_float;
+
+      t = atof_ieee_detail (input_line_pointer, 1, 8, words, &generic_float);
+
+      if (t)
+       input_line_pointer = t;
+      else
+       return _("invalid floating point number");
+
+      switch (generic_float.sign)
+       {
+       /* Is +Inf.  */
+       case 'P':
+         words[0] = 0x7f80;
+         break;
+
+       /* Is -Inf.  */
+       case 'N':
+         words[0] = 0xff80;
+         break;
+
+       /* Is NaN.  */
+       /* bfloat16 has two types of NaN - quiet and signalling.
+          Quiet NaN has bit[6] == 1 && faction != 0, whereas
+          signalling Nan's have bit[0] == 0 && fraction != 0.
+          Chose this specific encoding as it is the same form
+          as used by other IEEE 754 encodings in GAS.  */
+       case 0:
+         words[0] = 0x7fff;
+         break;
+
+       default:
+         break;
+       }
+
+      *sizeP = 2;
+
+      md_number_to_chars (litP, (valueT) words[0], sizeof (LITTLENUM_TYPE));
+
+      return NULL;
+    }
+

   return ieee_md_atof (type, litP, sizeP, target_big_endian);
 }
 
   return ieee_md_atof (type, litP, sizeP, target_big_endian);
 }
 


@@ -790,7 +856,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
    succeeds; otherwise return FALSE.
 
    Accept only one occurrence of:
    succeeds; otherwise return FALSE.
 
    Accept only one occurrence of:

-   8b 16b 2h 4h 8h 2s 4s 1d 2d
+   4b 8b 16b 2h 4h 8h 2s 4s 1d 2d

    b h s d q  */
 static bfd_boolean
 parse_vector_type_for_operand (aarch64_reg_type reg_type,
    b h s d q  */
 static bfd_boolean
 parse_vector_type_for_operand (aarch64_reg_type reg_type,


@@ -851,8 +917,10 @@ elt_size:
        first_error (_("missing element size"));
       return FALSE;
     }
        first_error (_("missing element size"));
       return FALSE;
     }

-  if (width != 0 && width * element_size != 64 && width * element_size != 128
-      && !(width == 2 && element_size == 16))
+  if (width != 0 && width * element_size != 64
+      && width * element_size != 128
+      && !(width == 2 && element_size == 16)
+      && !(width == 4 && element_size == 8))

     {
       first_error_fmt (_
                       ("invalid element size %d and vector size combination %c"),
     {
       first_error_fmt (_
                       ("invalid element size %d and vector size combination %c"),


@@ -992,7 +1060,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
          return PARSE_FAIL;
        }
 
          return PARSE_FAIL;
        }
 

-      if (in_reg_list == TRUE)
+      if (in_reg_list)

        {
          first_error (_("index not allowed inside register list"));
          return PARSE_FAIL;
        {
          first_error (_("index not allowed inside register list"));
          return PARSE_FAIL;


@@ -1916,6 +1984,28 @@ s_aarch64_elf_cons (int nbytes)
   demand_empty_rest_of_line ();
 }
 
   demand_empty_rest_of_line ();
 }
 

+/* Mark symbol that it follows a variant PCS convention.  */
+
+static void
+s_variant_pcs (int ignored ATTRIBUTE_UNUSED)
+{
+  char *name;
+  char c;
+  symbolS *sym;
+  asymbol *bfdsym;
+  elf_symbol_type *elfsym;
+
+  c = get_symbol_name (&name);
+  if (!*name)
+    as_bad (_("Missing symbol name in directive"));
+  sym = symbol_find_or_make (name);
+  restore_line_pointer (c);
+  demand_empty_rest_of_line ();
+  bfdsym = symbol_get_bfdsym (sym);
+  elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
+  gas_assert (elfsym);
+  elfsym->internal_elf_sym.st_other |= STO_AARCH64_VARIANT_PCS;
+}

 #endif /* OBJ_ELF */
 
 /* Output a 32-bit word, but mark as an instruction.  */
 #endif /* OBJ_ELF */
 
 /* Output a 32-bit word, but mark as an instruction.  */


@@ -1971,6 +2061,14 @@ s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
   demand_empty_rest_of_line ();
 }
 

+static void
+s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+  struct fde_entry *fde = frchain_now->frch_cfi_data->cur_fde_data;
+  fde->pauth_key = AARCH64_PAUTH_KEY_B;
+}
+

 #ifdef OBJ_ELF
 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction.  */
 
 #ifdef OBJ_ELF
 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction.  */
 


@@ -2045,6 +2143,7 @@ const pseudo_typeS md_pseudo_table[] = {
   {"arch", s_aarch64_arch, 0},
   {"arch_extension", s_aarch64_arch_extension, 0},
   {"inst", s_aarch64_inst, 0},
   {"arch", s_aarch64_arch, 0},
   {"arch_extension", s_aarch64_arch_extension, 0},
   {"inst", s_aarch64_inst, 0},

+  {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame, 0},

 #ifdef OBJ_ELF
   {"tlsdescadd", s_tlsdescadd, 0},
   {"tlsdesccall", s_tlsdesccall, 0},
 #ifdef OBJ_ELF
   {"tlsdescadd", s_tlsdescadd, 0},
   {"tlsdesccall", s_tlsdesccall, 0},


@@ -2053,7 +2152,10 @@ const pseudo_typeS md_pseudo_table[] = {
   {"long", s_aarch64_elf_cons, 4},
   {"xword", s_aarch64_elf_cons, 8},
   {"dword", s_aarch64_elf_cons, 8},
   {"long", s_aarch64_elf_cons, 4},
   {"xword", s_aarch64_elf_cons, 8},
   {"dword", s_aarch64_elf_cons, 8},

+  {"variant_pcs", s_variant_pcs, 0},

 #endif
 #endif

+  {"float16", float_cons, 'h'},
+  {"bfloat16", float_cons, 'b'},

   {0, 0, 0}
 };
 \f
   {0, 0, 0}
 };
 \f


@@ -2268,7 +2370,6 @@ parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
   char *str = *ccp;
   char *fpnum;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
   char *str = *ccp;
   char *fpnum;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];

-  int found_fpchar = 0;

   int64_t val = 0;
   unsigned fpword = 0;
   bfd_boolean hex_p = FALSE;
   int64_t val = 0;
   unsigned fpword = 0;
   bfd_boolean hex_p = FALSE;


@@ -2298,26 +2399,10 @@ parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p,
 
       hex_p = TRUE;
     }
 
       hex_p = TRUE;
     }

-  else
-    {
-      if (reg_name_p (str, reg_type))
-       {
-         set_recoverable_error (_("immediate operand required"));
-         return FALSE;
-       }
-
-      /* We must not accidentally parse an integer as a floating-point number.
-        Make sure that the value we parse is not an integer by checking for
-        special characters '.' or 'e'.  */
-      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
-       if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
-         {
-           found_fpchar = 1;
-           break;
-         }
-
-      if (!found_fpchar)
-       return FALSE;
+  else if (reg_name_p (str, reg_type))
+   {
+     set_recoverable_error (_("immediate operand required"));
+     return FALSE;

     }
 
   if (! hex_p)
     }
 
   if (! hex_p)


@@ -2566,6 +2651,69 @@ static struct reloc_table_entry reloc_table[] = {
    0,
    0},
 
    0,
    0},
 

+  /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
+  {"prel_g0", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G0,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
+  {"prel_g0_nc", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
+  {"prel_g1", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G1,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
+  {"prel_g1_nc", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
+  {"prel_g2", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G2,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
+  {"prel_g2_nc", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
+   0,
+   0,
+   0},
+
+  /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
+  {"prel_g3", 1,
+   0,                          /* adr_type */
+   0,
+   BFD_RELOC_AARCH64_MOVW_PREL_G3,
+   0,
+   0,
+   0},
+

   /* Get to the page containing GOT entry for a symbol.  */
   {"got", 1,
    0,                          /* adr_type */
   /* Get to the page containing GOT entry for a symbol.  */
   {"got", 1,
    0,                          /* adr_type */


@@ -2679,7 +2827,7 @@ static struct reloc_table_entry reloc_table[] = {
    0,                          /* adr_type */
    0,
    0,
    0,                          /* adr_type */
    0,
    0,

-   BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+   BFD_RELOC_AARCH64_TLSDESC_ADD_LO12,

    BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
    0},
 
    BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
    0},
 


@@ -2828,7 +2976,7 @@ static struct reloc_table_entry reloc_table[] = {
    0,
    0,
    BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
    0,
    0,
    BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,

-   0,
+   BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12,

    0},
 
   /* Get tp offset for a symbol.  */
    0},
 
   /* Get tp offset for a symbol.  */


@@ -2846,7 +2994,7 @@ static struct reloc_table_entry reloc_table[] = {
    0,
    0,
    BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
    0,
    0,
    BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,

-   0,
+   BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC,

    0},
 
   /* Most significant bits 32-47 of address/value: MOVZ.  */
    0},
 
   /* Most significant bits 32-47 of address/value: MOVZ.  */


@@ -3001,7 +3149,7 @@ parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
   switch (mode)
     {
     case SHIFTED_LOGIC_IMM:
   switch (mode)
     {
     case SHIFTED_LOGIC_IMM:

-      if (aarch64_extend_operator_p (kind) == TRUE)
+      if (aarch64_extend_operator_p (kind))

        {
          set_syntax_error (_("extending shift is not permitted"));
          return FALSE;
        {
          set_syntax_error (_("extending shift is not permitted"));
          return FALSE;


@@ -3092,7 +3240,7 @@ parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
     operand->shifter.amount = 1;
   else if (exp.X_op == O_absent)
     {
     operand->shifter.amount = 1;
   else if (exp.X_op == O_absent)
     {

-      if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
+      if (!aarch64_extend_operator_p (kind) || exp_has_prefix)

        {
          set_syntax_error (_("missing shift amount"));
          return FALSE;
        {
          set_syntax_error (_("missing shift amount"));
          return FALSE;


@@ -3303,6 +3451,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
      [base,Xm,SXTX {#imm}]
      [base,Wm,(S|U)XTW {#imm}]
    Pre-indexed
      [base,Xm,SXTX {#imm}]
      [base,Wm,(S|U)XTW {#imm}]
    Pre-indexed

+     [base]!                    // in ldraa/ldrab exclusive

      [base,#imm]!
    Post-indexed
      [base],#imm
      [base,#imm]!
    Post-indexed
      [base],#imm


@@ -3316,6 +3465,7 @@ parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
      [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
      [Zn.S,#imm]
      [Zn.D,#imm]
      [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
      [Zn.S,#imm]
      [Zn.D,#imm]

+     [Zn.S{, Xm}]

      [Zn.S,Zm.S{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
      [Zn.S,Zm.S{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D{,LSL #imm}]      // in ADR
      [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR


@@ -3481,6 +3631,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
                return FALSE;
            }
          /* We only accept:
                return FALSE;
            }
          /* We only accept:

+            [base,Xm]  # For vector plus scalar SVE2 indexing.

             [base,Xm{,LSL #imm}]
             [base,Xm,SXTX {#imm}]
             [base,Wm,(S|U)XTW {#imm}]  */
             [base,Xm{,LSL #imm}]
             [base,Xm,SXTX {#imm}]
             [base,Wm,(S|U)XTW {#imm}]  */


@@ -3494,7 +3645,10 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
                  return FALSE;
                }
              if (aarch64_get_qualifier_esize (*base_qualifier)
                  return FALSE;
                }
              if (aarch64_get_qualifier_esize (*base_qualifier)

-                 != aarch64_get_qualifier_esize (*offset_qualifier))
+                 != aarch64_get_qualifier_esize (*offset_qualifier)
+                 && (operand->type != AARCH64_OPND_SVE_ADDR_ZX
+                     || *base_qualifier != AARCH64_OPND_QLF_S_S
+                     || *offset_qualifier != AARCH64_OPND_QLF_X))

                {
                  set_syntax_error (_("offset has different size from base"));
                  return FALSE;
                {
                  set_syntax_error (_("offset has different size from base"));
                  return FALSE;


@@ -3612,18 +3766,43 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
     }
 
   /* If at this point neither .preind nor .postind is set, we have a
     }
 
   /* If at this point neither .preind nor .postind is set, we have a

-     bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0].  */
+     bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
+     ldrab, accept [Rn] as a shorthand for [Rn,#0].
+     For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
+     [Zn.<T>, xzr].  */

   if (operand->addr.preind == 0 && operand->addr.postind == 0)
     {
       if (operand->addr.writeback)
        {
   if (operand->addr.preind == 0 && operand->addr.postind == 0)
     {
       if (operand->addr.writeback)
        {

-         /* Reject [Rn]!   */
-         set_syntax_error (_("missing offset in the pre-indexed address"));
-         return FALSE;
+         if (operand->type == AARCH64_OPND_ADDR_SIMM10)
+            {
+              /* Accept [Rn]! as a shorthand for [Rn,#0]!   */
+              operand->addr.offset.is_reg = 0;
+              operand->addr.offset.imm = 0;
+              operand->addr.preind = 1;
+            }
+          else
+           {
+            /* Reject [Rn]!   */
+            set_syntax_error (_("missing offset in the pre-indexed address"));
+            return FALSE;
+          }
+       }
+       else
+       {
+          operand->addr.preind = 1;
+          if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
+          {
+            operand->addr.offset.is_reg = 1;
+            operand->addr.offset.regno = REG_ZR;
+            *offset_qualifier = AARCH64_OPND_QLF_X;
+          }
+          else
+          {
+            inst.reloc.exp.X_op = O_constant;
+            inst.reloc.exp.X_add_number = 0;
+          }

        }
        }

-      operand->addr.preind = 1;
-      inst.reloc.exp.X_op = O_constant;
-      inst.reloc.exp.X_add_number = 0;

     }
 
   *str = p;
     }
 
   *str = p;


@@ -3864,6 +4043,47 @@ parse_barrier_psb (char **str,
   return 0;
 }
 
   return 0;
 }
 

+/* Parse an operand for BTI.  Set *HINT_OPT to the hint-option record
+   return 0 if successful.  Otherwise return PARSE_FAIL.  */
+
+static int
+parse_bti_operand (char **str,
+                  const struct aarch64_name_value_pair ** hint_opt)
+{
+  char *p, *q;
+  const struct aarch64_name_value_pair *o;
+
+  p = q = *str;
+  while (ISALPHA (*q))
+    q++;
+
+  o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
+  if (!o)
+    {
+      set_fatal_syntax_error
+       ( _("unknown option to BTI"));
+      return PARSE_FAIL;
+    }
+
+  switch (o->value)
+    {
+    /* Valid BTI operands.  */
+    case HINT_OPD_C:
+    case HINT_OPD_J:
+    case HINT_OPD_JC:
+      break;
+
+    default:
+      set_syntax_error
+       (_("unknown option to BTI"));
+      return PARSE_FAIL;
+    }
+
+  *str = q;
+  *hint_opt = o;
+  return 0;
+}
+

 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
    Returns the encoding for the option, or PARSE_FAIL.
 
 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
    Returns the encoding for the option, or PARSE_FAIL.
 


@@ -3876,7 +4096,8 @@ parse_barrier_psb (char **str,
 
 static int
 parse_sys_reg (char **str, struct hash_control *sys_regs,
 
 static int
 parse_sys_reg (char **str, struct hash_control *sys_regs,

-              int imple_defined_p, int pstatefield_p)
+              int imple_defined_p, int pstatefield_p,
+              uint32_t* flags)

 {
   char *p, *q;
   char buf[32];
 {
   char *p, *q;
   char buf[32];


@@ -3907,6 +4128,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs,
          if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
            return PARSE_FAIL;
          value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
          if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
            return PARSE_FAIL;
          value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;

+         if (flags)
+           *flags = 0;

        }
     }
   else
        }
     }
   else


@@ -3921,6 +4144,8 @@ parse_sys_reg (char **str, struct hash_control *sys_regs,
        as_warn (_("system register name '%s' is deprecated and may be "
                   "removed in a future release"), buf);
       value = o->value;
        as_warn (_("system register name '%s' is deprecated and may be "
                   "removed in a future release"), buf);
       value = o->value;

+      if (flags)
+       *flags = o->flags;

     }
 
   *str = q;
     }
 
   *str = q;


@@ -4337,6 +4562,7 @@ record_operand_error (const aarch64_opcode *opcode, int idx,
   info.index = idx;
   info.kind = kind;
   info.error = error;
   info.index = idx;
   info.kind = kind;
   info.error = error;

+  info.non_fatal = FALSE;

   record_operand_error_info (opcode, &info);
 }
 
   record_operand_error_info (opcode, &info);
 }
 


@@ -4352,6 +4578,7 @@ record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
   info.data[0] = extra_data[0];
   info.data[1] = extra_data[1];
   info.data[2] = extra_data[2];
   info.data[0] = extra_data[0];
   info.data[1] = extra_data[1];
   info.data[2] = extra_data[2];

+  info.non_fatal = FALSE;

   record_operand_error_info (opcode, &info);
 }
 
   record_operand_error_info (opcode, &info);
 }
 


@@ -4413,7 +4640,7 @@ find_best_match (const aarch64_inst *instr,
       const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
 
       /* Most opcodes has much fewer patterns in the list.  */
       const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
 
       /* Most opcodes has much fewer patterns in the list.  */

-      if (empty_qualifier_sequence_p (qualifiers) == TRUE)
+      if (empty_qualifier_sequence_p (qualifiers))

        {
          DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
          break;
        {
          DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
          break;


@@ -4470,7 +4697,8 @@ print_operands (char *buf, const aarch64_opcode *opcode,
        break;
 
       /* Generate the operand string in STR.  */
        break;
 
       /* Generate the operand string in STR.  */

-      aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL);
+      aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL,
+                            NULL);

 
       /* Delimiter.  */
       if (str[0] != '\0')
 
       /* Delimiter.  */
       if (str[0] != '\0')


@@ -4516,12 +4744,14 @@ output_operand_error_record (const operand_error_record *record, char *str)
   enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
                                : AARCH64_OPND_NIL);
 
   enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
                                : AARCH64_OPND_NIL);
 

+  typedef void (*handler_t)(const char *format, ...);
+  handler_t handler = detail->non_fatal ? as_warn : as_bad;
+

   switch (detail->kind)
     {
     case AARCH64_OPDE_NIL:
       gas_assert (0);
       break;
   switch (detail->kind)
     {
     case AARCH64_OPDE_NIL:
       gas_assert (0);
       break;

-

     case AARCH64_OPDE_SYNTAX_ERROR:
     case AARCH64_OPDE_RECOVERABLE:
     case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
     case AARCH64_OPDE_SYNTAX_ERROR:
     case AARCH64_OPDE_RECOVERABLE:
     case AARCH64_OPDE_FATAL_SYNTAX_ERROR:


@@ -4531,21 +4761,21 @@ output_operand_error_record (const operand_error_record *record, char *str)
       if (detail->error != NULL)
        {
          if (idx < 0)
       if (detail->error != NULL)
        {
          if (idx < 0)

-           as_bad (_("%s -- `%s'"), detail->error, str);
+           handler (_("%s -- `%s'"), detail->error, str);

          else
          else

-           as_bad (_("%s at operand %d -- `%s'"),
-                   detail->error, idx + 1, str);
+           handler (_("%s at operand %d -- `%s'"),
+                    detail->error, idx + 1, str);

        }
       else
        {
          gas_assert (idx >= 0);
        }
       else
        {
          gas_assert (idx >= 0);

-         as_bad (_("operand %d must be %s -- `%s'"), idx + 1,
-               aarch64_get_operand_desc (opd_code), str);
+         handler (_("operand %d must be %s -- `%s'"), idx + 1,
+                  aarch64_get_operand_desc (opd_code), str);

        }
       break;
 
     case AARCH64_OPDE_INVALID_VARIANT:
        }
       break;
 
     case AARCH64_OPDE_INVALID_VARIANT:

-      as_bad (_("operand mismatch -- `%s'"), str);
+      handler (_("operand mismatch -- `%s'"), str);

       if (verbose_error_p)
        {
          /* We will try to correct the erroneous instruction and also provide
       if (verbose_error_p)
        {
          /* We will try to correct the erroneous instruction and also provide


@@ -4593,7 +4823,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
            && programmer_friendly_fixup (&inst);
          gas_assert (result);
          result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
            && programmer_friendly_fixup (&inst);
          gas_assert (result);
          result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,

-                                         NULL, NULL);
+                                         NULL, NULL, insn_sequence);

          gas_assert (!result);
 
          /* Find the most matched qualifier sequence.  */
          gas_assert (!result);
 
          /* Find the most matched qualifier sequence.  */


@@ -4621,7 +4851,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
            {
              /* Most opcodes has much fewer patterns in the list.
                 First NIL qualifier indicates the end in the list.   */
            {
              /* Most opcodes has much fewer patterns in the list.
                 First NIL qualifier indicates the end in the list.   */

-             if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
+             if (empty_qualifier_sequence_p (*qualifiers_list))

                break;
 
              if (i != qlf_idx)
                break;
 
              if (i != qlf_idx)


@@ -4642,36 +4872,36 @@ output_operand_error_record (const operand_error_record *record, char *str)
       break;
 
     case AARCH64_OPDE_UNTIED_OPERAND:
       break;
 
     case AARCH64_OPDE_UNTIED_OPERAND:

-      as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
-             detail->index + 1, str);
+      handler (_("operand %d must be the same register as operand 1 -- `%s'"),
+              detail->index + 1, str);

       break;
 
     case AARCH64_OPDE_OUT_OF_RANGE:
       if (detail->data[0] != detail->data[1])
       break;
 
     case AARCH64_OPDE_OUT_OF_RANGE:
       if (detail->data[0] != detail->data[1])

-       as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
-               detail->error ? detail->error : _("immediate value"),
-               detail->data[0], detail->data[1], idx + 1, str);
+       handler (_("%s out of range %d to %d at operand %d -- `%s'"),
+                detail->error ? detail->error : _("immediate value"),
+                detail->data[0], detail->data[1], idx + 1, str);

       else
       else

-       as_bad (_("%s must be %d at operand %d -- `%s'"),
-               detail->error ? detail->error : _("immediate value"),
-               detail->data[0], idx + 1, str);
+       handler (_("%s must be %d at operand %d -- `%s'"),
+                detail->error ? detail->error : _("immediate value"),
+                detail->data[0], idx + 1, str);

       break;
 
     case AARCH64_OPDE_REG_LIST:
       if (detail->data[0] == 1)
       break;
 
     case AARCH64_OPDE_REG_LIST:
       if (detail->data[0] == 1)

-       as_bad (_("invalid number of registers in the list; "
-                 "only 1 register is expected at operand %d -- `%s'"),
-               idx + 1, str);
+       handler (_("invalid number of registers in the list; "
+                  "only 1 register is expected at operand %d -- `%s'"),
+                idx + 1, str);

       else
       else

-       as_bad (_("invalid number of registers in the list; "
-                 "%d registers are expected at operand %d -- `%s'"),
-             detail->data[0], idx + 1, str);
+       handler (_("invalid number of registers in the list; "
+                  "%d registers are expected at operand %d -- `%s'"),
+              detail->data[0], idx + 1, str);

       break;
 
     case AARCH64_OPDE_UNALIGNED:
       break;
 
     case AARCH64_OPDE_UNALIGNED:

-      as_bad (_("immediate value must be a multiple of "
-               "%d at operand %d -- `%s'"),
-             detail->data[0], idx + 1, str);
+      handler (_("immediate value must be a multiple of "
+                "%d at operand %d -- `%s'"),
+              detail->data[0], idx + 1, str);

       break;
 
     default:
       break;
 
     default:


@@ -4685,10 +4915,15 @@ output_operand_error_record (const operand_error_record *record, char *str)
    When this function is called, the operand error information had
    been collected for an assembly line and there will be multiple
    errors in the case of multiple instruction templates; output the
    When this function is called, the operand error information had
    been collected for an assembly line and there will be multiple
    errors in the case of multiple instruction templates; output the

-   error message that most closely describes the problem.  */
+   error message that most closely describes the problem.
+
+   The errors to be printed can be filtered on printing all errors
+   or only non-fatal errors.  This distinction has to be made because
+   the error buffer may already be filled with fatal errors we don't want to
+   print due to the different instruction templates.  */

 
 static void
 
 static void

-output_operand_error_report (char *str)
+output_operand_error_report (char *str, bfd_boolean non_fatal_only)

 {
   int largest_error_pos;
   const char *msg = NULL;
 {
   int largest_error_pos;
   const char *msg = NULL;


@@ -4706,9 +4941,14 @@ output_operand_error_report (char *str)
   /* Only one error.  */
   if (head == operand_error_report.tail)
     {
   /* Only one error.  */
   if (head == operand_error_report.tail)
     {

-      DEBUG_TRACE ("single opcode entry with error kind: %s",
-                  operand_mismatch_kind_names[head->detail.kind]);
-      output_operand_error_record (head, str);
+      /* If the only error is a non-fatal one and we don't want to print it,
+        just exit.  */
+      if (!non_fatal_only || head->detail.non_fatal)
+       {
+         DEBUG_TRACE ("single opcode entry with error kind: %s",
+                      operand_mismatch_kind_names[head->detail.kind]);
+         output_operand_error_record (head, str);
+       }

       return;
     }
 
       return;
     }
 


@@ -4719,16 +4959,21 @@ output_operand_error_report (char *str)
     {
       gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
       DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
     {
       gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
       DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);

-      if (operand_error_higher_severity_p (curr->detail.kind, kind))
+      if (operand_error_higher_severity_p (curr->detail.kind, kind)
+         && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))

        kind = curr->detail.kind;
     }
        kind = curr->detail.kind;
     }

-  gas_assert (kind != AARCH64_OPDE_NIL);
+
+  gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);

 
   /* Pick up one of errors of KIND to report.  */
   largest_error_pos = -2; /* Index can be -1 which means unknown index.  */
   for (curr = head; curr != NULL; curr = curr->next)
     {
 
   /* Pick up one of errors of KIND to report.  */
   largest_error_pos = -2; /* Index can be -1 which means unknown index.  */
   for (curr = head; curr != NULL; curr = curr->next)
     {

-      if (curr->detail.kind != kind)
+      /* If we don't want to print non-fatal errors then don't consider them
+        at all.  */
+      if (curr->detail.kind != kind
+         || (non_fatal_only && !curr->detail.non_fatal))

        continue;
       /* If there are multiple errors, pick up the one with the highest
         mismatching operand index.  In the case of multiple errors with
        continue;
       /* If there are multiple errors, pick up the one with the highest
         mismatching operand index.  In the case of multiple errors with


@@ -4744,6 +4989,17 @@ output_operand_error_report (char *str)
        }
     }
 
        }
     }
 

+  /* The way errors are collected in the back-end is a bit non-intuitive.  But
+     essentially, because each operand template is tried recursively you may
+     always have errors collected from the previous tried OPND.  These are
+     usually skipped if there is one successful match.  However now with the
+     non-fatal errors we have to ignore those previously collected hard errors
+     when we're only interested in printing the non-fatal ones.  This condition
+     prevents us from printing errors that are not appropriate, since we did
+     match a condition, but it also has warnings that it wants to print.  */
+  if (non_fatal_only && !record)
+    return;
+

   gas_assert (largest_error_pos != -2 && record != NULL);
   DEBUG_TRACE ("Pick up error kind %s to report",
               operand_mismatch_kind_names[record->detail.kind]);
   gas_assert (largest_error_pos != -2 && record != NULL);
   DEBUG_TRACE ("Pick up error kind %s to report",
               operand_mismatch_kind_names[record->detail.kind]);


@@ -4768,7 +5024,8 @@ get_aarch64_insn (char *buf)
 {
   unsigned char *where = (unsigned char *) buf;
   uint32_t result;
 {
   unsigned char *where = (unsigned char *) buf;
   uint32_t result;

-  result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
+  result = ((where[0] | (where[1] << 8) | (where[2] << 16)
+            | ((uint32_t) where[3] << 24)));

   return result;
 }
 
   return result;
 }
 


@@ -4900,7 +5157,7 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
     = {1, 2, 4, 8, 16};
   const unsigned int ele_base [5] =
     {
     = {1, 2, 4, 8, 16};
   const unsigned int ele_base [5] =
     {

-      AARCH64_OPND_QLF_V_8B,
+      AARCH64_OPND_QLF_V_4B,

       AARCH64_OPND_QLF_V_2H,
       AARCH64_OPND_QLF_V_2S,
       AARCH64_OPND_QLF_V_1D,
       AARCH64_OPND_QLF_V_2H,
       AARCH64_OPND_QLF_V_2S,
       AARCH64_OPND_QLF_V_1D,


@@ -4918,8 +5175,18 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
   gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
 
   if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
   gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
 
   if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))

-    /* Vector element register.  */
-    return AARCH64_OPND_QLF_S_B + vectype->type;
+    {
+      /* Special case S_4B.  */
+      if (vectype->type == NT_b && vectype->width == 4)
+       return AARCH64_OPND_QLF_S_4B;
+
+      /* Special case S_2H.  */
+      if (vectype->type == NT_h && vectype->width == 2)
+       return AARCH64_OPND_QLF_S_2H;
+
+      /* Vector element register.  */
+      return AARCH64_OPND_QLF_S_B + vectype->type;
+    }

   else
     {
       /* Vector register.  */
   else
     {
       /* Vector register.  */


@@ -4935,7 +5202,7 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
         a vector-type dependent amount.  */
       shift = 0;
       if (vectype->type == NT_b)
         a vector-type dependent amount.  */
       shift = 0;
       if (vectype->type == NT_b)

-       shift = 4;
+       shift = 3;

       else if (vectype->type == NT_h || vectype->type == NT_s)
        shift = 2;
       else if (vectype->type >= NT_d)
       else if (vectype->type == NT_h || vectype->type == NT_s)
        shift = 2;
       else if (vectype->type >= NT_d)


@@ -4944,7 +5211,7 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
        gas_assert (0);
 
       offset = ele_base [vectype->type] + (vectype->width >> shift);
        gas_assert (0);
 
       offset = ele_base [vectype->type] + (vectype->width >> shift);

-      gas_assert (AARCH64_OPND_QLF_V_8B <= offset
+      gas_assert (AARCH64_OPND_QLF_V_4B <= offset

                  && offset <= AARCH64_OPND_QLF_V_1Q);
       return offset;
     }
                  && offset <= AARCH64_OPND_QLF_V_1Q);
       return offset;
     }


@@ -4974,6 +5241,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Rm:
     case AARCH64_OPND_Rt:
     case AARCH64_OPND_Rt2:
     case AARCH64_OPND_Rm:
     case AARCH64_OPND_Rt:
     case AARCH64_OPND_Rt2:

+    case AARCH64_OPND_Rt_SP:

     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
     case AARCH64_OPND_Rt_SYS:
     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
     case AARCH64_OPND_Rt_SYS:


@@ -4989,6 +5257,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Sd:
     case AARCH64_OPND_Sn:
     case AARCH64_OPND_Sm:
     case AARCH64_OPND_Sd:
     case AARCH64_OPND_Sn:
     case AARCH64_OPND_Sm:

+    case AARCH64_OPND_Va:

     case AARCH64_OPND_Vd:
     case AARCH64_OPND_Vn:
     case AARCH64_OPND_Vm:
     case AARCH64_OPND_Vd:
     case AARCH64_OPND_Vn:
     case AARCH64_OPND_Vm:


@@ -5000,6 +5269,8 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Ed:
     case AARCH64_OPND_En:
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Ed:
     case AARCH64_OPND_En:
     case AARCH64_OPND_Em:

+    case AARCH64_OPND_Em16:
+    case AARCH64_OPND_SM3_IMM2:

       operand->reglane.regno = default_value;
       break;
 
       operand->reglane.regno = default_value;
       break;
 


@@ -5016,6 +5287,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_UIMM3_OP1:
     case AARCH64_OPND_UIMM3_OP2:
     case AARCH64_OPND_IMM:
     case AARCH64_OPND_UIMM3_OP1:
     case AARCH64_OPND_UIMM3_OP2:
     case AARCH64_OPND_IMM:

+    case AARCH64_OPND_IMM_2:

     case AARCH64_OPND_WIDTH:
     case AARCH64_OPND_UIMM7:
     case AARCH64_OPND_NZCV:
     case AARCH64_OPND_WIDTH:
     case AARCH64_OPND_UIMM7:
     case AARCH64_OPND_NZCV:


@@ -5036,6 +5308,11 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
 
     case AARCH64_OPND_BARRIER_ISB:
       operand->barrier = aarch64_barrier_options + default_value;
 
     case AARCH64_OPND_BARRIER_ISB:
       operand->barrier = aarch64_barrier_options + default_value;

+      break;
+
+    case AARCH64_OPND_BTI_TARGET:
+      operand->hint_option = aarch64_hint_options + default_value;
+      break;

 
     default:
       break;
 
     default:
       break;


@@ -5059,6 +5336,10 @@ process_movw_reloc_info (void)
       case BFD_RELOC_AARCH64_MOVW_G0_S:
       case BFD_RELOC_AARCH64_MOVW_G1_S:
       case BFD_RELOC_AARCH64_MOVW_G2_S:
       case BFD_RELOC_AARCH64_MOVW_G0_S:
       case BFD_RELOC_AARCH64_MOVW_G1_S:
       case BFD_RELOC_AARCH64_MOVW_G2_S:

+      case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+      case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+      case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+      case BFD_RELOC_AARCH64_MOVW_PREL_G3:

       case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
       case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
       case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:


@@ -5076,6 +5357,8 @@ process_movw_reloc_info (void)
     case BFD_RELOC_AARCH64_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:

     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
     case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
     case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:


@@ -5089,6 +5372,8 @@ process_movw_reloc_info (void)
     case BFD_RELOC_AARCH64_MOVW_G1_NC:
     case BFD_RELOC_AARCH64_MOVW_G1_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
     case BFD_RELOC_AARCH64_MOVW_G1_NC:
     case BFD_RELOC_AARCH64_MOVW_G1_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:

     case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
     case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
     case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
     case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
     case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:


@@ -5101,6 +5386,8 @@ process_movw_reloc_info (void)
     case BFD_RELOC_AARCH64_MOVW_G2:
     case BFD_RELOC_AARCH64_MOVW_G2_NC:
     case BFD_RELOC_AARCH64_MOVW_G2_S:
     case BFD_RELOC_AARCH64_MOVW_G2:
     case BFD_RELOC_AARCH64_MOVW_G2_NC:
     case BFD_RELOC_AARCH64_MOVW_G2_S:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:

     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
       if (is32)
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
       if (is32)


@@ -5113,6 +5400,7 @@ process_movw_reloc_info (void)
       shift = 32;
       break;
     case BFD_RELOC_AARCH64_MOVW_G3:
       shift = 32;
       break;
     case BFD_RELOC_AARCH64_MOVW_G3:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G3:

       if (is32)
        {
          set_fatal_syntax_error
       if (is32)
        {
          set_fatal_syntax_error


@@ -5159,7 +5447,7 @@ ldst_lo12_determine_real_reloc_type (void)
   enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
   enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
 
   enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
   enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
 

-  const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
+  const bfd_reloc_code_real_type reloc_ldst_lo12[5][5] = {

     {
       BFD_RELOC_AARCH64_LDST8_LO12,
       BFD_RELOC_AARCH64_LDST16_LO12,
     {
       BFD_RELOC_AARCH64_LDST8_LO12,
       BFD_RELOC_AARCH64_LDST16_LO12,


@@ -5180,13 +5468,31 @@ ldst_lo12_determine_real_reloc_type (void)
       BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
       BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
       BFD_RELOC_AARCH64_NONE
       BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
       BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
       BFD_RELOC_AARCH64_NONE

+    },
+    {
+      BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12,
+      BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12,
+      BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12,
+      BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12,
+      BFD_RELOC_AARCH64_NONE
+    },
+    {
+      BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC,
+      BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,
+      BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,
+      BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,
+      BFD_RELOC_AARCH64_NONE

     }
   };
 
   gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
              || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
              || (inst.reloc.type
     }
   };
 
   gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
              || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
              || (inst.reloc.type

-                 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
+                 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
+             || (inst.reloc.type
+                 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
+             || (inst.reloc.type
+                 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC));

   gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
 
   if (opd1_qlf == AARCH64_OPND_QLF_NIL)
   gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
 
   if (opd1_qlf == AARCH64_OPND_QLF_NIL)


@@ -5197,7 +5503,9 @@ ldst_lo12_determine_real_reloc_type (void)
 
   logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
   if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
 
   logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
   if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12

-      || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
+      || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
+      || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
+      || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)

     gas_assert (logsz <= 3);
   else
     gas_assert (logsz <= 4);
     gas_assert (logsz <= 3);
   else
     gas_assert (logsz <= 4);


@@ -5256,7 +5564,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
   skip_whitespace (str);
 
   if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))
   skip_whitespace (str);
 
   if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE, *opcode->avariant))

-    imm_reg_type = REG_TYPE_R_Z_BHSDQ_VZP;
+    imm_reg_type = REG_TYPE_R_Z_SP_BHSDQ_VZP;

   else
     imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
 
   else
     imm_reg_type = REG_TYPE_R_Z_BHSDQ_V;
 


@@ -5310,6 +5618,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
        case AARCH64_OPND_Rd_SP:
        case AARCH64_OPND_Rn_SP:
 
        case AARCH64_OPND_Rd_SP:
        case AARCH64_OPND_Rn_SP:

+       case AARCH64_OPND_Rt_SP:

        case AARCH64_OPND_SVE_Rn_SP:
        case AARCH64_OPND_Rm_SP:
          po_int_reg_or_fail (REG_TYPE_R_SP);
        case AARCH64_OPND_SVE_Rn_SP:
        case AARCH64_OPND_Rm_SP:
          po_int_reg_or_fail (REG_TYPE_R_SP);


@@ -5380,6 +5689,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          reg_type = REG_TYPE_ZN;
          goto vector_reg;
 
          reg_type = REG_TYPE_ZN;
          goto vector_reg;
 

+       case AARCH64_OPND_Va:

        case AARCH64_OPND_Vd:
        case AARCH64_OPND_Vn:
        case AARCH64_OPND_Vm:
        case AARCH64_OPND_Vd:
        case AARCH64_OPND_Vn:
        case AARCH64_OPND_Vm:


@@ -5433,6 +5743,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
        case AARCH64_OPND_SVE_Zm3_INDEX:
        case AARCH64_OPND_SVE_Zm3_22_INDEX:
 
        case AARCH64_OPND_SVE_Zm3_INDEX:
        case AARCH64_OPND_SVE_Zm3_22_INDEX:

+       case AARCH64_OPND_SVE_Zm3_11_INDEX:
+       case AARCH64_OPND_SVE_Zm4_11_INDEX:

        case AARCH64_OPND_SVE_Zm4_INDEX:
        case AARCH64_OPND_SVE_Zn_INDEX:
          reg_type = REG_TYPE_ZN;
        case AARCH64_OPND_SVE_Zm4_INDEX:
        case AARCH64_OPND_SVE_Zn_INDEX:
          reg_type = REG_TYPE_ZN;


@@ -5441,6 +5753,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
        case AARCH64_OPND_Ed:
        case AARCH64_OPND_En:
        case AARCH64_OPND_Em:
        case AARCH64_OPND_Ed:
        case AARCH64_OPND_En:
        case AARCH64_OPND_Em:

+       case AARCH64_OPND_Em16:
+       case AARCH64_OPND_SM3_IMM2:

          reg_type = REG_TYPE_VN;
        vector_reg_index:
          val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);
          reg_type = REG_TYPE_VN;
        vector_reg_index:
          val = aarch64_reg_parse (&str, reg_type, NULL, &vectype);


@@ -5488,11 +5802,20 @@ parse_operands (char *str, const aarch64_opcode *opcode)
              val = parse_vector_reg_list (&str, reg_type, &vectype);
              if (val == PARSE_FAIL)
                goto failure;
              val = parse_vector_reg_list (&str, reg_type, &vectype);
              if (val == PARSE_FAIL)
                goto failure;

+

              if (! reg_list_valid_p (val, /* accept_alternate */ 0))
                {
                  set_fatal_syntax_error (_("invalid register list"));
                  goto failure;
                }
              if (! reg_list_valid_p (val, /* accept_alternate */ 0))
                {
                  set_fatal_syntax_error (_("invalid register list"));
                  goto failure;
                }

+
+             if (vectype.width != 0 && *str != ',')
+               {
+                 set_fatal_syntax_error
+                   (_("expected element type rather than vector type"));
+                 goto failure;
+               }
+

              info->reglist.first_regno = (val >> 2) & 0x1f;
              info->reglist.num_regs = (val & 0x3) + 1;
            }
              info->reglist.first_regno = (val >> 2) & 0x1f;
              info->reglist.num_regs = (val & 0x3) + 1;
            }


@@ -5546,19 +5869,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
        case AARCH64_OPND_CCMP_IMM:
        case AARCH64_OPND_SIMM5:
        case AARCH64_OPND_FBITS:
        case AARCH64_OPND_CCMP_IMM:
        case AARCH64_OPND_SIMM5:
        case AARCH64_OPND_FBITS:

+       case AARCH64_OPND_TME_UIMM16:

        case AARCH64_OPND_UIMM4:
        case AARCH64_OPND_UIMM4:

+       case AARCH64_OPND_UIMM4_ADDG:
+       case AARCH64_OPND_UIMM10:

        case AARCH64_OPND_UIMM3_OP1:
        case AARCH64_OPND_UIMM3_OP2:
        case AARCH64_OPND_IMM_VLSL:
        case AARCH64_OPND_IMM:
        case AARCH64_OPND_UIMM3_OP1:
        case AARCH64_OPND_UIMM3_OP2:
        case AARCH64_OPND_IMM_VLSL:
        case AARCH64_OPND_IMM:

+       case AARCH64_OPND_IMM_2:

        case AARCH64_OPND_WIDTH:
        case AARCH64_OPND_SVE_INV_LIMM:
        case AARCH64_OPND_SVE_LIMM:
        case AARCH64_OPND_SVE_LIMM_MOV:
        case AARCH64_OPND_SVE_SHLIMM_PRED:
        case AARCH64_OPND_SVE_SHLIMM_UNPRED:
        case AARCH64_OPND_WIDTH:
        case AARCH64_OPND_SVE_INV_LIMM:
        case AARCH64_OPND_SVE_LIMM:
        case AARCH64_OPND_SVE_LIMM_MOV:
        case AARCH64_OPND_SVE_SHLIMM_PRED:
        case AARCH64_OPND_SVE_SHLIMM_UNPRED:

+       case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:

        case AARCH64_OPND_SVE_SHRIMM_PRED:
        case AARCH64_OPND_SVE_SHRIMM_UNPRED:
        case AARCH64_OPND_SVE_SHRIMM_PRED:
        case AARCH64_OPND_SVE_SHRIMM_UNPRED:

+       case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:

        case AARCH64_OPND_SVE_SIMM5:
        case AARCH64_OPND_SVE_SIMM5B:
        case AARCH64_OPND_SVE_SIMM6:
        case AARCH64_OPND_SVE_SIMM5:
        case AARCH64_OPND_SVE_SIMM5B:
        case AARCH64_OPND_SVE_SIMM6:


@@ -5572,6 +5901,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
        case AARCH64_OPND_IMM_ROT3:
        case AARCH64_OPND_SVE_IMM_ROT1:
        case AARCH64_OPND_SVE_IMM_ROT2:
        case AARCH64_OPND_IMM_ROT3:
        case AARCH64_OPND_SVE_IMM_ROT1:
        case AARCH64_OPND_SVE_IMM_ROT2:

+       case AARCH64_OPND_SVE_IMM_ROT3:

          po_imm_nc_or_fail ();
          info->imm.value = val;
          break;
          po_imm_nc_or_fail ();
          info->imm.value = val;
          break;


@@ -5617,6 +5947,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          break;
 
        case AARCH64_OPND_IDX:
          break;
 
        case AARCH64_OPND_IDX:

+       case AARCH64_OPND_MASK:

        case AARCH64_OPND_BIT_NUM:
        case AARCH64_OPND_IMMR:
        case AARCH64_OPND_IMMS:
        case AARCH64_OPND_BIT_NUM:
        case AARCH64_OPND_IMMR:
        case AARCH64_OPND_IMMS:


@@ -6015,6 +6346,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 
        case AARCH64_OPND_ADDR_SIMM9:
        case AARCH64_OPND_ADDR_SIMM9_2:
 
        case AARCH64_OPND_ADDR_SIMM9:
        case AARCH64_OPND_ADDR_SIMM9_2:

+       case AARCH64_OPND_ADDR_SIMM11:
+       case AARCH64_OPND_ADDR_SIMM13:

          po_misc_or_fail (parse_address (&str, info));
          if (info->addr.pcrel || info->addr.offset.is_reg
              || (!info->addr.preind && !info->addr.postind)
          po_misc_or_fail (parse_address (&str, info));
          if (info->addr.pcrel || info->addr.offset.is_reg
              || (!info->addr.preind && !info->addr.postind)


@@ -6036,6 +6369,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          break;
 
        case AARCH64_OPND_ADDR_SIMM10:
          break;
 
        case AARCH64_OPND_ADDR_SIMM10:

+       case AARCH64_OPND_ADDR_OFFSET:

          po_misc_or_fail (parse_address (&str, info));
          if (info->addr.pcrel || info->addr.offset.is_reg
              || !info->addr.preind || info->addr.postind)
          po_misc_or_fail (parse_address (&str, info));
          if (info->addr.pcrel || info->addr.offset.is_reg
              || !info->addr.preind || info->addr.postind)


@@ -6068,7 +6402,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
                   || (inst.reloc.type
                       == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
                   || (inst.reloc.type
                   || (inst.reloc.type
                       == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
                   || (inst.reloc.type

-                      == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
+                      == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
+                  || (inst.reloc.type
+                      == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
+                  || (inst.reloc.type
+                      == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC))

            inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
          /* Leave qualifier to be determined by libopcodes.  */
          break;
            inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
          /* Leave qualifier to be determined by libopcodes.  */
          break;


@@ -6096,6 +6434,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          break;
 
        case AARCH64_OPND_SVE_ADDR_RI_S4x16:
          break;
 
        case AARCH64_OPND_SVE_ADDR_RI_S4x16:

+       case AARCH64_OPND_SVE_ADDR_RI_S4x32:

        case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
        case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
        case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
        case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
        case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
        case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:


@@ -6134,6 +6473,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          info->addr.offset.imm = inst.reloc.exp.X_add_number;
          break;
 
          info->addr.offset.imm = inst.reloc.exp.X_add_number;
          break;
 

+       case AARCH64_OPND_SVE_ADDR_R:
+         /* [<Xn|SP>{, <R><m>}]
+            but recognizing SVE registers.  */
+         po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
+                                             &offset_qualifier));
+         if (offset_qualifier == AARCH64_OPND_QLF_NIL)
+           {
+             offset_qualifier = AARCH64_OPND_QLF_X;
+             info->addr.offset.is_reg = 1;
+             info->addr.offset.regno = 31;
+           }
+         else if (base_qualifier != AARCH64_OPND_QLF_X
+             || offset_qualifier != AARCH64_OPND_QLF_X)
+           {
+             set_syntax_error (_("invalid addressing mode"));
+             goto failure;
+           }
+         goto regoff_addr;
+         

        case AARCH64_OPND_SVE_ADDR_RR:
        case AARCH64_OPND_SVE_ADDR_RR_LSL1:
        case AARCH64_OPND_SVE_ADDR_RR_LSL2:
        case AARCH64_OPND_SVE_ADDR_RR:
        case AARCH64_OPND_SVE_ADDR_RR_LSL1:
        case AARCH64_OPND_SVE_ADDR_RR_LSL2:


@@ -6180,6 +6538,33 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          info->qualifier = offset_qualifier;
          goto regoff_addr;
 
          info->qualifier = offset_qualifier;
          goto regoff_addr;
 

+       case AARCH64_OPND_SVE_ADDR_ZX:
+         /* [Zn.<T>{, <Xm>}].  */
+         po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
+                                             &offset_qualifier));
+         /* Things to check:
+             base_qualifier either S_S or S_D
+             offset_qualifier must be X
+             */
+         if ((base_qualifier != AARCH64_OPND_QLF_S_S
+              && base_qualifier != AARCH64_OPND_QLF_S_D)
+             || offset_qualifier != AARCH64_OPND_QLF_X)
+           {
+             set_syntax_error (_("invalid addressing mode"));
+             goto failure;
+           }
+         info->qualifier = base_qualifier;
+         if (!info->addr.offset.is_reg || info->addr.pcrel
+             || !info->addr.preind || info->addr.writeback
+             || info->shifter.operator_present != 0)
+           {
+             set_syntax_error (_("invalid addressing mode"));
+             goto failure;
+           }
+         info->shifter.kind = AARCH64_MOD_LSL;
+         break;
+
+

        case AARCH64_OPND_SVE_ADDR_ZI_U5:
        case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
        case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
        case AARCH64_OPND_SVE_ADDR_ZI_U5:
        case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
        case AARCH64_OPND_SVE_ADDR_ZI_U5x4:


@@ -6221,17 +6606,21 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          goto regoff_addr;
 
        case AARCH64_OPND_SYSREG:
          goto regoff_addr;
 
        case AARCH64_OPND_SYSREG:

-         if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
-             == PARSE_FAIL)
-           {
-             set_syntax_error (_("unknown or missing system register name"));
-             goto failure;
-           }
-         inst.base.operands[i].sysreg = val;
-         break;
+         {
+           uint32_t sysreg_flags;
+           if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
+                                     &sysreg_flags)) == PARSE_FAIL)
+             {
+               set_syntax_error (_("unknown or missing system register name"));
+               goto failure;
+             }
+           inst.base.operands[i].sysreg.value = val;
+           inst.base.operands[i].sysreg.flags = sysreg_flags;
+           break;
+         }

 
        case AARCH64_OPND_PSTATEFIELD:
 
        case AARCH64_OPND_PSTATEFIELD:

-         if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
+         if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL))

              == PARSE_FAIL)
            {
              set_syntax_error (_("unknown or missing PSTATE field name"));
              == PARSE_FAIL)
            {
              set_syntax_error (_("unknown or missing PSTATE field name"));


@@ -6244,14 +6633,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
          goto sys_reg_ins;
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
          goto sys_reg_ins;

+

        case AARCH64_OPND_SYSREG_DC:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
          goto sys_reg_ins;
        case AARCH64_OPND_SYSREG_DC:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
          goto sys_reg_ins;

+

        case AARCH64_OPND_SYSREG_AT:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
          goto sys_reg_ins;
        case AARCH64_OPND_SYSREG_AT:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
          goto sys_reg_ins;

+
+       case AARCH64_OPND_SYSREG_SR:
+         inst.base.operands[i].sysins_op =
+           parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
+         goto sys_reg_ins;
+

        case AARCH64_OPND_SYSREG_TLBI:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
        case AARCH64_OPND_SYSREG_TLBI:
          inst.base.operands[i].sysins_op =
            parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);


@@ -6296,6 +6693,12 @@ sys_reg_ins:
            goto failure;
          break;
 
            goto failure;
          break;
 

+       case AARCH64_OPND_BTI_TARGET:
+         val = parse_bti_operand (&str, &(info->hint_option));
+         if (val == PARSE_FAIL)
+           goto failure;
+         break;
+

        default:
          as_fatal (_("unhandled operand code %d"), operands[i]);
        }
        default:
          as_fatal (_("unhandled operand code %d"), operands[i]);
        }


@@ -6520,9 +6923,12 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
           == AARCH64_OPND_CLASS_INT_REG)
          && opnds[0].reg.regno == opnds[1].addr.base_regno
          && opnds[1].addr.base_regno != REG_SP
           == AARCH64_OPND_CLASS_INT_REG)
          && opnds[0].reg.regno == opnds[1].addr.base_regno
          && opnds[1].addr.base_regno != REG_SP

+         /* Exempt STG/STZG/ST2G/STZ2G.  */
+         && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13)

          && opnds[1].addr.writeback)
        as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       break;
          && opnds[1].addr.writeback)
        as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       break;

+

     case ldstpair_off:
     case ldstnapair_offs:
     case ldstpair_indexed:
     case ldstpair_off:
     case ldstnapair_offs:
     case ldstpair_indexed:


@@ -6532,6 +6938,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
          && (opnds[0].reg.regno == opnds[2].addr.base_regno
            || opnds[1].reg.regno == opnds[2].addr.base_regno)
          && opnds[2].addr.base_regno != REG_SP
          && (opnds[0].reg.regno == opnds[2].addr.base_regno
            || opnds[1].reg.regno == opnds[2].addr.base_regno)
          && opnds[2].addr.base_regno != REG_SP

+         /* Exempt STGP.  */
+         && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)

          && opnds[2].addr.writeback)
            as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       /* Load operations must load different registers.  */
          && opnds[2].addr.writeback)
            as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       /* Load operations must load different registers.  */


@@ -6539,11 +6947,38 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
          && opnds[0].reg.regno == opnds[1].reg.regno)
            as_warn (_("unpredictable load of register pair -- `%s'"), str);
       break;
          && opnds[0].reg.regno == opnds[1].reg.regno)
            as_warn (_("unpredictable load of register pair -- `%s'"), str);
       break;

+
+    case ldstexcl:
+      /* It is unpredictable if the destination and status registers are the
+        same.  */
+      if ((aarch64_get_operand_class (opnds[0].type)
+          == AARCH64_OPND_CLASS_INT_REG)
+         && (aarch64_get_operand_class (opnds[1].type)
+             == AARCH64_OPND_CLASS_INT_REG)
+         && (opnds[0].reg.regno == opnds[1].reg.regno
+             || opnds[0].reg.regno == opnds[2].reg.regno))
+       as_warn (_("unpredictable: identical transfer and status registers"
+                  " --`%s'"),
+                str);
+
+      break;
+

     default:
       break;
     }
 }
 
     default:
       break;
     }
 }
 

+static void
+force_automatic_sequence_close (void)
+{
+  if (now_instr_sequence.instr)
+    {
+      as_warn (_("previous `%s' sequence has not been closed"),
+              now_instr_sequence.instr->opcode->name);
+      init_insn_sequence (NULL, &now_instr_sequence);
+    }
+}
+

 /* A wrapper function to interface with libopcodes on encoding and
    record the error message if there is any.
 
 /* A wrapper function to interface with libopcodes on encoding and
    record the error message if there is any.
 


@@ -6554,15 +6989,15 @@ do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
           aarch64_insn *code)
 {
   aarch64_operand_error error_info;
           aarch64_insn *code)
 {
   aarch64_operand_error error_info;

+  memset (&error_info, '\0', sizeof (error_info));

   error_info.kind = AARCH64_OPDE_NIL;
   error_info.kind = AARCH64_OPDE_NIL;

-  if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
+  if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info, insn_sequence)
+      && !error_info.non_fatal)

     return TRUE;
     return TRUE;

-  else
-    {
-      gas_assert (error_info.kind != AARCH64_OPDE_NIL);
-      record_operand_error_info (opcode, &error_info);
-      return FALSE;
-    }
+
+  gas_assert (error_info.kind != AARCH64_OPDE_NIL);
+  record_operand_error_info (opcode, &error_info);
+  return error_info.non_fatal;

 }
 
 #ifdef DEBUG_AARCH64
 }
 
 #ifdef DEBUG_AARCH64


@@ -6602,6 +7037,9 @@ md_assemble (char *str)
       S_SET_SEGMENT (last_label_seen, now_seg);
     }
 
       S_SET_SEGMENT (last_label_seen, now_seg);
     }
 

+  /* Update the current insn_sequence from the segment.  */
+  insn_sequence = &seg_info (now_seg)->tc_segment_info_data.insn_sequence;
+

   inst.reloc.type = BFD_RELOC_UNUSED;
 
   DEBUG_TRACE ("\n\n");
   inst.reloc.type = BFD_RELOC_UNUSED;
 
   DEBUG_TRACE ("\n\n");


@@ -6699,6 +7137,9 @@ md_assemble (char *str)
              memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
              output_inst (copy);
            }
              memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
              output_inst (copy);
            }

+
+         /* Issue non-fatal messages if any.  */
+         output_operand_error_report (str, TRUE);

          return;
        }
 
          return;
        }
 


@@ -6712,7 +7153,7 @@ md_assemble (char *str)
   while (template != NULL);
 
   /* Issue the error messages if any.  */
   while (template != NULL);
 
   /* Issue the error messages if any.  */

-  output_operand_error_report (str);
+  output_operand_error_report (str, FALSE);

 }
 
 /* Various frobbings of labels and their addresses.  */
 }
 
 /* Various frobbings of labels and their addresses.  */


@@ -6731,6 +7172,13 @@ aarch64_frob_label (symbolS * sym)
   dwarf2_emit_label (sym);
 }
 
   dwarf2_emit_label (sym);
 }
 

+void
+aarch64_frob_section (asection *sec ATTRIBUTE_UNUSED)
+{
+  /* Check to see if we have a block to close.  */
+  force_automatic_sequence_close ();
+}
+

 int
 aarch64_data_in_code (void)
 {
 int
 aarch64_data_in_code (void)
 {


@@ -6762,6 +7210,7 @@ aarch64_canonicalize_symbol_name (char *name)
    also have mixed-case names. */
 
 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
    also have mixed-case names. */
 
 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }

+#define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}

 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
 #define REGSET16(p,t) \
   REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
 #define REGSET16(p,t) \
   REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \


@@ -6783,6 +7232,10 @@ static const reg_entry reg_names[] = {
   REGSET31 (x, R_64), REGSET31 (X, R_64),
   REGSET31 (w, R_32), REGSET31 (W, R_32),
 
   REGSET31 (x, R_64), REGSET31 (X, R_64),
   REGSET31 (w, R_32), REGSET31 (W, R_32),
 

+  REGDEF_ALIAS (ip0, 16, R_64), REGDEF_ALIAS (IP0, 16, R_64),
+  REGDEF_ALIAS (ip1, 17, R_64), REGDEF_ALIAS (IP1, 17, R_64),
+  REGDEF_ALIAS (fp, 29, R_64), REGDEF_ALIAS (FP, 29, R_64),
+  REGDEF_ALIAS (lr, 30, R_64), REGDEF_ALIAS (LR, 30, R_64),

   REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
   REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
 
   REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
   REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
 


@@ -6815,6 +7268,7 @@ static const reg_entry reg_names[] = {
 };
 
 #undef REGDEF
 };
 
 #undef REGDEF

+#undef REGDEF_ALIAS

 #undef REGNUM
 #undef REGSET16
 #undef REGSET31
 #undef REGNUM
 #undef REGSET16
 #undef REGSET31


@@ -6976,6 +7430,11 @@ aarch64_init_frag (fragS * fragP, int max_chars)
   if (!fragP->tc_frag_data.recorded)
     fragP->tc_frag_data.recorded = 1;
 
   if (!fragP->tc_frag_data.recorded)
     fragP->tc_frag_data.recorded = 1;
 

+  /* PR 21809: Do not set a mapping state for debug sections
+     - it just confuses other tools.  */
+  if (bfd_section_flags (now_seg) & SEC_DEBUGGING)
+    return;
+

   switch (fragP->fr_type)
     {
     case rs_align_test:
   switch (fragP->fr_type)
     {
     case rs_align_test:


@@ -7180,7 +7639,8 @@ try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
 
   DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
 
 
   DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
 

-  if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
+  if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL,
+                             insn_sequence))

     return FALSE;
 
   return TRUE;
     return FALSE;
 
   return TRUE;


@@ -7214,7 +7674,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
       opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,
       opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,

-                                &instr->value, NULL, NULL))
+                                &instr->value, NULL, NULL, insn_sequence))

        {
          put_aarch64_insn (buf, instr->value);
          return;
        {
          put_aarch64_insn (buf, instr->value);
          return;


@@ -7223,7 +7683,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
       opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,
       opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,

-                                &instr->value, NULL, NULL))
+                                &instr->value, NULL, NULL, insn_sequence))

        {
          put_aarch64_insn (buf, instr->value);
          return;
        {
          put_aarch64_insn (buf, instr->value);
          return;


@@ -7236,7 +7696,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
       opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,
       opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
       aarch64_replace_opcode (instr, opcode);
       if (aarch64_opcode_encode (instr->opcode, instr,

-                                &instr->value, NULL, NULL))
+                                &instr->value, NULL, NULL, insn_sequence))

        {
          put_aarch64_insn (buf, instr->value);
          return;
        {
          put_aarch64_insn (buf, instr->value);
          return;


@@ -7347,7 +7807,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
       idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
       new_inst->operands[idx].imm.value = value;
       if (aarch64_opcode_encode (new_inst->opcode, new_inst,
       idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
       new_inst->operands[idx].imm.value = value;
       if (aarch64_opcode_encode (new_inst->opcode, new_inst,

-                                &new_inst->value, NULL, NULL))
+                                &new_inst->value, NULL, NULL, insn_sequence))

        put_aarch64_insn (buf, new_inst->value);
       else
        as_bad_where (fixP->fx_file, fixP->fx_line,
        put_aarch64_insn (buf, new_inst->value);
       else
        as_bad_where (fixP->fx_file, fixP->fx_line,


@@ -7381,6 +7841,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
     case AARCH64_OPND_ADDR_SIMM9_2:
     case AARCH64_OPND_ADDR_SIMM10:
     case AARCH64_OPND_ADDR_UIMM12:
     case AARCH64_OPND_ADDR_SIMM9_2:
     case AARCH64_OPND_ADDR_SIMM10:
     case AARCH64_OPND_ADDR_UIMM12:

+    case AARCH64_OPND_ADDR_SIMM11:
+    case AARCH64_OPND_ADDR_SIMM13:

       /* Immediate offset in an address.  */
       insn = get_aarch64_insn (buf);
 
       /* Immediate offset in an address.  */
       insn = get_aarch64_insn (buf);
 


@@ -7401,7 +7863,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
 
       /* Encode/fix-up.  */
       if (aarch64_opcode_encode (new_inst->opcode, new_inst,
 
       /* Encode/fix-up.  */
       if (aarch64_opcode_encode (new_inst->opcode, new_inst,

-                                &new_inst->value, NULL, NULL))
+                                &new_inst->value, NULL, NULL, insn_sequence))

        {
          put_aarch64_insn (buf, new_inst->value);
          break;
        {
          put_aarch64_insn (buf, new_inst->value);
          break;


@@ -7572,12 +8034,16 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_NC:
     case BFD_RELOC_AARCH64_MOVW_G0_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:

       scale = 0;
       goto movw_common;
     case BFD_RELOC_AARCH64_MOVW_G1:
     case BFD_RELOC_AARCH64_MOVW_G1_NC:
     case BFD_RELOC_AARCH64_MOVW_G1_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
       scale = 0;
       goto movw_common;
     case BFD_RELOC_AARCH64_MOVW_G1:
     case BFD_RELOC_AARCH64_MOVW_G1_NC:
     case BFD_RELOC_AARCH64_MOVW_G1_S:
     case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:

       scale = 16;
       goto movw_common;
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
       scale = 16;
       goto movw_common;
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:


@@ -7599,9 +8065,12 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_MOVW_G2:
     case BFD_RELOC_AARCH64_MOVW_G2_NC:
     case BFD_RELOC_AARCH64_MOVW_G2_S:
     case BFD_RELOC_AARCH64_MOVW_G2:
     case BFD_RELOC_AARCH64_MOVW_G2_NC:
     case BFD_RELOC_AARCH64_MOVW_G2_S:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G2:
+    case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:

       scale = 32;
       goto movw_common;
     case BFD_RELOC_AARCH64_MOVW_G3:
       scale = 32;
       goto movw_common;
     case BFD_RELOC_AARCH64_MOVW_G3:

+    case BFD_RELOC_AARCH64_MOVW_PREL_G3:

       scale = 48;
     movw_common:
       if (fixP->fx_done || !seg->use_rela_p)
       scale = 48;
     movw_common:
       if (fixP->fx_done || !seg->use_rela_p)


@@ -7633,6 +8102,9 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
                case BFD_RELOC_AARCH64_MOVW_G0_S:
                case BFD_RELOC_AARCH64_MOVW_G1_S:
                case BFD_RELOC_AARCH64_MOVW_G2_S:
                case BFD_RELOC_AARCH64_MOVW_G0_S:
                case BFD_RELOC_AARCH64_MOVW_G1_S:
                case BFD_RELOC_AARCH64_MOVW_G2_S:

+               case BFD_RELOC_AARCH64_MOVW_PREL_G0:
+               case BFD_RELOC_AARCH64_MOVW_PREL_G1:
+               case BFD_RELOC_AARCH64_MOVW_PREL_G2:

                  /* NOTE: We can only come here with movz or movn. */
                  if (signed_overflow (value, scale + 16))
                    as_bad_where (fixP->fx_file, fixP->fx_line,
                  /* NOTE: We can only come here with movz or movn. */
                  if (signed_overflow (value, scale + 16))
                    as_bad_where (fixP->fx_file, fixP->fx_line,


@@ -7677,7 +8149,7 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
       fixP->fx_r_type = (ilp32_p
                         ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
     case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC:
       fixP->fx_r_type = (ilp32_p
                         ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC

-                        : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC);
+                        : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12);

       S_SET_THREAD_LOCAL (fixP->fx_addsy);
       /* Should always be exported to object file, see
         aarch64_force_relocation().  */
       S_SET_THREAD_LOCAL (fixP->fx_addsy);
       /* Should always be exported to object file, see
         aarch64_force_relocation().  */


@@ -7685,11 +8157,11 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
       gas_assert (seg->use_rela_p);
       break;
 
       gas_assert (seg->use_rela_p);
       break;
 

-    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:

     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:

-    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:

     case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
     case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
     case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
     case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:


@@ -7721,6 +8193,14 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:

+    case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:

     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:


@@ -7917,11 +8397,11 @@ aarch64_force_relocation (struct fix *fixp)
     case BFD_RELOC_AARCH64_LDST32_LO12:
     case BFD_RELOC_AARCH64_LDST64_LO12:
     case BFD_RELOC_AARCH64_LDST8_LO12:
     case BFD_RELOC_AARCH64_LDST32_LO12:
     case BFD_RELOC_AARCH64_LDST64_LO12:
     case BFD_RELOC_AARCH64_LDST8_LO12:

-    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:

     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
     case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:

-    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:

     case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
     case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
     case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:


@@ -7955,6 +8435,14 @@ aarch64_force_relocation (struct fix *fixp)
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
     case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:

+    case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
+    case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
+    case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:

     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:


@@ -7975,18 +8463,37 @@ aarch64_force_relocation (struct fix *fixp)
 
 #ifdef OBJ_ELF
 
 
 #ifdef OBJ_ELF
 

+/* Implement md_after_parse_args.  This is the earliest time we need to decide
+   ABI.  If no -mabi specified, the ABI will be decided by target triplet.  */
+
+void
+aarch64_after_parse_args (void)
+{
+  if (aarch64_abi != AARCH64_ABI_NONE)
+    return;
+
+  /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32.  */
+  if (strlen (default_arch) > 7 && strcmp (default_arch + 7, ":32") == 0)
+    aarch64_abi = AARCH64_ABI_ILP32;
+  else
+    aarch64_abi = AARCH64_ABI_LP64;
+}
+

 const char *
 elf64_aarch64_target_format (void)
 {
 const char *
 elf64_aarch64_target_format (void)
 {

-  if (strcmp (TARGET_OS, "cloudabi") == 0)
-    {
-      /* FIXME: What to do for ilp32_p ?  */
-      return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
-    }
+#ifdef TE_CLOUDABI
+  /* FIXME: What to do for ilp32_p ?  */
+  if (target_big_endian)
+    return "elf64-bigaarch64-cloudabi";
+  else
+    return "elf64-littleaarch64-cloudabi";
+#else

   if (target_big_endian)
     return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
   else
     return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
   if (target_big_endian)
     return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
   else
     return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";

+#endif

 }
 
 void
 }
 
 void


@@ -8167,6 +8674,7 @@ md_begin (void)
       || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL

+      || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL

       || (aarch64_reg_hsh = hash_new ()) == NULL
       || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
       || (aarch64_nzcv_hsh = hash_new ()) == NULL
       || (aarch64_reg_hsh = hash_new ()) == NULL
       || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
       || (aarch64_nzcv_hsh = hash_new ()) == NULL


@@ -8205,6 +8713,11 @@ md_begin (void)
                         aarch64_sys_regs_tlbi[i].name,
                         (void *) (aarch64_sys_regs_tlbi + i));
 
                         aarch64_sys_regs_tlbi[i].name,
                         (void *) (aarch64_sys_regs_tlbi + i));
 

+  for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
+    checked_hash_insert (aarch64_sys_regs_sr_hsh,
+                        aarch64_sys_regs_sr[i].name,
+                        (void *) (aarch64_sys_regs_sr + i));
+

   for (i = 0; i < ARRAY_SIZE (reg_names); i++)
     checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
                         (void *) (reg_names + i));
   for (i = 0; i < ARRAY_SIZE (reg_names); i++)
     checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
                         (void *) (reg_names + i));


@@ -8270,12 +8783,15 @@ md_begin (void)
   for (i = 0; aarch64_hint_options[i].name != NULL; i++)
     {
       const char* name = aarch64_hint_options[i].name;
   for (i = 0; aarch64_hint_options[i].name != NULL; i++)
     {
       const char* name = aarch64_hint_options[i].name;

+      const char* upper_name = get_upper_str(name);

 
       checked_hash_insert (aarch64_hint_opt_hsh, name,
                           (void *) (aarch64_hint_options + i));
 
       checked_hash_insert (aarch64_hint_opt_hsh, name,
                           (void *) (aarch64_hint_options + i));

-      /* Also hash the name in the upper case.  */
-      checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
-                          (void *) (aarch64_hint_options + i));
+
+      /* Also hash the name in the upper case if not the same.  */
+      if (strcmp (name, upper_name) != 0)
+       checked_hash_insert (aarch64_hint_opt_hsh, upper_name,
+                            (void *) (aarch64_hint_options + i));

     }
 
   /* Set the cpu variant based on the command-line options.  */
     }
 
   /* Set the cpu variant based on the command-line options.  */


@@ -8356,6 +8872,8 @@ struct aarch64_cpu_option_table
    recognized by GCC.  */
 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
   {"all", AARCH64_ANY, NULL},
    recognized by GCC.  */
 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
   {"all", AARCH64_ANY, NULL},

+  {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8,
+                                 AARCH64_FEATURE_CRC), "Cortex-A34"},

   {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A35"},
   {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
   {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A35"},
   {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,


@@ -8366,15 +8884,64 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
                                  AARCH64_FEATURE_CRC), "Cortex-A72"},
   {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A73"},
                                  AARCH64_FEATURE_CRC), "Cortex-A72"},
   {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A73"},

+  {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
+                                 "Cortex-A55"},
+  {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
+                                 "Cortex-A75"},
+  {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
+                                 "Cortex-A76"},
+  {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                   AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+                                   | AARCH64_FEATURE_DOTPROD
+                                   | AARCH64_FEATURE_SSBS),
+                                   "Cortex-A76AE"},
+  {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+                                 | AARCH64_FEATURE_DOTPROD
+                                 | AARCH64_FEATURE_SSBS),
+                                 "Cortex-A77"},
+  {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+                                 | AARCH64_FEATURE_DOTPROD
+                                 | AARCH64_FEATURE_SSBS),
+                                 "Cortex-A65"},
+  {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                   AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
+                                   | AARCH64_FEATURE_DOTPROD
+                                   | AARCH64_FEATURE_SSBS),
+                                   "Cortex-A65AE"},
+  {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
+                                 | AARCH64_FEATURE_DOTPROD
+                                 | AARCH64_FEATURE_PROFILE),
+                                 "Ares"},

   {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
                                "Samsung Exynos M1"},
   {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8,
   {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
                                "Samsung Exynos M1"},
   {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8,

-                             AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
+                             AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
+                             | AARCH64_FEATURE_RDMA),

    "Qualcomm Falkor"},
    "Qualcomm Falkor"},

+  {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
+                                 | AARCH64_FEATURE_DOTPROD
+                                 | AARCH64_FEATURE_SSBS),
+                                 "Neoverse E1"},
+  {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
+                                 | AARCH64_FEATURE_DOTPROD
+                                 | AARCH64_FEATURE_PROFILE),
+                                 "Neoverse N1"},

   {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
   {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,

-                              AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
+                              AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
+                              | AARCH64_FEATURE_RDMA),

    "Qualcomm QDF24XX"},
    "Qualcomm QDF24XX"},

+  {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4,
+                              AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_PROFILE),
+   "Qualcomm Saphira"},

   {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
    "Cavium ThunderX"},
   {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
    "Cavium ThunderX"},


@@ -8407,6 +8974,9 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv8.1-a", AARCH64_ARCH_V8_1},
   {"armv8.2-a", AARCH64_ARCH_V8_2},
   {"armv8.3-a", AARCH64_ARCH_V8_3},
   {"armv8.1-a", AARCH64_ARCH_V8_1},
   {"armv8.2-a", AARCH64_ARCH_V8_2},
   {"armv8.3-a", AARCH64_ARCH_V8_3},

+  {"armv8.4-a", AARCH64_ARCH_V8_4},
+  {"armv8.5-a", AARCH64_ARCH_V8_5},
+  {"armv8.6-a", AARCH64_ARCH_V8_6},

   {NULL, AARCH64_ARCH_NONE}
 };
 
   {NULL, AARCH64_ARCH_NONE}
 };
 


@@ -8439,17 +9009,63 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
                        AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
   {"fp16",             AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
                        AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
   {"fp16",             AARCH64_FEATURE (AARCH64_FEATURE_F16, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},

+  {"fp16fml",          AARCH64_FEATURE (AARCH64_FEATURE_F16_FML, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_FP
+                                        | AARCH64_FEATURE_F16, 0)},

   {"profile",          AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
                        AARCH64_ARCH_NONE},
   {"sve",              AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_F16
                                         | AARCH64_FEATURE_SIMD
                                         | AARCH64_FEATURE_COMPNUM, 0)},
   {"profile",          AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0),
                        AARCH64_ARCH_NONE},
   {"sve",              AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_F16
                                         | AARCH64_FEATURE_SIMD
                                         | AARCH64_FEATURE_COMPNUM, 0)},

+  {"tme",              AARCH64_FEATURE (AARCH64_FEATURE_TME, 0),
+                       AARCH64_ARCH_NONE},

   {"compnum",          AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_F16
                                         | AARCH64_FEATURE_SIMD, 0)},
   {"rcpc",             AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
                        AARCH64_ARCH_NONE},
   {"compnum",          AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
                        AARCH64_FEATURE (AARCH64_FEATURE_F16
                                         | AARCH64_FEATURE_SIMD, 0)},
   {"rcpc",             AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
                        AARCH64_ARCH_NONE},

+  {"dotprod",          AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD, 0),
+                       AARCH64_ARCH_NONE},
+  {"sha2",             AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0),
+                       AARCH64_ARCH_NONE},
+  {"sb",               AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
+                       AARCH64_ARCH_NONE},
+  {"predres",          AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
+                       AARCH64_ARCH_NONE},
+  {"aes",              AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
+                       AARCH64_ARCH_NONE},
+  {"sm4",              AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
+                       AARCH64_ARCH_NONE},
+  {"sha3",             AARCH64_FEATURE (AARCH64_FEATURE_SHA3, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0)},
+  {"rng",              AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
+                       AARCH64_ARCH_NONE},
+  {"ssbs",             AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
+                       AARCH64_ARCH_NONE},
+  {"memtag",           AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
+                       AARCH64_ARCH_NONE},
+  {"sve2",             AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
+  {"sve2-sm4",         AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+                                        | AARCH64_FEATURE_SM4, 0)},
+  {"sve2-aes",         AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+                                        | AARCH64_FEATURE_AES, 0)},
+  {"sve2-sha3",                AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SVE2
+                                        | AARCH64_FEATURE_SHA3, 0)},
+  {"sve2-bitperm",     AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
+  {"bf16",             AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
+                       AARCH64_ARCH_NONE},
+  {"i8mm",             AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
+                       AARCH64_ARCH_NONE},
+  {"f32mm",            AARCH64_FEATURE (AARCH64_FEATURE_F32MM, 0),
+                       AARCH64_ARCH_NONE},
+  {"f64mm",            AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
+                       AARCH64_ARCH_NONE},

   {NULL,               AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
   {NULL,               AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 


@@ -8914,3 +9530,35 @@ aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
 {
   AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);
 }
 {
   AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);
 }

+
+#ifdef OBJ_ELF
+/* Same as elf_copy_symbol_attributes, but without copying st_other.
+   This is needed so AArch64 specific st_other values can be independently
+   specified for an IFUNC resolver (that is called by the dynamic linker)
+   and the symbol it resolves (aliased to the resolver).  In particular,
+   if a function symbol has special st_other value set via directives,
+   then attaching an IFUNC resolver to that symbol should not override
+   the st_other setting.  Requiring the directive on the IFUNC resolver
+   symbol would be unexpected and problematic in C code, where the two
+   symbols appear as two independent function declarations.  */
+
+void
+aarch64_elf_copy_symbol_attributes (symbolS *dest, symbolS *src)
+{
+  struct elf_obj_sy *srcelf = symbol_get_obj (src);
+  struct elf_obj_sy *destelf = symbol_get_obj (dest);
+  if (srcelf->size)
+    {
+      if (destelf->size == NULL)
+       destelf->size = XNEW (expressionS);
+      *destelf->size = *srcelf->size;
+    }
+  else
+    {
+      if (destelf->size != NULL)
+       free (destelf->size);
+      destelf->size = NULL;
+    }
+  S_SET_SIZE (dest, S_GET_SIZE (src));
+}
+#endif